Logic Signal Voltage Levels

Chapter 3 - Logic Gates

Logic gate circuits are designed to input and output only two types of signals: high
(1) and low (0), as represented by a variable voltage: full power supply voltage for a
high state and zero voltage for a low state. In a perfect world, all logic circuit
signals would exist at these extreme voltage limits, and never deviate from them (i.e.,
less than full voltage for a high, or more than zero voltage for a low). However, in
reality, logic signal voltage levels rarely attain these perfect limits due to stray voltage
drops in the transistor circuitry, and so we must understand the signal level limitations
of gate circuits as they try to interpret signal voltages lying somewhere between full
supply voltage and zero.
TTL gates operate on a nominal power supply voltage of 5 volts, +/- 0.25 volts. Ideally,
a TTL high signal would be 5.00 volts exactly, and a TTL low signal 0.00 volts
exactly. However, real TTL gate circuits cannot output such perfect voltage levels, and
are designed to accept high and low signals deviating substantially from these
ideal values. Acceptable input signal voltages range from 0 volts to 0.8 volts for a
low logic state, and 2 volts to 5 volts for a high logic state. Acceptable output
signal voltages (voltage levels guaranteed by the gate manufacturer over a specified
range of load conditions) range from 0 volts to 0.5 volts for a low logic state, and 2.7
volts to 5 volts for a high logic state:

If a voltage signal ranging between 0.8 volts and 2 volts were to be sent into the input
of a TTL gate, there would be no certain response from the gate. Such a signal would
be considered uncertain, and no logic gate manufacturer would guarantee how their
gate circuit would interpret such a signal.
As you can see, the tolerable ranges for output signal levels are narrower than for
input signal levels, to ensure that any TTL gate outputting a digital signal into the input
of another TTL gate will transmit voltages acceptable to the receiving gate. The
difference between the tolerable output and input ranges is called thenoise margin of
the gate. For TTL gates, the low-level noise margin is the difference between 0.8 volts
and 0.5 volts (0.3 volts), while the high-level noise margin is the difference between
2.7 volts and 2 volts (0.7 volts). Simply put, the noise margin is the peak amount of
spurious or noise voltage that may be superimposed on a weak gate output voltage
signal before the receiving gate might interpret it wrongly:

CMOS gate circuits have input and output signal specifications that are quite different
from TTL. For a CMOS gate operating at a power supply voltage of 5 volts, the
acceptable input signal voltages range from 0 volts to 1.5 volts for a low logic state,
and 3.5 volts to 5 volts for a high logic state. Acceptable output signal voltages
(voltage levels guaranteed by the gate manufacturer over a specified range of load
conditions) range from 0 volts to 0.05 volts for a low logic state, and 4.95 volts to 5
volts for a high logic state:

It should be obvious from these figures that CMOS gate circuits have far greater noise
margins than TTL: 1.45 volts for CMOS low-level and high-level margins, versus a
maximum of 0.7 volts for TTL. In other words, CMOS circuits can tolerate over twice
the amount of superimposed noise voltage on their input lines before signal
interpretation errors will result.
CMOS noise margins widen even further with higher operating voltages. Unlike TTL,
which is restricted to a power supply voltage of 5 volts, CMOS may be powered by
voltages as high as 15 volts (some CMOS circuits as high as 18 volts). Shown here
are the acceptable high and low states, for both input and output, of CMOS
integrated circuits operating at 10 volts and 15 volts, respectively:

The margins for acceptable high and low signals may be greater than what is
shown in the previous illustrations. What is shown represents worst-case input signal
performance, based on manufacturers specifications. In practice, it may be found that
a gate circuit will tolerate high signals of considerably less voltage and low signals
of considerably greater voltage than those specified here.
Conversely, the extremely small output margins shownguaranteeing output states
for high and low signals to within 0.05 volts of the power supply railsare
optimistic. Such solid output voltage levels will be true only for conditions of
minimum loading. If the gate is sourcing or sinking substantial current to a load, the
output voltage will not be able to maintain these optimum levels, due to internal
channel resistance of the gates final output MOSFETs.

Within the uncertain range for any gate input, there will be some point of
demarcation dividing the gates actual low input signal range from its actual high
input signal range. That is, somewhere between the lowest high signal voltage level
and the highest low signal voltage level guaranteed by the gate manufacturer, there
is a threshold voltage at which the gate will actually switch its interpretation of a signal
from low or high or vice versa. For most gate circuits, this unspecified voltage is a
single point:

In the presence of AC noise voltage superimposed on the DC input signal, a single

threshold point at which the gate alters its interpretation of logic level will result in an
erratic output:

If this scenario looks familiar to you, its because you remember a similar problem with
(analog) voltage comparator op-amp circuits. With a single threshold point at which an

input causes the output to switch between high and low states, the presence of
significant noise will cause erratic changes in the output:

The solution to this problem is a bit of positive feedback introduced into the amplifier
circuit. With an op-amp, this is done by connecting the output back around to the
noninverting (+) input through a resistor. In a gate circuit, this entails redesigning the
internal gate circuitry, establishing the feedback inside the gate package rather than
through external connections. A gate so designed is called a Schmitt trigger. Schmitt
triggers interpret varying input voltages according to two threshold voltages:
a positive-going threshold (VT+), and a negative-going threshold (VT-):

Schmitt trigger gates are distinguished in schematic diagrams by the small

hysteresis symbol drawn within them, reminiscent of the B-H curve for a
ferromagnetic material. Hysteresis engendered by positive feedback within the gate
circuitry adds an additional level of noise immunity to the gates performance. Schmitt
trigger gates are frequently used in applications where noise is expected on the input
signal line(s), and/or where an erratic output would be very detrimental to system
performance.
The differing voltage level requirements of TTL and CMOS technology present
problems when the two types of gates are used in the same system. Although
operating CMOS gates on the same 5.00 volt power supply voltage required by the
TTL gates is no problem, TTL output voltage levels will not be compatible with CMOS
input voltage requirements.
Take for instance a TTL NAND gate outputting a signal into the input of a CMOS
inverter gate. Both gates are powered by the same 5.00 volt supply (V cc). If the TTL
gate outputs a low signal (guaranteed to be between 0 volts and 0.5 volts), it will be
properly interpreted by the CMOS gates input as a low (expecting a voltage between
0 volts and 1.5 volts):

However, if the TTL gate outputs a high signal (guaranteed to be between 5 volts
and 2.7 volts), it might not be properly interpreted by the CMOS gates input as a
high (expecting a voltage between 5 volts and3.5 volts):

Given this mismatch, it is entirely possible for the TTL gate to output a valid high
signal (valid, that is, according to the standards for TTL) that lies within the uncertain
range for the CMOS input, and may be (falsely) interpreted as a low by the receiving
gate. An easy fix for this problem is to augment the TTL gates high signal voltage
level by means of a pullup resistor:

Something more than this, though, is required to interface a TTL output with a CMOS
input, if the receiving CMOS gate is powered by a greater power supply voltage:

There will be no problem with the CMOS gate interpreting the TTL gates low output,
of course, but a high signal from the TTL gate is another matter entirely. The
guaranteed output voltage range of 2.7 volts to 5 volts from the TTL gate output is
nowhere near the CMOS gates acceptable range of 7 volts to 10 volts for a high
signal. If we use an open-collector TTL gate instead of a totem-pole output gate,
though, a pullup resistor to the 10 volt Vdd supply rail will raise the TTL gates high
output voltage to the full power supply voltage supplying the CMOS gate. Since an
open-collector gate can only sink current, not source current, the high state voltage
level is entirely determined by the power supply to which the pullup resistor is
attached, thus neatly solving the mismatch problem:

Due to the excellent output voltage characteristics of CMOS gates, there is typically
no problem connecting a CMOS output to a TTL input. The only significant issue is
the current loading presented by the TTL inputs, since the CMOS output must sink
current for each of the TTL inputs while in the low state.
When the CMOS gate in question is powered by a voltage source in excess of 5 volts
(Vcc), though, a problem will result. The high output state of the CMOS gate, being
greater than 5 volts, will exceed the TTL gates acceptable input limits for a high

signal. A solution to this problem is to create an open-collector inverter circuit using

a discrete NPN transistor, and use it to interface the two gates together:

The Rpullup resistor is optional, since TTL inputs automatically assume a high state
when left floating, which is what will happen when the CMOS gate output is low and
the transistor cuts off. Of course, one very important consequence of implementing
this solution is the logical inversion created by the transistor: when the CMOS gate
outputs a low signal, the TTL gate sees a high input; and when the CMOS gate
outputs a high signal, the transistor saturates and the TTL gate sees a low input.
So long as this inversion is accounted for in the logical scheme of the system, all will
be well.
TTL Logic switching levels and a comparison of the different logic families.
The threshold Level, logic level or transition point is shown to the left of the voltage range.

Voltage Levels Description:

The graph provides a comparison of Input and Output [I/O] logic switching levels for the CMOS, TTL,
mixed CMOS/TTL, ETL, BTL, GTL, and Low voltage glue logic families. The graph above provides a
comparison between the Input and Output [I/O] logic switching levels for CMOS, and TTL logic
families.
The graph shows 5 volt CMOS, TTL, and mixed CMOS/TTL IC devices, and 3.3 volt LVTTL LVCMOS
IC devices. BTL and GTL [Bus Driver] IC are shown for comparison. Note many Low Voltage [LV]
CMOS families are 5 volt tolerant [not damaged by applying 5v to the input pins]. The output logic
levels above are defined by the Terms section below. For a review of Noise Margin numbers and a short
description of many of the IC logic families, refer to the Logic Family Selection page.
A graph for Low Voltage [LV] devices resides on the LV Logic Threshold page.
An additional chart of Interface bus threshold levels is provided on the Interface Threshold Voltage
Level page.
The GTLP switching levels [not shown above] follows; Output-Low is less-then 0.5v, Output-High is
1.5v, and the receiver threshold is 1.0 volts.

The CMOS families [74ACxx, 74HCxx, 74AHCxx, and 74Cxx] have different input and output switching
levels than the TTL logic devices [74Fxx, 74Sxx, 74ASxx, 74LSxx, and 74ALSxxx]. The output
switching levels from CMOS ICs is higher then a TTL IC, which happens to result in a better design and
does not have a negative effect. However the difference in input logic switching level does impact your
design, the TTL output does not correctly switch a CMOS input. The switching difference between a TTL
IC output and a CMOS IC input has to be accounted for.
The mixed CMOS/TTL [74ACTxx, 74HCTxx, 74AHCTxx, and 74FCTxx] logic devices have TTL logic
input switching levels and CMOS output switching levels. The mixed TTL/CMOS devices are CMOS
devices which just happen to have TTL input trigger levels, but they are CMOS ICs.
So the rule is, if you use a CMOS IC for reduced current consumption [for example], and a TTL IC feeds
the CMOS chip, then you need to either provide a voltage translation or use one of the mixed CMOS/TTL
devices [which have a "T" in the part number].
Side Note: I used 74xx part numbers above. The 74xx families [or just 74 prefix] refer to a
commercial operating temperature range.
A 54xx part number [or just 54 prefix] may also be found which refers to a military operating temperature
range. Some 74xx device families may also work at the Industrial temperature range [but you have to
check the data sheet, there is no hard and fast rule]. So a 74xx244 works at a commercial operating
temperature, while a 54xx244 which is the same device [maybe the same pinout, and package] will
continue to operate to the military operating temperature range [which is wider].
The difference in operational temperature ranges is provided on the Logic Prefix page.
The logic switching level does not change between the different temperature ranges.

An important point to keep in mind is that these threshold levels are fixed. However the voltage level is
not fixed if the ground is moving, the levels apply to zero volt ground. If an IC is drifting above ground
because of current in the ground pin or if voltage shifts between ICs are occurring because of different
ground potentials than the static voltage levels shown above no longer work. The same applies to
excessive noise voltages occurring near a threshold level. The transition voltages are separated by guard
bands, but they only work when not effected by noise. Voltage spikes could cause the actual logic
transition to shift in time as the output of one IC becomes effected by coupled voltages from another
source, changing the point i time that a voltage level is reached..
Switching Terms VCC: The voltage applied to the power pin(s).
In most cases Vcc is the voltage the IC needs to operate at [see note below].
VIH: [Voltage Input High] The minimum positive voltage applied to the input which will be accepted by
the device as a logic high.
VIL: [Voltage Input Low] The maximum positive voltage applied to the input which will be accepted by

the device as a logic low.

VOL: [Voltage Output Low] The maximum positive voltage from an output which the device considers
will be accepted as the maximum positive low level.
VOH: [Voltage Output High] The maximum positive voltage from an output which the device considers
will be accepted as the minimum positive high level.
VT: [Threshold Voltage] The voltage applied to a device which is "transition-Operated", which cause the
device to switch.
May also be listed as a '+' or '-' value. Note most integrated circuits are level sensitive and not threshold
sensitive.
Return to the Logic Design page.
The voltage levels depend on the value of Vcc, so if the power rail varies so would the input threshold
level.

Description of TTL, ECL and CMOS Glue Logic Families

The pull-down table lists all the possible TTL and CMOS families.
However not all IC functions are available in all logic families, as some of the early TTL families are
reaching obsolescence.
It's difficult to say what parts may still be purchased in some of the early logic families that were released
first, but safe to say that the generic TTL family is obsolete.

Vcc Note; The power supply voltage could be called almost anything on a schematic.
The smaller the schematic the more control the designer has over the naming of the supply voltage.
In fact the absolute voltage may be identical on many ICs, but because of regulators or inductors may
have a different symbol.
For example; the voltage supply net [Vcc] on one side of a filter inductor needs to have a different name

[5v], so the nets don't connect to each other.

Because Vcc effects the input voltage level, the power supply should always be filtered and by-passed.

Logic level
From Wikipedia, the free encyclopedia

What is a Logic Level?

Put simply, a logic level is a specific voltage or a state in which a signal can exist. We often refer to
the two states in a digital circuit to be ON or OFF. Represented in binary, an ON translates to a
binary 1, and an OFF translates to a binary 0. In Arduino, we call these signals HIGH or LOW,
respectively. There are several different technologies that have evolved over the past 30 years in
electronics to define the various voltage levels.

Logic 0 or Logic 1
Digital electronics rely on binary logic to store, process, and transmit data or information. Binary
Logic refers to one of two states ON or OFF. This is commonly translated as a binary 1 or binary 0.
A binary 1 is also referred to as a HIGH signal and a binary 0 is referred to as a LOW signal.
The strength of a signal is typically described by its voltage level. How is a logic 0 (LOW) or a logic 1
(HIGH) defined? Manufacturers of chips generally define these in their spec sheets. The most
common standard is TTL or Transistor-Transistor Logic.

In digital circuits, a logic level is one of a finite number of states that a digital signal can have. Logic
levels are usually represented by the voltage difference between the signal and ground, although
other standards exist. The range of voltage levels that represents each state depends on the logic
family being used.
Contents
[hide]

12-level logic
o

1.1Active state

1.2Logic voltage levels

23-level logic

34-level logic

49-level logic

5See also

6References

7External links

2-level logic[edit]
See also: Boolean algebra
In binary logic the two levels are logical high and logical low, which generally correspond to
a binary 1 and 0 respectively. Signals with one of these two levels can be used in boolean logic for
digital circuit design or analysis.

Active state[edit]
The use of either the higher or the lower voltage level to represent either logic state is arbitrary. The
two options are active high and active low. Active-high and active-low states can be mixed at will:
for example, a read only memory integrated circuit may have a chip-select signal that is active-low,
but the data and address bits are conventionally active-high. Occasionally a logic design is simplified
by inverting the choice of active level (see De Morgan's theorem).

Binary signal representations

Logic level

Active-high signal

Active-low signal

Logical high

Logical low

The name of an active-low signal is written with a bar above it to distinguish it from an active-high
signal. For example, the name Q, read "Q bar" or "Q not", represents an active-low signal. The
conventions commonly used are:

a bar above (Q)

a leading slash (/Q)

a lower-case n prefix or suffix (nQ or Q_n)

a trailing # (Q#), or

an "_B" suffix (Q_B).

The slash convention is also used with signals that have a meaning in both states. For example, it is
common to have a read/write line written R/(W), indicating that the signal is high in case of a read
and low in case of a write.
Many control signals in electronics are active-low signals

[1]

(usually reset lines, chip-select lines and

so on). Logic families such as TTL can sink more current than they can source, so fanout and noise
immunity increase. It also allows for wired-OR logic if the logic gates are open-collector/opendrain with a pull-up resistor. Examples of this are the IC bus and the Controller Area
Network (CAN),and the PCI Local Bus. RS232 signaling, as used on some serial ports, uses activelow signals.

Logic voltage levels[edit]

The two logical states are usually represented by two different voltages, but current is used in some
logic families. A threshold is designed for each logic family. When below that threshold, the signal is
"low," when above "high". Intermediate levels are undefined and the behavior of the connected
circuits is highly implementation-specific. The problem of the circuit designer is to avoid
circumstances that produce intermediate levels, so that the circuit behaves predictably.

Examples of binary logic levels

Technology

L voltage

H voltage

Notes

CMOS[2]

0 V to 1/3 VDD

2/3 VDD to VDD

VDD = supply voltage

TTL[2]

0 V to 0.8 V

2 V to VCC

VCC = 5 V 10%

ECL[citation needed]

VEE to 1.4 V

1.2 V to 0 V

VEE is about 5.2 V; VCC=Ground

Nearly all digital circuits use a consistent logic level for all internal signals. That level, however,
varies from one system to another. Interconnecting any two logic families often required special
techniques such as additional pull-up resistors or purpose-built interface circuits known as level
shifters. A level shifter connects one digital circuit that uses one logic level to another digital circuit
that uses another logic level. Often two level shifters are used, one at each system: A line
driver converts from internal logic levels to standard interface line levels; a line receiver converts
from interface levels to internal voltage levels.
For example, TTL levels are different from those of CMOS. Generally a TTL output does not rise
high enough to be reliably recognized as a logic 1 by a CMOS input, especially if it is only connected
to a high-input-impedance CMOS input that does not source significant current. This problem was
solved by the invention of the 74HCT family of devices that uses CMOS technology but TTL input
logic levels. These devices only work with a 5V power supply.

3-level logic[edit]

Logic Levels
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TTL Logic Levels

A majority of systems we use rely on 5 V TTL Logic Levels. TTL is an acronym for TransistorTransistor Logic. It relies on circuits built from bipolar transistors to achieve switching and maintain
logic states. Transistors are basically fancy-speak for electrically controlled switches. For any logic
family, there are a number of threshold voltage levels to know:
VOH Minimum OUTPUT Voltage level a TTL device will provide for a HIGH signal.
VIH Minimum INPUT Voltage level to be considered a HIGH.

VOL Maximum OUTPUT Voltage level a device will provide for a LOW signal.
VIL Maximum INPUT Voltage level to still be considered a LOW.

You will notice that the minimum output HIGH voltage (VOH) is 2.7 V. Basically, this means that output
voltage of the device driving HIGH will always be at least 2.7 V. The minimum input HIGH voltage
(VIH) is 2 V, or basically any voltage that is at least 2 V will be read in as a logic 1 (HIGH) to a TTL
device.
You will also notice that there is cushion of 0.7 V between the output of one device and the input of
another. This is sometimes referred to as noise margin.
Likewise, the maximum output LOW voltage (VOL) is 0.4 V. This means that a device trying to send
out a logic 0 will always be below 0.4 V. The maximum input LOW voltage (VIL) is 0.8 V. So, any input
signal that is below 0.8 V will still be considered a logic 0 (LOW) when read into the device.
What happens if you have a voltage that is in between 0.8 V and 2 V? Well, your guess is as good as
mine. Honestly, this range of voltages is undefined and results in an invalid state, often referred to as
floating. If an output pin on your device is floating in this range, there is no certainty with what the
signal will result in. It may bounce arbitrarily between HIGH and LOW.
Here is another way of looking at the input / output tolerances for a generic TTL device.

Another common voltage standard that you will encounter are 3.3 V devices.

3.3 V CMOS Logic Levels

As technology has advanced, we have created devices that require lower power consumption and
run off a lower base voltage (Vcc = 3.3 V instead of 5 V). The fabrication technique is also a bit
different for 3.3 V devices that allows a smaller footprint and lower overall system costs.

In order to ensure general compatibility, you will notice that most of the voltage levels are almost all
the same as 5 V devices. A 3.3 V device can interface with a 5V device without any additional
components. For example, a logic 1 (HIGH) from a 3.3 V device will be at least 2.4 V. This will still be
interpreted as a logic 1 (HIGH) to a 5V system because it is above the VIH of 2 V.
A word of caution, however, is when going the other direction and interfacing from a 5 V to a 3.3 V
device to ensure that the 3.3 V device is 5 V tolerant. The specification you are interested in is
the maximum input voltage. On certain 3.3 V devices, any voltages above 3.6 V will cause
permanent damage to the chip. You can use a simple voltage divider (like a 1K and a 2K) to
knock down 5 V signals to 3.3 V levels or use one of our logic level shifters.

Active-Low and Active-High

When working with ICs and microcontrollers, youll likely encounter pins that are active-low and pins
that are active-high. Simply put, this just describes how the pin is activated. If its an active-low pin,
you must pull that pin LOW by connecting it to ground. For an active high pin, you connect it to your
HIGH voltage (usually 3.3V/5V).

For example, lets say you have a shift register that has a chip enable pin, CE. If you see the CE pin
anywhere in the datasheet with a line over it like this, CE, then that pin is active-low. The CE pin
would need to be pulled to GND in order for the chip to become enabled. If, however, the CE pin
doesnt have a line over it, then it is active high, and it needs to be pulled HIGH in order to enable the
pin.
Many ICs will have both active-low and active-high pins intermingled. Just be sure to double check
for pin names that have a line over them. The line is used to represent NOT (also known as bar).
When something is NOTTED, it changes to the opposite state. So if an active-high input is NOTTED,
then it is now active-low. Simple as that!

Transistortransistor logic
From Wikipedia, the free encyclopedia

A Motorola 68000-based computer with various TTL chips mounted on breadboards.

Transistortransistor logic (TTL) is a class of digital circuits built from bipolar junction
transistors (BJT) and resistors. It is called transistortransistor logic because both the logic gating
function (e.g., AND) and the amplifying function are performed by transistors (contrast with resistor
transistor logic (RTL) and diodetransistor logic (DTL)).
TTL is notable for being a widespread integrated circuit (IC) family used in many applications such
as computers, industrial controls, test equipment and instrumentation, consumer
electronics, synthesizers, etc. The designation TTL is sometimes used to mean TTL-compatible logic
levels, even when not associated directly with TTL integrated circuits, for example as a label on the
inputs and outputs of electronic instruments.[1]
After their introduction in integrated circuit form in 1963 by Sylvania, TTL integrated circuits were
manufactured by several semiconductor companies, with the 7400 series (also called 74xx)
by Texas Instrumentsbecoming particularly popular. TTL manufacturers offered a wide range of logic
gate, flip-flops, counters, and other circuits. Several variations of the original bipolar TTL concept
were developed, yielding circuits with higher speed or lower power dissipation to allow optimization

of a design. TTL circuits simplified system design compared to earlier logic families, offering speed
superior to RTL. The design of the input and outputs of TTL gates allowed many elements to be
interconnected.
TTL became the foundation of computers and other digital electronics. Even after much larger scale
integrated circuits made multiple-circuit-board processors obsolete, TTL devices still found extensive
use as the "glue" logic interfacing more densely integrated components. TTL devices were originally
made in ceramic and plastic dual-in-line (DIP) packages, and flat-pack form. TTL chips are now also
made in surface-mount packages. Successors to the original bipolar TTL logic often are
interchangeable in function with the original circuits, but with improved speed or lower power
dissipation.
Contents
[hide]

1History

2Implementation
o

2.1Fundamental TTL gate

2.2TTL with a "totem-pole" output stage

3Interfacing considerations

4Packaging

5Comparison with other logic families

6Sub-types

7Applications
o

7.1Analog applications

8See also

9References

10External links

History[edit]

A real-time clock built of TTL chips around 1979.

TTL was invented in 1961 by James L. Buie of TRW, "particularly suited to the newly developing
integrated circuit design technology", and it was originally named transistor-coupled transistor
logic (TCTL).[2] The first commercial integrated-circuit TTL devices were manufactured by Sylvania in
1963, called the Sylvania Universal High-Level Logic family (SUHL). [3] The Sylvania parts were used
in the controls of the Phoenix missile.[3] TTL became popular with electronic systems designers
after Texas Instruments introduced the 5400 series of ICs, with military temperature range, in 1964
and the later 7400 series, specified over a narrower range and with inexpensive plastic packages, in
1966.[4]
The Texas Instruments 7400 family became an industry standard. Compatible parts were made
by Motorola, AMD, Fairchild, Intel, Intersil, Signetics, Mullard, Siemens, SGS-Thomson, Rifa, Nation
al Semiconductor,[5][6] and many other companies, even in the Eastern Bloc (Soviet Union, GDR,
Poland, Czechoslovakia, Hungary, Romania - for details see 7400 series). Not only did others make
compatible TTL parts, but compatible parts were made using many other circuit technologies as well.
At least one manufacturer, IBM, produced non-compatible TTL circuits for its own use; IBM used the
technology in the IBM System/38, IBM 4300, and IBM 3081.[7]
The term "TTL" is applied to many successive generations of bipolar logic, with gradual
improvements in speed and power consumption over about two decades. The most recently
introduced family 74Fxx is still sold today, and was widely used into the late 90s. 74AS/ALS

Advanced Schottky was introduced in 1985.[8] As of 2008, Texas Instruments continues to supply the
more general-purpose chips in numerous obsolete technology families, albeit at increased prices.
Typically, TTL chips integrate no more than a few hundred transistors each. Functions within a single
package generally range from a few logic gates to a microprocessor bit-slice. TTL also became
important because its low cost made digital techniques economically practical for tasks previously
done by analog methods.[9]
The Kenbak-1, ancestor of the first personal computers, used TTL for its CPU instead of
a microprocessor chip, which was not available in 1971.[10] The Datapoint 2200 from 1970 used TTL
components for its CPU and was the basis for the 8008 and later the x86 instruction set.[11] The
1973 Xerox Alto and 1981 Star workstations, which introduced the graphical user interface, used
TTL circuits integrated at the level ofArithmetic logic units (ALU)s and bitslices, respectively. Most
computers used TTL-compatible "glue logic" between larger chips well into the 1990s. Until the
advent of programmable logic, discrete bipolar logic was used to prototype
and emulate microarchitectures under development.

Implementation[edit]
Fundamental TTL gate[edit]

Two-input TTL NAND gate with a simple output stage (simplified).

TTL inputs are the emitters of a multiple-emitter transistor. This IC structure is functionally equivalent
to multiple transistors where the bases and collectors are tied together.[12] The output is buffered by
a common emitter amplifier.
Inputs both logical ones. When all the inputs are held at high voltage, the baseemitter junctions
of the multiple-emitter transistor are reverse-biased. Unlike DTL, a small collector current
(approximately 10A) is drawn by each of the inputs. This is because the transistor is in reverseactive mode. An approximately constant current flows from the positive rail, through the resistor and
into the base of the multiple emitter transistor.[13] This current passes through the base-emitter
junction of the output transistor, allowing it to conduct and pulling the output voltage low (logical
zero).
An input logical zero. Note that the base-collector junction of the multiple-emitter transistor and the
base-emitter junction of the output transistor are in series between the bottom of the resistor and
ground. If one input voltage becomes zero, the corresponding base-emitter junction of the multipleemitter transistor is in parallel with these two junctions. A phenomenon called current steering means
that when two voltage-stable elements with different threshold voltages are connected in parallel, the

current flows through the path with the smaller threshold voltage. That is, current flows out of this
input and into the zero (low) voltage source. As a result, no current flows through the base of the
output transistor, causing it to stop conducting and the output voltage becomes high (logical one).
During the transition the input transistor is briefly in its active region; so it draws a large current away
from the base of the output transistor and thus quickly discharges its base. This is a critical
advantage of TTL over DTL that speeds up the transition over a diode input structure. [14]
The main disadvantage of TTL with a simple output stage is the relatively high output resistance at
output logical "1" that is completely determined by the output collector resistor. It limits the number of
inputs that can be connected (the fanout). Some advantage of the simple output stage is the high
voltage level (up to VCC) of the output logical "1" when the output is not loaded.
A common variation omits the collector resistor of the output transistor, making an open
collector output. This allows the designer to fabricate logic by connecting the open collector outputs
of several logic gates together and providing a single external pull-up resistor. If any of the logic
gates becomes logic low (transistor conducting), the combined output will be low. Examples of this
type of gate are the 7401[15] and 7403 series. Open collector outputs of some gates have a higher
maximum voltage, such as 15V for the 7426,[16]useful when driving other than TTL loads.

TTL with a "totem-pole" output stage[edit]

Standard TTL NAND with a "totem-pole" output stage, one of four in 7400

To solve the problem with the high output resistance of the simple output stage the second
schematic adds to this a "totem-pole" ("pushpull") output. It consists of the two n-p-n transistors
V3 and V4, the "lifting" diode V5 and the current-limiting resistor R3 (see the figure on the right). It is
driven by applying the same current steering idea as above.
When V2 is "off", V4 is "off" as well and V3 operates in active region as a voltage follower producing
high output voltage (logical "1"). When V2 is "on", it activates V4, driving low voltage (logical "0") to
the output. V2 and V4collectoremitter junctions connect V4 baseemitter junction in parallel to the
series-connected V3 baseemitter and V5 anodecathode junctions. V3 base current is deprived; the
transistor turns "off" and it does not impact on the output. In the middle of the transition, the resistor
R3 limits the current flowing directly through the series connected transistor V 3, diode V5 and

transistor V4 that are all conducting. It also limits the output current in the case of output logical "1"
and short connection to the ground. The strength of the gate may be increased without proportionally
affecting the power consumption by removing the pull-up and pull-down resistors from the output
stage.[17][18]
The main advantage of TTL with a "totem-pole" output stage is the low output resistance at output
logical "1". It is determined by the upper output transistor V3 operating in active region as a voltage
follower. The resistor R3does not increase the output resistance since it is connected in the
V3 collector and its influence is compensated by the negative feedback. A disadvantage of the
"totem-pole" output stage is the decreased voltage level (no more than 3.5 V) of the output logical
"1" (even if the output is unloaded). The reason of this reduction are the voltage drops across the
V3 baseemitter and V5 anodecathode junctions.

Interfacing considerations[edit]
Like DTL, TTL is a current-sinking logic since a current must be drawn from inputs to bring them to a
logic 0 level. At low input voltage, the TTL input sources current which must be absorbed by the
previous stage. The maximum value of this input current is about 1.6 mA for a standard TTL gate.
[19]
The input source has to be low-resistive enough (<500 ) so that the flowing current creates only
a negligible voltage drop (<0.4 V) across it, for the input to be considered as a logical "0" (with a
0.4 V "noise margin", see below). The output stage of the most common TTL gates is specified to
function correctly when driving up to 10 standard input stages (a fanout of 10). TTL inputs are
sometimes simply left floating to provide a logical "1", though this usage is not recommended.
Standard TTL circuits operate with a 5-volt power supply. A TTL input signal is defined as "low" when
between 0 V and 0.8 V with respect to the ground terminal, and "high" when between 2.2 V and
VCC (5 V),[20] and if a voltage signal ranging between 0.8 V and 2.0 V is sent into the input of a TTL
gate, there is no certain response from the gate and therefore it is considered "uncertain" (precise
logic levels vary slightly between sub-types and by temperature). TTL outputs are typically restricted
to narrower limits of between 0.0 V and 0.4 V for a "low" and between 2.6 V and VCC for a "high",
providing at least 0.4 V of noise immunity. Standardization of the TTL levels is so ubiquitous that
complex circuit boards often contain TTL chips made by many different manufacturers selected for
availability and cost, compatibility being assured; two circuit board units off the same assembly line
on different successive days or weeks might have a different mix of brands of chips in the same
positions on the board; repair is possible with chips manufactured years (sometimes over a decade)
later than original components. Within usefully broad limits, logic gates can be treated as ideal
Boolean devices without concern for electrical limitations. The 0.4V noise margins are adequate
because of the low output impedance of the driver stage, that is, a large amount of noise power
superimposed on the output is needed to drive an input into an undefined region.
In some cases (e.g., when the output of a TTL logic gate needs to be used for driving the input of a
CMOS gate), the voltage level of the "totem-pole" output stage at output logical "1" can be increased
up to VCC by connecting an external resistor between the V3collector and the positive rail. It pulls
up the V5 cathode and cuts-off the diode.[21] However, this technique actually converts the
sophisticated "totem-pole" output into a simple output stage having significant output resistance
when driving a high level (determined by the external resistor).

Packaging[edit]
Like most integrated circuits of the period 19631990, commercial TTL devices are usually
packaged in dual in-line packages (DIPs), usually with 14 to 24 pins,[22] for through-hole or socket
mounting. The DIPs were usually made of epoxy plastic (PDIP) for commercial-grade parts or of
ceramic (CDIP) for military-grade parts.
Beam-lead chip dies without packages were made for assembly into larger arrays as hybrid
integrated circuits. Parts for military and aerospace applications were packaged in flatpacks, a form
of surface-mount package, with leads suitable for welding or soldering to printed circuit boards.
Today, many TTL-compatible devices are available in surface-mount packages, which are available
in a wider array of types than through-hole packages.
TTL is particularly well suited to bipolar integrated circuits because additional inputs to a gate merely
required additional emitters on a shared base region of the input transistor. If individually packaged
transistors were used, the cost of all the transistors would discourage one from using such an input
structure. But in an integrated circuit, the additional emitters for extra gate inputs add only a small
area.
At least one computer manufacturer, IBM, built its own flip chip integrated circuits with TTL; these
chips were mounted on ceramic multi-chip modules.[23][24]

Comparison with other logic families[edit]

Main article: Logic family
TTL devices consume substantially more power than equivalent CMOS devices at rest, but power
consumption does not increase with clock speed as rapidly as for CMOS devices. [25] Compared to
contemporary ECL circuits, TTL uses less power and has easier design rules but is substantially
slower. Designers can combine ECL and TTL devices in the same system to achieve best overall
performance and economy, but level-shifting devices are required between the two logic families.
TTL is less sensitive to damage fromelectrostatic discharge than early CMOS devices.
Due to the output structure of TTL devices, the output impedance is asymmetrical between the high
and low state, making them unsuitable for driving transmission lines. This drawback is usually
overcome by buffering the outputs with special line-driver devices where signals need to be sent
through cables. ECL, by virtue of its symmetric low-impedance output structure, does not have this
drawback.
The TTL "totem-pole" output structure often has a momentary overlap when both the upper and
lower transistors are conducting, resulting in a substantial pulse of current drawn from the power
supply. These pulses can couple in unexpected ways between multiple integrated circuit packages,
resulting in reduced noise margin and lower performance. TTL systems usually have a decoupling
capacitor for every one or two IC packages, so that a current pulse from one TTL chip does not
momentarily reduce the supply voltage to another.
Several manufacturers now supply CMOS logic equivalents with TTL-compatible input and output
levels, usually bearing part numbers similar to the equivalent TTL component and with the

same pinouts. For example, the 74HCT00 series provides many drop-in replacements for
bipolar 7400 series parts, but uses CMOS technology.

Sub-types[edit]
Successive generations of technology produced compatible parts with improved power consumption
or switching speed, or both. Although vendors uniformly marketed these various product lines as TTL
with Schottky diodes, some of the underlying circuits, such as used in the LS family, could rather be
considered DTL.[26]
Variations of and successors to the basic TTL family, which has a typical gate propagation delay of
10ns and a power dissipation of 10 mW per gate, for a powerdelay product (PDP) or switching
energy of about 100 pJ, include:

Low-power TTL (L), which traded switching speed (33ns) for a reduction in power
consumption (1 mW) (now essentially replaced by CMOS logic)

High-speed TTL (H), with faster switching than standard TTL (6ns) but significantly higher
power dissipation (22 mW)

Schottky TTL (S), introduced in 1969, which used Schottky diode clamps at gate inputs to
prevent charge storage and improve switching time. These gates operated more quickly (3ns)
but had higher power dissipation (19 mW)

Low-power Schottky TTL (LS) used the higher resistance values of low-power TTL and the
Schottky diodes to provide a good combination of speed (9.5ns) and reduced power
consumption (2 mW), and PDP of about 20 pJ. Probably the most common type of TTL, these
were used as glue logic in microcomputers, essentially replacing the former H, L, and S subfamilies.

Fast (F) and Advanced-Schottky (AS) variants of LS from Fairchild and TI, respectively, circa
1985, with "Miller-killer" circuits to speed up the low-to-high transition. These families achieved
PDPs of 10 pJ and 4 pJ, respectively, the lowest of all the TTL families.

Low-voltage TTL (LVTTL) for 3.3-volt power supplies and memory interfacing.

Most manufacturers offer commercial and extended temperature ranges: for example Texas
Instruments 7400 series parts are rated from 0 to 70 C, and 5400 series devices over the militaryspecification temperature range of 55 to +125 C.
Special quality levels and high-reliability parts are available for military and aerospace applications.
Radiation-hardened devices are offered for space applications.

Applications[edit]
Before the advent of VLSI devices, TTL integrated circuits were a standard method of construction
for the processors of mini-computer and mainframe processors; such as the DEC VAX and Data

General Eclipse, and for equipment such as machine tool numerical controls, printers and video
display terminals. As microprocessors became more functional, TTL devices became important for
"glue logic" applications, such as fast bus drivers on a motherboard, which tie together the function
blocks realized in VLSI elements.

Analog applications[edit]
While originally designed to handle logic-level digital signals, a TTL inverter can be biased as an
analog amplifier. Connecting a resistor between the output and the input biases the TTL element as
a negative feedback amplifier. Such amplifiers may be useful to convert analog signals to the digital
domain but would not ordinarily be used where analog amplification is the primary purpose. [27] TTL
inverters can also be used in crystal oscillators where their analog amplification ability is significant.
A TTL gate may operate inadvertently as an analog amplifier if the input is connected to a slowly
changing input signal that traverses the unspecified region from 0.8 V to 2.2 V. The output can be
erratic when the input is in this range. A slowly changing input like this can also cause excess power
dissipation in the output circuit. If such an analog input must be used, there are specialized TTL
parts with Schmitt trigger inputs available that will reliably convert the analog input to a digital value,
effectively operating as a one bit A to D converter.

What Is the Definition of a TTL (Transistor-Transistor Logic)

Compatible Signal?
Hardware: Multifunction DAQ (MIO)

Problem:
What is the definition of a TTL (Transistor-Transistor Logic) compatible signal?
Solution:
A TTL signal must meet an output voltage and current specification, an input voltage and current specification, and a
rise/fall time specification. For any given hardware, the signal must also have a minimum pulse width.
Note: All specifications use the following notation:

Output Low = OL

Output High = OH

Input Low = IL

Input High = IH

1.

The output voltage and current specifications are as follows:

VOL = 0.4 V

VOH = 2.4 V

IOL = 16 mA

IOH = 400 A

2.

The input voltage and current specification are as follows:

VIL = 0.8 V

VIH = 2.0 V

IIL = 1.6 mA

IIH = 40 A

3.

The maximum rise/fall time is 50 ns between VIL and VIH. The minimum pulse width for:

NI-STC devices is 10 ns.

NI-TIO devices is 5 ns.

Note: The ratio between IOL and IIL as well as IOH and IIH is 10 due to the standard fanout of TTL logic.

What are the Basic Differences Between CMOS and TTL Signals?
Hardware: Multifunction DAQ (MIO)

Problem:
What are some of the differences between CMOS and TTL signals and how do they compare?
Solution:
Characteristics of CMOS logic:

Dissipates low power: The power dissipation is dependent on the power supply voltage, frequency, output
load, and input rise time. At 1 MHz and 50 pF load, the power dissipation is typically 10 nW per gate.

Short propagation delays: Depending on the power supply, the propagation delays are usually around 25 nS
to 50 nS.

Rise and fall times are controlled: The rise and falls are usually ramps instead of step functions, and they
are 20 - 40% longer than the propagation delays.

Noise immunity approaches 50% or 45% of the full logic swing.

Levels of the logic signal will be essentially equal to the power supplied since the input impedance is so
high.

Voltage levels range from 0 to VDD where VDD is the supply voltage. A low level is anywhere between 0
and 1/3 VDD while a high level is between 2/3 VDD and VDD.
Characteristics of TTL logic:

Power dissipation is usually 10 mW per gate.

Propagation delays are 10 nS when driving a 15 pF/400 ohm load.

Voltage levels range from 0 to Vcc where Vcc is typically 4.75V - 5.25V. Voltage range 0V - 0.8V creates
logic level 0. Voltage range 2V - Vcc creates logic level 1.

CMOS compared to TTL:

CMOS components are typically more expensive than TTL equivalents. However, CMOS technology is
usually less expensive on a system level due to CMOS chips being smaller and requiring less regulation.

CMOS circuits do not draw as much power as TTL circuits while at rest. However, CMOS power
consumption increases faster with higher clock speeds than TTL does. Lower current draw requires less power
supply distribution, therefore causing a simpler and cheaper design.

Due to longer rise and fall times, the transmission of digital signals becomes simpler and less expensive with
CMOS chips.
CMOS components are more susceptible to damage from electrostatic discharge than TTL components.

How Do I Interface TTL Signals With CMOS Circuits?

Hardware: Multifunction DAQ (MIO)

Problem:
I want to interface my digital lines on my National Instruments DAQ board to my CMOS circuit. How can I interface
the two? How do I connect two digital signals with different voltage levels?
Solution:
The following figures demonstrate how to interface a TTL signal to a CMOS circuit and a CMOS circuit to a TTL input.
The figures also show how to interface the two circuits if the voltage levels are incompatible.

Figure 1: TTL-to-CMOS interfacing using pull-up resistor

Figure 2: CMOS-to-TTL interfacing using a CMOS buffer IC

Figure 3: TTL-to-CMOS interfacing using a transistor

Figure 4: TTL-to-CMOS interfacing using a TLL open-collector buffer IC

Figure 5: CMOS-to-TTL interfacing using a CMOS buffer IC

(Roger L. Tokheim, Digital Electronics, 3d ed., McGraw-Hill, New York, 1990)

Digital Logic Gates

Introduction to Digital Logic Gates

A Digital Logic Gate is an electronic device that makes logical decisions based on the different
combinations of digital signals present on its inputs. Digital logic gates may have more than one
input but generally only have one digital output. Individual logic gates can be connected together
to form combinational or sequential circuits, or larger logic gate functions.

Standard commercially available digital logic gates are available in two basic families or
forms, TTL which stands for Transistor-Transistor Logic such as the 7400 series,
andCMOS which stands for Complementary Metal-Oxide-Silicon which is the 4000 series of
chips. This notation of TTL or CMOS refers to the logic technology used to manufacture the
integrated circuit, (IC) or a chip as it is more commonly called.

Digital Logic Gate

Generally speaking, TTL logic ICs use NPN and PNP type Bipolar Junction
Transistors while CMOS logic ICs use complementary MOSFET or JFET type Field Effect
Transistors for both their input and output circuitry.
As well as TTL and CMOS technology, simple digital logic gates can also be made by
connecting together diodes, transistors and resistors to produce RTL, Resistor-Transistor logic
gates, DTL, Diode-Transistor logic gates or ECL, Emitter-Coupled logic gates but these are less
common now compared to the popular CMOS family.
Integrated Circuits or ICs as they are more commonly called, can be grouped together into
families according to the number of transistors or gates that they contain. For example, a
simple AND gate my contain only a few individual transistors, were as a more complex

microprocessor may contain many thousands of individual transistor gates. Integrated circuits are
categorised according to the number of logic gates or the complexity of the circuits within a
single chip with the general classification for the number of individual gates given as:

Classification of Integrated Circuits

Small Scale Integration or (SSI) Contain up to 10 transistors or a few gates

within a single package such as AND, OR, NOT gates.

Medium Scale Integration or (MSI) between 10 and 100 transistors or tens

of gates within a single package and perform digital operations such as
adders, decoders, counters, flip-flops and multiplexers.

Large Scale Integration or (LSI) between 100 and 1,000 transistors or

hundreds of gates and perform specific digital operations such as I/O chips,
memory, arithmetic and logic units.

Very-Large

Scale

Integration or (VLSI) between 1,000 and 10,000

transistors or thousands of gates and perform computational operations such

as processors, large memory arrays and programmable logic devices.

Super-Large Scale Integration or (SLSI) between 10,000 and 100,000

transistors within a single package and perform computational operations
such as microprocessor chips, micro-controllers, basic PICs and calculators.

Ultra-Large Scale Integration or (ULSI) more than 1 million transistors

the big boys that are used in computers CPUs, GPUs, video processors, microcontrollers, FPGAs and complex PICs.

While the ultra large scale ULSI classification is less well used, another level of integration
which represents the complexity of the Integrated Circuit is known as theSystem-on-Chip or
(SOC) for short. Here the individual components such as the microprocessor, memory,
peripherals, I/O logic etc, are all produced on a single piece of silicon and which represents a
whole electronic system within one single chip, literally putting the word integrated into
integrated circuit.

These complete integrated chips which can contain up to 100 million individual silicon-CMOS
transistor gates within one single package are generally used in mobile phones, digital cameras,
micro-controllers, PICs and robotic type applications.

Moores Law
In 1965, Gordon Moore co-founder of the Intel corporation predicted that The number of
transistors and resistors on a single chip will double every 18 months regarding the
development of semiconductor gate technology. When Gordon Moore made his famous
comment way back in 1965 there were approximately only 60 individual transistor gates on a
single silicon chip or die.
The worlds first microprocessor in 1971 was the Intel 4004 that had a 4-bit data bus and
contained about 2,300 transistors on a single chip, operating at about 600kHz. Today, the Intel
Corporation have placed a staggering 1.2 Billion individual transistor gates onto its new Quadcore i7-2700K Sandy Bridge 64-bit microprocessor chip operating at nearly 4GHz, and the onchip transistor count is still rising, as newer faster microprocessors and micro-controllers are
developed.

Digital Logic States

The Digital Logic Gate is the basic building block from which all digital electronic circuits and
microprocessor based systems are constructed from. Basic digital logic gates perform logical
operations of AND, OR and NOT on binary numbers.
In digital logic design only two voltage levels or states are allowed and these states are generally
referred to as Logic 1 and Logic 0, High and Low, or True and False. These two states are
represented in Boolean Algebra and standard truth tables by the binary digits
of 1 and 0 respectively.
A good example of a digital state is a simple light switch as it is either ON or OFF but not
both at the same time. Then we can summarise the relationship between these various digital
states as being:

Most digital logic gates and digital logic systems use Positive logic, in which a logic level 0
or LOW is represented by a zero voltage, 0v or ground and a logic level 1 or HIGH is
represented by a higher voltage such as +5 volts, with the switching from one voltage level to the
other, from either a logic level 0 to a 1 or a 1 to a 0 being made as quickly as possible to
prevent any faulty operation of the logic circuit.
There also exists a complementary Negative Logic system in which the values and the rules of
a logic 0 and a logic 1 are reversed but in this tutorial section about digital logic gates we
shall only refer to the positive logic convention as it is the most commonly used.
In standard TTL (transistor-transistor logic) ICs there is a pre-defined voltage range for the input
and output voltage levels which define exactly what is a logic 1 level and what is a logic 0
level and these are shown below.

TTL Input & Output Voltage Levels

There are a large variety of logic gate types in both the bipolar 7400 and the CMOS 4000
families of digital logic gates such as 74Lxx, 74LSxx, 74ALSxx, 74HCxx, 74HCTxx, 74ACTxx
etc, with each one having its own distinct advantages and disadvantages compared to the other.
The exact switching voltage required to produce either a logic 0 or a logic 1 depends upon
the specific logic group or family.
However, when using a standard +5 volt supply any TTL voltage input between 2.0v and 5v is
considered to be a logic 1 or HIGH while any voltage input below 0.8v is recognised as a
logic 0 or LOW. The voltage region in between these two voltage levels either as an input or
as an output is called the Indeterminate Region and operating within this region may cause the
logic gate to produce a false output.
The CMOS 4000 logic family uses different levels of voltages compared to the TTL types as
they are designed using field effect transistors, or FETs. In CMOS technology a logic 1 level
operates between 3.0 and 18 volts and a logic 0 level is below 1.5 volts. Then the following
table shows the difference between the logic levels of traditional TTL and CMOS logic gates.

TTL and CMOS Logic Levels

Then from the above observations, we can define the ideal TTL digital logic gate as one that has
a LOW level logic 0 of 0 volts (ground) and a HIGH level logic 1 of +5 volts and this
can be demonstrated as:

Ideal TTL Digital Logic Gate Voltage Levels

Where the opening or closing of the switch produces either a logic level 1 or a logic level 0
with the resistor R being known as a pull-up resistor.

Digital Logic Noise

However, between these defined HIGH and LOW values lies what is generally called a nomans land (the blue areas above) and if we apply a signal voltage of a value within this nomans land area we do not know whether the logic gate will respond to it as a level 0 or as a
level 1, and the output will become unpredictable.
Noise is the name given to a random and unwanted voltage that is induced into electronic circuits
by external interference, such as from nearby switches, power supply fluctuations or from wires
and other conductors that pick-up stray electromagnetic radiation. Then in order for a logic gate
not to be influence by noise in must have a certain amount of noise margin or noise immunity.

Digital Logic Gate Noise Immunity

In the example above, the noise signal is superimposed onto the Vcc supply voltage and as long
as it stays above the minimum level (VON(min)) the input an corresponding output of the logic gate
are unaffected. But when the noise level becomes large enough and a noise spike causes the
HIGH voltage level to drop below this minimum level, the logic gate may interpret this spike as
a LOW level input and switch the output accordingly producing a false output switching. Then in
order for the logic gate not to be affected by noise it must be able to tolerate a certain amount of
unwanted noise on its input without changing the state of its output.

Simple Basic Digital Logic Gates

Simple digital logic gates can be made by combining transistors, diodes and resistors with a
simple example of a Diode-Resistor Logic (DRL) AND gate and a Diode-Transistor Logic
(DTL) NAND gate given below.

The simple 2-input Diode-Resistor AND gate can be converted into a NAND gate by the addition
of a single transistor inverting (NOT) stage. Using discrete components such as diodes, resistors
and transistors to make digital logic gate circuits are not used in practical commercially available
logic ICs as these circuits suffer from propagation delay or gate delay and also power loss due to
the pull-up resistors.
Another disadvantage of diode-resistor logic is that there is no Fan-out facility which is the
ability of a single output to drive many inputs of the next stages. Also this type of design does
not turn fully OFF as a Logic 0 produces an output voltage of 0.6v (diode voltage drop), so
the following TTL and CMOS circuit designs are used instead.

Basic TTL Logic Gates

The simple Diode-Resistor AND gate above uses separate diodes for its inputs, one for each
input. As a transistor is made up off two diode circuits connected together representing an NPN
or a PNP device, the input diodes of the DTL circuit can be replaced by one single NPN
transistor with multiple emitter inputs as shown.

2-input NAND Gate

As the NAND gate contains a single stage inverting NPN transistor circuit (TR ) an output logic
2

level 1 atQ is only present when both the emitters of TR are connected to logic level 0 or
1

ground allowing base current to pass through the PN junctions of the emitter and not the
collector. The multiple emitters of TR are connected as inputs thus producing a NAND gate
1

function.
In standard TTL logic gates, the transistors operate either completely in the cut off region, or
else completely in the saturated region, Transistor as a Switch type operation.

Emitter-Coupled Digital Logic Gate

Emitter Coupled Logic or ECL is another type of digital logic gate that uses bipolar transistor
logic where the transistors are not operated in the saturation region, as they are with the standard
TTL digital logic gate. Instead the input and output circuits are push-pull connected transistors
with the supply voltage negative with respect to ground.

This has the effect of increasing the speed of operation of the emitter coupled logic gates up to
the Gigahertz range compared with the standard TTL types, but noise has a greater effect in ECL
logic, because the unsaturated transistors operate within their active region and amplify as well
as switch signals.

The 74 Sub-families of Integrated Circuits

With improvements in the circuit design to take account of propagation delays, current
consumption, fan-in and fan-out requirements etc, this type of TTL bipolar transistor technology
forms the basis of the prefixed 74 family of digital logic ICs, such as the 7400 Quad 2input AND gate, or the 7402 Quad 2-input OR gate, etc.
Sub-families of the 74xx series ICs are available relating to the different technologies used to
fabricate the gates and they are denoted by the letters in between the 74 designation and the
device number. There are a number of TTL sub-families available that provide a wide range of
switching speeds and power consumption such as the 74L00 or 74ALS00 AND gate, were the
L stands for Low-power TTL and the ALS stands for Advanced Low-power Schottky
TTL and these are listed below.

74xx or 74Nxx: Standard TTL These devices are the original TTL family of
logic gates introduced in the early 70s. They have a propagation delay of
about 10ns and a power consumption of about 10mW. Supply voltage range:
4.75 to 5.25v

74Lxx: Low Power TTL Power consumption was improved over standard
types by increasing the number of internal resistances but at the cost of a
reduction in switching speed. Supply voltage range: 4.75 to 5.25v

74Hxx: High Speed TTL Switching speed was improved by reducing the
number of internal resistances. This also increased the power consumption.
Supply voltage range: 4.75 to 5.25v

74Sxx: Schottky TTL Schottky technology is used to improve input

impedance, switching speed and power consumption (2mW) compared to the
74Lxx and 74Hxx types. Supply voltage range: 4.75 to 5.25v

74LSxx: Low Power Schottky TTL Same as 74Sxx types but with increased
internal resistances to improve power consumption. Supply voltage range:
4.75 to 5.25v

74ASxx: Advanced Schottky TTL Improved design over 74Sxx Schottky

types optimised to increase switching speed at the expense of power
consumption of about 22mW. Supply voltage range: 4.5 to 5.5v

74ALSxx: Advanced Low Power Schottky TTL Lower power consumption of

about 1mW and higher switching speed of 4nS compared to 74LSxx types.
Supply voltage range: 4.5 to 5.5v

74HCxx: High Speed CMOS CMOS technology and transistors to reduce

power consumption of less than 1uA with CMOS compatible inputs. Supply
voltage range: 4.5 to 5.5v

74HCTxx: High Speed CMOS CMOS technology and transistors to reduce

power consumption of less than 1uA but has increased propagation delay of
about 16nS due to the TTL compatible inputs. Supply voltage range: 4.5 to
5.5v

Basic CMOS Digital Logic Gate

One of the main disadvantages with the TTL digital logic gate series is that the logic gates are
based on bipolar transistor logic technology and as transistors are current operated devices, they
consume large amounts of power from a fixed +5 volt power supply.
Also, TTL bipolar transistor gates have a limited operating speed when switching from an OFF
state to an ON state and vice-versa called the gate or propagation delay. To overcome
these limitations complementary MOS called CMOS
(Complementary Metal Oxide Semiconductor) logic gates which use Field Effect Transistors
or FETs were developed.
As these gates use both P-channel and N-channel MOSFETs as their input device, at quiescent
conditions with no switching, the power consumption of CMOS gates is almost zero, (1 to 2uA)
making them ideal for use in low-power battery circuits and with switching speeds upwards of
100MHz for use in high frequency timing and computer circuits.

2-input NAND Gate

This CMOS gate example contains 3 N-channel MOSFETs, one for each input FET1 and
FET2 and one for the output FET3. When both the inputs A and B are at logic level 0, FET1 and
FET2 are both switched OFF giving an output logic 1 from the source of FET3.
When one or both of the inputs are at logic level 1 current flows through the corresponding
FET giving an output state at Q equivalent to logic 0, thus producing a NAND gate function.
Improvements in the circuit design with regards to switching speed, low power consumption and
improved propagation delays has resulted in the standard CMOS 4000 CD family of logic ICs
being developed that complement the TTL range.
As with the standard TTL digital logic gates, all the major digital logic gates and devices are
available in the CMOS package such as the CD4011, a Quad 2-input NAND gate, or the CD4001,
a Quad 2-input NOR gate along with all their sub-families.
Like TTL logic, complementary MOS (CMOS) circuits take advantage of the fact that both Nchannel and P-channel devices can be fabricated together on the same substrate material to form
various logic functions.
One of the main disadvantage with the CMOS range of ICs compared to their equivalent TTL
types is that they are easily damaged by static electricity. Also unlike TTL logic gates that

operate on single +5V voltages for both their input and output levels, CMOS digital logic gates
operate on a single supply voltage of between +3 and +18 volts.
Common CMOS Sub-families include:

4000B Series: Standard CMOS These devices are the original Buffered
CMOS family of logic gates introduced in the early 70s and operate from a
supply voltage of 3.0 to 18v d.c.

74C Series: 5v CMOS These devices are pin-compatible with standard 5v

TTL devices as their logic switching is implemented in CMOS but with TTLcompatible inputs. They operate from a supply voltage of 3.0 to 18v d.c.

Note that CMOS logic gates and devices are static sensitive, so always take the appropriate
precautions of working on antistatic mats or grounded workbenches, wearing an antistatic
wristband and not removing a part from its antistatic packaging until required.
In the next tutorial about Digital Logic Gates, we will look at the digital Logic AND
Gatefunction as used in both TTL and CMOS logic circuits as well as its Boolean Algebra
definition and truth tables.

Summary of Transducers

Below is a summary of transducers and sensors we have looked at in this section along with a list
of the main characteristics associated with Transducers, Sensors and Actuators.

Input Devices or Sensors

Sensors are Input devices which convert one type of energy or quantity
into an electrical analogue signal.

The most common forms of sensors are those that detect Position,
Temperature, Light, Pressure and Velocity.

The simplest of all input devices is the switch or push button.

Some sensors called Self-generating sensors generate output voltages or

currents relative to the quantity being measured, such as thermocouples and
photo-voltaic solar cells and their output bandwidth equals that of the quantity
being measured.

Some sensors called Modulating sensors change their physical properties,

such as inductance or resistance relative to the quantity being measured such
as inductive sensors, LDRs and potentiometers and need to be biased to
provide an output voltage or current.

Not all sensors produce a straight linear output and linearisation circuitry may
be required.

Signal conditioning may also be required to provide compatibility between the

sensors low output signal and the detection or amplification circuitry.

Some form of amplification is generally required in order to produce a suitable

electrical signal which is capable of being measured.

Instrumentation type Operational Amplifiers are ideal for signal processing and
conditioning of a sensors output signal.

Output Devices or Actuators

Output devices are commonly called Actuators and the simplest of all
actuators is the lamp.

Relays provide good separation of the low voltage electronic control signals
and the high power load circuits.

Relays provide separation of DC and AC circuits (i.e. switching an alternating

current path via a DC control signal or vice versa).

Solid state relays have fast response, long life, no moving parts with no
contact arcing or bounce but require heat sinking.

Solenoids are electromagnetic devices that are used mainly to open or close
pneumatic valves, security doors and robot type applications. They are
inductive loads so a flywheel diode is required.

Permanent magnet DC motors are cheaper and smaller than equivalent wound
motors as they have no field winding.

Transistor switches can be used as simple ON/OFF unipolar controllers and

pulse width speed control is obtained by varying the duty cycle of the control
signal.

Bi-directional motor control can be achieved by connecting the motor inside a

transistor H-bridge.

Stepper

motors

can

be

controlled

directly

using

transistor

switching

techniques.

The speed and position of a stepper motor can be accurately controlled using
pulses so can operate in an Open-loop mode.

Microphones are input sound transducers that can detect acoustic waves
either in the Infra sound, Audible sound or Ultrasound range generated by a
mechanical vibration.

Loudspeakers, buzzers, horns and sounders are output devices and are used
to produce an output sound, note or alarm.