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Modelsim SE 10.0c Tutorial

1. The document provides instructions for using Modelsim software to design and simulate a basic OR gate circuit. 2. It instructs the user to create a project folder, design an OR3 gate entity with ports a, b, c as inputs and z as the output, and write a VHDL code for the OR3 gate architecture that assigns z to the OR of a, b, and c. 3. It then guides the user through compiling the code, simulating the design by applying inputs to the ports and observing the output, and modifying the code to add a delay to the output.

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ZavierWang
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45 views

Modelsim SE 10.0c Tutorial

1. The document provides instructions for using Modelsim software to design and simulate a basic OR gate circuit. 2. It instructs the user to create a project folder, design an OR3 gate entity with ports a, b, c as inputs and z as the output, and write a VHDL code for the OR3 gate architecture that assigns z to the OR of a, b, and c. 3. It then guides the user through compiling the code, simulating the design by applying inputs to the ports and observing the output, and modifying the code to add a delay to the output.

Uploaded by

ZavierWang
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Modelsim SE 10.

0c Tutorial
1. Log in using your Drexel email id and password.
2. Go to My Computer and create a new folder Z:\C302\examples
(Z may be your USB flash drive or Desktop dont use C drive which may need
administrator privileges)
3. Open Modelsim by:
Start -> All Programs -> Modelsim 10.4 -> ModelSim
Close the Jump Start popup window that opens
4. Click File -> New -> Project and browse to Z:\C302\examples
5. Give the name tutorial to the project and save in the folder Z:\C302\examples
6. In the small window which opens, click Create New File and give it the name
or3.vhd
7. Open the Editor window for the file by double clicking the file name and type the
following code and save it
entity or3 is
port(a,b,c:in bit;z:out bit);
end or3;
architecture df of or3 is
begin
z <= a or b or c;
end df;
8. Click Compile -> Compile Selected to compile the source code and watch for errors at
the bottom of the main window. If there are no errors , a message in green that
compilation was successful appears. If there are errors, go back to the Editor and fix
them The object file created by the compiler is automatically saved in a folder called
work.
9. Click Simulate -> Start Simulation. Open the work folder by clicking on its + sign
select or3 and click OK. Objects window opens where you will see the inputs
and output a,b,c,z all initialized to 0
10. Select or3 in the sim tab of workspace window
Then Click Add -> To Wave -> All items in region to open the waveform window
for the above signals
11. In the Signal (aka Object) Window or in the Wave Window, right click a , click
Force and enter the value 1 for a
12. Run the simulation for 100 ns by clicking on the button immediately to the right
of 100 ns (above the Wave window). You will see the output z turning to 1.
both in the Objects window and the Wave window.
13. Run other test cases by forcing a/b/c as required and confirm the correct output
z in each case. The Signal window shows only the current inputs/output. The
Wave window retains the history of all the test cases as waveforms.
14. Click Simulate -> End Simulation and edit the code to include a gate delay thus:

z <= a or b or c after 10 ns;


Repeat steps 8 13 and observe the delayed output in the wave window

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