FH5780897NP S

UnitedStates
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INDEX OF CLAIMS
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United States Patent
[I91
Krakauer
[a]
[54] ESD PROTECTION CLAMP FOR MIXED

VOLTAGE UO STAGES USING NMOS
TRANSISTORS
[75] Inventor:
David Benjamin Krakauer.

Cambridge. Mass.
[73] Assignee: Digital Equipment Corporation.

Maynard. Mass.
[21] AppL No.: 555,463

[22] Filed:
Nov. 13, 1995
[511 Int. CL6 .....................................................

HOlL 29R6
[52] U.S. C1. .......................... 257/368; 257/358;257/368;
2571360;257/355
[58] Field of Search ..................................... 257/360.358.
257/368.363. 486,606. 603. 355. 481.
551;327/94,100. 112. 375
[561
References Cited
U.S. PATENT DOCUMENTS
4,630,162
5,477,078
5,594,264
[ill
12/1986 Bell et al. ................................. 361/56

12/1995 Beige1 et al.
257/C&6
2571355
1/1997 Beigeletal.
...........................
...........................
Primary Emminer-Carl W. Whitehead
Patent Number:
Date of Patent:
5,780,897
Jul. 14, 1998
Attorney, Agent, or F i r 4 h r i s t o p h e r J. Cianciolo
ABSTRACT
1571
An electrostatic discharge protection device for protecting a

mixed voltage integrated circuit against damage is provided
which includes at least one pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor
pair includes a first transistor. having a drain region coupled
to an UO stage of the mixed voltage integrated circuit. and
a gate region coupled to the mixed voltage integrated
circuit's low p w e r supply. The protection device also
includes a second NMOS transistor. merged into the same
active area as the first transistor. having a gate region and
source region coupled to the ground plane of the mixed
voltage integrated circuit. The drain region of the second
transistor and the source region of the first transistor is
constructed by a shared NMOS diffusion region. This shared
diffusion region also constructs the common node coupling
the source region of the first transistor to the drain region of
the second The shared diffusion area is a further benefit of
the invention because its length controls the trigger voltage
and the holding voltage of each cascode configured transistor pair. This electrostatic discharge protection device can be
used either as a self protecting pull-down portion of a mixed
voltage VO stage or. in a further aspect of the present
invention. as a separate electrostatic discharge clamp.
9 Claims, 11 Drawing Sheet.
I
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UO PAD
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A
DRAIN
CURRENT
84
SNAP-BACK REGION
90
PUNCH-THROUGH
I
TRIGGER
VOLTAGE
HOLDING
VOLTAGE
\ 92
Figure 8
+
\ 86
DRAIN TO
SOURCE
VOLTAGE
4
DRAIN
CURRENT
84
HOLDING
VOLTAGE
Figure 9
U S , Patent
Jul. 14, 1998
Sheet 10 of 11
U.S. Patent
Sheet 11 of 11
- - - - - - - -I
r-------*
I
I
1
I
I
I
I
I--
I
L 0 122
I
f
i
GATE 1
I
SHARED
DIFFUSION
DRAIN
SOURCE
DRAIN
.------------
r---------__----
SOURCE
I
SHARED
DIFFUSION
I
1
SOURCE
1
I
SHARED
DlFFUSION
- - - _DRAIN
_--------GATE 1
SOURCE
I
I
I
I
. - _ - - - - - - - - - - - - -
i
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L 0 124
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DRAIN
GATE 1
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--I
GATE 2
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1
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DRAIN
GATE 2
SOURCE
I-,-,------------J
Figure I I
1
I,0 126
I
I
1
I
. II
1
5,780,897
1
ing diode conducts. Jn this circumstance. the conducting

diode shunts the current either to the supply voltage plane or
to the ground plane to protect the transistors of the I/O
driver.
BACKGROUND O F THE INVENTION
5
The problem with using this configuration in a mixed
voltage integrated circuit having only a low power supply is
This invention relates generally to integrated circuits and
that during normal operation. when the voltage at the I/O
more specifically to electrostatic discharge protection of
pad rises to the high level, the diode will conduct and clamp
mixed voltage integrated circuits (IC's).
the pad to the low power Supply voltage. In this situation. the
As it is known in the art. integrated circuits, and hence
computer systems, were historically designed to operate lo high level signal and the low level power supply are essenwith a 5 volt power supply. However. the rise of the laptop
t i d y shorted together which is unacceptable because the
and the portable
high level signal will be prevented from reaching its proper
computer. the hand held video g-e,
telephone markets obviated the need for increased perforvoltage. If the high level signal does not reach its appropriate
mance and decreased power consumption. The integrated
voltage level. functional or timing errors could occur in
circuit designers were able to meet these challenges by l 5 integrated circuits coupled to the mixed voltage IC.
reducing the geometry of the transistors which make up the
Accordingly. this form of ESD ~ r o t w ~ ois nnot acceptable
integrated circuits used in the above mentioned industries.
for mixed voltage I/o padsSince a transistor's physical size limits the voltage that the
Another common ESD protection strategy is to provide a
device can withstand before being damaged. the smaller
single NMOS transistor pulldown to ground for each L'0
geometry transistors were not capable of surviving the 5 volt 20 driver. This transistor is designed to safely protect the driver
signal levels. As a result, lower voltage standards were
by shunting the ESD current to electrical ground by operintroduced.
ating in a low impedance mode called snap-back However.
The lower voltage standards were not immediately
in advanced CMOS processes. thin gate oxides and short
required in all facets of the electronic industq and therefore
~hannellengths preclude the use of a single NMOS pullwere not fully adopted. As engineers migrated to using the 25 down transistor in the 110 driver due to normal operation
new standards. devices designed for use with the old stanreliability phenomena such as hot carriers and time &pendards were frequently interconnected in the s&sign
dent dielectric breakdown. In these phenomena a strong
with those designed for the new standards. Because of these
field. generated from a high level Power supply. across the
mixed standard systems. integrated circuit designers needed
short channel and Ulin oxide unacceptably degrades the
to ensure that devices manufactured to the new. lower 30 NMOS pulldown transistor over its lifetime.
To avoid the single pulldown transistor problem described
voltage standards would not be adversely harmed if used in
5 volt applications. These voltage tolerant devices are
above. the 110 driver puLldown in mixed voltage CMOS
referred to as mixed voltage IC's.
processes is typically designed as a cascode configuration of
One of the main problems with integrated circuits has 35 two distinct and independently disposed NMOS transistors
been their extreme sensitivity to electrostatic discharge.
which serve as a mechanism to reduce the field strength
Electrostatic discharge W D j is a high voltage electric pulse
across the channel and the oxide during normal operation.
of extremely short duration which is usually caused by static
The cascode configuration is created by connecting a comelectricity. When a transistor experiences a voltage of this
mon node between the source of a first transistor and the
magnitude. the oxide within the transistor breaks down and 40 drain of a second The gate of the first transistor is tied to the
the device is damaged. Consequently. the inputloutput CI/Oj
supply voltage while the gate and source of the second
transistor are tied to ground. The VO pad and the pull-up
pads of a mixed voltage integrated circuit need to be
portion of the
driver are c o ~ e d e to
d the drain of the first
protected such that the ESD voltage shock does not reach.
transistor. In normal mixed signal operating modes. the
nor destroy. their oxide Layas.
because the voltage at the common ride
There are two types of mixed voltage Kc's which employ 45 protection oc-s
different methods of normaloperating mode proteaion.
is limited to the supply voltage minus the threshold voltage
m e s e two types present different challenges in protecting
of the transistor. Because of this voltage limitation. voltages
against electrostatic discharge. ~n
the first type of mixed
across the oxides and channels of both devices are Limited to
voltage KC. the core logic area operates at one voltage level
Safe levelsAlthough this configuration limits voltages to safe levels
while the 110 area operates at a different, usually higher. 50
voltage. This type of IC is provided with two power supplies
in normal operating modes. it is inadequate for ESD protection because the transistors are laid-out as separate and
i.e. a low p w e r supply for the core logic area and a high
distinct devices. During an ESD event. snap-back must
power supply for the I/O area. In the second type of mixed
occur in both of the transistors before the current can be
voltage IC. only a low power supply is provided and the
external 110 area is designed to be tolerant of. and protected 55 shunted to ground. Since snapback for two independent
from. high level signals. It is this latter case which presents
devices results in a much higher voltage being presented to
the driver. this can both exceed the dielectric breakdown of
the most difficulty for providing robust ESD protection as
will be shown below.
the oxide and increase the power density at the drain
junction. Both situations are unacceptable since they can
A common fa
of ESD protedion is the use of a pair of
diodes. Two diodes are formed at the 110 pad where one is 60 result in damage to the integrated circuit.
connected to ground and the other to the supply voltage. The
Furhemore. in this cascode arrangement. in order to
anode of a first diode is connected to the UO pad while the
tailor the circuit to have a sufficiently high trigger voltage
cathode is connected to the supply voltage. The cathmie of
and low holding voltage. the channel length of each device
a second diode is c o ~ e c t e dto the same U 0 pad while its
must be increased separately. Increasing the channel length
anode is connected to ground. During an ESD event. when 65 of each device has the undesired effects of increasing
the voltage on the I/O pad reaches a value higher than the
capacitance. reducing the drive strength. and increasing the
supply voltage or lower than ground level. the correspondchannel leakage current of the driver.
ESD PROTECTION CLAMP FOR MIXED

VOLTAGE VO STAGES USING NMOS
TRANSISTORS
A protection device is needed which is acceptable for use

in a mixed voltage integrated circuit during normal operating modes as well as during ESI) events.
SUMMARY OF THE: INVENTION

In accordance with the present invention, an electrostatic
discharge protection device for protecting a mixed voltage
integrated circuit against damage includes at least one pair
of NMOS transistors connected in a cascode configuration.
Each NMOS transistor pair includes a first transistor. having
a drain region coupled to an I/O stage of the mixed voltage
integrated circuit. and a gate region coupled to the mixed
voltage integrated circuit's low power supply.
The protection device also includes a second NMOS
transistor. merged into the same active area as the first
transistor. having a gate region and source region coupled to
the ground plane of the mixed voltage integrated circuit. The
drain region of the second transistor and the source region of
the first transistor is constructed by a shared NMOS diffusion region. This shared diffusion region also constructs the
common node coupling the source region of the first transistor to the drain region of the second.
The shared diffusion area is a futher benefit of the
invention because its length controls the trigger voltage and
the holding voltage of each cascode configured transistor
pair.
This electrostatic discharge protection device can be used
either as a self protecting pull-down portion of a mixed
voltage V0 stage or. in a further aspect of the present
invention. as a separate electrostatic discharge clamp. In
addition. a further advantage of this arrangement is that the
length of the shared diffusion region of the two transistors
may be altered to tailor both the trigger voltage and the
holding voltage of both of the transistors in the cascode
configured pair.
In accordance with another aspect of the present
invention. a method for protecting a mixed voltage integrated cicuit from damage caused by electrostatic discharge
includes the steps of disposing at least one pair of cascode
configured NMOS transistors in the same active area in a
mixed voltage integrated circuit. and constructing a shared
dilTusion region which constructs the drain region of the first
transistor and the source region of the second transistor of
each pair as well as couples each pair of transistors.
In accordance with yet another aspect of the present
invention. a layout of a cascode electrostatic discharge
protection device includes an active area constructed i f
diffused PMOS material. and at least one cascode configuration of NMOS transistors. In each pair of transistors. two
polysilicon regions construct the
regions of the NMOS
transistors. A first NMOS reEion is dis~osedin the active
area to construct the drain Gf the firs; NMOS transistor.
Likewise. a second NMOS region constructs the source of
the first NMOS transistor as well as the drain of the second
NMOS transistor. The source of the second NMOS transistar
is then constructed by a third NMOS region, also disposed
in the same active area.
With such an arrangement. a protection device is provided
that is acceptable for use in a mixed voltage IC during
normal operating modes as well as during ESD events.
BRIEF DESCRIPTION OF THI3 DRAWINGS

The foregoing features of thi.3 invention. as well as the
invention itself. may be more Fully understood from the
following detailed description when read in conjunction
with theaccompanying drawings. in which:
FIG. 1 depicts a block diagram of a computer system in

which the present invention may be applied;
FIG. 2 depicts an electrostatic discharge protection circuit
coupled to a mixed voltage integrated circuit's input/output
WO) pad;
FIG. 3 depicts a plurality of parallel casco& configured
transistors which may be coupled to the VO pad of FIG. 1;
FIG. 4 depicts the electrostatic discharge protection
device of FIG. 2 employed as the pull-down stage of an VO
driver;
FIG. 5 depicts the depletion regions surrounding the drain
and source in a cross section view of an NMOS transistor
comprising the electrostatic discharge protection circuit of
FIG. 2;
FIG. 6 depicts the state of the depletion regions surrounding the drain and source in a aoss section view of an NMOS
transistor comprising the electrostatic discharge protection
circuit of FIG. 2 when Punch-through occurs;
FIG. 7 depicts a cross-section view of the electrostatic
discharge protection device when both NMOS transistors
are in snap-back and the ESD current is being shunted to
ground;
FIG. 8 is a diagram depicting drain current versus the
drain-to-source voltage of the NMOS transistor of FIG. 5;
FIG. 9 depicts the current versus voltage curve of the
NMOS transistor of FIG. 5 superimposed over the operating
curve of a device to be protected from electrostatic discharge;
FIG. 10 depicts a top, or layout. view of the cascode
configured NMOS protection transistors of FIG. 2; and
FIG. 11 depicts a top view of a plurality of cascode
configured NMOS protection transistors comected in parallel as shown in FIG. 3. disposed in a mixed voltage
integrated circuit.
DESCRIF'TION OF A PREFERRED
EMBODIMENT
Refemng to FIG. 1. a computer system 1 is shown to
include a central processing unit (CPU)2. a memory system
3, and an input/output (VO) system 4. interconnected by a
system bus 5. Each portion of the computer system 1 further
comprises many coupled integrated circuits tk,6b,dc. some
of which run on a 5 volt power supply level and some of
which run on lower voltage power supply levels. The present
invention protects each of these integrated circuits from
electrostatic discharge damage in such a way that does not
hamper its normal operation.
Refemng to FIG. 2. an electrostatic discharge (ESD)
protection &vice 10 is shown coupled to a mixed voltage
integrated circuit's 6 inputioutput (VO) pad 11. During the
occurrence of an ESD event, the circuitry 12 coupled to the
V0 pad 12 will be protected against damage based on the
ability of the protection device 10 to limit voltage and shunt
current to electrical ground 14.
The ESD protection device is based on a cascode configuration of NMOS transistors whose common nodes are
formed by a shared difhsion 18. By shared diffusion it is
meant that the same m s i o n of NMOS material constructing the source region 20 of the first transistor 22 also
constructs the drain region 24 of the second transistor 26.
The arrangement of the present invention is in contrast to the
usual layout of a casco& structure where the transistors are
laid-out as distinct &vices or. in the case of a multi-fingered
device. where the devices are merged into the same active
area and only one finger shares the common diffusion.
5,780.897
5
The cascc.de configuration of the present invention is

diate area. Therefore if a metal contact is placed too close to
superior to that of the prior art in part because of its inherent
the hot spot. i t will melt and damage the device.
flexibility. The cascc.de configuration with shared difFusions
Accordingly, to overcome this problem in the current h e n can be used as a self protecting pulldown stage of a mixed
tion the silicik is preferably blocked from being deposited
voltage I/O driver. or as a separate ESD voltage protection 5 over certain sections of the drain and source. As a result. the
clamp. The device is laid-out having a shared diffusion 18
contacts are pushed farther from the gate and farther &om
which includes a common node constructing both the source
the hot spot. A greater degree of heat is then required for the
contacts to reach the melting point. By blocking the silicide
20 of a f i s t NMOS transistor (NMOST) 22 and the drain 24
and LDD, the ESD protection &vice is more reliable and
of a second transistor 26. Both transistors are merged into
less likely to become damaged during an ESD event.
the same active area. The gate 28 of the first NMOST is tied
In each of the NMOST cascode configurations of FIGS. 2,
to the low supply voltage (Vdd) while the gate 30 and source
3, and 4. snapbackmust occur in the device before the ESD
32 of the second NMOST are tied to ground 14. The UO pad
current can be shunted to ground The term snapback refers
12 and pull-up portion of the VO driver are connected to the
to an operating region of MOS transistors. Referring now to
drain 34 of the first transistor 22.
appreciate ,5 FIG. 5 a cross section view of an NMOS transistor 50 used
A person having
skill in the art
in the present invelltion is shown. The NMOS transistor 50
that the number of cascade configured transistors 10 is not
com~risesa gate region 52. a source region 54 and a drain
limited to a single pair such as depicted in FIG. 2. or
region 56 coupled to a PMOS region 58.
example. as shown in FIG. 3. an ESD protection device 46
To understand the phenomena of snapback first consider
is shown to include a plurality of cascode configured NMOS
transistor pairs 4 & 4 x sharing a common active area, and 20 that the gate 52 and source 54 regions of the NMOST 50 are
connected in parallel. Although only three pairs of
coupled to ground 14 and that a voltage source is coupled to
transistors, 442, 44b, and eLy are shown. it should be
the drain region 56. Initially. this configuration will not
conduct current from drain-to-source because there is no
understcmd that the number of cascode pairs are design
forward biased threshold voltage imposed across the gatedependent. That is. the number of parallel cascode configurations depends upon the amount of current that each pair of 25 to-source junction 60. As the voltage coupled to the drain 56
NMOS transistms can carry and the maximum current that
is increased. a held 62 is built up in the PMOS region 58
the devices are likely to experience during normal operation
around the drain 56 and source 54. This is called the
and electrostatic discharge.
depletion region 62. and it increases proportionately with the
Referring again to FIG. 2. the cascode configured device
inmeasing voltage on the drain 56Refemng now to FIG. 6 an NMOS transistor 50. similar
10 is protected during normal operation because the voltage 30
to that of FIG. 5. along with associated source and drain
at each shared diEusion 18 is limited to the supply voltage
depletion regions 62 are shown. In the NMOST 50 of FIG.
(Vdd) minus the threshold voltage of the NMOS transistor.
6. it can be seen that the depletion regions 62 of the source
Because of this limitation, voltages across the oxides a d
54 and drain 56 are merged. Such an event occurs in the
channels of each part of the &vice are restricted to safe
levels during normal operation while. during an ESD event. 35 fouowing manner. when the drain voltage reaches a certain
the cascode configuration provides a path for the S D
value. referred to as the trigger voltage, the two depletion
culrent to reach electrical ground 14. By shunting the IZSD
regions 62 intasect with each other. This action. called
current to ground 14 via transistors 22 and 26. an UO driver
Punch-through. allows a small number of electrons 66 to
stage connected to the drain 34 of M O S T device 22 is
pass from source 54 to drain 56 through the PMOS region
protected from damaging voltage and current levels. Refer- 4 58. The action of the electron 66 jumping into the NMOS
ring now to FIG. 4. an I/O driver stage 48 is shown having
drain region 56 causes a collision with the silicon lattice
kmown as impact ionization. During impact ionization. an
a pull-up stage 480 coupled to the cascc.de configured
NMOS transistor device 48b of the present invention. The
electron is disengaged from its covalent bond and generates
cascode NMOST device is used as the pulldown stage of the
a space referred to as a hole 68. The hole 68, following the
driver. thus constructing a self protecting VO driver circuit. 45 closest path 70 to a lower potential. passes through the
When the protection device is used as a separate =D
PMOS region 58 and into ekctrical ground 14. Because
there is resistance in the PMOS substrate 58. the current
clamp, as shown in FIG. 2. its robustness can be increased
generated by the migrating hole gives rise to a voltage 72.
by blocking both sficide and LDD. The salicide process
reduces propagation delay in transistors by depositing metal
As the depletion regions 62 grow in strength. more electrons
on top of an existing transistor. LDD involves doping the 50 66 pass from source 54 to drain 58 causing more holes 68 to
Pass through the substrate 58.
drain region closest to the channel lighter than the rest of the
voltage of a
When the voltage 72 exceeds the --on
area. The result is a less abrupt, or more graded, junction
between the drain and channel regions, After the salicide
diode 74. formed by the junction of the NMOS material of
process is complete the propagation time between &vices is
the drain region 56 and the PMOS material 58 of the active
thereafter determined by the characteristics of the metal 55 region, it conducts. Once the diode 74 turns on. a larger hole
used, while the properties of the transistor itself are detercurrent 70 will flow directly from the drain 56 through the
mined by the polysilicon gate's characteristics. The problem
substrate 58 and a larger electron current will flow from
with the salici& process is that it produces a non-uniform
source 54 to drain 56. It should be noted that this flow of
electrons 66 is not n o d channel conduction but rather.
thickness of metal and hence a non-uniform resistance dong
the drain and source areas of the device. Current flows rn happens below the channel. Once the current flow 70 is
started. it will sustain the forward bias voltage 72 on the
unevenly through this non-uniform resistance producing a
diode 74 and only a very small depletion region 62 will be
hot spot where the current flow is the strongest. As the
necessary to allow the current to remain flowing. This
temperature of the hot spot increases, the current flow &o
operating region is referred to as snap-back and is used by
increases. These related effects develop into a self supporting loop referred to as thermal runaway. Thermal runaway 6 5 the device 10 to provide ESD protection.
occurs when most of the current flows through the hot spot.
Refemng now to FIG. 7. a cross section view 80 of the
raising its temperature enough to melt metal in the imrnecasco& configured NMOST device 10 of the present inven-
7
tion is depicted The shared diffusion area 18 constructs the
source 20 of a first transistor 22 and the drain 24 of a second
transistor 26. Once both transistors enter the snap-back
region of operation. a low impedance path 81 from the V 0
pad to electrical ground is formed. ESD current is shunted 5
to ground along this path 81,and the associated device is
protected from damage.
Referring now to FIG. 8,a graph is shown depicting the
drain current 84 versus the drain-to-source voltage 86 of the
typqof NMOS transistor used in the preferred embodiments. 10
D m g an ESD event. the drain-to-source voltage 84 will
increase very rapidly until it reaches the trigger voltage 88.
At this point the transistor will experience punch-through
90. and will clamp the drain-to-source voltage 86. and hence
the coupled IIO driver. to the lower holding voltage 92.
Referring now to FIG.9. the current versus voltage curve l5
94 of a punch-through device is superimposed over the
operating curve % of a transistor to be protected from an
ESD event. Because an ESD event occurs very quickly. the
amount of time that the punch-through transistor takes to
reach the trigger voltage 88.and then to clamp at the holding 20
voltage 92. is very small when cornpared to the time it would
take the same voltage to destroy the transistor's oxide layer.
Therefore. no destruction occurs before the protection circuit clamps the J/0 pad to the holding voltage 88.The curves
depicted in FIG. 9 show that when the transistor clamps the 25
IIO stage to the holding voltage 92. the UO transistor is at an
acceptable level of drain current 84. Therefore no damage to
the U O stage will occur.
Referring now to FIG. 10.a t q >view of the layout 100 of
the cascode configured ESD protection transistors is 30
depicted. The transistors are fabricated as a single device in
the same active area 102. The common node which joins the
two transistors is a shared dilTusion 104which constructs the
source 106 of one transistor and the drain 108 of another. A
critical feature of the ESD protection device is that the 35
bipolar base width 110 of the equivalent transistor. which
determines the trigger voltage 88 and holding voltage 92, is
defined by the distance between the top 1UI and bottom 122
dfisions. Changing this critical distance 110.by changing
the length of the shared diffusion 104 when the device is
laid-out. tailors the trigger voltage 88 and holding voltage 92
to the required values. This is a benefit over having to
increase the channel length of each device separately, which
is required when the transistors are fabricated as independent devices. Increasing the len@h of the shared diffusion 45
104 has the benefits of not increasing the capacitance. not
reducing the drive strength. and not haeasing the channel
leakage current of the driver. In this beneficial manner. the
ESD protection circuit can be tailored to the specific U 0
driver by making the trigger voltage suficiently large so that 50
the devices will not punch-through and enter the snap-back
region during normal operation.
Referring now to FIG. 11. the layout 120 of a parallel
connection of three cascode configurations is depicted
When more than one pair of casc:o& configured transistors 55
are used. they are interleaved rather than simply having one
finger share the common diffusion. In such a configuration
each pair of NMOS transistors will experience a percentage
of the total ESD current flowing through the structure to
ground. It will be appreciated by one with ordinary skill in
the art that increasing the number of cascode amfigurations
will proportionately reduce the amount of current flowing
through each pair of transistors. Therefore, the number of
transistors to be used is unlimited by this method of ESD
protection.
65
Having described a preferred embodiment of the
invention. it will now become apparent to one of ordinary
skill in the art that other embodiments incorporating its

concepts may be used. It is felt. therefore. that this embodiment should not be limited to the disclosed embodiment. but
rather should be limited only by the spirit and scope of the
appended claims.
What is claimed is:
1.An electrostatic discharge protection device for coupling to a mixed voltage integrated circuit to protect said
integrated circuit against damage from electrostatic discharge comprising:
at least one cascode configured transistor pair. each of said
pairs comprising:
a first NMOS transistor having a gate region. a source
region, and a drain region. said drain region coupled to
said mixed voltage integrated circuit. said gate region
coupled to a low power supply of said mixed voltage
integrated circuit;
a second NMOS transistor. merged into the same active
area as said first transistor. having a gate region. a
source region. and a drain region. said gate region and
said source region of said second NMOS transistor
coupled to a ground plane of said mixed voltage
integrated circuit;
a shared difiusion region coupling the source region of
said first NMOS transistor to the drain region of said
second NMOS transistor. said shared diffusion region
constructing the source region of said first NMOS
transistor and constructing said drain region of said
second NMOS transistor.
2. The electrostatic discharge protection device of claim 1
wherein the length of said shared diffusion region controls a
trigger voltage and a holding voltage of said transistor pair.
wherein said electrostatic discharge protection device protects an input stage of said mixed voltage integrated circuit.
wherein said electrostatic discharge protection device protects an output stage of said mixed voltage integrated circuit.
said protection device comprising a pulldown portion of said
output stage of said mixed voltage integrated circuit.
wherein said electrostatic discharge protection device protects an output stage of said mixed voltage integrated circuit,
said protection device comprising a separate protection
clamp.
6.The electrostatic discharge protection device of claim 2
wherein said electrostatic discharge protection device protects an input/output stage of said &ed voltage integrated
circuit. said protection device comprising a pulldown portion of said input/output stage of said mixed voltage integrated circuit.
wherein said electrostatic discharge protection device prtects an input/output stage of said mixed voltage integrated
circuit. said protection &vice comprising a separate protection clamp.
8. A cascode electrostatic discharge protection device
comprising:
an active area constructed of diffused PMOS material;
a first polysilicon region disposed over said active area.
said polysilicon region constructing the gate region of
a first NMOS transistor;
a second polysilicon region disposed over said active area
and parallel to said first polysilicon region, said second
polysilicon region constructing the gate region of a
second NMOS transistor;
5.780.897
10
9
a first NMOS region. disposed in said active area, construtting the drain of said fist NMOS transistor;
a second NMOS region. disposed in said active area,
constructing the source of said first NMOS transistor
and constructing the drain of said second NMOS Wansistor;
a third NMOS region, disposed in said active area,
constructing the source of said second NMOS transistor.
9. A casco& electrostatic discharge protection device
comprising:
an active area constructed of diffused PMOS material;
a plurality of polysilicon regions disposed over said active
area. said plurality of polysilicon regions constructing
lo
the gate regions of a plurality of pairs of NMOS

transistors, each of said pairs of NMOS transistors
comprising:
a first NMOS region. disposed in said active area.
constructing the drain of said first NMOS transistor;
a second NMOS region. disposed i n said active area.
constructing the source of said first NMOS transistor
and conskucting the drain of said second NMOS
transistor;
a third NMOS region. disposed in said active area,
constructing the source of said second NMOS transistor.
* * * * *
PATENT APPLICATION SERIAL NO.
U . S . DEPARTMENT OF COmERCE
PATENT AND TRADEMARK OFFICE
FEE RECORD SHEET
An e l e c t r o s t a t i c % i s c h a r g e p r o t e c t i o n d e v i c e f o r
TP
i n t e g r a t e d c i r c u i t a g a i n s t damage
p r o t e c t i n g a mixed voJ?
Pge
i s p r o v i d e d which i n c l u d e s a t l e a s t one p a i r o f NMOS
t r a n s i s t o r s connected i n a cascode c o n f i g u r a t i o n .
Each NMOS
t r a n s i s t o r p a i r i n c l u d e s a f i r s t t r a n s i s t o r , having a d r a i n
r e g i o n coupled t o an I/O s t a g e o f t h e mixed v o l t a g e i n t e g r a t e d
c i r c u i t , and a g a t e r e g i o n coupled t o t h e mixed v o l t a g e
i n t e g r a t e d c i r c u i t ' s low power supply.
The p r o t e c t i o n d e v i c e
a l s o i n c l u d e s a second NMOS t r a n s i s t o r , merged i n t o t h e same

a c t i v e a r e a a s t h e f i r s t t r a n s i s t o r , having a g a t e r e g i o n and
s o u r c e r e g i o n coupled t o t h e ground p l a n e of t h e mixed v o l t a g e
integrated circuit.
The d r a i n r e g i o n of t h e second t r a n s i s t o r
and t h e s o u r c e r e g i o n o f t h e f i r s t t r a n s i s t o r i s c o n s t r u c t e d
by a s h a r e d NMOS d i f f u s i o n r e g i o n .
This shared d i f f u s i o n
r e g i o n a l s o c o n s t r u c t s t h e common node c o u p l i n g t h e s o u r c e
r e g i o n of t h e f i r s t t r a n s i s t o r t o t h e d r a i n r e g i o n o f t h e
second.
The s h a r e d d i f f u s i o n a r e a i s a f u r t h e r b e n e f i t of t h e
i n v e n t i o n because i t s l e n g t h c o n t r o l s t h e t r i g g e r v o l t a g e and
t h e h o l d i n g v o l t a g e o f each cascode c o n f i g u r e d t r a n s i s t o r
pair.
T h i s e l e c t r o s t a t i c d i s c h a r g e p r o t e c t i o n d e v i c e can be
used e i t h e r a s a s e l f p r o t e c t i n g pull-down p o r t i o n of a mixed

v o l t a g e 1 / 0 s t a g e o r , i n a f u r t h e r a s p e c t of t h e p r e s e n t
i n v e n t i o n , a s a s e p a r a t e e l e c t r o s t a t i c discharge clamp.
BACKGROUND OF THE INVENTION
This invention r e l a t e s generally t o i n t e g r a t e d c i r c u i t s

and more s p e c i f i c a l l y t o e l e c t r o s t a t i c d i s c h a r g e p r o t e c t i o n
of .nixed v o l t a g e i n t e g r a t e d c i r c u i t s ( I C ' s )
A s it i s known i n t h e a r t , i n t e g r a t e d c i r c u i t s , and
hence computer systems, w e r e h i s t o r i c a l l y designed t o o p e r a t e

w i t h a 5 v o l t power supply.
However, t h e r i s e of t h e l a p t o p
computer, t h e hand h e l d video game, and t h e p o r t a b l e telephone

markets o b v i a t e d t h e need f o r i n c r e a s e d performance and
d e c r e a s e d power consumption.
The i n t e g r a t e d c i r c u i t d e s i g n e r s
were able t o m e e t t h e s e c h a l l e n g e s by reducing t h e geometry of

t h e t r a n s i s t o r s which make up t h e i n t e g r a t e d c i r c u i t s used i n
t h e above mentioned i n d u s t r i e s .
Since a t r a n s i s t o r ' s p h y s i c a l
s i z e l i m i t s t h e v o l t a g e t h a t t h e d e v i c e can w i t h s t a n d b e f o r e
b e i n g damaged, t h e s m a l l e r geometry t r a n s i s t o r s were n o t
c a p a b l e of s u r v i v i n g t h e 5 v o l t s i g n a l l e v e l s .
As a result,
lower v o l t a g e s t a n d a r d s were i n t r o d u c e d .
The lower v o l t a g e s t a n d a r d s w e r e not immediately
r e q u i r e d i n a l l f a c e t s of t h e e l e c t r o n i c i n d u s t r y and
t h e r e f o r e were n o t f u l l y adopted.
A s engineers migrated t o
u s i n g t h e new standards, devices designed f o r use with t h e o l d

s t a n d a r d s were f r e q u e n t l y interconnected i n t h e same design
with t h o s e designed f o r t h e new s t a n d a r d s .
5
Because of t h e s e
mixed s t a n d a r d systems, i n t e g r a t e d c i r c u i t d e s i g n e r s needed t o

e n s u r e t h a t devices manufactured t o t h e new, lower v o l t a g e
s t a n d a r d s would not be adversely harmed i f used i n 5 v o l t
applications.
These v o l t a g e t o l e r a n t devices a r e r e f e r r e d t o
a s mixed v o l t a g e I C f s.
10
One of t h e main problems with i n t e g r a t e d c i r c u i t s has

been t h e i r extreme s e n s i t i v i t y t o e l e c t r o s t a t i c d i s c h a r g e .
E l e c t r o s t a t i c discharge (ESD) i s a high v o l t a g e e l e c t r i c p u l s e
of extremely s h o r t d u r a t i o n which i s u s u a l l y caused by s t a t i c
electricity.
15
When a t r a n s i s t o r experiences a v o l t a g e of t h i s
magnitude, t h e oxide within t h e t r a n s i s t o r breaks down and t h e

device i s damaged.
Consequently, t h e i n p u t / o u t p u t
(I/O)
pads
of a mixed v o l t a g e i n t e g r a t e d c i r c u i t need t o be p r o t e c t e d
such t h a t t h e ESD v o l t a g e shock does not reach, nor d e s t r o y ,
t h e i r oxide l a y e r s .
20
There a r e two t y p e s of mixed v o l t a g e I C f s which employ

d i f f e r e n t methods of normal o p e r a t i n g mode p r o t e c t i o n .
These
two t y p e s p r e s e n t d i f f e r e n t challenges i n p r o t e c t i n g a g a i n s t
e l e c t r o s t a t i c discharge.
IC,
I n t h e f i r s t t y p e of mixed v o l t a g e
t h e c o r e l o g i c a r e a o p e r a t e s a t one v o l t a g e l e v e l while
t h e 1/0 area operates a t a d i f f e r e n t , usually higher, voltage.

This t y p e of I C i s provided with two power s u p p l i e s i . e . a
5
low power supply f o r t h e c o r e l o g i c a r e a and a high power

supply f o r t h e 1 / 0 a r e a .
IC,
I n t h e second t y p e of mixed v o l t a g e
only a low power supply i s provided and t h e e x t e r n a l 1 / 0
a r e a i s designed t o be t o l e r a n t o f , and p r o t e c t e d from, high

level signals.
10
I t i s t h i s l a t t e r c a s e which p r e s e n t s t h e most
d i f f i c u l t y f o r providing robust ESD p r o t e c t i o n a s w i l l be

shown below.
A common form of ESD p r o t e c t i o n i s t h e use of a p a i r of
diodes.
Two diodes a r e formed a t t h e 1 / 0 pad where one i s
connected t o ground and t h e o t h e r t o t h e supply v o l t a g e .

15
The
anode of a f i r s t diode i s connected t o t h e 1 / 0 pad while t h e

cathode i s connected t o t h e supply v o l t a g e .
The cathode of a
second diode i s connected t o t h e same I / O pad while i t s anode
i s connected t o ground.
During an ESD event, when t h e v o l t a g e
on t h e 1 / 0 pad reaches a value h i g h e r t h a n t h e supply v o l t a g e

20
o r lower t h a n ground l e v e l , t h e corresponding diode conducts.

I n t h i s circumstance, t h e conducting diode shunts t h e c u r r e n t
e i t h e r t o t h e supply v o l t a g e plane o r t o t h e ground plane t o

p r o t e c t t h e t r a n s i s t o r s of t h e 1 / 0 d r i v e r .
The problem with using t h i s c o n f i g u r a t i o n i n a mixed
v o l t a g e i n t e g r a t e d c i r c u i t having only a low power supply i s
t h a t d u r i n g normal o p e r a t i o n , when t h e v o l t a g e a t t h e 1 / 0 pad
r i s e s t o t h e high l e v e l , t h e diode w i l l conduct and clamp t h e
pa?&t o t h e low power supply v o l t a g e .
In t h i s situation, t h e
high l e v e l s i g n a l and t h e low l e v e l power supply a r e

e s s e n t i a l l y s h o r t e d t o g e t h e r which i s unacceptable because t h e
high l e v e l s i g n a l w i l l be prevented from reaching i t s proper
voltage.
I f t h e high l e v e l s i g n a l does not reach i t s
a p p r o p r i a t e v o l t a g e l e v e l , f u n c t i o n a l o r timing e r r o r s could
occur i n i n t e g r a t e d c i r c u i t s coupled t o t h e mixed v o l t a g e I C .
Accordingly, t h i s form of ESD p r o t e c t i o n i s not acceptable f o r
mixed v o l t a g e 1 / 0 pads.
Another common ESD p r o t e c t i o n s t r a t e g y i s t o provide a
s i n g l e NMOS t r a n s i s t o r pulldown t o ground f o r each 1 / 0 d r i v e r .
This t r a n s i s t o r i s designed t o s a f e l y p r o t e c t t h e d r i v e r by
s h u n t i n g t h e ESD c u r r e n t t o e l e c t r i c a l ground by o p e r a t i n g i n
a low impedance mode c a l l e d snap-back.
However, i n advanced
CMOS p r o c e s s e s , t h i n g a t e oxides and s h o r t channel l e n g t h s

p r e c l u d e t h e use of a s i n g l e NMOS pulldown t r a n s i s t o r i n t h e
I/O
d r i v e r due t o normal o p e r a t i o n r e l i a b i l i t y phenomena such
a s hot c a r r i e r s and time dependent d i e l e c t r i c breakdown.
In
t h e s e phenomena a s t r o n g f i e l d , generated from a high l e v e l

power supply, a c r o s s t h e s h o r t channel and t h i n oxide
5
unacceptably degrades t h e NMOS pulldown t r a n s i s t o r over i t s

lifetime.
To avoid t h e s i n g l e pulldown t r a n s i s t o r problem
d e s c r i b e d above, t h e 1/0 d r i v e r pulldown i n mixed v o l t a g e CMOS
p r o c e s s e s i s t y p i c a l l y designed a s a cascode c o n f i g u r a t i o n of
10
two d i s t i n c t and independently disposed NMOS t r a n s i s t o r s which

s e r v e a s a mechanism t o reduce t h e f i e l d s t r e n g t h a c r o s s t h e
channel and t h e oxide during normal o p e r a t i o n .
The cascode
c o n f i g u r a t i o n i s c r e a t e d by connecting a common node between

t h e source of a f i r s t t r a n s i s t o r and t h e d r a i n of a second.
15
The g a t e of t h e f i r s t t r a n s i s t o r i s t i e d t o t h e supply v o l t a g e
while t h e g a t e and source of t h e second t r a n s i s t o r a r e t i e d t o
ground.
The 1 / 0 pad and t h e pull-up p o r t i o n of t h e 1 / 0 d r i v e r
a r e connected t o t h e d r a i n of t h e f i r s t t r a n s i s t o r .
I n normal
mixed s i g n a l o p e r a t i n g modes, t h e p r o t e c t i o n occurs because

20
t h e v o l t a g e a t t h e common node i s l i m i t e d t o t h e supply

v o l t a g e minus t h e t h r e s h o l d v o l t a g e of t h e t r a n s i s t o r .
Because of t h i s v o l t a g e l i m i t a t i o n , v o l t a g e s a c r o s s t h e oxides
and channels of both devices a r e l i m i t e d t o s a f e l e v e l s .
Although t h i s c o n f i g u r a t i o n l i m i t s v o l t a g e s t o s a f e
l e v e l s i n normal o p e r a t i n g modes, it i s inadequate f o r ESD
5
p r o t e c t i o n because t h e t r a n s i s t o r s a r e l a i d - o u t a s s e p a r a t e
and d i s t i n c t devices.
During an ESD event, snap-back must
occur i n both of t h e t r a n s i s t o r s b e f o r e t h e c u r r e n t can be

shunted t o ground.
Since snap-back f o r two independent
d e v i c e s r e s u l t s i n a much higher v o l t a g e being p r e s e n t e d t o

10
t h e d r i v e r , t h i s can both exceed t h e d i e l e c t r i c breakdown of

t h e oxide and i n c r e a s e t h e power d e n s i t y a t t h e d r a i n
junction.
Both s i t u a t i o n s a r e unacceptable s i n c e t h e y can
r e s u l t i n damage t o t h e i n t e g r a t e d c i r c u i t .
Furthermore, i n t h i s cascode arrangement, i n o r d e r t o
15
t a i l o r t h e c i r c u i t t o have a s u f f i c i e n t l y high t r i g g e r v o l t a g e
and low holding v o l t a g e , t h e channel l e n g t h of each device
must be i n c r e a s e d s e p a r a t e l y . I n c r e a s i n g t h e channel l e n g t h of
each device has t h e undesired e f f e c t s of i n c r e a s i n g
capacitance, reducing t h e d r i v e s t r e n g t h , and i n c r e a s i n g t h e
20
channel leakage c u r r e n t of t h e d r i v e r .
A p r o t e c t i o n device i s needed which i s acceptable f o r
use i n a mixed voltage i n t e g r a t e d c i r c u i t during normal

operating modes a s well a s during ESD events.
SUMMARY O F THE I N V E N T I O N
I n accordance w i t h t h e p r e s e n t i n v e n t i o n , an
e l e c t r o s t a t i c discharge p r o t e c t i o n device f o r p r o t e c t i n g a
mixed v o l t a g e i n t e g r a t e d c i r c u i t a g a i n s t damage i n c l u d e s a t
l e a s t one p a i r of NMOS t r a n s i s t o r s connected i n a cascode
5
configuration.
Each NMOS t r a n s i s t o r p a i r i n c l u d e s a f i r s t
t r a n s i s t o r , having a d r a i n r e g i o n coupled t o an 1 / 0 s t a g e of
t h e mixed v o l t a g e i n t e g r a t e d c i r c u i t , and a g a t e r e g i o n
coupled t o t h e mixed v o l t a g e i n t e g r a t e d c i r c u i t ' s low power
supply
10
The p r o t e c t i o n d e v i c e a l s o i n c l u d e s a second NMOS

t r a n s i s t o r , merged i n t o t h e same a c t i v e a r e a a s t h e f i r s t
t r a n s i s t o r , having a g a t e r e g i o n and s o u r c e r e g i o n coupled t o
t h e ground p l a n e of t h e mixed v o l t a g e i n t e g r a t e d c i r c u i t .
The
d r a i n r e g i o n of t h e second t r a n s i s t o r and t h e s o u r c e r e g i o n of
15
t h e f i r s t t r a n s i s t o r i s c o n s t r u c t e d by a s h a r e d NMOS d i f f u s i o n
region.
This s h a r e d d i f f u s i o n r e g i o n a l s o c o n s t r u c t s t h e
common node coupling t h e source r e g i o n of t h e f i r s t t r a n s i s t o r

t o t h e d r a i n r e g i o n of t h e second.
The s h a r e d d i f f u s i o n a r e a i s a f u r t h e r b e n e f i t of t h e
20
i n v e n t i o n because i t s l e n g t h c o n t r o l s t h e t r i g g e r v o l t a g e and
t h e holding v o l t a g e of each cascode configured t r a n s i s t o r

pair.
This e l e c t r o s t a t i c d i s c h a r g e p r o t e c t i o n device can be
used e i t h e r a s a s e l f p r o t e c t i n g pull-down p o r t i o n of a mixed
5
v o l t a g e 1 / 0 s t a g e o r , i n a f u r t h e r a s p e c t of t h e p r e s e n t
i n v e n t i o n , a s a s e p a r a t e e l e c t r o s t a t i c d i s c h a r g e clamp.
In
a d d i t i o n , a f u r t h e r advantage of t h i s arrangement i s t h a t t h e
l e n g t h of t h e shared d i f f u s i o n region of t h e two t r a n s i s t o r s
may be a l t e r e d t o t a i l o r both t h e t r i g g e r v o l t a g e and t h e
10
holding v o l t a g e of both of t h e t r a n s i s t o r s i n t h e cascode

configured p a i r .
I n accordance with another a s p e c t of t h e p r e s e n t
i n v e n t i o n , a method f o r p r o t e c t i n g a mixed v o l t a g e i n t e g r a t e d
c i r c u i t from damage caused by e l e c t r o s t a t i c d i s c h a r g e i n c l u d e s
15
t h e s t e p s of d i s p o s i n g a t l e a s t one p a i r of cascode configured

NMOS t r a n s i s t o r s i n t h e same a c t i v e a r e a i n a mixed v o l t a g e
i n t e g r a t e d c i r c u i t , and c o n s t r u c t i n g a shared d i f f u s i o n region

which c o n s t r u c t s t h e d r a i n region of t h e f i r s t t r a n s i s t o r and
t h e source region of t h e second t r a n s i s t o r of each p a i r a s
20
w e l l a s couples each p a i r of t r a n s i s t o r s .
I n accordance with y e t another a s p e c t of t h e p r e s e n t
i n v e n t i o n , a layout of a cascode e l e c t r o s t a t i c discharge
p r o t e c t i o n d e v i c e i n c l u d e s an a c t i v e a r e a c o n s t r u c t e d of
d i f f u s e d PMOS m a t e r i a l , and a t l e a s t one cascode c o n f i g u r a t i o n
of NMOS t r a n s i s t o r s .
I n each p a i r of t r a n s i s t o r s , two
p o l y s i l i c o n r e g i o n s c o n s t r u c t t h e g a t e r e g i o n s of t h e NMOS
5
transistors.
A f i r s t NMOS r e g i o n
i s disposed i n t h e a c t i v e
a r e a t o c o n s t r u c t t h e d r a i n of t h e f i r s t NMOS t r a n s i s t o r .
Likewise,
a second NMOS r e g i o n c o n s t r u c t s t h e s o u r c e of t h e
f i r s t NMOS t r a n s i s t o r a s w e l l a s t h e d r a i n of t h e second NMOS
transistor.
10
The s o u r c e of t h e second NMOS t r a n s i s t o r i s t h e n
c o n s t r u c t e d by a t h i r d NMOS r e g i o n , a l s o d i s p o s e d i n t h e same
active area.
With such an arrangement, a p r o t e c t i o n d e v i c e i s
p r o v i d e d t h a t i s a c c e p t a b l e f o r u s e i n a mixed v o l t a g e I C
d u r i n g normal o p e r a t i n g modes a s w e l l a s d u r i n g ESD e v e n t s .
BRIEF DESCRIPTION OF THE DRAWINGS

f-C
.I--
The foregoing
features of this invention, as well as
the invention itself, may be more fully understood from the

following detailed description when read in conjunction with
the accompanying drawings, in which:
FIG. 1 depicts a block diagram of a computer system in which

the present invention may be applied;
FIG. 2 depicts an electrostatic discharge protection circuit

coupled to a mixed voltage integrated circuit's input/output
(1/0) pad;
10
FIG. 3 depicts a plurality of parallel cascode configured

transistors which may be coupled to the 1/0 pad of FIG 1;
FIG. 4 depicts the electrostatic discharge protection device

of FIG. 2 employed as the pull-down stage of an 1/0 driver;
FIG. 5 depicts the depletion regions surrounding the drain and

15
source in a cross section view of an NMOS transistor
comprising t h e e l e c t r o s t a t i c d i s c h a r g e p r o t e c t i o n c i r c u i t of
FIG. 2;
FIG. 6 d e p i c t s t h e s t a t e of t h e d e p l e t i o n r e g i o n s surrounding
t h e d r a i n and source i n a c r o s s s e c t i o n view of an NMOS
5
t r a n s i s t o r comprising t h e e l e c t r o s t a t i c d i s c h a r g e p r o t e c t i o n
c i r c u i t of FIG. 2 when Punch-through occurs;
FIG. 7 d e p i c t s a c r o s s - s e c t i o n view of t h e e l e c t r o s t a t i c
d i s c h a r g e p r o t e c t i o n d e v i c e when b o t h NMOS t r a n s i s t o r s a r e i n
snap-back and t h e ESD c u r r e n t i s b e i n g shunted t o ground;
10
FIG. 8 i s a diagram d e p i c t i n g d r a i n c u r r e n t v e r s u s t h e d r a i n t o - s o u r c e v o l t a g e of t h e NMOS t r a n s i s t o r of FIG. 5;
FIG. 9 d e p i c t s t h e c u r r e n t v e r s u s v o l t a g e curve of t h e NMOS

t r a n s i s t o r of FIG. 5 superimposed over t h e o p e r a t i n g curve of
a d e v i c e t o be p r o t e c t e d from e l e c t r o s t a t i c d i s c h a r g e ;
15
F i g . 1 0 d e p i c t s a t o p , o r l a y o u t , view of t h e cascode
c o n f i g u r e d NMOS p r o t e c t i o n t r a n s i s t o r s of FIG. 2; and
FIG. 11 d e p i c t s a t o p view of a p l u r a l i t y of cascode
configured NMOS p r o t e c t i o n t r a n s i s t o r s connected i n p a r a l l e l

a s shown i n FIG. 3, disposed i n a mixed v o l t a g e i n t e g r a t e d
circuit.
DESCRIPTION OF A PREFERRED EMBODIMENT

R e f e r r i n g t o FIG. 1, a computer system 1 i s shown t o
i n c l u d e a c e n t r a l p r o c e s s i n g u n i t (CPU) 2, a memory system 3,
and a n i n p u t / o u t p u t
bus 5.
5
(I/O)
system 4, i n t e r c o n n e c t e d by a system
em 1 further
Ea
c o m ~ r i s e smany c o u p l e d i n t e g r a t e d c i r c u i t
ome o f
which r u n on a 5 v o l t power s u p p l y level a n d some o f which r u n

on l o w e r v o l t a g e power s u p p l y levels.
The p r e s e n t i n v e n t i o n
p r o t e c t s e a c h o f t h e s e i n t e g r a t e d c i r c u i t s from e l e c t r o s t a t i c
d i s c h a r g e damage i n s u c h a way t h a t d o e s n o t hamper i t s normal
10
operation.
R e f e r r i n g t o FIG. 2, an e l e c t r o s t a t i c d i s c h a r g e (ESD)
p r o t e c t i o n d e v i c e 10 i s shown c o u p l e d t o a mixed v o l t a g e
integrated c i r c u i t ' s 6 input/output
(I/o)
p a d 11.
During t h e
o c c u r r e n c e o f a n ESD e v e n t , t h e c i r c u i t r y 12 c o u p l e d t o t h e
15
I/O
p a d 12 w i l l b e p r o t e c t e d a g a i n s t damage b a s e d on t h e
a b i l i t y o f t h e p r o t e c t i o n d e v i c e 10 t o l i m i t v o l t a g e a n d s h u n t
c u r r e n t t o e l e c t r i c a l ground 1 4 .
The ESD p r o t e c t i o n d e v i c e i s b a s e d on a c a s c o d e
c o n f i g u r a t i o n o f NMOS t r a n s i s t o r s whose common nodes a r e
20
formed by a s h a r e d d i f f u s i o n 18.
By s h a r e d d i f f u s i o n it i s
meant t h a t t h e same d i f f u s i o n of NMOS m a t e r i a l c o n s t r u c t i n g

t h e s o u r c e r e g i o n 20 of t h e f i r s t t r a n s i s t o r 22 a l s o
c o n s t r u c t s t h e d r a i n r e g i o n 24 of t h e second t r a n s i s t o r 26.
The arrangement of t h e p r e s e n t i n v e n t i o n i s i n c o n t r a s t t o t h e
5
u s u a l l a y o u t of a cascode s t r u c t u r e where t h e t r a n s i s t o r s a r e
l a i d - o u t a s d i s t i n c t d e v i c e s o r , i n t h e c a s e of a m u l t i f i n g e r e d d e v i c e , where t h e d e v i c e s a r e merged i n t o t h e same
a c t i v e a r e a and only one f i n g e r s h a r e s t h e common d i f f u s i o n .
The cascode c o n f i g u r a t i o n of t h e p r e s e n t i n v e n t i o n i s
10
s u p e r i o r t o t h a t of t h e p r i o r a r t i n p a r t because of i t s
inherent f l e x i b i l i t y .
The cascode c o n f i g u r a t i o n w i t h s h a r e d
d i f f u s i o n s can be used a s a s e l f p r o t e c t i n g pulldown s t a g e of

a mixed v o l t a g e 1 / 0 d r i v e r , o r a s a s e p a r a t e ESD v o l t a g e
p r o t e c t i o n clamp.
15
The d e v i c e i s l a i d - o u t having a s h a r e d
d i f f u s i o n 18 which i n c l u d e s a common node c o n s t r u c t i n g b o t h

t h e s o u r c e 20 of a f i r s t NMOS t r a n s i s t o r (NMOST) 22 and t h e
d r a i n 24 of a second t r a n s i s t o r 26.
merged i n t o t h e same a c t i v e a r e a .
Both t r a n s i s t o r s a r e
The g a t e 28 of t h e f i r s t
NMOST i s t i e d t o t h e low supply v o l t a g e

20
(Vdd) while t h e g a t e
30 and s o u r c e 32 of t h e second NMOST a r e t i e d t o ground 1 4 .

The 1 / 0 pad 12 and pull-up p o r t i o n of t h e 1 / 0 d r i v e r a r e
connected t o t h e d r a i n 34 of t h e f i r s t t r a n s i s t o r 22.
A person having ordinary s k i l l i n t h e a r t w i l l
a p p r e c i a t e t h a t t h e number o f c a s c o d e c o n f i g u r e d t r a n s i s t o r s
10 i s n o t l i m i t e d t o a s i n g l e p a i r s u c h a s d e p i c t e d i n F i g . 2 .
F o r example, a s shown i n FIG. 3, a n ESD p r o t e c t i o n d e v i c e 46
5
i s shown t o i n c l u d e a p l u r a l i t y o f c a s c o d e c o n f i g u r e d NMOS
t r a n s i s t o r p a i r s 44a-44x s h a r i n g a common a c t i v e a r e a , and

connected i n p a r a l l e l .
Although o n l y t h r e e p a i r s of
t r a n s i s t o r s , 44a, 44b, and 44x, a r e shown, it s h o u l d be

u n d e r s t o o d t h a t t h e number o f c a s c o d e p a i r s a r e d e s i g n
10
dependent.
That i s , t h e number o f p a r a l l e l c a s c o d e
c o n f i g u r a t i o n s depends upon t h e amount o f c u r r e n t t h a t e a c h

p a i r o f NMOS t r a n s i s t o r s can c a r r y and t h e maximum c u r r e n t
t h a t t h e d e v i c e s a r e l i k e l y t o e x p e r i e n c e d u r i n g normal
o p e r a t i o n and e l e c t r o s t a t i c d i s c h a r g e .
15
R e f e r r i n g a g a i n t o FIG. 2, t h e c a s c o d e c o n f i g u r e d d e v i c e
10 i s p r o t e c t e d d u r i n g normal o p e r a t i o n b e c a u s e t h e v o l t a g e a t
each shared d i f f u s i o n 18 i s l i m i t e d t o t h e supply voltage
(Vdd) minus t h e t h r e s h o l d v o l t a g e o f t h e NMOS t r a n s i s t o r .
Because o f t h i s l i m i t a t i o n , v o l t a g e s a c r o s s t h e o x i d e s and
20
c h a n n e l s of e a c h p a r t o f t h e d e v i c e a r e restricted t o s a f e
l e v e l s d u r i n g normal o p e r a t i o n w h i l e , d u r i n g a n ESD e v e n t , t h e
c a s c o d e c o n f i g u r a t i o n p r o v i d e s a p a t h f o r t h e ESD c u r r e n t t o
reach e l e c t r i c a l ground 1 4 .
By shunting t h e ESD c u r r e n t t o
ground 1 4 v i a t r a n s i s t o r s 22 and 2 6 , an I / O d r i v e r s t a g e
connected t o t h e d r a i n 34 of NMOST device 22 i s p r o t e c t e d from
damaging v o l t a g e and c u r r e n t l e v e l s .
5
R e f e r r i n g now t o F I G . 4 ,
an 1 / 0 d r i v e r s t a g e 48 i s shown having a pull-up s t a g e 48a

coupled t o t h e cascode configured NMOS t r a n s i s t o r device 48b
of t h e p r e s e n t invention.
The cascode NMOST device i s used a s
t h e pulldown s t a g e of t h e d r i v e r , t h u s c o n s t r u c t i n g a s e l f
protecting I/O
10
driver circuit.
When t h e p r o t e c t i o n device i s used a s a s e p a r a t e ESD

clamp, a s shown i n F I G . 2, i t s robustness can be i n c r e a s e d by
The s a l i c i d e process reduces
blocking both s i l i c i d e and LDD.
propagation delay i n t r a n s i s t o r s by d e p o s i t i n g metal on t o p of

an e x i s t i n g t r a n s i s t o r . LDD involves doping t h e d r a i n region
15
c l o s e s t t o t h e channel l i g h t e r t h a n t h e r e s t of t h e a r e a . The
r e s u l t i s a l e s s abrupt, o r more graded, junction between t h e
d r a i n and channel regions.
A f t e r t h e s a l i c i d e process i s
complete t h e propagation time between devices i s t h e r e a f t e r

determined by t h e c h a r a c t e r i s t i c s of t h e metal used, while t h e
20
p r o p e r t i e s of t h e t r a n s i s t o r i t s e l f a r e determined by t h e
polysilicon gate's characteristics.
The problem with t h e
s a l i c i d e process i s t h a t it produces a non-uniform t h i c k n e s s
-18
of metal and hence a non-uniform r e s i s t a n c e along t h e d r a i n

and source a r e a s of t h e device.
Current flows unevenly
through t h i s non-uniform r e s i s t a n c e producing a hot s p o t where

t h e c u r r e n t flow i s t h e s t r o n g e s t . A s t h e temperature of t h e
5
h o t s p o t i n c r e a s e s , t h e c u r r e n t flow a l s o i n c r e a s e s . These
r e l a t e d e f f e c t s develop i n t o a s e l f supporting loop r e f e r r e d
t o 3s thermal runaway. Thermal runaway occurs when most of t h e
c u r r e n t flows through t h e hot s p o t , r a i s i n g i t s temperature
enough t o melt metal i n t h e immediate a r e a .
10
Therefore i f a
metal c o n t a c t i s placed t o o c l o s e t o t h e h o t s p o t , it w i l l
melt and damage t h e device.
Accordingly, t o overcome t h i s
problem i n t h e c u r r e n t invention t h e s i l i c i d e i s p r e f e r a b l y
blocked from being deposited over c e r t a i n s e c t i o n s of t h e
d r a i n and source.
15
A s a r e s u l t , t h e c o n t a c t s a r e pushed
f a r t h e r from t h e g a t e and f a r t h e r from t h e hot s p o t .

g r e a t e r degree of h e a t i s t h e n ;equired
reach t h e melting p o i n t .
f o r t h e contacts t o
By blocking t h e s i l i c i d e and LDD,
t h e ESD p r o t e c t i o n device i s more r e l i a b l e and l e s s l i k e l y t o

become damaged during an ESD e v e n t .
20
I n each of t h e NMOST cascode c o n f i g u r a t i o n s of F I G S .

3, and 4 ,
2,
snap-back must occur i n t h e device b e f o r e t h e ESD
c u r r e n t can be shunted t o ground.
The term snap-back r e f e r s
to an operating region of MOS transistors.
Referring now to
FIG. 5 a cross section view of an NMOS transistor 50 used in

the present invention is shown.
The NMOS transistor 50
comprises a gate region 52, a source region 54 and a drain

5
region 56 coupled to a PMOS region 58.

To understand the phenomena of snap-back, first consider
that the gate 52 and source 54 regions of the NMOST 50 are
coupled to ground 14 and that a voltage source is coupled to
the drain region 56.
10
Initially, this configuration
will not
conduct current from drain-to-source because there is no

forward biased threshold voltage imposed across the gate-tosource junction 60. As the voltage coupled to the drain 56 is
increased, a field 62 is built up in the PMOS region 58 around
the drain 56 and source 54.
15
This is called the depletion
region 62, and it increases proportionately with the

increasing voltage on the drain 56.
Referring now to FIG. 6 an NMOS transistor 50, similar
to that of FIG. 5, along with associated source and drain
depletion regions 62 are shown.
20
In the NMOST 50 of FIG. 6, it
can be seen that the depletion regions 62 of the source 54 and

drain 56 are merged. Such an event occurs in the following
manner.
When the drain voltage reaches a certain value,
r e f e r r e d t o a s t h e t r i g g e r v o l t a g e , t h e two d e p l e t i o n r e g i o n s
62 i n t e r s e c t w i t h each o t h e r .
This a c t i o n , c a l l e d Punch-
through, allows a small number of e l e c t r o n s 6 6 t o p a s s from

s o u r c e 54 t o d r a i n 56 through t h e PMOS r e g i o n 58.
5
The a c t i o n
of t h e e l e c t r o n 66 jumping i n t o t h e NMOS d r a i n r e g i o n 56
c a u s e s a c o l l i s i o n with t h e s i l i c o n l a t t i c e known a s impact
ionization.
During impact i o n i z a t i o n , an e l e c t r o n i s
disengaged from i t s c o v a l e n t bond and g e n e r a t e s a space

r e f e r r e d t o a s a h o l e 68.
10
The h o l e 68, following t h e c l o s e s t
p a t h 70 t o a lower p o t e n t i a l , p a s s e s through t h e PMOS r e g i o n

58 and i n t o e l e c t r i c a l ground 1 4 .
Because t h e r e i s r e s i s t a n c e
i n t h e PMOS s u b s t r a t e 58, t h e c u r r e n t g e n e r a t e d by t h e
m i g r a t i n g h o l e g i v e s r i s e t o a v o l t a g e 72.
As t h e depletion
r e g i o n s 62 grow i n s t r e n g t h , more e l e c t r o n s 66 p a s s from

15
s o u r c e 54 t o d r a i n 58 causing more h o l e s 68 t o p a s s through

t h e s u b s t r a t e 58.
When t h e v o l t a g e 72 exceeds t h e turn-on v o l t a g e of a
d i o d e 74, formed by t h e junction of t h e NMOS m a t e r i a l of t h e
d r a i n r e g i o n 56 and t h e PMOS m a t e r i a l 58 of t h e a c t i v e r e g i o n ,
20
it conducts.
Once t h e diode 74 t u r n s on, a l a r g e r h o l e
c u r r e n t 70 w i l l flow d i r e c t l y from t h e d r a i n 56 through t h e

s u b s t r a t e 58 and a l a r g e r e l e c t r o n c u r r e n t w i l l flow from
source 5 4 t o d r a i n 5 6 .
I t should be noted t h a t t h i s flow of
e l e c t r o n s 66 i s not normal channel conduction but r a t h e r ,

happens below t h e channel.
Once t h e c u r r e n t flow 70 i s
s t a r t e d , it w i l l s u s t a i n t h e forward b i a s v o l t a g e 72 on t h e
5
diode 74 and only a very small d e p l e t i o n region 62 w i l l be

necessary t o allow t h e c u r r e n t t o remain flowing.
This
o p e r a t i n g region i s r e f e r r e d t o a s snap-back and i s used by

t h e device 1 0 t o provide ESD p r o t e c t i o n .
R e f e r r i n g now t o F I G . 7, a c r o s s s e c t i o n view 80 of t h e
10
cascode configured NMOST device 1 0 of t h e p r e s e n t invention i s

depicted.
The shared d i f f u s i o n a r e a 18 c o n s t r u c t s t h e source
20 of a f i r s t t r a n s i s t o r 22 and t h e d r a i n 24 of a second
t r a n s i s t o r 26.
Once both t r a n s i s t o r s e n t e r t h e snap-back
region of o p e r a t i o n , a low impedance p a t h 81 from t h e I / O pad

15
t o e l e c t r i c a l ground i s formed.
ESD c u r r e n t i s shunted t o
ground along t h i s p a t h 81, and t h e a s s o c i a t e d device i s

p r o t e c t e d from damage.
R e f e r r i n g now t o Fig. 8, a graph i s shown d e p i c t i n g t h e
d r a i n c u r r e n t 84 v e r s u s t h e drain-to-source v o l t a g e 86 of t h e
20
t y p e of NMOS t r a n s i s t o r used i n t h e p r e f e r r e d embodiments.

During an ESD event, t h e drain-to-source v o l t a g e 86 w i l l
i n c r e a s e very r a p i d l y u n t i l it reaches t h e t r i g g e r v o l t a g e 88.
At this point the transistor will experience punch-through

90, and will clamp the drain-to-source voltage 86, and hence
the coupled I/O driver, to the lower holding voltage 92.
Referring now to FIG. 9, the current versus voltage
5
curve 94 of a punch-through device is superimposed over the

operating curve 96 of a transistor to be protected from an ESD
event.
Because an ESD event occurs very quickly, the amount
of time that the punch-through transistor takes to reach the

trigger voltage 88, and then to clamp at the holding voltage
lo
92, is very small when compared to the time it would take the
same voltage to destroy the transistor's oxide layer.
Therefore, no destruction occurs before the protection circuit
clamps the I/O pad to the holding voltage 88.
The curves
depicted in Fig. 9 show that when the transistor clamps the

15
1/0 stage to the holding voltage 92, the 1/0 transistor is at

an acceptable level of drain current 84.
Therefore no damage
to the 1/0 stage will occur.

Referring now to FIG. 10, a top view of the layout 100
of the cascode configured ESD protection transistors is
20
depicted.
The transistors are fabricated as a single device
in the same active area 102.
The common node which joins the
two transistors is a shared diffusion 104 which constructs the
source 106 of one t r a n s i s t o r and t h e d r a i n 108 of a n o t h e r .
c r i t i c a l f e a t u r e of t h e ESD p r o t e c t i o n device i s t h a t t h e
b i p o l a r base width 1 1 0 of t h e e q u i v a l e n t t r a n s i s t o r , which
determines t h e t r i g g e r v o l t a g e 88 and holding v o l t a g e 92, i s
5
d e f i n e d by t h e d i s t a n c e between t h e t o p 120 and bottom 122

diffusions.
Changing t h i s c r i t i c a l d i s t a n c e 1 1 0 , by changing
t h e l e n g t h of t h e shared d i f f u s i o n 1 0 4 when t h e device i s

laid-out,
t a i l o r s t h e t r i g g e r v o l t a g e 88 and holding v o l t a g e
92 t o t h e r e q u i r e d v a l u e s .
lo
This i s a b e n e f i t over having t o
i n c r e a s e t h e channel l e n g t h of each device s e p a r a t e l y , which

i s r e q u i r e d when t h e t r a n s i s t o r s a r e f a b r i c a t e d a s independent
devices.
I n c r e a s i n g t h e l e n g t h of t h e shared d i f f u s i o n 1 0 4
has t h e b e n e f i t s of n o t i n c r e a s i n g t h e capacitance, n o t
reducing t h e d r i v e s t r e n g t h , and not i n c r e a s i n g t h e channel
15
leakage c u r r e n t of t h e d r i v e r .
I n t h i s b e n e f i c i a l manner, t h e
ESD p r o t e c t i o n c i r c u i t can be t a i l o r e d t o t h e s p e c i f i c 1 / 0
d r i v e r by making t h e t r i g g e r v o l t a g e s u f f i c i e n t l y l a r g e s o
t h a t t h e devices w i l l not punch-through and e n t e r t h e snapback region d u r i n g normal o p e r a t i o n .
R e f e r r i n g now t o Fig. 11, t h e l a y o u t 120 of a p a r a l l e l
connection of t h r e e cascode c o n f i g u r a t i o n s i s d e p i c t e d .
When
more t h a n one p a i r of cascode configured t r a n s i s t o r s a r e used,
t h e y a r e i n t e r l e a v e d r a t h e r t h a n simply having one f i n g e r

s h a r e t h e common d i f f u s i o n . I n such a c o n f i g u r a t i o n each p a i r
of NMOS t r a n s i s t o r s w i l l e x p e r i e n c e a p e r c e n t a g e of t h e t o t a l
ESD c u r r e n t flowing through t h e s t r u c t u r e t o ground.
5
It w i l l
be a p p r e c i a t e d by one w i t h o r d i n a r y s k i l l i n t h e a r t t h a t
i n c r e a s i n g t h e number of cascode c o n f i g u r a t i o n s w i l l
p r o p o r t i o n a t e l y reduce t h e amount of c u r r e n t flowing through
e a c h p a i r of t r a n s i s t o r s .
T h e r e f o r e , t h e number of
t r a n s i s t o r s t o be used i s u n l i m i t e d by t h i s method of ESD
lo
protection.
Having d e s c r i b e d a p r e f e r r e d embodiment of t h e
i n v e n t i o n , it w i l l now become a p p a r e n t t o one of o r d i n a r y
s k i l l i n t h e a r t t h a t o t h e r embodiments i n c o r p o r a t i n g i t s
c o n c e p t s may be used.
15
It is felt, therefore, t h a t t h i s
embodiment s h o u l d n o t be l i m i t e d t o t h e d i s c l o s e d embodiment,
b u t r a t h e r s h o u l d be l i m i t e d o n l y by t h e s p i r i t and scope of
t h e appended c l a i m s .
WHAT IS CLAIMED IS:

1.
An e l e c t r o s t a t i c discharge p r o t e c t i o n device f o r
coupling t o a mixed v o l t a g e i n t e g r a t e d c i r c u i t t o p r o t e c t s a i d
i n t e g r a t e d c i r c u i t a g a i n s t damage from e l e c t r o s t a t i c discharge
comprising:
a t l e a s t one cascode configured t r a n s i s t o r p a i r , each of
s a i d p a i r s comprising:
a f i r s t NMOS t r a n s i s t o r having a g a t e region, a source
70
region, and a d r a i n region, s a i d d r a i n region c o u p l e d ~ s a i d

mixed v o l t a g e i n t e g r a t e d c i r c u i t , s a i d g a t e region coupled t o
a low power supply of s a i d mixed v o l t a g e i n t e g r a t e d c i r c u i t ;
a second NMOS t r a n s i s t o r , merged i n t o t h e same a c t i v e
a r e a a s s a i d f i r s t t r a n s i s t o r , having a g a t e region, a source
region, and a d r a i n region, s a i d g a t e region and s a i d source
region of s a i d second NMOS t r a n s i s t o r coupled t o a ground
p l a n e of s a i d mixed v o l t a g e i n t e g r a t e d c i r c u i t ;
a shared d i f f u s i o n region. -coupling
t h e source region of
- s a i d f i r s t NMOS t r a n s i s t o r t o t h e d r a i n region of s a i d second
NMOS t r a n s i s t o r ,
s a i d shared d i f f u s i o n region c o n s t r u c t i n g t h e
source region of s a i d f i r s t NMOS t r a n s i s t o r and c o n s t r u c t i n g

s a i d d r a i n region of s a i d second NMOS t r a n s i s t o r .
CM'
y78
2.
The e l e c t r o s t a t i c discharge p r o t e c t i o n device of
Claim 1 wherein t h e l e n g t h of s a i d shared d i f f u s i o n region

c o n t r o l s a t r i g g e r v o l t a g e and a holding v o l t a g e of s a i d
transistor pair.
3.
Claim 2 wherein s a i d e l e c t r o s t a t i c discharge p r o t e c t i o n device

p r o t e c t s an i n p u t s t a g e of s a i d mixed v o l t a g e i n t e g r a t e d
circuit.
4.

p r o t e c t s an output s t a g e of s a i d mixed v o l t a g e i n t e g r a t e d
c i r c u i t , s a i d p r o t e c t i o n device comprising a pulldown p o r t i o n
of s a i d output s t a g e of s a i d mixed v o l t a g e i n t e g r a t e d c i r c u i t .
5.

p r o t e c t s an output s t a g e of s a i d mixed v o l t a g e i n t e g r a t e d
c i r c u i t , s a i d p r o t e c t i o n device comprising a s e p a r a t e
p r o t e c t i o n clamp.
6.
p r o t e c t s an i n p u t / o u t p u t s t a g e of s a i d mixed v o l t a g e
i n t e g r a t e d c i r c u i t , s a i d p r o t e c t i o n d e v i c e comprising a
pulldown p o r t i o n of s a i d i n p u t / o u t p u t s t a g e of s a i d mixed
voltage integrated c i r c u i t .
7.
Claim 2 wherein s a i d e l e c t r o s t a t i c d i s c h a r g e p r o t e c t i o n d e v i c e
p r o t e c t s an i n p u t / o u t p u t s t a g e of s a i d mixed v o l t a g e
i n t e g r a t e d c i r c u i t , s a i d p r o t e c t i o n d e v i c e comprising a
s e p a r a t e p r o t e c t i o n clamp.
8.
A method f o r
a mixed v o l t a g e i n t e g r a t e d
c i r c u i t from damage caused by
method comprising t h e s t e p s
disposing a t l e a
t r a n s i s t o r s i n a mixe
d c i r c u i t wherein each
p a i r of s a i d NMOS t r a
i n t o t h e same a c t i v e
area;
The e l e c t r o s t a t i c d i s c h a r g e p r o t e c t i o n d e v i c e of
constructing
9
10
p a i r of s a i d NMOS
l e c t r o s t a t i c discharge, s a i d
i r of cascode c o n f i g u r e d NMOS
r e g i o n t o couple each
d i f f u s i o n region
c o n s t r u c t i n g a d r d i n r e g i o n of a' f i r s t t r a n s i s t o r of s a i d p a i r
PD95-0080
of NMOS t r a n s i s t o r s and a source region o f ,
of s a i d p a i r of NMOS t r a n s i s t o r s .
9.
The method of Claim 8 f u r t h h comprising t h e s t e p
of:
r.
regulating the trigger voltag

l e v e l of s a i d NMOS t r a n s i s t o r s b
shared diffusion.
10.
second t r a n s i s t o r
l e v e l and holding v o l t a g e
changing t h e l e n g t h of s a i d
The met
of:
coupling s a i d c
t o an i n p u t s t a g e
11.
a t i o n of NMOS t r a n s i s t o r s
ge i n t e g r a t e d c i r c u i t ;
The met
9 f u r t h e r comprising t h e s t e p
of:
coupling s a i
cascode c o n f i g u r a t i o n of NMOS t r a n s i s t o r s
t o an output s t a e of s a i d mixed v o l t a g e i n t e g r a t e d c i r c u i t ;
12.
The,,akethod of Claim 9 f u r t h e r comprising t h e s t e p
PD95-0080
coupling s a i d cascode
3
4
t o an i n p u t / o u t p u t
circuit;
NMOS t r a n s i s t o r s
integrated
,
'
/'
13.
1
A computer system
A c e n t r a l processing unit/
programs t o be run on s a i d
A memory system f-or
--
c e n t r a l processing u n i t ;
An 1/0 system f o
u n i c a t i n g with I / O devices;
t e d c i r c u i t comprising an
At
comprising a t l e a s t
one cascode c o n f i
4'
e d . t r a n s i s t o r p a i r , each of s a i d p a i r s
comprising:
t r a n s i s t o r having a g a t e region, a source
region, s a i d d r a i n region coupled s a i d
c i r c u i t , s a i d g a t e region coupled t o
mixed v o l t a g e i n t e g r a t e d c i r c u i t ;
nd NMOS t r a n s i s t o r , merged i n t o t h e same a c t i v e
- -- - f i r s t t r a n s i s t o r , having a g a t e region, a source
region, and a drain region, said g
e region and said source
tor coupled to a ground
region of said second NMOS
circuit;
plane of said mixed voltage
j/!
a shared diffusion reg'o boupling the source region of

said first NMOS
region of said second
NMOS transistor,
region constructing the
souzce region of said fi#t
N M O ~transistor and constructing
d' 4
said drain region of s id secon NMOS transistor.
Y
A cascade
discharge protection device
comprising:
a-rea constructed of diffused PMOS material;
an active
--
.-
a first polysilicon region disposed over said active

area, said polysilicon region constructing the gate region of
a first NMOS transistor;
a secondgo_l
-
said active
area and parallel to said first polysilicon region, said

second polysilicon region constructing the gate region of a
second.NMOS transistor;
a first NMOS region, disposed in said active area,
constructing the drain of said first NMOS transistor;
a second NMOS region, disposed i n s a i d a c t i v e a r e a ,

c o n s t r u c t i n g t h e source of s a i d f i r s t NMOS t r a n s i s t o r and
c o n s t r u c t i n g t h e d r a i n of s a i d second NMOS t r a n s i s t o r ;
a t h i r d NMOS region, disposed i n s a i d a c t i v e a r e a ,
c o n s t r u c t i n g t h e source of s a i d second NMOS t r a n s i s t o r .
9
38.
A cascode e l e c t r o s t a t i c discharge p r o t e c t i o n device
comprising:
an a c t i v e a r e a c o n s t r u c t e d of d i f f u s e d PMOS m a t e r i a l ;
a p l u r a l i t y of p o l y s i l i c o n r e g i o n s disposed over s a i d
a c t i v e a r e a , s a i d p l u r a l i t y of p o l y s i l i c o n r e g i o n s
c o n s t r u c t i n g t h e g a t e regions of a p l u r a l i t y of p a i r s of NMOS
t r a n s i s t o r s , each of s a i d p a i r s of NMOS t r a n s i s t o r s
comprising:
a f i r s t NMOS region, disposed i n s a i d a c t i v e a r e a ,
c o n s t r u c t i n g t h e d r a i n of s a i d f i r s t NMOS t r a n s i s t o r ;
a second NMOS region, disposed i n s a i d a c t i v e a r e a ,
c o n s t r u c t i n g t h e source of s a i d f i r s t NMOS t r a n s i s t o r
and c o n s t r u c t i n g t h e d r a i n of s a i d second NMOS
transistor;
a t h i r d NMOS region, disposed i n s a i d a c t i v e a r e a ,
c o n s t r u c t i n g t h e source of s a i d second NMOS t r a n s i s t o r .
DECLARATION AND POWER OF ATTORNEY

DECLARATION:
As a below named inventor, I hereby declare that:

MY residence, post office address and citizenship are
as stated below next to my name.
I believe, I am the original, first and sole inventor
(if only one name is listed below) or, the below named
inventors are the original, first and joint inventors (if
plural names are listed below) of the subject matter which
is claimed and for which a patent is sought on the invention
for ESD Protection clam^ for Mixed Voltase I/O Stases Usins
NMOS Transistors , the specification of which is attached
hereto unless the following box is checked.
[I
was filed on - as Application Serial Number - and was

amended on - (if applicable) .
I hereby state that I have reviewed and understand the

contents of the above-identified specification, including
the claims.
I acknowledge the duty to disclose information which is
material to patentability in accordance with Title 37, Code
of Federal Regulations, 81.56.
I hereby claim foreign priority benefits under Title

35, United States Code, I19 (a)- (dl of any foreign
application(s) for patent or inventor's certificate listed
below and have also identified below any foreign application
for patent or inventor's certificate having a filing date
before that of the application on which priority is claimed:
PLG 6/95
DECL-APP.FRM
PD95-0080
PRIOR FOREIGN APPLICATIONS
Number
Country
Date
Filed
Priority
Claimed
(Yes/No)
I hereby claim the benefit under ~ i t l e35, United

States Code 119(e) of any United States ~rovisional
application(s) listed below.
APPLICATION NUMBER
FILING DATE
I hereby claim the benefit under Title 35, United States

Code, I20 of any United States application(s) listed below
and, insofar as the subject matter of each of the claims of
this application is not disclosed in the prior United States
application in the manner provided by the first paragraph of
~ i t l e35, united States Code, 112, I acknowledge the duty
to disclose material information as defined in Title 37,
Code of Federal ~egulations,51.56 which became available
between the filing date of the prior application and the
national or PCT international filing date of this
application:
PRIOR UNITED STATES APPLICATIONS
Application
Serial Number
PLG 6/95
DECL-APP.FRM
Filing Date
Status
I hereby declare that all statements made of my own

knowledge are true and that all statements made on information and belief are believed to be true; and further that
these statements were made with the knowledge that willful
false statements and the like so made are punishable by fine
or imprisonment, or both, under Section 1001 of Title 18 of
the United States Code and that such willful false statements may jeopardize the validity of the application or any
patent issued thereon.
POWER OF ATTORNEY:
On behalf of Digital Equipment Corporation, Assignee of my

entire right, title and interest, I hereby appoint the
following attorney(s1 and/or agent(s) with full power of
substitution to act exclusively for Digital to prosecute
this application and transact all business in the Patent and
Trademark Office connected therewith: Arthur W. Fisher, Reg.
No. 27,549; Albert Sidney Johnston, Reg. No. 29,548; Rama B.
~ a t h ,Reg. No. 27,072; Ronald C. Hudgens, Reg. No. 24,288;
eni is G. Maloney, Reg. No. 29,67O;,~irk Brinkman, Reg. No.'
25,460; Gary E. Ross, Reg. NK29,431; Kenneth F. ~ o z i k ,
Reg. No. 36,572;-James F. Thompson, Reg. No. 36,699; avid
A. Dagg, Reg. No. 37,809; Christine M. Kuta,rkeg. No.
r38,001; Krishnendu Gupta, Reg. No. 2 7 . 9 7 7 ~Mary M. Steubing,
Reg. No. u 4 & Mark J. Casey, Reg. No. 37,796, Lindsay G.
McGuinness, Reg. No. -38,549; Diane C. Drozenski, P-39,177.
correspondence should be addressed to:
Patent Law Group
Digital Equipment Corporation
111 Powdermill Road, MSO~-~!G~-
PLG 6/95
DECL-APP.FRM
~ ~ 9 5 - 0 6 8. 0
telephone calls should be directed
Lindsay b .
'
McGuinness, telephone number (508) 493-8257.
?
,
*
%.
Inventor's ~ u l lName:
h v i d F&n
amin brakaueJ
Inventor's Signature:
Residence:
(City, State and/or

cc~imtry)
. Ca&rid/:~assachusetts
Citizenship:
United States of America
post Office Address:
20 Hubbard Avenue # 9
Cambridge, MA 02140
/ u . S .A.
;
J
PLG 6/95
DECL-APP.FRM
*<*.%,
.-
3.'
2,"
Case No. PD95-0080

David Benjamin K&kauer
Sheet 1 of 11
Case No. PD95-0080
. D a p a - ~ e namin
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Krakauer
.'
Sheet 2 of 11
Case No. PD95-0080

David Benjamin Krakauer
sheet 3 of 1k
PRINT OF DRAWINGS
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sheit 4 of of1
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Dayid B&lj&n$n Krakauer
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PRINT OF DRAWINGS
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Sheet 7 of 11
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avid Benjamin Krakauer
Sheet 8 of 11
PRINT O F D R A W G S
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of 11
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avid Benjamin Krakauer
'sheet 8 of 11
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Dagid ~ e naminXrakauer
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Case No. PQ95z0080

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David43enja,min Krakauer
shekt 11 of 1 1 ' I
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Application or Docket Number
PATENT APPLICATION FEE DETERMINATION RECORD

Effective October 1 , 1997
C L A I M S AS FILED P A R T I
(Column I)
FOR
'
NUMBER FILED
TOTAL CLAIMS
NDEPENDENT CLAIMS
OTHER THAN
"T
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0"
NUMBER EXTRA
mlnus 20 =
SMALL ENTITY
(Column 2)
minus 3 =
x$ll=
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TOTAL
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TOTAL
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MULTIPLE DEPENDENT CLAIM PRESENT

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If the d~tferencaIn column 1 Is less than zero, enter '0' In COl~mn2
C L A I M S AS AMENDED
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SMALL ENTITY
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FIRST PRESENTATION O F MULTIPLE DEPENDENT CLAIM
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Application or Docket Number
Effective October 1, 1995
OTHER THAN
SMALL ENTITY
CLAIMS AS FILED PART I

OR
SMALL ENTITY
FOR
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NUMBER
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TOTAL
CLAIMS AS AMENDED PART II

(Column 2)
(Column 1)
(Column 3)
SMALL ENTITY
ADDITIONAL
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RATE
I Minus
I Minus
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3=: Ilndependent /I *
I **
II ***
(Column 1)
(Column 2)
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CLAIMS
HIGHEST
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PREVIOUSLY
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x78=
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If the "Highest Number Previously Paid For" IN THlS SPACE is less than 20, enter "20."
ADDIT. FEE
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The " ~ i ~ h eNumber
st
~ r e v i o u s l ~ ' ~ For"
a i d (Total or Independent) is the highest number found in the appropriate box in column 1.
FORM PTO-875
(Rev. 10195)
Patent and Trademark Office, U.S. DEPARTMENT OF COMMERCE
1,ARCODE LABEL
I
U.S. PATENT APPLICATION

SERIAL NUMBER
FILING DATE
CLASS
GROUP ART UNIT
DAVID B. KRAKAUER, CAMBRIDGE, MA.
**FOREIGN/PCT APPLICATIONS************
VERIFIED
FOREIGN FILING LICENSE GRANTED 02/28/96

;TATEOR
:OUNTRY
MA
V)
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II
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I
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SHEETS
DRAWING
11
TOTAL
CLAIMS
INDEPENDENT
CLAIMS
15
FILING FEE
RECEIVED
ATTORNEY DOCKET NO.
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PATENT LAW GROUP

DIGITAL EQUIPMENT CORPORATION
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ESD PROTECTION CLAMP FOR MIXED VOLTAGE

TRANSISTORS
110 STAGES
USING NMOS
This is to certif that annexed hereto is a true copy from the records of the United States
Patent and ~ r a & m a r k Office of the application which is identified above.
By authority of the
COMMISSIONER OF PATENTS AND TRADEMARKS
Date
Certifying Officer
PD95-0080
STATES PATENT AND TRADEMARK OFFICE
"Express ail" Mailing Label No, TB541672527US
Date of Deposit: November 10, 1995
I hereby certify that this paper or fee is
being deposited with the United States Postal
Service
"EXPRESS MAIL
Post
Off ice
to
Addressee" service under 37 CFR 1.10 on the
date indicated above and is addressed to the
Commissioner of Patents and Trademarks,
Washington, D.C. 20231.
MARIE R. BENNETT
Printed name of depositor
TRANSMITTAL LETTER
THE COMMISSIONER OF PATENTS AND TRADEMARKS
washington, D.C. 20231
ATTN:
BOX PATENT APPLICATION
Sir:
Transmitted herewith for filing is the patent application
of:
INVENTOR: David
en jam in Krakauer
FOR: ESD PROTECTION CLAMP FOR MIXED VOLTAGE I/O STAGES

USING NMOS TRANSISTORS
Enclosed are:
[u]
pages
of specification, claims and abstract

of 8 informal drawings
[XI Declaration and Power of Attorney
[XI Assignment of the application to Digital Equipment Corporation.
[ ] Information Disclosure Statement
[ ] Preliminary Amendment
[ ] Power of Attorney
[ 1
[u]
sheets
The filing fee is calculated as follows:
CLAIMS AS F I L E D
NUMBER
NUMBER
EXTRA
FILED
Basic Fee
T o t a l Claims
XXXXX
AMOUNT
$ 750.00
15
-20
x22.00
-3
x78.00
Independent
Claims
XXXXX
LARGE
ENTITY
Assignment
Recordins Fee
$ 750.00
0
156.00
40.00
40.00
Multiple Dependent Claim
Fee
250.00
Other
TOTAL F E E
946.00
[XI
Please record the accompanying Assignment.
[XI
Please charge Deposit Account No. 04-1079 in the amount

of $946.00.
[XI
The Commissioner is hereby authorized to charge any

additional fees due or credit any overpayment to Deposit
Account No. 04-1079.
All future correspondence should be addressed to:

Patent Law Group
111 Powdermill Road, ~S02-3/G3
Maynard, Massachusetts 01754-1499
Duplicate copies of this letter are enclosed.
Respectfully submitted,
Reg. No.: 38,549

Agent for ~ssignee
111 powdermill Road, ~S02-3/G3
(508) 493-8257
PLG 10/94
PTO-XMTL.FRM
Applicant: David Benjamin Krakauer

Serial No.: 08/555,463
Group Art Unit:
Filed: Nov. 10, 1995
Examiner:
Title:
ESD PROTECTION CLAMP FOR MIXED VOLTAGE 1 / 0 STAGES

OCT 1 5 1998
I hereby certify that this correspondence is

Service as FIRST CLASS MAIL in an envelope
addressed
to:
Assistant
Commissioner
of
Patents
and
Trademarks,
Washington,
D.C.
20231, on:
n n .~ 133 CO'Y
1
Signature
* * *
LETTER PURSUANT TO 37 C.F.R. 81.56
e o f Depos!
.; :
N o v ~b e r 10,1995
ing deposited with t h e

MAIL P o s t O f f i c e t o
e s s e e " s e r v i c e under 37 CFR 1 . : O
on t h e d a t e i n d i c a t e d
-%reand i s a d d r e s s e d t o t h e Comnissioner o f P a t e n t s and
d m a r k s ; Washington, DC 20231.
Marie R. Benr'ett
Typed name of p e r s o n m ; i l i n g p a p e r o r f e e
Signature
APPLICATION FOR UNITED STATES LETTERS PATENT
Title :
Inventor:
D P-ROTECTION CLAMP FOR MIXED VOLTAGE 110 STAGES

Hon. Assistant Commissioner of Patents and Trademarks

Washington, DC 20231
Sir:
Applicant wishes to bring to the attention of the
Patent and Trademark Office that the invention claimed in
the aforementioned patent is part of a microprocessor
product entitled "LCA-45". The LCA-45 is manufactured by
Digital Equipment Corporation, 111 Powdermill Rd., Maynard
Mass. 01754 and was not available for public sale prior to
November 16,1994.
During a period beginning July 26,1994 and continuing
through November 16,1994, prototypes of the LCA-45
microprocessor were delivered to ArrayComm Inc., 3255 Scott
Blvd., Santa Clara Ca. 95054-3013 for experimental testing.
The purpose of the testing was for evaluating the functional
and performance characteristics of the device as well as for
uncovering and reporting latent defects.
As part of the
evaluation, reports were furnished to Digital Equipment

Corporation from ArrayComm Inc. identifying problems and
stating test results.
PD95-0080
Attached hereto are exhibits A and B which are

evaluation reports furnished to Digital Equipment
Corporation during the stated testing period.
Exhibits A
and B describe power and speed measurements performed using

ArrayComrn Inc.'s benchmark testing structure as well as
problems encountered during the analysis.
The data is
further illustrated by the appended charts and graphs.

Further, attached hereto as exhibit C is a mail message
from ArrayComm Inc. to Digital Equipment Corporation.
The
mail message specifies efforts made to solve a reported

problem and identifies the outcome of the implemented
solution.
The stated test dates as well as Exhibits A, B, and C
are disclosed to facilitate the Patent and Trademark Office
in establishing the date of first commercial use pursuant to
35 U.S.C. 102(b).
Date:
II
6ifndsay&c~uinness
Reg. No. 38,549
Attorney for Assignee
1
APPLICATION NO.
%
.-:
5:.>= ~jpr; c
j . -c
s.-3..4E~:3
FILING DATE
Ifj'13/85
UNITED STA's cS DEPARTMENT OF COMMERCE

Patent and Trademark Office
Address:

Washington, D.C. 20231
FIRST NAMED INVENTOR
KRfiKAlJEH
ATTORNEY DOCKET NO.
Please find below and/or attached an Office communication concerning this application or
proceeding.
Cornrnlsslsner of Patents and Trademarks
PTO-9OC (Rev. 2/95)
'US. GPO: 1997422.1 98160031
1- File Copy
Application
Office Action Summary
Applicant(s)
No.
081555.463
Krakauer
I
Group Art Unit
Examiner
2503
Carl Whitehead, Jr.
iX] Responsive t o communication(s) filed on 73 Nov 1995
0 This action is FINAL.

3 Since this application
is in condition for allowance except for formal matters, prosecution as t o the merits is closed
in accordance with the practice under Ex parte Quayle, 1 9 3 5 C.D. 1 1 ; 4 5 3 O.G. 2 1 3 .
m o n t h k ) , or thirty days, whichever

0
A shortened statutory period for response t o this action is set t o expire
is longer, from the mailing date of this communication. Failure t o respond within the period for response will cause the
application t o become abandoned. (35 U.S.C. 133). Extensions of time may be obtained under the provisions of
3 7 CFR 1 .I36(a).
Disposition of Claims
a Claim(s) 7-75
islare pending in the application.

islare withdrawn from consideration.
Of the above, claim(s1
0 Claim(s)
islare allowed.
m Claimts)
islare rejected.
0 Claim(s)
islare objected to.
iX] Claims 7-75
are subject t o restriction or election requirement.
Application Papers
See the attached Notice of Draftsperson's Patent Drawing Review, PTO-948.
a The drawing(s1 filed on
islare objected to by the Examiner.
5 The proposed drawing correction, filed on

0 The specification is objected t o by the Examiner.
is @ approved
L
l disapproved.
-- The oath or declaration is objected to by the Examiner.

I._]
Priority under 35 U.S.C. 4 119

Acknowledgement is made of a claim for foreign priority under 3 5 U.S.C. 4 1 1 9(a)-(dl.
All
@ Some*
one
of the CERTIFIED copies of the priority documents have been
received.
received in Application No. (Series CodeISerial Number)
received in this national stage application from the International Bureau (PCT Rule 17.2(a)I.
"Certified copies not received:
Acknowledgement is made of a claim for domestic priority under 3 5 U.S.C. 1 1 9(e).
Attachment(s1
Notice of References Cited, PTO-892
C! Information Disclosure Statementb), PTO-1449,
Paper No(s).
@ Interview Summary, PTO-413
a Notice of Draftsperson's Patent Drawing Review, PTO-948

i? Notice of
Informal Patent Application, PTO-152
--- SEE
OFFICE ACTION ON THE FOLLOWING PAGES ---
U S. Patent and Trademark O f f ~ c e
PTO-326 (Rev. 9-95)
Office Action Summary
Part of Paper No.
DETAILED ACTION
ElectionlRestriction
Restriction to one of the following inventions is required under 35

U.S.C. 121:
Group I. Claims 1 to 7, 14 and 15 are drawn to a semiconductor device,
classified in Class 257, subclass 368.
Group II. Claims 8 to 12 are drawn to a process for making
semiconductor devices, classified in Class 437, subclass 141.
Group Ill. Claim 13 is drawn to a computer system, classified in Class 364,
subclass 492.
The inventions are distinct, each from the other because of the following
reasons:
Inventions II and I are related as process of making and product made.
The inventions are distinct if either or both of the following can be shown: ( 1 )
that the process as claimed can be used to make other and materially different
product or (2) that the product as claimed can be made by another and
materially different process (M.P.E.P. 5 806.05(f)). In the instant case
unpatentability of the group I invention would not necessarily imply
Serial Nuxnber: 08/SSS,463

2kx-t Unit: 2503
unpatentability of the group II invention, since the device of the group I

invention could be made by a process materially different than that of the
group ll invention, for example, a different manufacturing method could be
employed.
Because these inventions are distinct for the reasons given above and
have acquired a separate status in the art as shown by their different
classification, the fields of search are not co-extensive. Therefore, separate
examination would be required and restriction for examination purposes as
indicated is proper.
Applicant is advised that the response to this requirement to be complete

must include an election of the invention to be examined even though the
requirement be traversed.
Serial N n b e r : OS/SSS,463
2 k r t Unit: 2 S 0 3
Conclusion
Any inquiry concerning this communication or earlier communications

from the Examiner should be directed to (703)308-4940.
Carl ~ h i t e h e b d ,r
Primary Examiner
Art Unit 2503
CW
May 28, 1997
b"
Dir-ccf ;I ny ir~qirir-ies cor~cer-11

iog dl-awing review
f f he i)r-:l\viog Review Ih-;mcll (703) 305-8404.
u~m-kfis
mwmmw OF COMMERCE

Address: COMMISSIONER OF PATENTS AND TRADEMARKS
Washington, D.C. 2 0 2 3 1
SERIAL NUMBER
FILING DATE
FIRST NAMED APPLICANT
ATTORNEY DOCKETT NO.
EXAMINER
ART UNIT
PAPERNUMBER
DATE MAILED:
EXAMINER INTERVIEW SUMMARY RECORD

All participants (applicant, applicant's representative, PTO personnel):
Date of interview
%J f i H
Type: &ephonic
0 Personal (copy is given to
Exhibit shown or demonstration conducted:
Yes
0 applicant 0 applicant's representative).

d
f yes, brief description:
Agreement h a s reached with respect to some or all of the claims in question.

Claims discussed:
was not reached.
Identification of prior art discussed:
R/owF
Description of the general nature of what was agreed to if an agreement was reached, or any other comments:
k-LK
.fs
7-0
?L
,A
M&~A/
kh@T C A #/ M-?
l - 12;14
(A fuller description, if necessary, and a copy of the amendments, if available, which the examiner agreed would render the claims allowable must be
attached. Also, where no copy of the amendments which would render the claims allowable is available, a summary thereof must be attached.)
1. It is not necessary for applicant to provide a separate record of the substance of the interview.
Unless the paragraph below has been checked to indicate to the contrary, A FORMAL WRITTEN RESPONSE TO THE LAST OFFICE ACTION IS NOT
WAIVED AND MUST INCLUDE THE SUBSTANCE OF THE INTERVIEW (e.g., items 1-7 on the reverse side of this form). if a response to the last Office
action has already been filed, then applicant is given one month from this interview date to provide a statement of the substance of the interview.
2. Since the examiner's interview summary above (including any attachments) reflects a complete response to each of the objections, rejections and
requirements that may be present in the last Office action, and since the claims are now allowable, this completed form is considered to fulfill the
response requirements of the last Office action. Applicant is not relieved from providing a separate record of the substance of the interview unless
box 1 above is also checked.
~xkiner's~knature
PTOL-413 (REV. 2 -93)
ORIGINAL FOR INSERTION I N RIGHT HAND FLAP OF FILE WRAPPER
* U S . GOVERNMENT PRINTING OFFICE: 1995-401

A
-891
e / r ~ ' ~ q 6 43
PD95-0080
IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
Serial No.: 08/555,463
Group Art Unit: 2503
Filed: November 13, 1995
Examiner: Whitehead Jr., C.
Title:
ESD PROTECTION CLAMP FOR MIXED VOLTAGE 1/0 STAGES

I hereby certify that this correspondence is being

deposited with the United States Postal Service as
FIRST CLASS MAIL in an envelope addressed to:
Assistant Commissioner for Patents, Washington,
PETITION FOR EXTENSION OF TIME

Assistant Commissioner for Patents
Sir:
Applicant hereby petitions for a two (2) month
extension of time to respond to the outstanding Office
Action, dated June 2, 1997. The new period for response
will expire November 2, 1997.
authorized to charge the extension fee for this Petition
to the Digital Equipment Corporation Deposit Account No.:

04-1079 in the amount of $400.00. A duplicate copy of this
sheet is enclosed.
In the event the requested extension of time is

insufficient, consider this as a Petition for an extension
for the required period and charge the fee required to
Digital Equipment Corporation Deposit Account No.: 04-1079
A response to the outstanding Office Action is being

filed herewith.
Reg. No. 40,117

Date:
October 31, 1997

111 Powdermill Road, MS02-3/G3
(978) 493-6951
PLG
10/94
EXTEN. FRM
/"

~pplicant:
Krakauer, D.
Serial No.: 08/555,463
Group Art Unit:
Filed: 11/13/95
Title:
2503
ESD PROTECTION CLAMP FOR MIXED VOLTAGE 1/0 STAGES

I hereby certify that this correspondence is being

FIRST CLASS MAIL in an envelope addressed to: Assistant Commissioner for Patents, Washington, D.C.
20231, on:
Date of mailing:
c'p+oj?
?r
199 7
AMENDMENT
Sir:
In response to the office action dated June 2,1997,
please amend this amendment as follows:
IN THE CLAIMS:
Please cancel claims 8-13 without prejudice.
REMARKS
The above identified patent application has been
amended and reconsideration and reexamination are hereby
requested.
The Applicant has canceled Claims 8-13. Claims 1-7, 14
and 15 are pending and presented for examination.
Responsive to the restriction requirement of paragraph
1 of page 2 of the office action of June 2, 1997, the
Applicant has cancelled pending claims 8-13 and elects to
prosecute claims 1-7, 14 and 15. Applicant respectfully
traverses the restriction requirement and reserves the right
to file divisional applications under 35 U.S.C. 120 on the
non-elective subject matter of claims 8-13
The Applicant further reserves the right to add
additional claims on the elected subject matter as well as
on the subject matter of the above mentioned divisional
applications.
In view of the foregoing amendment and remarks, the

Applicant believes that the restriction requirement has been
overcome.
Reconsideration and re-examination are hereby
requested.
Joanne Pappas' U V
Reg. No. 40,117
111 powdermill Road, MS02-3/G3
Maynard, MA 01754-1499
978/493-6951
UNITED STATES DEPARTMENT OF COMMERCE

Address:
APPLICATION NO.
FILING DATE

FIRST NAMED INVENTOR
B5Ml /ti202
PATENT LAW GROUP

DIGITAL EaUIPMENT CORPORATION
I I 1 POWDERMILL ROAD MS02 63
MfaYNAHD M A 01754-1499
AlTORNEY DOCKET NO.
EXAMINER
WHITEHEAD JR. C
ART UNIT
PAPER NUMBER
25i13
DATE MAILED:
02/02/98
Please find below and/or attached an Office communication concerning this application or
proceeding.
Cornrnlssioner of Patents and Trademarks
PTO-OOC (Rev. 2/05)

'U.S. GPO: 1996-404-496140510
1- File Copy
Applicantk)
Application No.
081555,463
Notice of Allo wabilit y
Krakauer
Examiner
Group Art Unit
Carl Whitehead, Jr.
2503
All claims being allowable, PROSECUTION ON THE MERITS IS (OR REMAINS) CLOSED in this application. If not included
herewith (or previously mailed), a Notice of Allowance and Issue Fee Due or other appropriate communication will be
mailed in due course.
[X1 This communication is responsive t o election filed on 3 November 1997
FJ
The allowed claim(s) islare 7-7, 14, a n d 15
The drawings filed on
are acceptable.
Acknowledgement is made of a claim for foreign priority under 3 5 U.S.C. 1 1 9(a)-(dl.
n All
Some*
C] None
of the CERTIFIED copies of the priority documents have been
.-
2 received.
a received in Application No. (Series Codelserial Number)

U received in this national stage application from the International Bureau (PCT Rule 17.2(a)).
*Certified copies not received:
il
Acknowledgement is made of a claim for domestic priority under 3 5 U.S.C. 1 1 9(e).
A SHORTENED STATUTORY PERIOD FOR RESPONSE t o comply with the requirements noted below is set to EXPIRE
THREE MONTHS FROM THE "DATE MAILED" of this Office action. Failure t o timely comply will result in
ABANDONMENT of this application. Extensions of time may be obtained under the provisions of 3 7 CFR 1.136(a).
Note the attached EXAMINER'S AMENDMENT or NOTICE OF INFORMAL APPLICATION, PTO-152, which discloses
that the oath or declaration is deficient. A SUBSTITUTE OATH OR DECLARATION IS REQUIRED.
Applicant MUST submit NEW FORMAL DRAWINGS
because the originally filed drawings were declared by applicant t o be informal.
including changes required by the Notice of Draftsperson's Patent Drawing Review, PTO-948, attached hereto or
t o Paper No.
.
C] including changes required by the proposed drawing correction filed on
, which has been
approved by the examiner.

including changes required by the attached Examiner's AmendmentlComment.
Identifying indicia such as the application number (see 37 CFR 1.84(c)) should be written on the reverse side of the
drawings. The drawings should be filed as a separate paper w i t h a transmittal lettter addressed t o the Official
Draftsperson.
!1
Note the attached Exammer's comment regarding REQUIREMENT FOR THE DEPOSIT OF BIOLOGICAL MATERIAL.
Any response t o this letter should include, in the upper right hand corner, the APPLICATION NUMBER (SERIES
CODEISERIAL NUMBER). If applicant has received a Notice of Allowance and Issue Fee Due, the ISSUE BATCH NUMBER
and DATE of the NOTICE OF ALLOWANCE should also be included.
Attachmentb)
FJ Notice of References Cited, PTO-892
I3 Information Disclosure Statement(s1, PTO-1449, Paper No(s).

Notice of Draftsperson's Patent Drawing Review, PTO-948
Notice of Informal Patent Application, PTO-152
Interview Summary, PTO-413
Examiner's AmendmentlComment
Examiner's Comment Regarding Requirement for Deposit of Biological Material
Examiner's Statement of Reasons for Allowance
CARL
WHITYEHE&,
JR
PRIMARY EXAMINE
ART UNIT 2503
U. S. Patent and Trademark Offlce
PTO-37 (Rev. 9-95)
Notice of Allowability
Part of Paper No.
--
ApplicantW
Application No.
Krakauer
081555,463
Notice of References Cited
Group A r t Unit
Examiner
Page 1 of 1
2503
Carl Whitehead, Jr.

--
U.S. PATENT DOCUMENTS

DOCUMENT NO.
DATE
NAME
CLASS
SUBCLASS
5,594,266
1 4 J a n 97
Beigel et al.
257
355
5,477,078
19 Dec 95
Beigel et al.
257
606
4,630,162
16 Dec 86
Bell et al.
36 1
56
E
I
-.
-
--
--
Ir
/
2-1
FOREIGN PATENT DOCUMENTS

* ;
DOCUMENTNO
DATE
COUNTRY
NAME
CLASS
SUBCLASS
NON-PATENT DOCUMENTS
DOCUMENT (Including Author, Title. Source, and Pertinent Pages)
DATE
* A copy of this reference is not being furnished with this Office actlon
(See Manual of Patent Examining Procedure. Section 7 0 7 . 0 5 ( a ) . )
U S. P a t e n t and Trademark O f f ~ c e
PTO-892 (Rev. 9 - 9 5 )
Notice of References Cited
Part of Paper No.
UNITED STATES DEPARTMENT OF GQMMERCE

NOTICE OF ALLOWANCE AND ISSUFFEE DUE
THE APPLICATION IDENTIFIED ABOVE HAS BEEN EXAMINED AND IS ALLOWED FOR ISSUANCE AS A PATENT.
PROSECUTION ON THE MERITS IS CLOSED.
THE ISSUE FEE MUST BE PAID WITHIN THREE MONTHS FROM THE MAILING DATE OF THlS NOTICE OR THlS
APPLICATION SHALL BE REGARDED AS ABANDONED. THlS STATUTORY PERIOD CANNOT BE EXTENDED.
HOW TO RESPOND TO THIS NOTICE:

I. Review the SMALL ENTITY status shown above.
If the SMALL ENTITY is shown as YES, verify your
current SMALL ENTITY status:
If the SMALL ENTITY is shown as NO:
A. If the status is changed, pay twice the amount of the

FEE DUE shown above and notify the Patent and
Trademark Office of the change in status, or
B. If the status is the same, pay the FEE DUE shown
above.
A. Pay FEE
Or
6. File verified statement of Small Entity Status before, or with,

payment of 112 the FEE DUE shown above.
II. Part 6-Issue Fee Transmittal should be completed and returned to the Patent and Trademark Office (PTO) with your
ISSUE FEE. Even if the ISSUE FEE has already been paid by charge to deposit account, Part B Issue Fee Transmittal
should be completed and returned. If you are charging the ISSUE FEE to your deposit account, section " 4 b of Part
B-Issue Fee Transmittal should be completed and an extra copy of the form should be submitted.
Ill. All communications regarding this application must give application number and batch number.
Please direct all communications prior to issuance to Box ISSUE FEE unless advised to the contrary.
IMPORTANT REMINDER: Utility patents issuing on applications filed on or after Dec. 12, 198Qmay require payment of
maintenance fees. It is patentee's responsibility to ensure timely payment of maintenance
fees when due.
PTOL-85 (REV. 10-96) Approved for use through 06130199. (0651-0033)
PATENT AND TRADEMARK OFFICE COPY

*U.S.GOVERNMENT
PRINTING OFFICE 1997-433-221162716
PART B-58Ssf3 FEE TRANSMIITAL

'Complete and mail this form, together with app,.
Ae fees, to:
Box !%SUEFEE
Assistant Commissioner for Patenrs
MAILING INSTRUCTKINS: This form should be used for transmitting the ISSUE FEE. Blocks 1
through 4 should be completed where appropriate. All further correspondence including the lssue Fee
;and notification of maintenance fees will be mailed to the current
Receipt, the Patent, advance or
correspondence address as indicated unless corrected below or directed otherwise in Block 1, by (a)
specifying a new correspondence address; andlor (b) indicating a separate "FEE ADDRESS" for
maintenance fee notifications.
Note: The certificate of mailing below can only be used for domestic
mailings of the lssue Fee Transmittal. This certificate cannot be used
for any other accompanyingpapers. Each additionalpaper, such as an
assignment or formal drawing, must have its own certificate of mailing.
Certificate of Mailing
I hereby certify that this lssue Fee Transmittal is being deposited with
the United States Postal Service with sufficient postage for first class
mail in an envelope addressed to the Box lssue Fee address above on
the date indicated below.
CURRENT CORRESPONDENCE ADDRESS (Note: Legibly mark-up with any
PATENT LAW GROUP

D I G I T A L EQUIPMENT CBRPORAT
111 POWDERMILL ROAD M S 0 2 G
MAYNARD MA 01754-1499
(Date)
APPLICATION NO.
TOTAL CLAIMS
FILING DATE
2503
WHITEHEAD JR. C
009
First Named
Applicant
EXAMINER AND GROUP ART UNIT
DATE MAILED
02/02/98
D A V I D B.
KRAKAIJER,
PROTECTION CLAMP FOR M I X E D VOLTAGE I / O STAGES USING NMOS

l N V E N TI
' STORS
y~d~~
TlTLEoFESB
ATWS DOCKET NO.
CLASS-SUBCLASS
257-368.000
UTILITY
W96
FEE DUE
SMALL ENTITY
APPLN. TYPE
BATCH NO.
NO
$1320.00
DATE DUE
05/04/98
I
1. Change of correspondenceaddress or indication of ' Fee Address" (37 CFR 1.363).
Use of PTO form(s) and Customer Number are recommended, but not required.
2. For printing on the patent front page, list

(I) the names of up to 3 registered patent
attorneys or agents OR, alternatively, (2)
the name of a single firm (having as a
member a registered attorney or agent)
and the names of up to 2 registered patent
attorneysor agents. If no name is listed, no
name will be printed.
Change of correspondenceaddress (or Change of Correspondence Address form

PTOISBf122) attached.
0"Fee Address" indication (or "Fee Address" Indication form PTOISBf47) attached.
I
4a.The foilowmg fees are enclosed (make check payable to Commlssloner

of Patents and Trademarks):
I?
I?
lssue Fee
Advance Order - # of Coples
-
fBI RESIDENCE: (CITY & STATE OR COUNTRY)
L 11 ~dwciermill'Road, Maynard, ~ a s s a c h u s e t t,s 01 754, USA

Please check the appropriate assignee category indicated below (will not be printed on the patent)
4b The followmg fees or def~c~ency

In these fees should be charged to
ligital E s u i m e n t C o r n r a t i o n
corporation or other private group entity
C h r i s t p h e r J CiancioLo
---
3. ASSIGNEE NAME AND RESIDENCE DATA TO BE PRINTED ON THE PATENT (print or type)
PLEASE NOTE: Unless an assignee is identified below, no assignee data will appear on the patent.
Inclusion of assignee data is only appropiate when an assignment has been previously submitted to
the PTO or is being submitted under separate cover. Completion of this form is NOT a subsititue for
filing an assignment.
(A) NAME OF ASSIGNEE
individual
government
DEPOSIT ACCOUNT NUMBER

04-1 079
(ENCLOSE AN EXTRA COPY OF THlS FORM)
a
T
&
Issue Fee
Advance Order - # of Copies
1
0
The COMMISSIONER OF- PATENTS AND TRADEMARKS

IS reauested to amlv the lssue Fee to the ap~licationidentified above
I
{I
(puthonzed ~igjature)
J -'
'I
(Date) f
J .($ @ R G ~ .
,ch~&to~b?$,
L
.x:&-j
' 1
I
NOTE; The lssde Fee will not be accepted from anyone other than the applicant; a registeredattoGey
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Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE

Applicant:
David Krakauer
Serial No:
081555.463
Group Art unit:

Examiner:
2503
Whitehead, Jr., C.
Filed:
November 13, 1995
Title:
ESD PROTECTION CLAMP FOR MIXED VOLTAGE 110 STAGES USING

NMOS TRANSISTORS

MAIL in an envelope addressed to: Assistant
~ ~ ~ i ~ ~ for
i o patents,
n e r
Washington. D.C 202311 On:
May 4 , 1998
* * *
TRANSMITTAL LETTER
Sir:
Transmitted herewith for the above-identified application
and in response to Office Action dated February 2. 1998, are:
1) Notice of Allowance
2) Return postcard
The Assistant Commissioner for Patents is hereby authorized
to charge the TOTAL FEE of $1.350.00 and any other fees that may
be required by this paper to ~epositAccount No. 04-1079.
A11 future correspondence should be addressed to:

Christopher J. Cianciolo
Patent Law Group
,.
. * .
Date:..-J
I
/,'C
r/;;(,,
,[I.
Reg. No.: P42,417

Patent Law Group

978/493-9286
CJC : rmj

Applicant:
David Krakauer
Serial No:
08/555,463
Group Art Unit:

Examiner:
2503
Filed:
November 13, 1995
Whitehead, Jr., C.
Title:
ESD PROTECTION CLAMP FOR MIXED VOLTAGE 1/0 STAGES USING

NMOS TRANSISTORS
I hereby certify that this correspondence is 1

deposited with the United States Postal Service as 1
CLASS MAIL in an envelope addressed to: Assi:
Commissioner for Patents, Washington, D.C. 20231, or
Date of mailing:
May 4 , 1998
* * *
TRANSMITTAL LETTER
Sir:
Transmitted herewith for the above-identified application
and in response to Office Action dated February 2, 1998, are:
1) Notice of Allowance
2) Return Postcard
The Assistant Commissioner for Patents is hereby authorized
to charge the TOTAL FEE of $1,350.00 and any other fees that may
be required by this paper to Deposit Account No. 04-1079.
All future correspondence should be addressed to:

Patent Law Group
By :
. Cianciolo"
Reg. No.: P42,417
Patent Law Group

978/493-9286
CJC :rmj
Applicant: Krakauer
Serial No.: 08/555,463
Group Art Unit: 2503
Filed: November 13, 1995
Date Of Notice
Eatch No.: W96
Of Allowance: February 2 , 1998
ESD Protection Clamp for Mixed Voltage I/O Stages
Using NMOS Transistors
Title:
I hereby certify that this correspondence is

Service as FIRST CLASS MAIL in an envelope
addressed to: Assistant Commissioner for
Patents, Washington, D.C. 20231, on:
Mary E. Hadad
TRANSMITTAL OF FORMAL DRAWING(S) TO CORRECT INFORMALITIES

ATTN:
Official Draftsperson
Enclosed herewith are formal drawings for the aboveidentified patent application.
PLG - 1 / 9 3
DRW-XMTL.FRM
The enclosed drawings correct the informalities as

noted ,in the Draftsperson's objection(s):
[
[XI
on PTO-948 dated >.

on Office Letter dated February 2, 1998.
11.
Number of sheets of drawing submitted Respectfully submitted,
Reg. No.: P42, 417
Date: March 26, 1998
Patent Law Group
(508) 493-9286
CJC :meh
PLG - 1 / 9 3
DRW-XMTL.FRM
APPROVED
F/rj
CL,iSS Sijb,
DRAFTSMAN
/ 6 MIXED VOLTAGE
INTERATED CIRCUIT
,
I
.28\11/=
DRAIN 34
I
I
Vdd
'OURCE
DRAIN 24
2o
30
I
I
I
I
I
,'
18 SHARED
DIFFUSION
vss
SOURCE 32
1\14
Figure 2
I
I
GATE
DEPLETION REGION
. . . -72
I -
Figure 6
DEPLETION REGION
".- ......-. .. . .
26
32
18
GATE
24
i 20
22
- UO PAD
,GAT:
/ 34
oR
.. .. .. D ~ I N SOUR&. - .. .. , .. ...-. 181 NMOS
..
NMOS
....,...
. .DEPLETION
REGION
DEPLETION REGION . .-.''... . DEPLETION REGION - .- '
- .- ...
* _ . - . . - . ..-
.- . . . . . _ . . ., . -_ . . .
s o u R c k
I NMOS
' a .
PMOS S~JBSTRATE
Figure 7
DRAIN
CURRENT
84
90
PUNCH-THROUGH
TRIGGER
VOLTAGE
HOLDING
VOLTAGE
\ 88
Figure 9
DRAIN TO
SOURCE
VOLTAGE
P..
j1
I
I
I
SHARED
DIFFUSION
I
I
I
DRAIN
I
GATE 1
SOURCE
DRAIN
L A 2 2
I'
GATE 2
I
GATE 1
SHARED
DIFFUSION
I
I
SOURCE
DRAIN
GATE 2
SOURCE
Figure 11
The Commissioner of Patents

and Trademarks
Has received an applicationfor a patent for a
new and useful invention The title and description of the invention are enclosed The
requirements of law have been complied with,
and it has been determined that a patent on
the invention shall be granted under the law.
Therefore, this
United States Patent

Grants to the person(s) having title to this
patent the right to exclude others from making, using, offeringfor sale, or selling the invention throughout the United States of
America or importing the invention into the
UnitedStates of America for the term set forth
below, subject to the payment of maintenance
fees as provided by law.
If this application was filed prior to June 8,

1995, the term of this patent is the longer of
seventeen years from the date of grant of this
patent or twenty years from the earliest effective U.S. filing date of the application, subject to any statutory extension.
If this application was filed
on or afier June
8,1995, the term of this patent is twenryyears
from the US. filing date, subject to an statutory extension. I f the application contains a
specific reference to an earlierfiled application or applicationsunder 35 U.S.C. 120,121
or 365(c),the term of theparent is twenty years
from the date on which the earliest application wasfiled, subject to any statutory extension.
Commissioner of Parenrs and Trademarks
PATENT APPLICATION
Docket No.: DEC98-68 (PD95-0080)
..

nt:
David B. fiakauer
Application No.:
Filed:
081555,463
Group Unit: 2503
November 13, 1995
Examiner:
Patent No.: 5,780,897

T~tle:
./'
Whitehead, Jr. C.
Issue Date: July 14, 1998
ESD PROTECTION CLAMP FOR MIXED VOLTAGE I10 STAGES USING NMOS
TRANSISTORS
CERTIFICATE OF MAILING
I hereby certify that this correspondence is being deposited with
the United States Postal Service with sufficient postage as First
Class Mail in an envelope addressed to Assistant Commissioner
for Patents, Washington, D.C. 20231 on
1-4-79
Date
ASSOCIATE P O W E R O F ATTORNEY AND

CHANGE O F CORRESPONDENCE ADDRESS
Washington, D.C. 2023 1
Sir:
Associate Power of Attorney
An Associate Power of Attorney is hereby granted to all attorneys andlor agents associated with the film of
Hamilton, Brook, Smith & Reynolds, P.C., Customer No. 21005.
Change of C o r r e s ~ o n d e n c eA d m
Please note a change in correspondmce address and direct all future correspondence to Mary Lou
Wakimura, Esq., Hamilton, Brook, Smith & Reynolds, P.C., Two Militia Drive, Lexington, MA 02421-4799.
Please d~rectall telephone calls to Mary Lou Wakimura at (781) 861-6240.
Registration No.: 27,072

Telephone (78 1) 861-6240
Facsimile (78 1) 86 1-9540
Lexington, Massachusetts
f-4.1999.
Date:
PATENT APPLICATION
'. y + y
~ $ 3 ~
ant:

David B. Krakauer
Application No.:
Filed:
081555,463
Group Unit: 2503

Examiner:
November 13, 1995
Patent No.: 5,780,897

Title:
/'
COPY FOR ~ONTINUI~~
Whitehead, Jr. C.
APPl/~
ESD PROTECTION CLAMP FOR MIXED VOLTAGE I/O STAGES USING NMOS
TMNSISTORS
I hereby certify that this correspondence is bang deposited with

Class Mail in an envelope addressed to Assistant commissioner
1-4-79
Date
ASSOCIATE POWER OF ATTORNEY AND

CHANGE OF CORRESPONDENCE ADDRESS
Sir:
Associate Power of Attornev
An Associate Power of Attorney is hereby granted to all attorneys andor agents associated with the firm of
Change of Correspondence Address
Please note a change in correspondence address and direct all future correspondence to Mary Lou
Wakimura, Esq., Hamilton, Brook, Smith & Reynolds, P.C., Two Militia Drive, Lexington, MA 02421-4799.
Please direct all telephone calls to Mary Lou Walumura at (781) 861-6240.

Telephone (781) 861-6240
Facsimile (78 1) 861-9540
Lexington, iMassachusetts
fm4-.10/94.
Date:
PATENT APPLICATION
INTHE UNITED STATES PATENT AND TRADEMARK OFFICE

\
Applicant:
David B. Krakauer
Application No.:
Filed:
081555,463
Group Unit: 2503
November 13, 1995
Examiner:
Patent No.: 5,780,897

.-
_-.
COPY FOR CONTINUING

APPLICATION
Whitehead, Jr. C.
6"
Title:
ESD PROTECTION CLAMP FOR MIXED VOLTAGE 110 STAGES U S N G NMOS

TRANSISTORS
I hereby certify that this correspondence is being deposited with

Class Mail in an envelope addressed to Assistant Commissioner
I-'i-99
Date
ASSOCIATE POWER OF ATTORNEY AND

Sir:
Associate Power of Attorney
An Associate Power of Attorney is hereby granted to all attorneys andlor agents associated with the firm of
Chanpe of Corres~ondenceAddress
Please note a change in correspondence address and direct all future correspondence to Mary Lou
Wakirnura, Esq., Hamilton, Brook, Smith & Reynolds, P.C., Two Militia Drive, Lexington, MA 02421-4799.
Please direct all telephone calls to Mary Lou Wakirnura at (781) 861-6240.

Telephone (78 1) 861-6240
Facsimile (78 1) 861-9540
Lexington, Massachusetts
f- 4:. I 7 9 9
Date:
&PFDeslctop\ O D M A / M H O D M A / H B S R O S , I M
.6,1
PATENT
D O C K E T N O 0 9 18 1 167-000
JMSipcl
Mdy 15.2006
J
N THE UNITED STATES PATENT AND TRADEMARK OFFICE
Applicant :
David Benjamin
Patent No.:
5,780,897
Application No.:
081555,463
Issued :
July 14, 1998
Filing Date:
November 13, 1995
For:
ESD Protection Clam
Voltage YO Stages Usmg NMOS Transistors
CERTIFICATE OF MAILING OR TRANSMISSION

I liei-eby certii'y that this correspondence is being deposited with tllc
IJnitcd States Postal Service with sufficient postage as I'ii-si Class Ma11
in an envelope addressed to Commissioiier for Pateiits, P 0 BOY 1450,
Alexandria, V.4 22313.1450, or is being facs~miletransiniited to the
United States P tent and Trad
-c / i Sd a tOL
e
Signatlire
Pamela E. Ross
Typed or printed name of person signing certificate

Mail Stop Post Issue
Commissioner for Patents
P.O. Box 1450
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Sir:
Please change the correspondence address for the above captioned patent as follows:
All coi-respondeilce should be sent to Hewlett-Pacltard Company, Lntellectual Property
Administration, P.O. Box 272400, Fort Collins, Colorado 80527-2400. Please direct all
telephone calls to L. Joy Griebenow, Esq., at (970) 898-3884, and all facsimile communications
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Respectf~dlysubmitted,
HAMILTON, BROOK, SMITH Rc REYNOLDS, P.C
Mary Lou ~ & i m u r a

Registration No.: 3 1,804
Telephone: (978) 34 1-0036
Facsimile: (978) 34 1-0136
Concord, MA 0 1 742-9 133

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APPROVED FOR LICENSE

(Through nurnberal) Canceled

a$@ " -..

United States Patent

[54] ESD PROTECTION CLAMP FOR MIXED

David Benjamin Krakauer.

[73] Assignee: Digital Equipment Corporation.

[21] AppL No.: 555,463

Nov. 13, 1995

[511 Int. CL6 .....................................................

12/1986 Bell et al. ................................. 361/56

Primary Emminer-Carl W. Whitehead

Attorney, Agent, or F i r 4 h r i s t o p h e r J. Cianciolo

An electrostatic discharge protection device for protecting a

Jul. 14, 1998

Jul. 14, 1998

Jul. 14, 1998

JUI. 14, 1998

Jul. 14, 1998

Jul. 14, 1998

Jul. 14, 1998

Jul. 14, 1998

ing diode conducts. Jn this circumstance. the conducting

ESD PROTECTION CLAMP FOR MIXED

A protection device is needed which is acceptable for use

SUMMARY OF THE: INVENTION

BRIEF DESCRIPTION OF THI3 DRAWINGS

FIG. 1 depicts a block diagram of a computer system in

The cascc.de configuration of the present invention is

skill in the art that other embodiments incorporating its

the gate regions of a plurality of pairs of NMOS

PATENT APPLICATION SERIAL NO.

a l s o i n c l u d e s a second NMOS t r a n s i s t o r , merged i n t o t h e same

used e i t h e r a s a s e l f p r o t e c t i n g pull-down p o r t i o n of a mixed

BACKGROUND OF THE INVENTION

This invention r e l a t e s generally t o i n t e g r a t e d c i r c u i t s

hence computer systems, w e r e h i s t o r i c a l l y designed t o o p e r a t e

computer, t h e hand h e l d video game, and t h e p o r t a b l e telephone

were able t o m e e t t h e s e c h a l l e n g e s by reducing t h e geometry of

u s i n g t h e new standards, devices designed f o r use with t h e o l d

mixed s t a n d a r d systems, i n t e g r a t e d c i r c u i t d e s i g n e r s needed t o

One of t h e main problems with i n t e g r a t e d c i r c u i t s has

magnitude, t h e oxide within t h e t r a n s i s t o r breaks down and t h e

There a r e two t y p e s of mixed v o l t a g e I C f s which employ

t h e 1/0 area operates a t a d i f f e r e n t , usually higher, voltage.

low power supply f o r t h e c o r e l o g i c a r e a and a high power

only a low power supply i s provided and t h e e x t e r n a l 1 / 0

a r e a i s designed t o be t o l e r a n t o f , and p r o t e c t e d from, high

d i f f i c u l t y f o r providing robust ESD p r o t e c t i o n a s w i l l be

Two diodes a r e formed a t t h e 1 / 0 pad where one i s

connected t o ground and t h e o t h e r t o t h e supply v o l t a g e .

anode of a f i r s t diode i s connected t o t h e 1 / 0 pad while t h e

second diode i s connected t o t h e same I / O pad while i t s anode

During an ESD event, when t h e v o l t a g e

on t h e 1 / 0 pad reaches a value h i g h e r t h a n t h e supply v o l t a g e

o r lower t h a n ground l e v e l , t h e corresponding diode conducts.

e i t h e r t o t h e supply v o l t a g e plane o r t o t h e ground plane t o