dsPIC30F5011, dsPIC30F5013

dsPIC30F5011, dsPIC30F5013
Data Sheet
High-Performance
Digital Signal Controllers
2004 Microchip Technology Inc.
Preliminary
DS70116D
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device

applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Companys quality system processes and
procedures are for its PICmicro 8-bit MCUs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70116D-page ii
Preliminary
dsPIC30F5011/5013
dsPIC30F5011/5013 High Performance
Digital Signal Controllers
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30F
Programmers Reference Manual (DS70030).
High Performance Modified RISC CPU:
Modified Harvard architecture

C compiler optimized instruction set architecture
Flexible addressing modes
84 base instructions
24-bit wide instructions, 16-bit wide data path
66 Kbytes on-chip Flash program space
4 Kbytes of on-chip data RAM
1 Kbytes of non-volatile data EEPROM
16 x 16-bit working register array
Up to 30 MIPs operation:
- DC to 40 MHz external clock input
- 4 MHz-10 MHz oscillator input with
PLL active (4x, 8x, 16x)
Up to 41 interrupt sources:
- 8 user selectable priority levels
- 5 external interrupt sources
- 4 processor traps
DSP Features:
Dual data fetch
Modulo and Bit-reversed modes
Two 40-bit wide accumulators with optional
saturation logic
17-bit x 17-bit single cycle hardware fractional/
integer multiplier
All DSP instructins are single cycle
- Multiply-Accumulate (MAC) operation
Single cycle 16 shift
Peripheral Features:
High current sink/source I/O pins: 25 mA/25 mA
Five 16-bit timers/counters; optionally pair up 16bit timers into 32-bit timer modules
16-bit Capture input functions
16-bit Compare/PWM output functions:
Data Converter Interface (DCI) supports common
audio Codec protocols, including I2S and AC97
3-wire SPI modules (supports 4 Frame modes)
I2C module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
Two addressable UART modules with FIFO
buffers
Two CAN bus modules compliant with CAN 2.0B
standard
Analog Features:
12-bit Analog-to-Digital Converter (A/D) with:
- 100 Ksps conversion rate
- Up to 16 input channels
- Conversion available during Sleep and Idle
Programmable Low Voltage Detection (PLVD)
Programmable Brown-out Detection and Reset
generation
Special Microcontroller Features:

Enhanced Flash program memory:
- 10,000 erase/write cycle (min.) for
industrial temperature range, 100K (typical)
Data EEPROM memory:
- 100,000 erase/write cycle (min.) for
industrial temperature range, 1M (typical)
Self-reprogrammable under software control
Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
Flexible Watchdog Timer (WDT) with on-chip low
power RC oscillator for reliable operation
Preliminary
DS70116D-page 1
dsPIC30F5011/5013
Special Microcontroller Features (Cont.):
CMOS Technology:
Fail-Safe Clock Monitor operation:

- Detects clock failure and switches to on-chip
low power RC oscillator
Programmable code protection
In-Circuit Serial Programming (ICSP)
Selectable Power Management modes:
- Sleep, Idle and Alternate Clock modes
Low power, high speed Flash technology

Wide operating voltage range (2.5V to 5.5V)
Industrial and Extended temperature ranges
Low power consumption
dsPIC30F5011/5013 Controller Family

SPI
I2C
CAN
Output
SRAM EEPROM Timer Input
Codec A/D 12-bit
Comp/Std
Bytes
16-bit Cap
Interface 100 Ksps
Bytes Instructions Bytes
PWM
Pins
UART
Program Memory
Device
dsPIC30F5011
64
66K
22K
4096
1024
AC97, I2S
16 ch
dsPIC30F5013
80
66K
22K
4096
1024
AC97, I2S
16 ch
DS70116D-page 2
Preliminary
dsPIC30F5011/5013
Pin Diagrams
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CSDO/RG13
CSDI/RG12
CSCK/RG14
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VSS
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
EMUD2/OC2/RD1
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC30F5011
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/T4CK/CN1/RC13
EMUC2/OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKI
VDD
SCL/RG2
SDA/RG3
EMUC3/SCK1/INT0/RF6
U1RX/SDI1/RF2
EMUD3/U1TX/SDO1/RF3
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/CN17/RF4
U2TX/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
COFS/RG15
T2CK/RC1
T3CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
Note:
For descriptions of individual pins, see Section 1.0.
Preliminary
DS70116D-page 3
dsPIC30F5011/5013
Pin Diagrams (Continued)
IC5/RD12
OC4/RD3
OC3/RD2
EMUD2/OC2/RD1
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
OC7/CN15/RD6
CSCK/RG14
CN23/RA7
CN22/RA6
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VSS
OC8/CN16/RD7
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
CSDO/RG13
CSDI/RG12
80-Pin TQFP
COFS/RG15
T2CK/RC1
T3CK/RC2
T4CK/RC3
T5CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
5
6
SS2/CN11/RG9
VSS
10
VDD
12
INT1/RA12
13
INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
59
EMUD1/SOSCI/CN1/RC13
58
EMUC2/OC1/RD0
57
56
IC4/RD11
IC3/RD10
55
IC2/RD9
54
IC1/RD8
53
INT4/RA15
52
INT3/RA14
VSS
51
dsPIC30F5013
11
60
49
OSC2/CLKO/RC15
OSC1/CLKI
48
VDD
50
14
15
16
17
47
SCL/RG2
46
SDA/RG3
45
44
EMUC3/SCK1/INT0/RF6
SDI1/RF7
Note:
29
30
31
32
33
34
35
36
37
38
39
40
VSS
VDD
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
IC7/CN20/RD14
IC8/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
28
AN11/RB11
27
AN9/RB9
AN10/RB10
26
AVDD
AVSS
25
AN8/RB8
24
U1TX/RF3
VREF+/RA10
41
23
20
VREF-/RA9
U1RX/RF2
PGD/EMUD/AN0/CN2/RB0
21
EMUD3/SDO1/RF8
42
22
43
19
AN7/RB7
18
AN6/OCFA/RB6
PGC/EMUC/AN1/CN3/RB1
For descriptions of individual pins, see Section 1.0.
DS70116D-page 4
Preliminary
dsPIC30F5011/5013
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 CPU Architecture Overview........................................................................................................................................................ 13
3.0 Memory Organization ................................................................................................................................................................. 23
4.0 Address Generator Units............................................................................................................................................................ 35
5.0 Interrupts .................................................................................................................................................................................... 41
6.0 Flash Program Memory.............................................................................................................................................................. 47
7.0 Data EEPROM Memory ............................................................................................................................................................. 53
8.0 I/O Ports ..................................................................................................................................................................................... 59
9.0 Timer1 Module ........................................................................................................................................................................... 65
10.0 Timer2/3 Module ........................................................................................................................................................................ 69
11.0 Timer4/5 Module ....................................................................................................................................................................... 75
12.0 Input Capture Module................................................................................................................................................................. 79
13.0 Output Compare Module ............................................................................................................................................................ 83
14.0 SPI Module................................................................................................................................................................................. 87
15.0 I2C Module ................................................................................................................................................................................. 91
16.0 Universal Asynchronous Receiver Transmitter (UART) Module ................................................................................................ 99
17.0 CAN Module ............................................................................................................................................................................. 107
18.0 Data Converter Interface (DCI) Module.................................................................................................................................... 119
19.0 12-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 129
20.0 System Integration ................................................................................................................................................................... 135
21.0 Instruction Set Summary .......................................................................................................................................................... 151
22.0 Development Support............................................................................................................................................................... 159
23.0 Electrical Characteristics .......................................................................................................................................................... 165
24.0 Packaging Information.............................................................................................................................................................. 205
Index .................................................................................................................................................................................................. 209
On-Line Support................................................................................................................................................................................. 215
Systems Information and Upgrade Hot Line ...................................................................................................................................... 215
Reader Response .............................................................................................................................................................................. 216
Product Identification System ............................................................................................................................................................ 217
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Preliminary
DS70116D-page 5
dsPIC30F5011/5013
NOTES:
DS70116D-page 6
Preliminary
dsPIC30F5011/5013
1.0
DEVICE OVERVIEW

This document contains specific information for the

dsPIC30F5011/5013 Digital Signal Controller (DSC)
devices. The dsPIC30F5011/5013 devices contain
extensive Digital Signal Processor (DSP) functionality
within a high performance 16-bit microcontroller (MCU)
architecture. Figure 1-1 and Figure 1-2 show device
block diagrams for dsPIC30F5011 and dsPIC30F5013
respectively.
Preliminary
DS70116D-page 7
dsPIC30F5011/5013
FIGURE 1-1:
dsPIC30F5011 BLOCK DIAGRAM

Y Data Bus
X Data Bus
16
16
Interrupt
Controller
PSV & Table

Data Access
24 Control Block
Data Latch
Y Data
RAM
(4 Kbytes)
Address
Latch
16
24
Address Latch
Data EEPROM
(4 Kbytes)
AN0/CN2/RB0
AN1/CN3/RB1
AN3/CN5/RB3
AN4/CN6/RB4
AN5/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
16
16
X RAGU
X WAGU
Y AGU
PCU PCH PCL

Program Counter
Loop
Stack
Control
Control
Logic
Logic
Data Latch
X Data
RAM
(4 Kbytes)
Address
Latch
16
16
24
Program Memory
(66 Kbytes)
16
16
Effective Address
16
Data Latch
ROM Latch
PORTB
16
24
IR
16
16 x 16
W Reg Array
Decode
PORTC
Instruction
Decode &
Control
16 16
Control Signals
to Various Blocks
OSC1/CLKI
Power-up
Timer
DSP
Engine
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
OC8/CN16/RD7
IC1/RD8
IC2/RD9
IC3/RD10
IC4/RD11
Divide
Unit
Oscillator
Start-up Timer
Timing
Generation
ALU<16>
POR/BOR
Reset
MCLR
VDD, VSS
AVDD, AVSS
CAN1,
CAN2
T2CK/RC1
T3CK/RC2
OSC2/CLKO/RC15
16
Watchdog
Timer
Low Voltage
Detect
12-bit ADC
Timers
Input
Capture
Module
DCI
16
16
PORTD
Output
Compare
Module
I2C
SPI1,
SPI2
UART1,
UART2
C1RX/RF0
C1TX/RF1
U1RX/SDI1/RF2
EMUD3/U1TX/SDO1/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
PORTF
C2RX/RG0
C2TX/RG1
SCL/RG2
SDA/RG3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
SS2/CN11/RG9
CSDI/RG12
CSDO/RG13
CSCK/RG14
COFS/RG15
PORTG
DS70116D-page 8
Preliminary
dsPIC30F5011/5013
FIGURE 1-2:
dsPIC30F5013 BLOCK DIAGRAM

CN22/RA6
CN23/RA7
VREF-/RA9
VREF+/RA10
INT1/RA12
INT2/RA13
INT3/RA14
INT4/RA15
Y Data Bus
X Data Bus
Interrupt
Controller
PSV & Table

Data Access
24 Control Block
16
16
16
Data Latch
Y Data
RAM
(4 Kbytes)
Address
Latch
16
24
24
Address Latch
Data EEPROM
(4 Kbytes)
16
PORTA
PGD/EMUD/AN0/CN2/RB0
PGC/EMUC/AN1/CN3/RB1
AN3/CN5/RB3
AN4/CN6/RB4
AN5/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
16
X RAGU
X WAGU
Y AGU
PCU PCH PCL

Program Counter
Loop
Stack
Control
Control
Logic
Logic
Data Latch
X Data
RAM
(4 Kbytes)
Address
Latch
16
16
Program Memory
(66 Kbytes)
16
Effective Address
16
Data Latch
ROM Latch
16
24
PORTB
T2CK/RC1
T3CK/RC2
T4CK/RC3
T5CK/RC4
OSC2/CLKO/RC15
IR
16
16
16 x 16
W Reg Array
Decode
Instruction
Decode &
Control
Control Signals
to Various Blocks
OSC1/CLKI
Power-up
Timer
DSP
Engine
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
OC8/CN16/RD7
IC1/RD8
IC2/RD9
IC3/RD10
IC4/RD11
IC5/RD12
IC6/CN19/RD13
IC7/CN20/RD14
IC8/CN21/RD15
Divide
Unit
Oscillator
Start-up Timer
Timing
Generation
ALU<16>
POR/BOR
Reset
MCLR
VDD, VSS
AVDD, AVSS
CAN1,
CAN2
PORTC
16 16
Watchdog
Timer
Low Voltage
Detect
12-bit ADC
Timers
16
16
PORTD
Input
Capture
Module
DCI
Output
Compare
Module
I2C
SPI1,
SPI2
UART1,
UART2
C1RX/RF0
C1TX/RF1
U1RX/RF2
U1TX/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
SDI1/RF7
EMUD3/SDO1/RF8
PORTF
C2RX/RG0
C2TX/RG1
SCL/RG2
SDA/RG3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
SS2/CN11/RG9
CSDI/RG12
CSDO/RG13
CSCK/RG14
COFS/RG15
PORTG
Preliminary
DS70116D-page 9
dsPIC30F5011/5013
Table 1-1 provides a brief description of device I/O
pinouts and the functions that may be multiplexed to a
port pin. Multiple functions may exist on one port pin.
When multiplexing occurs, the peripheral modules
functional requirements may force an override of the
data direction of the port pin.
TABLE 1-1:
PINOUT I/O DESCRIPTIONS

Pin
Type
Buffer
Type
AN0-AN15
Analog
Pin Name
Description
Analog input channels.
AN0 and AN1 are also used for device programming data and
clock inputs, respectively.
AVDD
AVSS
CLKI
ST/CMOS
CLKO
CN0-CN23
ST
Input change notification inputs.

Can be software programmed for internal weak pull-ups on all
inputs.
COFS
CSCK
CSDI
CSDO
I/O
I/O
I
O
ST
ST
ST
Data Converter Interface Frame Synchronization pin.

Data Converter Interface Serial Clock input/output pin.
Data Converter Interface Serial data input pin.
Data Converter Interface Serial data output pin.
C1RX
C1TX
C2RX
C2TX
I
O
I
O
ST
ST
CAN1 Bus Receive pin.

CAN1 Bus Transmit pin.
CAN2 Bus Receive pin.
CAN2 Bus Transmit pin
EMUD
EMUC
EMUD1
I/O
I/O
I/O
ST
ST
ST
EMUC1
EMUD2
EMUC2
EMUD3
I/O
I/O
I/O
I/O
ST
ST
ST
ST
EMUC3
I/O
ST
ICD Primary Communication Channel data input/output pin.

ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data
input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
ICD Quaternary Communication Channel data
input/output pin.
ICD Quaternary Communication Channel clock input/output pin.
IC1-IC8
ST
Capture inputs 1 through 8.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
LVDIN
Analog
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This

pin is an active low Reset to the device.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
Compare Fault A input (for Compare channels 1, 2, 3 and 4).

Compare Fault B input (for Compare channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
Legend:
Positive supply for analog module.

Ground reference for analog module.
External clock source input. Always associated with OSC1 pin
function.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC
and EC modes. Always associated with OSC2 pin
function.
Low Voltage Detect Reference Voltage input pin.
CMOS = CMOS compatible input or output

ST
= Schmitt Trigger input with CMOS levels
I
= Input
DS70116D-page 10
Analog = Analog input

O
= Output
P
= Power
Preliminary
dsPIC30F5011/5013
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin
Type
Buffer
Type
OSC1
ST/CMOS
OSC2
I/O
Oscillator crystal input. ST buffer when configured in RC mode;

CMOS otherwise.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC
and EC modes.
PGD
PGC
I/O
I
ST
ST
In-Circuit Serial Programming data input/output pin.

In-Circuit Serial Programming clock input pin.
RA6-RA7
RA9-RA10
RA12-RA15
I/O
I/O
I/O
ST
ST
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
RC1-RC4
RC13-RC15
I/O
I/O
ST
ST
PORTC is a bidirectional I/O port.
RD0-RD15
I/O
ST
PORTD is a bidirectional I/O port.
RF0-RF8
I/O
ST
PORTF is a bidirectional I/O port.
RG0-RG3
RG6-RG9
RG12-RG15
I/O
I/O
I/O
ST
ST
ST
PORTG is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I
I/O
I
O
I
ST
ST
ST
ST
ST
ST
Synchronous serial clock input/output for SPI1.

SPI1 Data In.
SPI1 Data Out.
SPI1 Slave Synchronization.
Synchronous serial clock input/output for SPI2.
SPI2 Data In.
SPI2 Data Out.
SPI2 Slave Synchronization.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C.

Synchronous serial data input/output for I2C.
SOSCO
SOSCI
O
I
ST/CMOS
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
Timer1 external clock input.

U1RX
U1TX
U1ARX
U1ATX
U2RX
U2TX
I
O
I
O
I
O
ST
ST
ST
UART1 Receive.
UART1 Transmit.
UART1 Alternate Receive.
UART1 Alternate Transmit.
UART2 Receive.
UART2 Transmit.
VDD
Positive supply for logic and I/O pins.
VSS
Ground reference for logic and I/O pins.
VREF+
Analog
Analog Voltage Reference (High) input.
Analog
Analog Voltage Reference (Low) input.
Pin Name
VREF-
Legend:
Description
32 kHz low power oscillator crystal output.

32 kHz low power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.
CMOS = CMOS compatible input or output

ST
= Schmitt Trigger input with CMOS levels
I
= Input
Analog = Analog input

O
= Output
P
= Power
Preliminary
DS70116D-page 11
dsPIC30F5011/5013
NOTES:
DS70116D-page 12
Preliminary
dsPIC30F5011/5013
2.0
CPU ARCHITECTURE
OVERVIEW
There are two methods of accessing data stored in

program memory:

2.1
Core Overview
This section contains a brief overview of the CPU

architecture of the dsPIC30F. For additional hardware and programming information, please refer to
the dsPIC30F Family Reference Manual and
the dsPIC30F Programmers Reference Manual
respectively.
The core has a 24-bit instruction word. The Program
Counter (PC) is 23-bits wide with the Least Significant
(LS) bit always clear (refer to Section 3.1), and the
Most Significant (MS) bit is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction
words of user program space. An instruction pre-fetch
mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and
REPEAT instructions, both of which are interruptible at
any point.
The working register array consists of 16 x 16-bit registers, each of which can act as data, address or offset
registers. One working register (W15) operates as a
software stack pointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely
through the X memory, AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2). The X and Y data space boundary is
device specific and cannot be altered by the user. Each
data word consists of 2 bytes, and most instructions
can address data either as words or bytes.
The upper 32 Kbytes of data space memory can

be mapped into the lower half (user space) of program space at any 16K program word boundary,
defined by the 8-bit Program Space Visibility Page
(PSVPAG) register. This lets any instruction
access program space as if it were data space,
with a limitation that the access requires an additional cycle. Moreover, only the lower 16 bits of
each instruction word can be accessed using this
method.
Linear indirect access of 32K word pages within
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
Overhead-free circular buffers (modulo addressing) are
supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports bit-reversed addressing on
destination effective addresses to greatly simplify input
or output data reordering for radix-2 FFT algorithms.
Refer to Section 4.0 for details on modulo and
bit-reversed addressing.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct, Register Direct, Register
Indirect, Register Offset and Literal Offset Addressing
modes. Instructions are associated with predefined
Addressing modes, depending upon their functional
requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working register (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A+B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the accumulator or any working register can be shifted up to 15 bits
right, or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear for all others. This has been
achieved in a transparent and flexible manner, by dedicating certain working registers to each address space
for the MAC class of instructions.
Preliminary
DS70116D-page 13
dsPIC30F5011/5013
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction pre-fetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle with certain
exceptions.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest), in conjunction with a predetermined natural
order. Traps have fixed priorities ranging from 8 to 15.
2.2
Programmers Model
The programmers model is shown in Figure 2-1 and

consists of 16 x 16-bit working registers (W0 through
W15), 2 x 40-bit accumulators (AccA and AccB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT) and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
PUSH.S and POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
DO instruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start, and popped on loop end.
2.2.1
SOFTWARE STACK POINTER/

FRAME POINTER
The dsPIC devices contain a software stack. W15 is

the dedicated software Stack Pointer (SP), and will be
automatically modified by exception processing and
subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the stack pointer (e.g., creating
stack frames).
Note:
In order to protect against misaligned

stack accesses, W15<0> is always clear.
W15 is initialized to 0x0800 during a Reset. The user

may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a stack frame pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2
STATUS REGISTER
The dsPIC core has a 16-bit STATUS register (SR), the

LS Byte of which is referred to as the SR Low byte
(SRL) and the MS Byte as the SR High byte (SRH).
See Figure 2-1 for SR layout.
SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Priority Level status bits, IPL<2:0> and the Repeat Active
status bit, RA. During exception processing, SRL is
concatenated with the MS Byte of the PC to form a
complete word value which is then stacked.
The upper byte of the STATUS register contains the
DSP Adder/Subtracter status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) status bit.
2.2.3
PROGRAM COUNTER
The program counter is 23-bits wide; bit 0 is always

clear. Therefore, the PC can address up to 4M
instruction words.
When a byte operation is performed on a working register, only the Least Significant Byte of the target register is affected. However, a benefit of memory mapped
working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide
data memory space accesses.
DS70116D-page 14
Preliminary
dsPIC30F5011/5013
FIGURE 2-1:
PROGRAMMERS MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
AD39
AD15
AD31
AD0
AccA
DSP
Accumulators
AccB
PC22
PC0
Program Counter
0
0
7
TABPAG
TBLPAG
7
Data Table Page Address

0
PSVPAG
Program Space Visibility Page Address

15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
DC IPL2 IPL1 IPL0 RA
OV
Status Register
SRL
Preliminary
DS70116D-page 15
dsPIC30F5011/5013
2.3
Divide Support
The dsPIC devices feature a 16/16-bit signed fractional

divide operation, as well as 32/16-bit and 16/16-bit
signed and unsigned integer divide operations, in the
form of single instruction iterative divides. The following
instructions and data sizes are supported:
1.
2.
3.
4.
5.
DIVF - 16/16 signed fractional divide

DIV.sd - 32/16 signed divide
DIV.ud - 32/16 unsigned divide
DIV.sw - 16/16 signed divide
DIV.uw - 16/16 unsigned divide
The divide instructions must be executed within a

REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT instruction as shown in Table 2-1 (REPEAT will execute the target instruction {operand value+1} times). The REPEAT
loop count must be setup for 18 iterations of the DIV/
DIVF instruction. Thus, a complete divide operation
requires 19 cycles.
The 16/16 divides are similar to the 32/16 (same number

of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
TABLE 2-1:
The divide flow is interruptible. However,

the user needs to save the context as
appropriate.
DIVIDE INSTRUCTIONS
Instruction
DIVF
Note:
Function
Signed fractional divide: Wm/Wn W0; Rem W1
DIV.sd
Signed divide: (Wm+1:Wm)/Wn W0; Rem W1
DIV.sw or
DIV.s
Signed divide: Wm/Wn W0; Rem W1
DIV.ud
Unsigned divide: (Wm+1:Wm)/Wn W0; Rem W1
DIV.uw or
DIV.u
Unsigned divide: Wm/Wn W0; Rem W1
DS70116D-page 16
Preliminary
dsPIC30F5011/5013
2.4
DSP Engine
The DSP engine consists of a high speed 17-bit x

17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The DSP engine also has the capability to perform
inherent
accumulator-to-accumulator
operations,
which require no additional data. These instructions are
ADD, SUB and NEG.
The dsPIC30F is a single-cycle instruction flow architecture, threfore, concurrent operation of the DSP
engine with MCU instruction flow is not possible.
However, some MCU ALU and DSP engine resources
may be used concurrently by the same instruction (e.g.,
ED, EDAC).
TABLE 2-2:
The DSP engine has various options selected through

various bits in the CPU Core Configuration register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
Fractional or integer DSP multiply (IF).

Signed or unsigned DSP multiply (US).
Conventional or convergent rounding (RND).
Automatic saturation on/off for AccA (SATA).
Automatic saturation on/off for AccB (SATB).
Automatic saturation on/off for writes to data
memory (SATDW).
Accumulator Saturation mode selection
(ACCSAT).
7.
Note:
For CORCON layout, see Table 4-2.
A block diagram of the DSP engine is shown in

Figure 2-2.
DSP INSTRUCTION SUMMARY
Instruction
CLR
ED
Algebraic Operation
A=0
ACC WB?
Yes
A = (x y)2
No
2
No
EDAC
A = A + (x y)
MAC
A = A + (x * y)
MAC
A = A + x2
No
No change in A
Yes
A=x*y
No
A=x*y
No
A=Ax*y
Yes
MOVSAC
MPY
MPY.N
MSC
Preliminary
Yes
DS70116D-page 17
dsPIC30F5011/5013
FIGURE 2-2:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-bit Accumulator A
40-bit Accumulator B
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
Negate
40
40
40
16
X Data Bus
Barrel
Shifter
40
Y Data Bus
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
DS70116D-page 18
Preliminary
dsPIC30F5011/5013
2.4.1
MULTIPLIER
2.4.2.1
The 17 x 17-bit multiplier is capable of signed or

unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17 x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to
40 bits. Integer data is inherently represented as a
signed twos complement value, where the MSB is
defined as a sign bit. Generally speaking, the range of
an N-bit twos complement integer is -2N-1 to 2N-1 1.
For a 16-bit integer, the data range is -32768 (0x8000)
to 32767 (0x7FFF) including 0. For a 32-bit integer,
the data range is -2,147,483,648 (0x8000 0000) to
2,147,483,645 (0x7FFF FFFF).
When the multiplier is configured for fractional multiplication, the data is represented as a twos complement
fraction, where the MSB is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX format). The range of an N-bit twos complement fraction
with this implied radix point is -1.0 to (1 21-N). For a
16-bit fraction, the Q15 data range is -1.0 (0x8000) to
0.999969482 (0x7FFF) including 0 and has a precision of 3.01518x10-5. In Fractional mode, the 16x16
multiply operation generates a 1.31 product which has
a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU multiply instructions which include integer 16-bit signed,
unsigned and mixed sign multiplies.
The adder/subtracter is a 40-bit adder with an optional

zero input into one side and either true, or complement
data into the other input. In the case of addition, the
carry/borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active low and the
other input is complemented. The adder/subtracter
generates overflow status bits SA/SB and OA/OB,
which are latched and reflected in the STATUS register:
Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow status bits
described above, and the SATA/B (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when and to what value to saturate.
Six Status register bits have been provided to support
saturation and overflow; they are:
1.
2.
3.
The MUL instruction may be directed to use byte or

word sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
2.4.2
4.
DATA ACCUMULATORS AND

ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/

subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter, prior to accumulation.
Adder/Subtracter, Overflow and

Saturation
5.
6.
OA:
AccA overflowed into guard bits
OB:
AccB overflowed into guard bits
SA:
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB:
AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB:
Logical OR of OA and OB
SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data

passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATEN, OVBTEN) in
the INTCON1 register (refer to Section 5.0) is set. This
allows the user to take immediate action, for example,
to correct system gain.
Preliminary
DS70116D-page 19
dsPIC30F5011/5013
The SA and SB bits are modified each time data
passes through the adder/subtracter but can only be
cleared by the user. When set, they indicate that the
accumulator has overflowed its maximum range (bit 31
for 32-bit saturation, or bit 39 for 40-bit saturation) and
will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has
occurred. If the COVTE bit in the INTCON1 register is
set, SA and SB bits will generate an arithmetic warning
trap when saturation is disabled.
The overflow and saturation status bits can optionally
be viewed in the STATUS register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This would be useful
for complex number arithmetic which typically uses
both the accumulators.
The device supports three saturation and overflow
modes:
1.
2.
3.
Bit 39 Overflow and Saturation:

When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF), or maximally negative 9.31
value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as super
saturation and provides protection against erroneous data, or unexpected algorithm problems
(e.g., gain calculations).
Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF), or maximally
negative 1.31 value (0x0080000000) into the
target accumulator. The SA or SB bit is set and
remains set until cleared by the user. When this
Saturation mode is in effect, the guard bits are
not used (so the OA, OB or OAB bits are never
set).
Bit 39 Catastrophic Overflow:
The bit 39 overflow status bit from the adder is
used to set the SA or SB bit which remain set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
DS70116D-page 20
2.4.2.2
Accumulator Write Back
The MAC class of instructions (with the exception of

MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following Addressing modes are supported:
1.
2.
W13, Register Direct:

The rounded contents of the non-target
accumulator are written into W13 as a 1.15
fraction.
[W13]+=2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumulator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
2.4.2.3
Round Logic
The round logic is a combinational block which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write
(store). The Round mode is determined by the state of
the RND bit in the CORCON register. It generates a 16bit, 1.15 data value which is passed to the data space
write saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the LS Word is simply discarded.
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word
(bits 0 through 15 of the accumulator) is between
0x8000 and 0xFFFF (0x8000 included), ACCxH is
incremented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding
operations, the value will tend to be biased slightly
positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the LS bit
(bit 16 of the accumulator) of ACCxH is examined. If it
is 1, ACCxH is incremented. If it is 0, ACCxH is not
modified. Assuming that bit 16 is effectively random in
nature, this scheme will remove any rounding bias that
may accumulate.
The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory via the X bus
(subject to data saturation, see Section 2.4.2.4). Note
that for the MAC class of instructions, the accumulator
write back operation will function in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
Preliminary
dsPIC30F5011/5013
2.4.2.4
Data Space Write Saturation
2.4.3
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data

space may also be saturated but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These are
combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.
The barrel shifter is capable of performing up to 16-bit

arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators, or the X bus (to support multi-bit
shifts of register or memory data).
If the SATDW bit in the CORCON register is set, data

(after rounding or truncation) is tested for overflow and
adjusted accordingly, For input data greater than
0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less
than 0xFF8000, data written to memory is forced to the
maximum negative 1.15 value, 0x8000. The MS bit of
the source (bit 39) is used to determine the sign of the
operand being tested.
The barrel shifter is 40-bits wide, thereby obtaining a

40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to
31 for right shifts, and bit positions 0 to 16 for left shifts.
The shifter requires a signed binary value to determine

both the magnitude (number of bits) and direction of the
shift operation. A positive value will shift the operand
right. A negative value will shift the operand left. A
value of 0 will not modify the operand.
If the SATDW bit in the CORCON register is not set, the

input data is always passed through unmodified under
all conditions.
Preliminary
DS70116D-page 21
dsPIC30F5011/5013
NOTES:
DS70116D-page 22
Preliminary
dsPIC30F5011/5013
3.0
MEMORY ORGANIZATION
FIGURE 3-1:

PROGRAM SPACE
MEMORY MAP
Reset - GOTO Instruction
Reset - Target Address
000000
000002
000004
Vector Tables
Interrupt Vector Table
Program Address Space
The program address space is 4M instruction words. It

is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space as defined by Table 3-1. Note that the program
space address is incremented by two between successive program words in order to provide compatibility
with data space addressing.
User Memory
Space
3.1
User program space access is restricted to the lower

4M instruction word address range (0x000000 to
0x7FFFFE) for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configuration space access. In Table 3-1, Program Space
Address Construction, bit 23 allows access to the
Device ID, the User ID and the configuration bits.
Otherwise, bit 23 is always clear.
Reserved
Alternate Vector Table
User Flash
Program Memory
(22K instructions)
Reserved
(Read 0s)
Data EEPROM
(1 Kbyte)
00007E
000080
000084
0000FE
000100
00AFFE
00B000
7FFBFE
7FFC00
7FFFFE
800000
Configuration Memory
Space
Reserved
UNITID (32 instr.)
8005BE
8005C0
8005FE
800600
Reserved
Device Configuration
Registers
F7FFFE
F80000
F8000E
F80010
Reserved
DEVID (2)
Preliminary
FEFFFE
FF0000
FFFFFE
DS70116D-page 23
dsPIC30F5011/5013
TABLE 3-1:
PROGRAM SPACE ADDRESS CONSTRUCTION

Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
Instruction Access
User
TBLRD/TBLWT
User
(TBLPAG<7> = 0)
TBLPAG<7:0>
Data EA<15:0>
TBLRD/TBLWT
Configuration
(TBLPAG<7> = 1)
TBLPAG<7:0>
Data EA<15:0>
Program Space Visibility
User
FIGURE 3-2:
<0>
PC<22:1>
PSVPAG<7:0>
Data EA<14:0>
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

23 bits
Using
Program
Counter
Program Counter
Select
Using
Program
Space
Visibility
EA
PSVPAG Reg
8 bits
15 bits
EA
Using
Table
Instruction
1/0
User/
Configuration
Space
Select
Note:
DS70116D-page 24
TBLPAG Reg
8 bits
16 bits
24-bit EA
Byte
Select
Program space visibility cannot be used to access bits <23:16> of a word in program memory.
Preliminary
dsPIC30F5011/5013
3.1.1
DATA ACCESS FROM PROGRAM

MEMORY USING TABLE
INSTRUCTIONS
A set of table instructions are provided to move byte or

word sized data to and from program space.
1.
This architecture fetches 24-bit wide program memory.

Consequently, instructions are always aligned.
However, as the architecture is modified Harvard, data
can also be present in program space.
There are two methods by which program space can
be accessed: via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2). The
TBLRDL and TBLWTL instructions offer a direct method
of reading or writing the LS Word of any address within
program space, without going through data space. The
TBLRDH and TBLWTH instructions are the only method
whereby the upper 8 bits of a program space word can
be accessed as data.
2.
3.
The PC is incremented by two for each successive

24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the LS Data Word,
and TBLRDH and TBLWTH access the space which
contains the MS Data Byte.
4.
TBLRDL: Table Read Low

Word: Read the LS Word of the program address;
P<15:0> maps to D<15:0>.
Byte: Read one of the LS Bytes of the program
address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> maps to the destination byte when byte
select = 1.
TBLWTL: Table Write Low (refer to Section 6.0
for details on Flash Programming)
TBLRDH: Table Read High
Word: Read the MS Word of the program address;
P<23:16> maps to D<7:0>; D<15:8> will always
be = 0.
Byte: Read one of the MS Bytes of the program
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
TBLWTH: Table Write High (refer to Section 6.0
for details on Flash Programming)
Figure 3-2 shows how the EA is created for table operations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
FIGURE 3-3:
PROGRAM DATA TABLE ACCESS (LS WORD)
PC Address
0x000000
0x000002
0x000004
0x000006
23
16
00000000
00000000
00000000
00000000
Program Memory
Phantom Byte
(read as 0)
TBLRDL.W
TBLRDL.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
Preliminary
DS70116D-page 25
dsPIC30F5011/5013
FIGURE 3-4:
PROGRAM DATA TABLE ACCESS (MS BYTE)

TBLRDH.W
PC Address
0x000000
0x000002
0x000004
0x000006
23
16
00000000
00000000
00000000
00000000
TBLRDH.B (Wn<0> = 0)
Program Memory
Phantom Byte
(read as 0)
3.1.2
TBLRDH.B (Wn<0> = 1)
DATA ACCESS FROM PROGRAM

MEMORY USING PROGRAM
SPACE VISIBILITY
The upper 32 Kbytes of data space may optionally be

mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions).
Program space access through the data space occurs
if the MS bit of the data space EA is set and program
space visibility is enabled by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 2.4, DSP Engine.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically contain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) data.
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 3-5), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits should be programmed to force an illegal
instruction to maintain machine robustness. Refer to
the Programmers Reference Manual (DS70030) for
details on instruction encoding.
DS70116D-page 26
Note that by incrementing the PC by 2 for each

program memory word, the LS 15 bits of data space
addresses directly map to the LS 15 bits in the corresponding program space addresses. The remaining
bits are provided by the Program Space Visibility Page
register, PSVPAG<7:0>, as shown in Figure 3-5.
Note:
PSV access is temporarily disabled during

table reads/writes.
For instructions that use PSV which are executed

outside a REPEAT loop:
The following instructions will require one
instruction cycle in addition to the specified
execution time:
- MAC class of instructions with data operand
pre-fetch
- MOV instructions
- MOV.D instructions
All other instructions will require two instruction
cycles in addition to the specified execution time
of the instruction.
For instructions that use PSV which are executed
inside a REPEAT loop:
The following instances will require two instruction
cycles in addition to the specified execution time
of the instruction:
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
interrupt
- Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow
the instruction accessing data, using PSV, to
execute in a single cycle.
Preliminary
dsPIC30F5011/5013
FIGURE 3-5:
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

Program Space
Data Space
0x0000
EA<15> = 0
PSVPAG(1)
0x01
8
15
Data 16
Space
15
EA
EA<15> = 1
0x8000
15
Address
Concatenation 23
23
15
0x008000
0x008200
Upper Half of Data

Space is Mapped
into Program Space
0x00FFFF
0xFFFF
BSET
MOV
MOV
MOV
CORCON,#2
#0x21, W0
W0, PSVPAG
0x8200, W0
; PSV bit set

; Set PSVPAG register
; Access program memory location
; using a data space access
Data Read
Note:
3.2
PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines
the page in program space to which the upper half of data space is being mapped).
Data Address Space
3.2.1
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instructions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and

Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
Preliminary
DS70116D-page 27
dsPIC30F5011/5013
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the 64Kbyte data address space (including all Y addresses).
When executing one of the MAC class of instructions,
the X block consists of the 64-Kbyte data address
space excluding the Y address block (for data reads
only). In other words, all other instructions regard the
entire data memory as one composite address space.
FIGURE 3-6:
The MAC class instructions extract the Y address space

from data space and address it using EAs sourced from
W10 and W11. The remaining X data space is
addressed using W8 and W9. Both address spaces are
concurrently accessed only with the MAC class
instructions.
The data space memory map is shown in Figure 3-6.
DATA SPACE MEMORY MAP

MS Byte
Address
16 bits
MSB
2 Kbyte
SFR Space
LS Byte
Address
LSB
0x0000
0x0001
SFR Space
0x07FE
0x0800
0x07FF
0x0801
X Data RAM (X)
4 Kbyte
SRAM Space
0x0FFF
0x1001
Y Data RAM (Y)
0x17FF
0x1801
0x17FE
0x1800
0x1FFF
0x1FFE
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS70116D-page 28
8 Kbyte
Near
Data
Space
0x0FFE
0x1000
0xFFFE
Preliminary
dsPIC30F5011/5013
DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE
SFR SPACE
SFR SPACE
X SPACE
FIGURE 3-7:
Y SPACE
UNUSED
X SPACE
(Y SPACE)
X SPACE
UNUSED
UNUSED
Non-MAC Class Ops (Read/Write)

MAC Class Ops (Write)
Indirect EA using any W
MAC Class Ops (Read)
Indirect EA using W8, W9
Preliminary
Indirect EA using W10, W11
DS70116D-page 29
dsPIC30F5011/5013
3.2.2
DATA SPACES
3.2.3
The X data space is used by all instructions and supports all Addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The X data space also supports modulo addressing for
all instructions, subject to Addressing mode restrictions. Bit-reversed addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur across the Y bus. This class of instructions dedicates two W register pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write back, the data
address space is considered a combination of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.
The Y data space can only be used for the data prefetch operation associated with the MAC class of
instructions. It also supports modulo addressing for
automated circular buffers. Of course, all other instructions can access the Y data address space through the
X data path as part of the composite linear space.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-6 and is not user programmable. Should an EA point to data outside its own
assigned address space, or to a location outside physical memory, an all zero word/byte will be returned. For
example, although Y address space is visible by all
non-MAC instructions using any Addressing mode, an
attempt by a MAC instruction to fetch data from that
space using W8 or W9 (X space pointers) will return
0x0000.
TABLE 3-2:
The core data width is 16 bits. All internal registers are

organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.4
As a consequence of this byte accessibility, all effective

address calculations (including those generated by the
DSP operations which are restricted to word sized
data) are internally scaled to step through word aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws+1 for byte operations
and Ws+2 for word operations.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. Should a misaligned read or write be attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be executed but
the write will not occur. In either case, a trap will then
be executed, allowing the system and/or user to examine the machine state prior to execution of the address
fault.
15
Data Returned
EA = an unimplemented address
0x0000
W8 or W9 used to access Y data

space in a MAC instruction
0x0000
W10 or W11 used to access X

data space in a MAC instruction
0x0000
DATA ALIGNMENT
To help maintain backward compatibility with

PICmicro devices and improve data space memory
usage efficiency, the dsPIC30F instruction set supports
both word and byte operations. Data is aligned in data
memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word which contains the byte, using the LS bit of any
EA to determine which byte to select. The selected byte
is placed onto the LS Byte of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
FIGURE 3-8:
EFFECT OF INVALID
MEMORY ACCESSES
Attempted Operation
DATA SPACE WIDTH
DATA ALIGNMENT
MS Byte
87
LS Byte
0001
Byte1
Byte 0
0000
0003
Byte3
Byte 2
0002
0005
Byte5
Byte 4
0004
All effective addresses are 16 bits wide and point to

bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
DS70116D-page 30
Preliminary
dsPIC30F5011/5013
All byte loads into any W register are loaded into the
LS Byte. The MSB is not modified.
A sign-extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.5
NEAR DATA SPACE
An 8-Kbyte near data space is reserved in X address

memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
There is a Stack Pointer Limit register (SPLIM) associated with the stack pointer. SPLIM is uninitialized at
Reset. As is the case for the stack pointer, SPLIM<0>
is forced to 0 because all stack operations must be
word aligned. Whenever an effective address (EA) is
generated using W15 as a source or destination
pointer, the address thus generated is compared with
the value in SPLIM. If the contents of the Stack Pointer
(W15) and the SPLIM register are equal and a push
operation is performed, a Stack Error Trap will not
occur. The Stack Error Trap will occur on a subsequent
push operation. Thus, for example, if it is desirable to
cause a Stack Error Trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the
value, 0x1FFE.
Similarly, a stack pointer underflow (stack error) trap is
generated when the stack pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-9:
3.2.6
SOFTWARE STACK
0x0000
The stack pointer always points to the first available

free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops
and post-increments for stack pushes as shown in
Figure 3-9. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
Note:
Stack Grows Towards

Higher Address
The dsPIC devices contain a software stack. W15 is

used as the stack pointer.
A PC push during exception processing

will concatenate the SRL register to the
MSB of the PC prior to the push.
Preliminary
CALL STACK FRAME
15
PC<15:0>
W15 (before CALL)
000000000 PC<22:16>
<Free Word>
W15 (after CALL)

POP : [--W15]
PUSH : [W15++]
DS70116D-page 31
DS70116D-page 32
Preliminary
003C
003E
0040
0042
DOSTARTH
DOENDL
DOENDH
SR
OA
Bit 15
u = uninitialized bit
003A
DOSTARTL
Legend:
0038
0032
TBLPAG
DCOUNT
0030
PCH
0036
002E
PCL
RCOUNT
002C
ACCBU
0034
002A
ACCBH
PSVPAG
0028
001A
W13
ACCBL
0018
W12
0026
0016
W11
ACCAU
0014
W10
0024
0012
W9
ACCAH
0010
W8
0022
000E
W7
ACCAL
000C
W6
0020
000A
W5
SPLIM
0008
W4
001E
0006
W3
W15
0004
W2
001C
0002
W1
W14
0000
W0
SFR Name
OB
Bit 14
Bit 12
Bit 11
SA
SB
OAB
Sign-Extension (ACCB<39>)
SAB
Bit 10
Sign-Extension (ACCA<39>)
Bit 13
CORE REGISTER MAP
Address
(Home)
TABLE 3-3:
DA
DCOUNT
RCOUNT
PCL
ACCBH
ACCBL
ACCAH
ACCAL
SPLIM
W15
W14
W13
W12
W11
W10
W9
W8
W7
W6
W5
W4
W3
W2
W1
DC
DOENDL
IPL2
Bit 7
W0 / WREG
Bit 8
DOSTARTL
Bit 9
IPL1
Bit 6
IPL0
Bit 5
Bit 3
RA
DOENDH
DOSTARTH
PSVPAG
TBLPAG
PCH
ACCBU
ACCAU
Bit 4
OV
Bit 2
Bit 1
Bit 0
0000 0000 0000 0000
0000 0000 0uuu uuuu
uuuu uuuu uuuu uuu0
0000 0000 0uuu uuuu
uuuu uuuu uuuu uuu0
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 1000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Reset State
dsPIC30F5011/5013
004E
0050
0052
YMODSRT
YMODEND
XBREV
DISICNT
BREN
YMODEN
Bit 14
US
Bit 12
Bit 13
EDT
Bit 11
DL1
Bit 9
BWM<3:0>
DL2
Bit 10
YE<15:1>
YS<15:1>
XE<15:1>
XS<15:1>
DL0
Bit 8
Bit 4
SATDW ACCSAT
Bit 5
YWM<3:0>
SATB
Bit 6
DISICNT<13:0>
XB<14:0>
SATA
Bit 7
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
004C
XMODEND
Legend:
0048
004A
XMODSRT
XMODEN
0044
0046
CORCON
Bit 15
CORE REGISTER MAP (CONTINUED)
Address
(Home)
MODCON
SFR Name
TABLE 3-3:
IPL3
Bit 3
RND
Bit 1
XWM<3:0>
PSV
Bit 2
IF
Bit 0
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuu1
uuuu uuuu uuuu uuu0
uuuu uuuu uuuu uuu1
uuuu uuuu uuuu uuu0
0000 0000 0000 0000
0000 0000 0010 0000
Reset State
dsPIC30F5011/5013
Preliminary
DS70116D-page 33
dsPIC30F5011/5013
NOTES:
DS70116D-page 34
Preliminary
dsPIC30F5011/5013
4.0
ADDRESS GENERATOR UNITS

Manual (DS70046).
The dsPIC core contains two independent address

generator units: the X AGU and Y AGU. The Y AGU
supports word sized data reads for the DSP MAC class
of instructions only. The dsPIC AGUs support three
types of data addressing:
Linear Addressing
Modulo (Circular) Addressing
Bit-Reversed Addressing
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field

(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register, or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space during file register
operation.
4.1.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Linear and Modulo Data Addressing modes can be

applied to data space or program space. Bit-reversed
addressing is only applicable to data space addresses.
4.1
4.1.1
Instruction Addressing Modes
The addressing modes in Table 4-1 form the basis of

the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a working register (i.e., the
addressing mode can only be register direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or an address
location. The following addressing modes are
supported by MCU instructions:
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
5-bit or 10-bit Literal
Note:
TABLE 4-1:
Not all instructions support all the addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct
The address of the File register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the EA.
The contents of Wn forms the EA. Wn is post-modified (incremented or

decremented) by a constant value.
Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
The sum of Wn and a literal forms the EA.
Preliminary
DS70116D-page 35
dsPIC30F5011/5013
4.1.3
MOVE AND ACCUMULATOR

INSTRUCTIONS
In summary, the following addressing modes are

supported by the MAC class of instructions:
Move instructions and the DSP accumulator class of

instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU instructions, move and accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
Note:
For the MOV instructions, the addressing

mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (register offset)
field is shared between both source and
destination (but typically only used by
one).
In summary, the following addressing modes are

supported by move and accumulator instructions:
Register Direct
Register Indirect
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
4.1.4
Register Indirect
Register Indirect Post-modified by 2
Register Indirect with Register Offset (Indexed)
4.1.5
OTHER INSTRUCTIONS
Besides the various addressing modes outlined above,

some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
4.2
Modulo Addressing
Modulo addressing is a method of providing an automated means to support circular data buffers using
hardware. The objective is to remove the need for software to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
Not all instructions support all the addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
referred to as MAC instructions, utilize a simplified set of
addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
The 2 source operand pre-fetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.
Note:
Modulo addressing can operate in either data or program space (since the data pointer mechanism is
essentially the same for both). One circular buffer can
be supported in each of the X (which also provides the
pointers into program space) and Y data spaces. Modulo addressing can operate on any W register pointer.
However, it is not advisable to use W14 or W15 for modulo addressing since these two registers are used as
the stack frame pointer and stack pointer, respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing
buffers) based upon the direction of the buffer.
The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bidirectional mode (i.e., address boundary
checks will be performed on both the lower and upper
address boundaries).
Register indirect with register offset

addressing is only available for W9 (in X
space) and W11 (in Y space).
DS70116D-page 36
Preliminary
dsPIC30F5011/5013
4.2.1
START AND END ADDRESS
4.2.2
The modulo addressing scheme requires that a starting

and an ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 3-3).
Note:
Y space modulo addressing EA calculations assume word sized data (LS bit of
every EA is always clear).
The length of a circular buffer is not directly specified. It

is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words
(64 Kbytes).
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control register MODCON<15:0> contains enable flags as well as
a W register field to specify the W address registers.
The XWM and YWM fields select which registers will
operate with modulo addressing. If XWM = 15, X
RAGU and X WAGU modulo addressing is disabled.
Similarly, if YWM = 15, Y AGU modulo addressing is
disabled.
The X Address Space Pointer W register (XWM), to
which modulo addressing is to be applied, is stored in
MODCON<3:0> (see Table 3-3). Modulo addressing is
enabled for X data space when XWM is set to any value
other than 15 and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM), to
which modulo addressing is to be applied, is stored in
MODCON<7:4>. Modulo addressing is enabled for Y
data space when YWM is set to any value other than
15 and the YMODEN bit is set at MODCON<14>.
FIGURE 4-1:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
0x1100
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100,W0
W0,XMODSRT
#0x1163,W0
W0,MODEND
#0x8001,W0
W0,MODCON
MOV
#0x0000,W0
;W0 holds buffer fill value
MOV
#0x1110,W1
;point W1 to buffer
DO
AGAIN,#0x31
MOV
W0,[W1++]
AGAIN: INC W0,W0
;set modulo start address

;set modulo end address
;enable W1, X AGU for modulo
;fill the 50 buffer locations

;fill the next location
;increment the fill value
0x1163
Start Addr = 0x1100

End Addr = 0x1163
Length = 0x0032 words
Preliminary
DS70116D-page 37
dsPIC30F5011/5013
4.2.3
MODULO ADDRESSING
APPLICABILITY
Modulo addressing can be applied to the effective

address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than, or greater than the
upper (for incrementing buffers), and lower (for decrementing buffers) boundary addresses (not just equal
to). Address changes may, therefore, jump beyond
boundaries and still be adjusted correctly.
Note:
4.3
The modulo corrected effective address is

written back to the register only when PreModify or Post-Modify Addressing mode is
used to compute the effective address.
When an address offset (e.g., [W7+W2]) is
used, modulo address correction is performed but the contents of the register
remain unchanged.
Bit-Reversed Addressing
Bit-reversed addressing is intended to simplify data reordering for radix-2 FFT algorithms. It is supported by
the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.3.1
2.
3.
XB<14:0> is the bit-reversed address modifier or pivot

point which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
BWM (W register selection) in the MODCON

register is any value other than 15 (the stack
cannot be accessed using bit-reversed
addressing) and
the BREN bit is set in the XBREV register and
the addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
FIGURE 4-2:
All bit-reversed EA calculations assume

word sized data (LS bit of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, bit-reversed addressing will only be

executed for register indirect with pre-increment or
post-increment addressing and word sized data writes.
It will not function for any other addressing mode or for
byte sized data, and normal addresses will be generated instead. When bit-reversed addressing is active,
the W address pointer will always be added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode will be ignored.
In addition, as word sized data is a requirement, the LS
bit of the EA is ignored (and always clear).
Note:
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-reversed addressing is enabled when:

1.
If the length of a bit-reversed buffer is M = 2N bytes,

then the last N bits of the data buffer start address
must be zeros.
Modulo addressing and bit-reversed

addressing should not be enabled together.
In the event that the user attempts to do
this, bit-reversed addressing will assume
priority when active for the X WAGU, and X
WAGU modulo addressing will be disabled.
However, modulo addressing will continue
to function in the X RAGU.
If bit-reversed addressing has already been enabled by

setting the BREN (XBREV<15>) bit, then a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
BIT-REVERSED ADDRESS EXAMPLE

Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b4
b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b1
b2 b3 b4
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-word Bit-Reversed Buffer
DS70116D-page 38
Preliminary
dsPIC30F5011/5013
TABLE 4-2:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

Normal Address
A3
A2
A1
A0
Bit-Reversed Address
Decimal
A3
A2
A1
A0
Decimal
12
10
14
10
11
13
12
13
11
14
15
15
TABLE 4-3:
BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER

Buffer Size (Words)
XB<14:0> Bit-Reversed Address Modifier Value
2048
0x0400
1024
0x0200
512
0x0100
256
0x0080
128
0x0040
64
0x0020
32
0x0010
16
0x0008
0x0004
0x0002
0x0001
Preliminary
DS70116D-page 39
dsPIC30F5011/5013
NOTES:
DS70116D-page 40
Preliminary
dsPIC30F5011/5013
5.0
INTERRUPTS
Note:

Manual (DS70046).
The dsPIC30F Sensor and General Purpose Family

has up to 41 interrupt sources and 4 processor exceptions (traps) which must be arbitrated based on a
priority scheme.
The CPU is responsible for reading the Interrupt Vector
Table (IVT) and transferring the address contained in
the interrupt vector to the program counter. The interrupt vector is transferred from the program data bus
into the program counter via a 24-bit wide multiplexer
on the input of the program counter.
The Interrupt Vector Table (IVT) and Alternate Interrupt
Vector Table (AIVT) are placed near the beginning of
program memory (0x000004). The IVT and AIVT are
shown in Figure 5-1.
The interrupt controller is responsible for preprocessing the interrupts and processor exceptions
prior to them being presented to the processor core.
The peripheral interrupts and traps are enabled, prioritized and controlled using centralized Special Function
Registers:
IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
All interrupt request flags are maintained in these
three registers. The flags are set by their respective peripherals or external signals, and they are
cleared via software.
IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
IPC0<15:0>... IPC10<7:0>
The user assignable priority level associated with
each of these 41 interrupts is held centrally in
these twelve registers.
IPL<3:0>
The current CPU priority level is explicitly stored
in the IPL bits. IPL<3> is present in the CORCON
register, whereas IPL<2:0> are present in the
STATUS register (SR) in the processor core.
INTCON1<15:0>, INTCON2<15:0>
Global interrupt control functions are derived from
these two registers. INTCON1 contains the control and status flags for the processor exceptions.
The INTCON2 register controls the external
interrupt request signal behavior and the use of
the alternate vector table.
Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
All interrupt sources can be user assigned to one of 7
priority levels, 1 through 7, via the IPCx registers. Each
interrupt source is associated with an interrupt vector,
as shown in Table 5-1. Levels 7 and 1 represent the
highest and lowest maskable priorities, respectively.
Note:
Assigning a priority level of 0 to an interrupt source is equivalent to disabling that

interrupt.
If the NSTDIS bit (INTCON1<15>) is set, nesting of

interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is prevented even if the new interrupt is of higher priority than
the one currently being serviced.
Note:
The IPL bits become read only whenever

the NSTDIS bit has been set to 1.
Certain interrupts have specialized control bits for features like edge or level triggered interrupts, interrupton-change, etc. Control of these features remains
within the peripheral module which generates the
interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program memory that corresponds to the interrupt. There are 63 different vectors within the IVT (refer to Table 5-1). These
vectors are contained in locations 0x000004 through
0x0000FE of program memory (refer to Table 5-1).
These locations contain 24-bit addresses and in order
to preserve robustness, an address error trap will take
place should the PC attempt to fetch any of these
words during normal execution. This prevents execution of random data as a result of accidentally decrementing a PC into vector space, accidentally mapping
a data space address into vector space, or the PC rolling over to 0x000000 after reaching the end of implemented program memory space. Execution of a GOTO
instruction to this vector space will also generate an
address error trap.
Preliminary
DS70116D-page 41
dsPIC30F5011/5013
5.1
TABLE 5-1:
Interrupt Priority
The user assignable interrupt priority (IP<2:0>) bits for

each individual interrupt source are located in the LS
3 bits of each nibble within the IPCx register(s). Bit 3 of
each nibble is not used and is read as a 0. These bits
define the priority level assigned to a particular interrupt
by the user.
Note:
The user selectable priority levels start at

0 as the lowest priority and level 7 as the
highest priority.
Natural Order Priority is determined by the position of

an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC device and their associated
vector numbers.
Note 1: The natural order priority scheme has 0
as the highest priority and 53 as the
lowest priority.
2: The natural order priority number is the
same as the INT number.
The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PLVD (Low
Voltage Detect) can be given a priority of 7. The INT0
(External Interrupt 0) may be assigned to priority level
1, thus giving it a very low effective priority.
DS70116D-page 42
INT
Number
INTERRUPT VECTOR TABLE
Vector
Number
Interrupt Source
Highest Natural Order Priority

0
8
INT0 - External Interrupt 0
1
9
IC1 - Input Capture 1
2
10
OC1 - Output Compare 1
3
11
T1 - Timer 1
4
12
5
13
6
14
T2 - Timer 2
7
15
T3 - Timer 3
8
16
SPI1
9
17
U1RX - UART1 Receiver
10
18
U1TX - UART1 Transmitter
11
19
ADC - ADC Convert Done
12
20
NVM - NVM Write Complete
13
21
SI2C - I2C Slave Interrupt
14
22
MI2C - I2C Master Interrupt
15
23
Input Change Interrupt
16
24
17
25
18
26
19
27
20
28
21
29
T4 - Timer 4
22
30
T5 - Timer 5
23
31
24
32
U2RX - UART2 Receiver
25
33
U2TX - UART2 Transmitter
26
34
SPI2
27
35
C1 - Combined IRQ for CAN1
28
36
29
37
30
38
31
39
32
40
33
41
34
42
35
43
36
44
37
45
38
46
C2 - Combined IRQ for CAN2
39-40
47-48 Reserved
41
49
DCI - Codec Transfer Done
42
50
LVD - Low Voltage Detect
43-53
51-61 Reserved
Lowest Natural Order Priority
Preliminary
dsPIC30F5011/5013
5.2
Reset Sequence
5.3
A Reset is not a true exception, because the interrupt

controller is not involved in the Reset process. The processor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory location immediately followed by the address target for the
GOTO instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
5.2.1
Traps
Traps can be considered as non-maskable interrupts

indicating a software or hardware error, which adhere
to a predefined priority as shown in Figure 5-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note:
RESET SOURCES
In addition to external Reset and Power-on Reset

(POR), there are 6 sources of error conditions which
trap to the Reset vector.
Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an address pointer will cause a Reset.
Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
Trap Lockout:
Occurrence of multiple trap conditions
simultaneously will cause a Reset.
Note that many of these trap conditions can only be

detected when they occur. Consequently, the questionable instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which implies that the IPL3 is always
set during processing of a trap.
If the user is not currently executing a trap, and he sets
the IPL<3:0> bits to a value of 0111 (Level 7), then all
interrupts are disabled, but traps can still be processed.
5.3.1
TRAP SOURCES
The following traps are provided with increasing priority. However, since all traps can be nested, priority has
little effect.
Math Error Trap:

The Math Error trap executes under the following three
circumstances:
1.
2.
3.
4.
If the user does not intend to take corrective action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
containing an invalid address is called, an
address error trap is generated.
Preliminary
Should an attempt be made to divide by zero,

the divide operation will be aborted on a cycle
boundary and the trap taken.
If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A
or B causes an overflow from bit 31 and the
accumulator guard bits are not utilized.
If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.
If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap will occur.
DS70116D-page 43
dsPIC30F5011/5013
Address Error Trap:
5.3.2
This trap is initiated when any of the following

circumstances occurs:
It is possible that multiple traps can become active

within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-2 is implemented,
which may require the user to check if other traps are
pending, in order to completely correct the fault.
1.
2.
3.
4.
A misaligned data word access is attempted.

A data fetch from our unimplemented data
memory location is attempted.
A data access of an unimplemented program
memory location is attempted.
An instruction fetch from vector space is
attempted.
Note:
5.
6.
In the MAC class of instructions, wherein

the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
Execution of a BRA #literal instruction or a

GOTO #literal instruction, where literal
is an unimplemented program memory address.
Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
HARD AND SOFT TRAPS
Soft traps include exceptions of priority level 8 through

level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.
Hard traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict will occur.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR status bit (RCON<15>) is set
when the Reset occurs, so that the condition may be
detected in software.
FIGURE 5-1:
Stack Error Trap:
TRAP VECTORS
1.
2.
The stack pointer is loaded with a value which is

greater than the (user programmable) limit value
written into the SPLIM register (stack overflow).
The stack pointer is loaded with a value which is
less than 0x0800 (simple stack underflow).
Oscillator Fail Trap:
Decreasing
Priority
This trap is initiated under the following conditions:
IVT
This trap is initiated if the external oscillator fails and

operation becomes reliant on an internal RC backup.
AIVT
DS70116D-page 44
Preliminary
Reset - GOTO Instruction

Reset - GOTO Address
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 52 Vector
Interrupt 53 Vector
Reserved
Reserved
Reserved
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 52 Vector
Interrupt 53 Vector
0x000000
0x000002
0x000004
0x000014
0x00007E
0x000080
0x000082
0x000084
0x000094
0x0000FE
dsPIC30F5011/5013
5.4
Interrupt Sequence
5.5
All interrupt event flags are sampled in the beginning of

each instruction cycle by the IFSx registers. A pending
interrupt request (IRQ) is indicated by the flag bit being
equal to a 1 in an IFSx register. The IRQ will cause an
interrupt to occur if the corresponding bit in the Interrupt
Enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current program counter
and the low byte of the processor STATUS register
(SRL), as shown in Figure 5-2. The low byte of the
STATUS register contains the processor priority level at
the time prior to the beginning of the interrupt cycle.
The processor then loads the priority level for this interrupt into the STATUS register. This action will disable
all lower priority interrupts until the completion of the
Interrupt Service Routine.
FIGURE 5-2:
Stack Grows Towards

Higher Address
0x0000 15
INTERRUPT STACK
FRAME
0
Alternate Vector Table
In program memory, the Interrupt Vector Table (IVT) is

followed by the Alternate Interrupt Vector Table (AIVT),
as shown in Figure 5-1. Access to the alternate vector
table is provided by the ALTIVT bit in the INTCON2 register. If the ALTIVT bit is set, all interrupt and exception
processes will use the alternate vectors instead of the
default vectors. The alternate vectors are organized in
the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a
means to switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time.
If the AIVT is not required, the program memory allocated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
5.6
Fast Context Saving
A context saving option is available using shadow registers. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The shadow
registers are accessible using the PUSH.S and POP.S
instructions only.
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
PC<15:0>
SRL IPL3 PC<22:16>
<Free Word>
W15 (before CALL)

W15 (after CALL)
POP : [--W15]
If an ISR of a certain priority uses the PUSH.S and

POP.S instructions for fast context saving, then a
higher priority ISR should not include the same instructions. Users must save the key registers in software
during a lower priority interrupt if the higher priority ISR
uses fast context saving.
PUSH: [W15++]
5.7
Note 1: The user can always lower the priority
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority, in order to avoid recursive
interrupts.
2: The IPL3 bit (CORCON<3>) is always
clear when interrupts are being processed. It is set only during execution of
traps.
The RETFIE (return from interrupt) instruction will
unstack the program counter and STATUS registers to
return the processor to its state prior to the interrupt
sequence.
External Interrupt Requests
The interrupt controller supports up to five external

interrupt request signals, INT0-INT4. These inputs are
edge sensitive; they require a low-to-high or a high-tolow transition to generate an interrupt request. The
INTCON2 register has five bits, INT0EP-INT4EP, that
select the polarity of the edge detection circuitry.
5.8
Wake-up from Sleep and Idle
The interrupt controller may be used to wake-up the

processor from either Sleep or Idle modes, if Sleep or
Idle mode is active when the interrupt is generated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from Sleep or
Idle and begin execution of the Interrupt Service
Routine (ISR) needed to process the interrupt request.
Preliminary
DS70116D-page 45
0084
0086
0088
008C
008E
0090
0094
0096
0098
009A
009C
IFS0
IFS1
DS70116D-page 46
IFS2
IEC0
IEC1
IEC2
IPC0
IPC1
IPC2
IPC3
IPC4
Preliminary
Legend:
IC3IE
C1IE
ADIE
C1IF
ADIF
Bit 11
DCIIF
U2TXIF
U1RXIF
OVBTE
Bit 9
LVDIE
SPI2IE
SPI1IE
U2RXIF
SPI1IF
COVTE
Bit 8
LVDIP<2:0>
C2IP<2:0>
OC7IP<2:0>
IC5IP<2:0>
SPI2IP<2:0>
T5IP<2:0>
IC8IP<2:0>
MI2CIP<2:0>
U1TXIP<2:0>
T2IP<2:0>
OC1IP<2:0>
DCIIE
U2TXIE U2RXIE
U1TXIE U1RXIE
LVDIF
SPI2IF
U1TXIF
OVATE
Bit 10
INT2IE
T3IE
INT2IF
T3IF
Bit 7
C2IE
T5IE
T2IE
C2IF
T5IF
T2IF
Bit 6
Bit 4
INT3IE
OC4IE
IC2IE
INT3IF
OC4IF
IC2IF
INT4EP
MATHERR
DCIIP<2:0>
INT41IP<2:0>
OC6IP<2:0>
IC4IP<2:0>
U2TXIP<2:0>
T4IP<2:0>
IC7IP<2:0>
SI2CIP<2:0>
U1RXIP<2:0>
OC2IP<2:0>
IC1IP<2:0>
INT4IE
T4IE
OC2IE
INT4IF
T4IF
OC2IF
Bit 5
00A8
IPC10
OC8IP<2:0>
00A6
IPC9
00A4
IPC8
IC6IP<2:0>
00A2
IPC7
C1IP<2:0>
00A0
IPC6
009E
IPC5
IC3IF
NVMIE
OC3IP<2:0>
CNIP<2:0>
ADIP<2:0>
T31P<2:0>
T1IP<2:0>
IC4IE
SI2CIE
INT2IP<2:0>
IC5IE
IC4IF
Bit 12
NVMIF
IC6IE
MI2CIE
CNIE
IC5IF
SI2CIF
MI2CIF
Bit 13
Bit 14
IC6IF
CNIF
0082 ALTIVT
INTCON2
Bit 15
0080 NSTDIS
ADR
INTERRUPT CONTROLLER REGISTER MAP
INTCON1
SFR
Name
TABLE 5-2:
OC8IE
OC3IE
T1IE
OC8IF
OC3IF
T1IF
INT3EP
ADDRERR
Bit 3
Bit 1
OC7IE
IC8IE
OC1IE
OC7IF
IC8IF
OC1IF
INT2EP
INT3IP<2:0>
OC5IP<2:0>
IC3IP<2:0>
U2RXIP<2:0>
OC4IP<2:0>
INT1IP<2:0>
NVMIP<2:0>
SPI1IP<2:0>
IC2IP<2:0>
INT0IP<2:0>
OC6IE
IC7IE
IC1IE
OC6IF
IC7IF
IC1IF
INT1EP
STKERR OSCFAIL
Bit 2
0000 0000 0000 0000
Reset State
OC5IE
INT1IE
INT0IE
OC5IF
INT1IF
INT0IF
0000 0100 0100 0000
0000 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
INT0EP 0000 0000 0000 0000
Bit 0
dsPIC30F5011/5013
dsPIC30F5011/5013
6.0
FLASH PROGRAM MEMORY
6.2

Manual (DS70046).
RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions.
With RTSP, the user may erase program memory, 32
instructions (96 bytes) at a time and can write program
memory data, 32 instructions (96 bytes) at a time.
The dsPIC30F family of devices contains internal program Flash memory for executing user code. There are
two methods by which the user can program this
memory:
1.
2.
6.1
6.3
Run-Time Self-Programming (RTSP)

Table Instruction Operation

Summary
The TBLRDL and the TBLWTL instructions are used to

read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
Word or Byte mode.
In-Circuit Serial Programming

(ICSP)
The TBLRDH and TBLWTH instructions are used to read

or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can access program memory in Word or
Byte mode.
dsPIC30F devices can be serially programmed while in

the end application circuit. This is simply done with two
lines for Programming Clock and Programming Data
(which are named PGC and PGD respectively), and
three other lines for Power (VDD), Ground (VSS) and
Master Clear (MCLR). this allows customers to manufacture boards with unprogrammed devices, and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
FIGURE 6-1:
Run-Time Self-Programming
(RTSP)
A 24-bit program memory address is formed using

bits<7:0> of the TBLPAG register and the effective
address (EA) from a W register specified in the table
instruction, as shown in Figure 6-1.
ADDRESSING FOR TABLE AND NVM REGISTERS

24 bits
Using
Program
Counter
Program Counter
NVMADR Reg EA
Using
NVMADR
Addressing
1/0
NVMADRU Reg
8 bits
16 bits
Working Reg EA
Using
Table
Instruction
User/Configuration
Space Select
1/0
TBLPAG Reg
8 bits
16 bits
24-bit EA
Preliminary
Byte
Select
DS70116D-page 47
dsPIC30F5011/5013
6.4
RTSP Operation
6.5
The dsPIC30F Flash program memory is organized

into rows and panels. Each row consists of 32 instructions, or 96 bytes. Each panel consists of 128 rows, or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program four
instructions at one time. RTSP may be used to program
multiple program memory panels, but the table pointer
must be changed at each panel boundary.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction 0, instruction 1,
etc. The instruction words loaded must always be from
a group of 32 boundary.
The basic sequence for RTSP programming is to set up
a table pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. 32
TBLWTL and four TBLWTH instructions are required to
load the 32 instructions. If multiple panel programming
is required, the table pointer needs to be changed and
the next set of multiple write latches written.
All of the table write operations are single word writes
(2 instruction cycles), because only the table latches
are written. A programming cycle is required for
programming each row.
The Flash Program Memory is readable, writable and
erasable during normal operation over the entire VDD
range.
The four SFRs used to read and write the program

Flash memory are:
NVMCON
NVMADR
NVMADRU
NVMKEY
6.5.1
NVMCON REGISTER
The NVMCON register controls which blocks are to be

erased, which memory type is to be programmed, and
start of the programming cycle.
6.5.2
NVMADR REGISTER
The NVMADR register is used to hold the lower two

bytes of the effective address. The NVMADR register
captures the EA<15:0> of the last table instruction that
has been executed and selects the row to write.
6.5.3
NVMADRU REGISTER
The NVMADRU register is used to hold the upper byte

of the effective address. The NVMADRU register captures the EA<23:16> of the last table instruction that
has been executed.
6.5.4
NVMKEY REGISTER
NVMKEY is a write-only register that is used for write

protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 6.6 for
further details.
Note:
DS70116D-page 48
Control Registers
Preliminary
The user can also directly write to the

NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
dsPIC30F5011/5013
6.6
Programming Operations
4.
A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 2 msec in
duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.
6.6.1
5.
PROGRAMMING ALGORITHM FOR

PROGRAM FLASH
The user can erase or program one row of program

Flash memory at a time. The general process is:
1.
2.
3.
Read one row of program Flash (32 instruction

words) and store into data RAM as a data
image.
Update the data image with the desired new
data.
Erase program Flash row.
a) Setup NVMCON register for multi-word,
program Flash, erase, and set WREN bit.
b) Write address of row to be erased into
NVMADRU/NVMDR.
c) Write 55 to NVMKEY.
d) Write AA to NVMKEY.
e) Set the WR bit. This will begin erase cycle.
f) CPU will stall for the duration of the erase
cycle.
g) The WR bit is cleared when erase cycle
ends.
EXAMPLE 6-1:
6.
Write 32 instruction words of data from data

RAM image into the program Flash write
latches.
Program 32 instruction words into program
Flash.
a) Setup NVMCON register for multi-word,
program Flash, program, and set WREN
bit.
b) Write 55 to NVMKEY.
c) Write AA to NVMKEY.
d) Set the WR bit. This will begin program
cycle.
e) CPU will stall for duration of the program
cycle.
f) The WR bit is cleared by the hardware
when program cycle ends.
Repeat steps 1 through 5 as needed to program
desired amount of program Flash memory.
6.6.2
ERASING A ROW OF PROGRAM

MEMORY
Example 6-1 shows a code sequence that can be used

to erase a row (32 instructions) of program memory.
ERASING A ROW OF PROGRAM MEMORY
; Setup NVMCON for erase operation, multi word

; program memory selected, and writes enabled
MOV
#0x4041,W0
;
;
MOV
W0,NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR),W0
;
;
MOV
W0,NVMADRU
MOV
#tbloffset(PROG_ADDR),W0
;
MOV
W0, NVMADR
;
DISI
#5
;
;
MOV
#0x55,W0
;
MOV
W0,NVMKEY
MOV
#0xAA,W1
;
;
MOV
W1,NVMKEY
BSET
NVMCON,#WR
;
NOP
;
NOP
;
write
Init NVMCON SFR
Initialize PM Page Boundary SFR

Intialize in-page EA[15:0] pointer
Initialize NVMADR SFR
Block all interrupts with priority <7 for
next 5 instructions
Write the 0x55 key
Write the 0xAA key
Start the erase sequence
Insert two NOPs after the erase
command is asserted
Preliminary
DS70116D-page 49
dsPIC30F5011/5013
6.6.3
LOADING WRITE LATCHES
Example 6-2 shows a sequence of instructions that

can be used to load the 96 bytes of write latches. 32
TBLWTL and 32 TBLWTH instructions are needed to
load the write latches selected by the table pointer.
EXAMPLE 6-2:
LOADING WRITE LATCHES
; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled
MOV
#0x0000,W0
;
; Initialize PM Page Boundary SFR
MOV
W0,TBLPAG
MOV
#0x6000,W0
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
#LOW_WORD_0,W2
;
MOV
#HIGH_BYTE_0,W3
;
; Write PM low word into program latch
TBLWTL W2,[W0]
TBLWTH W3,[W0++]
; Write PM high byte into program latch
; 1st_program_word
MOV
#LOW_WORD_1,W2
;
MOV
#HIGH_BYTE_1,W3
;
TBLWTL W2,[W0]
TBLWTH W3,[W0++]
; 2nd_program_word
MOV
#LOW_WORD_2,W2
;
MOV
#HIGH_BYTE_2,W3
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; 31st_program_word
MOV
#LOW_WORD_31,W2
;
MOV
#HIGH_BYTE_31,W3
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
Note: In Example 6-2, the contents of the upper byte of W3 has no effect.
6.6.4
INITIATING THE PROGRAMMING

SEQUENCE
For protection, the write initiate sequence for NVMKEY

must be used to allow any erase or program operation
to proceed. After the programming command has been
executed, the user must wait for the programming time
until programming is complete. The two instructions following the start of the programming sequence should
be NOPs.
EXAMPLE 6-3:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
W0,NVMKEY
#0xAA,W1
W1,NVMKEY
NVMCON,#WR
DS70116D-page 50
;
;
;
;
;
;
;
;
;

next 5 instructions
Write the 0x55 key
Write the 0xAA key
Start the erase sequence
Insert two NOPs after the erase
command is asserted
Preliminary
0764
0766
NVMADRU
NVMKEY
WREN
Bit 14
WR
Bit 15
Bit 12 Bit 11 Bit 10
Bit 9
Bit 7
NVMADR<15:0>
TWRI
Bit 8
Bit 6
Bit 5
WRERR
Bit 13
NVM REGISTER MAP
0762
Legend:
0760
NVMCON
Addr.
NVMADR
File Name
TABLE 6-1:
Bit 3
Bit 2
KEY<7:0>
NVMADR<23:16>
PROGOP<6:0>
Bit 4
Bit 1
Bit 0
0000 0000 0000 0000
0000 0000 uuuu uuuu
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
All RESETS
dsPIC30F5011/5013
Preliminary
DS70116D-page 51
dsPIC30F5011/5013
NOTES:
DS70116D-page 52
Preliminary
dsPIC30F5011/5013
7.0
DATA EEPROM MEMORY

Manual (DS70046).
The Data EEPROM Memory is readable and writable

during normal operation over the entire VDD range. The
data EEPROM memory is directly mapped in the
program memory address space.
The four SFRs used to read and write the program
Flash memory are used to access data EEPROM
memory, as well. As described in Section 6.5, these
registers are:
NVMCON
NVMADR
NVMADRU
NVMKEY
Control bit WR initiates write operations similar to program Flash writes. This bit cannot be cleared, only set,
in software. They are cleared in hardware at the completion of the write operation. The inability to clear the
WR bit in software prevents the accidental or
premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal operation. In these situations, following Reset, the user can
check the WRERR bit and rewrite the location. The
address register NVMADR remains unchanged.
Note:
7.1
The EEPROM data memory allows read and write of

single words and 16-word blocks. When interfacing to
data memory, NVMADR in conjunction with the
NVMADRU register are used to address the EEPROM
location being accessed. TBLRDL and TBLWTL
instructions are used to read and write data EEPROM.
The dsPIC30F devices have up to 8 Kbytes (4K
words) of data EEPROM with an address range from
0x7FF000 to 0x7FFFFE.
Interrupt flag bit NVMIF in the IFS0 register is set when write is complete. It must be
cleared in software.
Reading the Data EEPROM
A TBLRD instruction reads a word at the current program word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4 as shown in Example 7-1.
EXAMPLE 7-1:
MOV
MOV
MOV
TBLRDL
DATA EEPROM READ
#LOW_ADDR_WORD,W0 ; Init Pointer

#HIGH_ADDR_WORD,W1
W1,TBLPAG
[ W0 ], W4
; read data EEPROM
A word write operation should be preceded by an erase

of the corresponding memory location(s). The write typically requires 2 ms to complete but the write time will
vary with voltage and temperature.
A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is responsible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
Preliminary
DS70116D-page 53
dsPIC30F5011/5013
7.2
7.2.1
Erasing Data EEPROM

ERASING A BLOCK OF DATA
EEPROM
In order to erase a block of data EEPROM, the

NVMADRU and NVMADR registers must initially point
to the block of memory to be erased. Configure
NVMCON for erasing a block of data EEPROM, and
set the ERASE and WREN bits in the NVMCON
register. Setting the WR bit initiates the erase as
shown in Example 7-2.
EXAMPLE 7-2:
DATA EEPROM BLOCK ERASE
; Select data EEPROM block, ERASE, WREN bits

MOV
#4045,W0
; Initialize NVMCON SFR
MOV
W0,NVMCON
; Start erase cycle by setting WR after writing key sequence
DISI
#5
; Block all interrupts with priority <7 for
; next 5 instructions
MOV
#0x55,W0
;
; Write the 0x55 key
MOV
W0,NVMKEY
MOV
#0xAA,W1
;
; Write the 0xAA key
MOV
W1,NVMKEY
BSET
NVMCON,#WR
; Initiate erase sequence
NOP
NOP
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
7.2.2
ERASING A WORD OF DATA

EEPROM
The TBLPAG and NVMADR registers must point to the

block. Select erase a block of data Flash, and set the
ERASE and WREN bits in the NVMCON register. Setting the WR bit initiates the erase as shown in
Example 7-3.
EXAMPLE 7-3:
DATA EEPROM WORD ERASE
; Select data EEPROM word, ERASE, WREN bits

MOV
#4044,W0
MOV
W0,NVMCON
; Start erase cycle by setting WR after writing key sequence
DISI
#5
MOV
#0x55,W0
;
MOV
W0,NVMKEY
MOV
#0xAA,W1
;
MOV
W1,NVMKEY
BSET
NVMCON,#WR
; Initiate erase sequence
NOP
NOP
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
DS70116D-page 54
Preliminary
dsPIC30F5011/5013
7.3
Writing to the Data EEPROM
To write an EEPROM data location, the following

sequence must be followed:
1.
2.
3.
Erase data EEPROM word.

a) Select word, data EEPROM erase, and set
WREN bit in NVMCON register.
b) Write address of word to be erased into
NVMADR.
c) Enable NVM interrupt (optional).
d) Write 55 to NVMKEY.
e) Write AA to NVMKEY.
f) Set the WR bit. This will begin erase cycle.
g) Either poll NVMIF bit or wait for NVMIF
interrupt.
h) The WR bit is cleared when the erase cycle
ends.
Write data word into data EEPROM write
latches.
Program 1 data word into data EEPROM.
a) Select word, data EEPROM program, and
set WREN bit in NVMCON register.
b) Enable NVM write done interrupt (optional).
c) Write 55 to NVMKEY.
d) Write AA to NVMKEY.
e) Set the WR bit. This will begin program
cycle.
f) Either poll NVMIF bit or wait for NVM
interrupt.
g) The WR bit is cleared when the write cycle
ends.
EXAMPLE 7-4:
The write will not initiate if the above sequence is not

exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code execution. The WREN bit should be kept clear at all times
except when updating the EEPROM. The WREN bit is
not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the Non-Volatile Memory
Write Complete Interrupt Flag bit (NVMIF) is set. The
user may either enable this interrupt or poll this bit.
NVMIF must be cleared by software.
7.3.1
WRITING A WORD OF DATA

EEPROM
Once the user has erased the word to be programmed,

then a table write instruction is used to write one write
latch, as shown in Example 7-4.
DATA EEPROM WORD WRITE
; Point to data memory

MOV
#LOW_ADDR_WORD,W0
MOV
#HIGH_ADDR_WORD,W1
MOV
W1,TBLPAG
MOV
#LOW(WORD),W2
TBLWTL
W2,[ W0]
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
MOV
#0x4004,W0
MOV
W0,NVMCON
; Operate key to allow write operation
DISI
#5
; Init pointer
; Get data
; Write data

MOV
#0x55,W0
MOV
W0,NVMKEY
MOV
#0xAA,W1
MOV
W1,NVMKEY
BSET
NVMCON,#WR
; Initiate program sequence
NOP
NOP
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
Preliminary
DS70116D-page 55
dsPIC30F5011/5013
7.3.2
WRITING A BLOCK OF DATA

EEPROM
To write a block of data EEPROM, write to all sixteen

latches first, then set the NVMCON register and
program the block.
EXAMPLE 7-5:
DATA EEPROM BLOCK WRITE
MOV
MOV
MOV
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
MOV
DISI
#5
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1,TBLPAG
#data1,W2
W2,[ W0]++
#data2,W2
W2,[ W0]++
#data3,W2
W2,[ W0]++
#data4,W2
W2,[ W0]++
#data5,W2
W2,[ W0]++
#data6,W2
W2,[ W0]++
#data7,W2
W2,[ W0]++
#data8,W2
W2,[ W0]++
#data9,W2
W2,[ W0]++
#data10,W2
W2,[ W0]++
#data11,W2
W2,[ W0]++
#data12,W2
W2,[ W0]++
#data13,W2
W2,[ W0]++
#data14,W2
W2,[ W0]++
#data15,W2
W2,[ W0]++
#data16,W2
W2,[ W0]++
#0x400A,W0
W0,NVMCON
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
W0,NVMKEY
#0xAA,W1
W1,NVMKEY
NVMCON,#WR
DS70116D-page 56
; Init pointer
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Get 1st data

write data
Get 2nd data
write data
Get 3rd data
write data
Get 4th data
write data
Get 5th data
write data
Get 6th data
write data
Get 7th data
write data
Get 8th data
write data
Get 9th data
write data
Get 10th data
write data
Get 11th data
write data
Get 12th data
write data
Get 13th data
write data
Get 14th data
write data
Get 15th data
write data
Get 16th data
write data. The NVMADR captures last table access address.
Select data EEPROM for multi word op
Operate Key to allow program operation
next 5 instructions

; Start write cycle
Preliminary
dsPIC30F5011/5013
7.4
Write Verify
7.5
Depending on the application, good programming

practice may dictate that the value written to the memory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
Protection Against Spurious Write
There are conditions when the device may not want to

write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared;
also, the Power-up Timer prevents EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
Preliminary
DS70116D-page 57
dsPIC30F5011/5013
NOTES:
DS70116D-page 58
Preliminary
dsPIC30F5011/5013
8.0
I/O PORTS
Any bit and its associated data and control registers

that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx
registers and the port pin will read as zeros.

Manual (DS70046).
When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.
All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKI) are shared between the peripherals and
the parallel I/O ports.
The format of the registers for PORTA are shown in

Table 8-1.
All I/O input ports feature Schmitt Trigger inputs for

improved noise immunity.
8.1
The TRISA (Data Direction Control) register controls

the direction of the RA<7:0> pins, as well as the INTx
pins and the VREF pins. The LATA register supplies
data to the outputs and is readable/writable. Reading
the PORTA register yields the state of the input pins,
while writing the PORTA register modifies the contents
of the LATA register.
Parallel I/O (PIO) Ports
When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read but the output driver for the parallel port bit
will be disabled. If a peripheral is enabled but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
A parallel I/O (PIO) port that shares a pin with a peripheral is, in general, subservient to the peripheral. The
peripherals output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell. Figure 8-2 shows how ports are shared
with other peripherals and the associated I/O cell (pad)
to which they are connected. Table 8-2 through
Table 8-9 show the formats of the registers for the
shared ports, PORTB through PORTG.
All port pins have three registers directly associated

with the operation of the port pin. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a 1, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch (LATx). Reads from
the port (PORTx), read the port pins and writes to the
port pins, write the latch (LATx).
FIGURE 8-1:
Note:
The actual bits in use vary between

devices.
BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE

Dedicated Port Module
Read TRIS
I/O Cell
TRIS Latch
Data Bus
WR TRIS
CK
Data Latch
D
WR LAT +
WR Port
I/O Pad
CK
Read LAT
Read Port
Preliminary
DS70116D-page 59
dsPIC30F5011/5013
FIGURE 8-2:
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

Output Multiplexers
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
I/O Cell
Peripheral Output Enable
1 Output Enable
0
Peripheral Output Data
PIO Module
Output Data
0
Read TRIS
I/O Pad
Data Bus
WR TRIS
CK
TRIS Latch
D
WR LAT +
WR Port
CK
Data Latch
Read LAT
Input Data
Read Port
8.2
8.2.1
Configuring Analog Port Pins
The use of the ADPCFG and TRIS registers control the

operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
When reading the Port register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a
digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
DS70116D-page 60
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port

direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
EXAMPLE 8-1:
MOV
0xFF00, W0
MOV
NOP
W0, TRISB
btss
PORTB, #13
Preliminary
PORT WRITE/READ
EXAMPLE
;
;
;
;
Configure PORTB<15:8>
as inputs
and PORTB<7:0> as outputs
additional instruction
cylcle
; bit test RB13 and skip if
set
Bit 13
Bit 12

LATA10
Bit 11
Bit 10
Preliminary
02D0
LATC
Legend:
Bit 14
Bit 13
LATC14
RC14
LATC13
RC13
02D0
LATC
Legend:
LATC15
RC15
02CE
Bit 14
Bit 13
LATC14
RC14
LATC13
RC13
TRISC15 TRISC14 TRISC13
02CC
Bit 15
PORTC
Addr.
TRISC
SFR
Name
LATB11
RB11
LATB10
RB10
LATB9
RB9
TRISB9
Bit 11
Bit 12
Bit 10
Bit 9
Bit 11
Bit 12
Bit 10
Bit 9
PORTC REGISTER MAP FOR dsPIC30F5013
LATC15
RC15
02CE
TABLE 8-4:
LATB12
RB12
TRISC15 TRISC14 TRISC13
02CC
Bit 15
PORTC
Addr.
LATB13
RB13
Bit 9
PORTC REGISTER MAP FOR dsPIC30F5011
TRISC
SFR
Name
LATB14
RB14
TABLE 8-3:
Legend:
LATB15
RB15
02CB
Bit 12
LATB
Bit 13
02C8
Bit 14
02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10
Bit 15
PORTB
Addr.
LATA9
RA9
Bit 8
Bit 8
Bit 8
LATB8
RB8
Bit 6
LATA6
RA6
TRISA6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
1111 0110 1100 0000
Reset State
Bit 7
Bit 6
RB6
Bit 5
Bit 5
LATB6
Bit 6
LATB7
RB7
LATC4
RC4
RB4
LATC3
RC3
TRISC3
Bit 3
RB3
RB2
LATC2
RC2
TRISC2
Bit 2
LATC2
RC2
TRISC2
RB1
Bit 1
LATB1
LATC1
RC1
TRISC1
Bit 1
LATC1
RC1
TRISC1
LATB2
Bit 2
LATB3
Bit 3
LATB4
TRISC4
Bit 4
Bit 4
LATB5
RB5
Bit 0
Bit 0
LATB0
RB0
0000 0000 0000 0000
0000 0000 0000 0000
1110 0000 0001 1110
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
1110 0000 0000 0110
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
Bit 7
LATA7
RA7
TRISA7
Bit 7
Bit 7
TRISB8
Bit 8
PORTB REGISTER MAP FOR dsPIC30F5011/5013
LATA12
RA10
TRISB
SFR
Name
TABLE 8-2:
LATA13
Bit 9
TRISA10 TRISA9
Bit 10
PORTA is not implemented in the dsPIC30F5011 device.
LATA14
RA12
Note:
LATA15
RA13
02C4
RA14
RA15
Bit 11
Legend:
02C2
PORTA
Bit 14
TRISA15 TRISA14 TRISA13 TRISA12
Bit 15
PORTA REGISTER MAP FOR dsPIC30F5013
LATA
02C0
Addr.
TRISA
SFR
Name
TABLE 8-1:
dsPIC30F5011/5013
DS70116D-page 61
DS70116D-page 62
02D6
LATD
Bit 13
Bit 12
Bit 10
Bit 9
LATD11
RD11
LATD10
RD10
LATD9
RD9
TRISD11 TRISD10 TRISD9
Bit 11
02E0
02E2
LATF
Preliminary
02E0
02E2
PORTF
LATF
Bit 14
Bit 15
02E8
LATG
LATD11
LATD10
RD10
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 8
LATF8
RF8
Bit 14
Bit 13
Bit 12
LATG15
RG15
LATG14
RG14
LATG12
RG12
Bit 10
Bit 11
LATG9
RG9
TRISG9
Bit 9
LATG8
RG8
TRISG8
Bit 8
LATG7
RG7
RD5
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
RD4
Bit 4
LATD4
RD3
Bit 3
LATD3
RD2
Bit 2
LATD2
RD1
Bit 1
LATD1
RD0
Bit 0
LATD0
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
Bit 5
RF5
Bit 5
LATF5
RF5
TRISF5
Bit 5
RD4
Bit 4
Bit 4
LATF4
RF4
TRISF4
Bit 4
LATF4
RF4
RD3
Bit 3
LATG3
RG3
TRISG3
Bit 3
LATF3
RF3
TRISF3
Bit 3
LATF3
RF3
RD2
Bit 2
LATF2
RF2
TRISF2
Bit 2
LATF2
RF2
TRISF2
Bit 2
LATG2
RG2
RD1
Bit 1
LATF1
RF1
TRISF1
Bit 1
LATF1
RF1
TRISF1
Bit 1
LATG1
RG1
RD0
Bit 0
LATF0
RF0
TRISF0
Bit 0
LATF0
RF0
TRISF0
Bit 0
LATD0
LATG0
RG0
TRISG0
LATD1
TRISG1
LATD2
TRISG2
LATD3
TRISF3
LATD4
TRISF4
LATD5
RD5
0000 0000 0000 0000
0000 0000 0000 0000
1111 0011 1100 1111
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0001 1111 1111
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0111 1111
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
Bit 5
LATD5
LATF5
LATG6
RG6
Bit 4
TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0000 1111 1111 1111
Bit 5
TRISF5
TRISG6
Bit 6
LATF6
RF6
TRISF6
TRISG7
Bit 7
LATF7
RF7
Bit 6
LATF6
RF6
TRISF6
Bit 6
LATD6
RD6
TRISD6
Bit 6
LATD6
RD6
TRISD6
Bit 6
LATG13
RG13
TRISG15 TRISG14 TRISG13 TRISG12
Bit 15
Bit 7
Bit 7
LATD7
RD7
TRISD7
Bit 7
LATD7
RD7
TRISD7
Bit 7
TRISF7
LATD8
RD8
TRISD8
TRISF8
LATD9
RD9
Bit 8
LATD8
RD8
TRISD8
Bit 8
PORTG REGISTER MAPFOR dsPIC30F5011/5013
02E6
Legend:
02E4
TRISG
Addr.
PORTG
SFR
Name
TABLE 8-9:
LATD12
RD11
PORTF REGISTER MAP FOR dsPIC30F5013
02DE
TRISF
Legend:
Addr.
SFR
Name
TABLE 8-8:
02DE
TRISF
PORTF
Bit 14
Bit 15
Legend:
LATD13
RD12
PORTF REGISTER MAP FOR dsPIC30F5011
Addr.
SFR
Name
LATD14
TABLE 8-7:
Legend:
LATD15
RD13
Bit 9
02D6
RD14
Bit 10
LATD
RD15
Bit 11
02D4
Bit 12
02D2 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9
Bit 13
PORTD
Bit 14
TRISD
Bit 15
Addr.
SFR
Name
PORTD REGISTER MAP FOR dsPIC30F5013
TABLE 8-6:
Legend:
02D4
02D2
TRISD
PORTD
Bit 14
Bit 15
PORTD REGISTER MAP FOR dsPIC30F5011
Addr.
SFR
Name
TABLE 8-5:
dsPIC30F5011/5013
dsPIC30F5011/5013
8.3
Input Change Notification Module
The input change notification module provides the

dsPIC30F devices the ability to generate interrupt
requests to the processor, in response to a change of
state on selected input pins. This module is capable of
detecting input change of states even in Sleep mode,
when the clocks are disabled. There are up to 24 external signals (CN0 through CN23) that may be selected
(enabled) for generating an interrupt request on a
change of state.
TABLE 8-10:
SFR
Name
INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5011 (BITS 15-8)
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset State
CNEN1
00C0
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
0000 0000 0000 0000
CNEN2
00C2
0000 0000 0000 0000
CNPU1
00C4
CN9PUE
CN8PUE
0000 0000 0000 0000
CNPU2
00C6
0000 0000 0000 0000
Legend:
TABLE 8-11:
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
SFR
Name
Addr.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CNEN1
00C0
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CNEN2
00C2
CN18IE
CNPU1
00C4
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CNPU2
00C6
Legend:
TABLE 8-12:
Bit 2
Bit 1
Bit 0
Reset State
CN1IE
CN0IE
0000 0000 0000 0000
CN17IE
CN16IE
0000 0000 0000 0000
CN1PUE
CN0PUE
0000 0000 0000 0000
CN18PUE CN17PUE
CN16PUE
0000 0000 0000 0000
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CNEN1
00C0
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
0000 0000 0000 0000
CNEN2
00C2
0000 0000 0000 0000
CNPU1
00C4
CN9PUE
CN8PUE
0000 0000 0000 0000
CNPU2
00C6
0000 0000 0000 0000
Legend:
TABLE 8-13:
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
Reset State
SFR
Name
Addr.
CNEN1
00C0
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CNEN2
00C2
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CNPU1
00C4
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CNPU2
00C6
Legend:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
CN1IE
CN0IE
0000 0000 0000 0000
CN17IE
CN16IE
0000 0000 0000 0000
CN1PUE
CN0PUE
0000 0000 0000 0000
CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE
CN16PUE
0000 0000 0000 0000
Preliminary
DS70116D-page 63
dsPIC30F5011/5013
NOTES:
DS70116D-page 64
Preliminary
dsPIC30F5011/5013
9.0
TIMER1 MODULE
These Operating modes are determined by setting the

appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
presents a block diagram of the 16-bit timer module.

Manual (DS70046).
16-bit Timer Mode: In the 16-bit Timer mode, the timer

increments on every instruction cycle up to a match
value preloaded into the Period register PR1, then
resets to 0 and continues to count.
This section describes the 16-bit General Purpose

(GP) Timer1 module and associated Operational
modes. Figure 9-1 depicts the simplified block diagram
of the 16-bit Timer1 module.
When the CPU goes into the Idle mode, the timer will
stop incrementing unless the TSIDL (T1CON<13>)
bit = 0. If TSIDL = 1, the timer module logic will resume
the incrementing sequence upon termination of the
CPU Idle mode.
The following sections provide a detailed description

including setup and control registers, along with associated block diagrams for the Operational modes of the
timers.
16-bit Synchronous Counter Mode: In the 16-bit

Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to 0 and continues.
The Timer1 module is a 16-bit timer which can serve as

the time counter for the real-time clock, or operate as a
free-running interval timer/counter. The 16-bit timer has
the following modes:
stop incrementing unless the respective TSIDL bit = 0.
If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
Idle mode.
16-bit Timer
16-bit Synchronous Counter
16-bit Asynchronous Counter
Further, the following operational characteristics are
supported:
16-bit Asynchronous Counter Mode: In the 16-bit

Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to 0 and continues.
Timer gate operation

Selectable prescaler settings
Timer operation during CPU Idle and Sleep
modes
Interrupt on 16-bit Period register match or falling
edge of external gate signal
FIGURE 9-1:
When the timer is configured for the Asynchronous

mode of operation and the CPU goes into the Idle
mode, the timer will stop incrementing if TSIDL = 1.
16-BIT TIMER1 MODULE BLOCK DIAGRAM

PR1
Equal
Comparator x 16
TSYNC
1
Reset
Sync
TMR1
0
T1IF
Event Flag
0
1
CK
TGATE
TCS
TGATE
TGATE
TON
SOSCO/
T1CK
1x
LPOSCEN
SOSCI
TCKPS<1:0>
2
Gate
Sync
01
TCY
00
Preliminary
Prescaler
1, 8, 64, 256
DS70116D-page 65
dsPIC30F5011/5013
9.1
Timer Gate Operation
9.4
The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to
increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
stop incrementing unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode.
9.2
Timer Prescaler
The input clock (FOSC/4 or external clock) to the 16-bit

Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256,
selected by control bits TCKPS<1:0> (T1CON<5:4>).
The prescaler counter is cleared when any of the
following occurs:
a write to the TMR1 register
a write to the T1CON register
device Reset, such as POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
TMR1 is not cleared when T1CON is written. It is
cleared by writing to the TMR1 register.
9.3
Timer Interrupt
The 16-bit timer has the ability to generate an interrupt on

period match. When the timer count matches the Period
register, the T1IF bit is asserted and an interrupt will be
generated if enabled. The T1IF bit must be cleared in
software. The timer interrupt flag, T1IF, is located in the
IFS0 Control register in the interrupt controller.
When the Gated Time Accumulation mode is enabled,
an interrupt will also be generated on the falling edge of
the gate signal (at the end of the accumulation cycle).
Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 Control register in the
interrupt controller.
9.5
Real-Time Clock
Timer1, when operating in Real-Time Clock (RTC)

mode, provides time of day and event time-stamping
capabilities. Key operational features of the RTC are:
Operation from 32 kHz LP oscillator

8-bit prescaler
Low power
Real-Time Clock interrupts
These operating modes are determined by setting the

appropriate bit(s) in the T1CON Control register.
FIGURE 9-2:
RECOMMENDED
COMPONENTS FOR
TIMER1 LP OSCILLATOR
RTC
Timer Operation During Sleep

Mode
During CPU Sleep mode, the timer will operate if:

The timer module is enabled (TON = 1) and
The timer clock source is selected as external
(TCS = 1) and
The TSYNC bit (T1CON<2>) is asserted to a logic
0 which defines the external clock source as
asynchronous.
When all three conditions are true, the timer will continue to count up to the Period register and be reset to
0x0000.
When a match between the timer and the Period register occurs, an interrupt can be generated if the
respective timer interrupt enable bit is asserted.
DS70116D-page 66
Preliminary
C1
SOSCI
32.768 kHz
XTAL
dsPIC30FXXXX
SOSCO
C2
C1 = C2 = 18 pF; R = 100K
dsPIC30F5011/5013
9.5.1
RTC OSCILLATOR OPERATION
9.5.2
When the TON = 1, TCS = 1 and TGATE = 0, the timer

increments on the rising edge of the 32 kHz LP oscillator output signal, up to the value specified in the Period
register and is then reset to 0.
The TSYNC bit must be asserted to a logic 0
(Asynchronous mode) for correct operation.
Enabling LPOSCEN (OSCCON<1>) will disable the
normal Timer and Counter modes and enable a timer
carry-out wake-up event.
RTC INTERRUPTS
When an interrupt event occurs, the respective interrupt

flag, T1IF, is asserted and an interrupt will be generated
if enabled. The T1IF bit must be cleared in software. The
respective Timer interrupt flag, T1IF, is located in the
IFS0 Status register in the interrupt controller.
Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 Control register in the
interrupt controller.
When the CPU enters Sleep mode, the RTC will continue to operate provided the 32 kHz external crystal
oscillator is active and the control bits have not been
changed. The TSIDL bit should be cleared to 0 in
order for RTC to continue operation in Idle mode.
Preliminary
DS70116D-page 67
0102
0104
PR1
T1CON
Legend:
DS70116D-page 68
Bit 14
TSIDL
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 7
Bit 6
TGATE
Period Register 1
Timer1 Register
Bit 8
Bit 4
TCKPS1 TCKPS0
Bit 5
TON
0100
TMR1
Bit 15
Addr.
TIMER1 REGISTER MAP
SFR Name
TABLE 9-1:
Bit 3
TSYNC
Bit 2
TCS
Bit 1
Bit 0
0000 0000 0000 0000
1111 1111 1111 1111
uuuu uuuu uuuu uuuu
Reset State
dsPIC30F5011/5013
Preliminary
dsPIC30F5011/5013
10.0
TIMER2/3 MODULE
For 32-bit timer/counter operation, Timer2 is the LS

Word and Timer3 is the MS Word of the 32-bit timer.

Manual (DS70046).
This section describes the 32-bit General Purpose

(GP) Timer module (Timer2/3) and associated Operational modes. Figure 10-1 depicts the simplified block
diagram of the 32-bit Timer2/3 module. Figure 10-2
and Figure 10-3 show Timer2/3 configured as two
independent 16-bit timers, Timer2 and Timer3,
respectively.
The Timer2/3 module is a 32-bit timer (which can be
configured as two 16-bit timers) with selectable
Operating modes. These timers are utilized by other
peripheral modules, such as:
Input Capture
Output Compare/Simple PWM
The following sections provide a detailed description,
including setup and control registers, along with associated block diagrams for the Operational modes of the
timers.
The 32-bit timer has the following modes:
Further, the following operational characteristics are

supported:
ADC event trigger
Timer gate operation
Selectable prescaler settings
Timer operation during Idle and Sleep modes
Interrupt on a 32-bit period register match

appropriate bit(s) in the 16-bit T2CON and T3CON
SFRs.
For 32-bit timer operation, T3CON control

bits are ignored. Only T2CON control bits
are used for setup and control. Timer2
clock and gate inputs are utilized for the
32-bit timer module but an interrupt is generated with the Timer3 interrupt flag (T3IF)
and the interrupt is enabled with the
Timer3 interrupt enable bit (T3IE).
16-bit Timer Mode: In the 16-bit mode, Timer2 and

Timer3 can be configured as two independent 16-bit
timers. Each timer can be set up in either 16-bit Timer
mode or 16-bit Synchronous Counter mode. See
Section 9.0, Timer1 Module for details on these two
Operating modes.
The only functional difference between Timer2 and
Timer3 is that Timer2 provides synchronization of the
clock prescaler output. This is useful for high frequency
external clock inputs.
32-bit Timer Mode: In the 32-bit Timer mode, the timer
increments on every instruction cycle, up to a match
value preloaded into the combined 32-bit Period
register PR3/PR2, then resets to 0 and continues to
count.
For synchronous 32-bit reads of the Timer2/Timer3
pair, reading the LS Word (TMR2 register) will cause
the MS word to be read and latched into a 16-bit
holding register, termed TMR3HLD.
Two independent 16-bit timers (Timer2 and

Timer3) with all 16-bit Operating modes (except
Asynchronous Counter mode)
Single 32-bit timer operation
Single 32-bit synchronous counter
Note:
For synchronous 32-bit writes, the holding register

(TMR3HLD) must first be written to. When followed by
a write to the TMR2 register, the contents of TMR3HLD
will be transferred and latched into the MSB of the
32-bit timer (TMR3).
32-bit Synchronous Counter Mode: In the 32-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in the
combined 32-bit period register PR3/PR2, then resets
to 0 and continues.
When the timer is configured for the Synchronous
Counter mode of operation and the CPU goes into the
Idle mode, the timer will stop incrementing unless the
TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
module logic will resume the incrementing sequence
upon termination of the CPU Idle mode.
Preliminary
DS70116D-page 69
dsPIC30F5011/5013
FIGURE 10-1:
32-BIT TIMER2/3 BLOCK DIAGRAM

Data Bus<15:0>
TMR3HLD
16
16
Write TMR2
Read TMR2
16
Reset
TMR3
TMR2
MSB
LSB
Sync
ADC Event Trigger

Equal
Comparator x 32
PR3
PR2
T3IF
Event Flag
CK
TGATE (T2CON<6>)
TCS
TGATE
TGATE
(T2CON<6>)
TON
T2CK
Note:
TCKPS<1:0>
2
1x
Gate
Sync
01
TCY
00
Prescaler
1, 8, 64, 256
Timer configuration bit T32 (T2CON<3>) must be set to 1 for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.
DS70116D-page 70
Preliminary
dsPIC30F5011/5013
FIGURE 10-2:
16-BIT TIMER2 BLOCK DIAGRAM

PR2
Equal
Comparator x 16
TMR2
Sync
Reset
T2IF
Event Flag
0
1
CK
TGATE
TCS
TGATE
TGATE
TON
T2CK
FIGURE 10-3:
TCKPS<1:0>
2
1x
Gate
Sync
01
TCY
00
Prescaler
1, 8, 64, 256

PR3
ADC Event Trigger
Equal
Comparator x 16
TMR3
Reset
0
1
CK
TGATE
TCS
TGATE
T3IF
Event Flag
TGATE
T3CK
Sync
TON
1x
01
TCY
Preliminary
TCKPS<1:0>
2
Prescaler
1, 8, 64, 256
00
DS70116D-page 71
dsPIC30F5011/5013
10.1
Timer Gate Operation
10.4
The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to
increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit TGATE
(T2CON<6>) must be set to enable this mode. When in
this mode, Timer2 is the originating clock source. The
TGATE setting is ignored for Timer3. The timer must be
enabled (TON = 1) and the timer clock source set to
internal (TCS = 0).
The falling edge of the external signal terminates the
count operation but does not reset the timer. The user
must reset the timer in order to start counting from zero.
10.2
ADC Event Trigger
When a match occurs between the 32-bit timer (TMR3/

TMR2) and the 32-bit combined period register (PR3/
PR2), or between the 16-bit timer TMR3 and the 16-bit
period register PR3, a special ADC trigger event signal
is generated by Timer3.
10.3
Timer Operation During Sleep

Mode
During CPU Sleep mode, the timer will not operate

because the internal clocks are disabled.
10.5
Timer Interrupt
The 32-bit timer module can generate an interrupt on

period match or on the falling edge of the external gate
signal. When the 32-bit timer count matches the
respective 32-bit period register, or the falling edge of
the external gate signal is detected, the T3IF bit
(IFS0<7>) is asserted and an interrupt will be generated if enabled. In this mode, the T3IF interrupt flag is
used as the source of the interrupt. The T3IF bit must
be cleared in software.
Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T3IE (IEC0<7>).
Timer Prescaler
The input clock (FOSC/4 or external clock) to the timer

has a prescale option of 1:1, 1:8, 1:64, and 1:256,
selected by control bits TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
originating clock source is Timer2. The prescaler operation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
a write to the TMR2/TMR3 register
a write to the T2CON/T3CON register
device Reset, such as POR and BOR
However, if the timer is disabled (TON = 0), then the
Timer 2 prescaler cannot be reset since the prescaler
clock is halted.
TMR2/TMR3 is not cleared when T2CON/T3CON is
written.
DS70116D-page 72
Preliminary
010A
010C
010E
0110
0112
TMR3
PR2
PR3
T2CON
T3CON
Legend:
TSIDL
TSIDL
Bit 12
Bit 11
Bit 9
Bit 7
Timer2 Register
Bit 8
Bit 6
Bit 5
TGATE
TGATE
Period Register 3
Period Register 2
Timer3 Register
Bit 4
TCKPS1 TCKPS0
TCKPS1 TCKPS0
Timer3 Holding Register (for 32-bit timer operations only)
Bit 10
TON
0108
TMR3HLD
TON
0106
TMR2
Bit 13
Bit 15
SFR Name Addr.
Bit 14
TIMER2/3 REGISTER MAP
TABLE 10-1:
T32
Bit 3
Bit 2
TCS
TCS
Bit 1
Bit 0
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
Reset State
dsPIC30F5011/5013
Preliminary
DS70116D-page 73
dsPIC30F5011/5013
NOTES:
DS70116D-page 74
Preliminary
dsPIC30F5011/5013
11.0
TIMER4/5 MODULE
The Timer4/5 module does not support the ADC

event trigger feature
Timer4/5 can not be utilized by other peripheral
modules, such as input capture and
output compare

Manual (DS70046).
The Operating modes of the Timer4/5 module are

determined by setting the appropriate bit(s) in the
16-bit T4CON and T5CON SFRs.
This section describes the second 32-bit General Purpose (GP) Timer module (Timer4/5) and associated
Operational modes. Figure 11-1 depicts the simplified
block diagram of the 32-bit Timer4/5 module.
Figure 11-2 and Figure 11-3 show Timer4/5 configured
as two independent 16-bit timers, Timer4 and Timer5,
respectively.
For 32-bit timer/counter operation, Timer4 is the LS

Word and Timer5 is the MS Word of the 32-bit timer.
Note:
The Timer4/5 module is similar in operation to the

Timer2/3 module. However, there are some differences
which are listed as follows:
FIGURE 11-1:
For 32-bit timer operation, T5CON control

bits are ignored. Only T4CON control bits
are used for setup and control. Timer4
clock and gate inputs are utilized for the
32-bit timer module but an interrupt is generated with the Timer5 interrupt flag (T5IF)
and the interrupt is enabled with the
Timer5 interrupt enable bit (T5IE).
32-BIT TIMER4/5 BLOCK DIAGRAM

Data Bus<15:0>
TMR5HLD
16
16
Write TMR4
Read TMR4
16
Reset
Equal
TMR5
TMR4
MSB
LSB
Sync
Comparator x 32
PR5
PR4
0
T5IF
Event Flag
CK
TGATE (T4CON<6>)
TCS
TGATE
TGATE
(T4CON<6>)
TON
T4CK
Note:
TCKPS<1:0>
2
1x
Gate
Sync
01
TCY
00
Prescaler
1, 8, 64, 256
Timer configuration bit T32 (T4CON<3>) must be set to 1 for a 32-bit timer/counter operation. All control
bits are respective to the T4CON register.
Preliminary
DS70116D-page 75
dsPIC30F5011/5013
FIGURE 11-2:

PR4
Equal
Reset
TMR4
Sync
0
1
CK
TGATE
TCS
TGATE
T4IF
Event Flag
Comparator x 16
TGATE
TON
T4CK
FIGURE 11-3:
TCKPS<1:0>
2
1x
Gate
Sync
01
TCY
00
Prescaler
1, 8, 64, 256

PR5
ADC Event Trigger
Equal
Comparator x 16
TMR5
Reset
0
1
CK
TGATE
TCS
TGATE
T5IF
Event Flag
TGATE
T5CK
TON
Sync
1x
01
TCY
Note:
TCKPS<1:0>
2
Prescaler
1, 8, 64, 256
00
In the dsPIC30F5011 device, there is no T5CK pin. Therefore, in this device the following modes should
not be used for Timer5:
1: TCS = 1 (16-bit counter)
2: TCS = 0, TGATE = 1 (gated time accumulation)
DS70116D-page 76
Preliminary
0120
T5CON
TON
TON
Bit 15
Bit 14
TSIDL
TSIDL
Bit 13
Bit 12
TIMER4/5 REGISTER MAP
u = uninitialized
011E
T4CON
Legend:
011A
011C
0118
TMR5
PR4
0116
PR5
0114
TMR4
Addr.
TMR5HLD
SFR Name
TABLE 11-1:
Bit 11
Bit 9
Bit 7
Bit 6
Timer 4 Register
Bit 8
Bit 5
TGATE
TGATE
Period Register 5
Period Register 4
Timer 5 Register
TCKPS1
TCKPS1
Timer 5 Holding Register (for 32-bit operations only)
Bit 10
TCKPS0
TCKPS0
Bit 4
T45
Bit 3
Bit 2
TCS
TCS
Bit 1
Bit 0
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
Reset State
dsPIC30F5011/5013
Preliminary
DS70116D-page 77
dsPIC30F5011/5013
NOTES:
DS70116D-page 78
Preliminary
dsPIC30F5011/5013
12.0
INPUT CAPTURE MODULE
12.1
Simple Capture Event Mode
The simple capture events in the dsPIC30F product

family are:

Manual (DS70046).
This section describes the input capture module and

associated Operational modes. The features provided
by this module are useful in applications requiring frequency (period) and pulse measurement. Figure 12-1
depicts a block diagram of the input capture module.
Input capture is useful for such modes as:
Capture every falling edge

Capture every rising edge
Capture every 4th rising edge
Capture every 16th rising edge
Capture every rising and falling edge
These simple Input Capture modes are configured by

setting the appropriate bits ICM<2:0> (ICxCON<2:0>).
12.1.1
Frequency/Period/Pulse Measurements
Additional Sources of External Interrupts
CAPTURE PRESCALER
There are four input capture prescaler settings specified by bits ICM<2:0> (ICxCON<2:0>). Whenever the
capture channel is turned off, the prescaler counter will
be cleared. In addition, any Reset will clear the
prescaler counter.
The key operational features of the input capture

module are:
Simple Capture Event mode
Timer2 and Timer3 mode selection
Interrupt on input capture event
appropriate bits in the ICxCON register (where
x = 1,2,...,N). The dsPIC devices contain up to 8
capture channels (i.e., the maximum value of N is 8).
FIGURE 12-1:
INPUT CAPTURE MODE BLOCK DIAGRAM

From GP Timer Module
T3_CNT
T2_CNT
16
ICx pin
Prescaler
1, 4, 16
3
Clock
Synchronizer
Edge
Detection
Logic
16
ICTMR
FIFO
R/W
Logic
ICM<2:0>
Mode Select
ICxBUF
ICBNE, ICOV
ICI<1:0>
ICxCON
Interrupt
Logic
Data Bus
Note:
Set Flag
ICxIF
Where x is shown, reference is made to the registers or bits associated to the respective input capture
channels 1 through N.
Preliminary
DS70116D-page 79
dsPIC30F5011/5013
12.1.2
CAPTURE BUFFER OPERATION
12.2
Each capture channel has an associated FIFO buffer

which is four 16-bit words deep. There are two status
flags which provide status on the FIFO buffer:
ICBFNE - Input Capture Buffer Not Empty
ICOV - Input Capture Overflow
The ICBFNE will be set on the first input capture event
and remain set until all capture events have been read
from the FIFO. As each word is read from the FIFO, the
remaining words are advanced by one position within
the buffer.
In the event that the FIFO is full with four capture
events and a fifth capture event occurs prior to a read
of the FIFO, an overflow condition will occur and the
ICOV bit will be set to a logic 1. The fifth capture event
is lost and is not stored in the FIFO. No additional
events will be captured until all four events have been
read from the buffer.
If a FIFO read is performed after the last read and no
new capture event has been received, the read will
yield indeterminate results.
12.1.3
TIMER2 AND TIMER3 SELECTION

MODE
The input capture module consists of up to 8 input capture channels. Each channel can select between one of
two timers for the time base, Timer2 or Timer3.
Selection of the timer resource is accomplished
through SFR bit, ICTMR (ICxCON<7>). Timer3 is the
default timer resource available for the input capture
module.
12.1.4
HALL SENSOR MODE
When the input capture module is set for capture on

every edge, rising and falling, ICM<2:0> = 001, the following operations are performed by the input capture
logic:
The input capture interrupt flag is set on every
edge, rising and falling.
The interrupt on Capture mode setting bits,
ICI<1:0>, is ignored since every capture
generates an interrupt.
A capture overflow condition is not generated in
this mode.
Input Capture Operation During

Sleep and Idle Modes
An input capture event will generate a device wake-up

or interrupt, if enabled, if the device is in CPU Idle or
Sleep mode.
Independent of the timer being enabled, the input capture module will wake-up from the CPU Sleep or Idle
mode when a capture event occurs if ICM<2:0> = 111
and the interrupt enable bit is asserted. The same wakeup can generate an interrupt if the conditions for processing the interrupt have been satisfied. The wake-up
feature is useful as a method of adding extra external pin
interrupts.
12.2.1
INPUT CAPTURE IN CPU SLEEP

MODE
CPU Sleep mode allows input capture module operation with reduced functionality. In the CPU Sleep mode,
the ICI<1:0> bits are not applicable and the input capture module can only function as an external interrupt
source.
The capture module must be configured for interrupt
only on rising edge (ICM<2:0> = 111) in order for the
input capture module to be used while the device is in
Sleep mode. The prescale settings of 4:1 or 16:1 are
not applicable in this mode.
12.2.2
INPUT CAPTURE IN CPU IDLE

MODE
CPU Idle mode allows input capture module operation

with full functionality. In the CPU Idle mode, the Interrupt mode selected by the ICI<1:0> bits is applicable,
as well as the 4:1 and 16:1 capture prescale settings
which are defined by control bits ICM<2:0>. This mode
requires the selected timer to be enabled. Moreover,
the ICSIDL bit must be asserted to a logic 0.
If the input capture module is defined as
ICM<2:0> = 111 in CPU Idle mode, the input capture
pin will serve only as an external interrupt pin.
12.3
Input Capture Interrupts
The input capture channels have the ability to generate

an interrupt based upon the selected number of capture events. The selection number is set by control bits
ICI<1:0> (ICxCON<6:5>).
Each channel provides an interrupt flag (ICxIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx Status register.
Enabling an interrupt is accomplished via the respective capture channel interrupt enable (ICxIE) bit. The
capture interrupt enable bit is located in the
corresponding IEC Control register.
DS70116D-page 80
Preliminary
014A
014C
014E
0150
0152
0154
0156
0158
015A
015C
015E
IC3CON
IC4BUF
IC4CON
IC5BUF
IC5CON
IC6BUF
IC6CON
IC7BUF
IC7CON
IC8BUF
IC8CON
Bit 15
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
Bit 13
Bit 12
Bit 11
Bit 10
Bit 8
Bit 7
ICTMR
ICTMR
ICTMR
ICTMR
ICTMR
ICTMR
ICTMR
ICTMR
Input 8 Capture Register
Bit 9
Bit 5
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
Bit 6
Bit 14
INPUT CAPTURE REGISTER MAP
0148
IC3BUF
Legend:
0144
0146
IC2CON
IC1CON
IC2BUF
0140
0142
IC1BUF
Addr.
SFR Name
TABLE 12-1:
ICOV
ICOV
ICOV
ICOV
ICOV
ICOV
ICOV
ICOV
Bit 4
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
Bit 3
Bit 2
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
Bit 1
Bit 0
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
Reset State
dsPIC30F5011/5013
Preliminary
DS70116D-page 81
dsPIC30F5011/5013
NOTES:
DS70116D-page 82
Preliminary
dsPIC30F5011/5013
13.0
OUTPUT COMPARE MODULE
The key operational features of the output compare

module include:

Manual (DS70046).
This section describes the output compare module and

associated Operational modes. The features provided
by this module are useful in applications requiring
Operational modes, such as:
Generation of Variable Width Output Pulses
Power Factor Correction
Figure 13-1 depicts a block diagram of the output
compare module.
FIGURE 13-1:
Timer2 and Timer3 Selection mode

Simple Output Compare Match mode
Dual Output Compare Match mode
Simple PWM mode
Output Compare During Sleep and Idle modes
Interrupt on Output Compare/PWM Event

appropriate bits in the 16-bit OCxCON SFR (where
x = 1,2,3,...,N). The dsPIC devices contain up to 8
compare channels (i.e., the maximum value of N is 8).
OCxRS and OCxR in Figure 13-1 represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
OUTPUT COMPARE MODE BLOCK DIAGRAM

Set Flag bit
OCxIF
OCxRS
Output
Logic
OCxR
OCTSEL
Note:
OCx
OCFA
(for x = 1, 2, 3 or 4)
or OCFB
(for x = 5, 6, 7 or 8)
From GP
Timer Module
TMR2<15:0
Output
Enable
OCM<2:0>
Mode Select
Comparator
S Q
R
TMR3<15:0> T2P2_MATCH
T3P3_MATCH
Where x is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
Preliminary
DS70116D-page 83
dsPIC30F5011/5013
13.1
Timer2 and Timer3 Selection Mode
Each output compare channel can select between one

of two 16-bit timers, Timer2 or Timer3.
The selection of the timers is controlled by the OCTSEL
bit (OCxCON<3>). Timer2 is the default timer resource
for the output compare module.
13.2
Simple Output Compare Match

Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 001,

010 or 011, the selected output compare channel is
configured for one of three simple Output Compare
Match modes:
Compare forces I/O pin low
Compare forces I/O pin high
Compare toggles I/O pin
Dual Output Compare Match Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 100

or 101, the selected output compare channel is configured for one of two Dual Output Compare modes,
which are:
Single Output Pulse mode
Continuous Output Pulse mode
13.3.1
Determine instruction cycle time TCY.

Calculate desired pulse width value based on TCY.
Calculate time to start pulse from timer start value
of 0x0000.
Write pulse width start and stop times into OCxR
and OCxRS Compare registers (x denotes
channel 1, 2, ...,N).
Set Timer Period register to value equal to, or
greater than value in OCxRS Compare register.
Set OCM<2:0> = 100.
Enable timer, TON (TxCON<15>) = 1.
To initiate another single pulse, issue another write to
set OCM<2:0> = 100.
Simple PWM Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 110

or 111, the selected output compare channel is configured for the PWM mode of operation. When configured
for the PWM mode of operation, OCxR is the main latch
(read only) and OCxRS is the secondary latch. This
enables glitchless PWM transitions.
The user must perform the following steps in order to
configure the output compare module for PWM
operation:
1.
2.
4.
For the user to configure the module for the generation

of a single output pulse, the following steps are
required (assuming timer is off):
DS70116D-page 84
Determine instruction cycle time TCY.

Calculate desired pulse value based on TCY.
Calculate timer to start pulse width from timer start
value of 0x0000.
Write pulse width start and stop times into OCxR
and OCxRS (x denotes channel 1, 2, ...,N)
Compare registers, respectively.
Set Timer Period register to value equal to, or
greater than value in OCxRS Compare register.
Set OCM<2:0> = 101.
Enable timer, TON (TxCON<15>) = 1.
3.
SINGLE PULSE MODE
CONTINUOUS PULSE MODE
For the user to configure the module for the generation

of a continuous stream of output pulses, the following
steps are required:
13.4
The OCxR register is used in these modes. The OCxR

register is loaded with a value and is compared to the
selected incrementing timer count. When a compare
occurs, one of these Compare Match modes occurs. If
the counter resets to zero before reaching the value in
OCxR, the state of the OCx pin remains unchanged.
13.3
13.3.2
Set the PWM period by writing to the appropriate

period register.
Set the PWM duty cycle by writing to the OCxRS
register.
Configure the output compare module for PWM
operation.
Set the TMRx prescale value and enable the
Timer, TON (TxCON<15>) = 1.
13.4.1
INPUT PIN FAULT PROTECTION

FOR PWM
When control bits OCM<2:0> (OCxCON<2:0>) = 111,

the selected output compare channel is again configured for the PWM mode of operation with the additional
feature of input FAULT protection. While in this mode,
if a logic 0 is detected on the OCFA/B pin, the respective PWM output pin is placed in the high impedance
input state. The OCFLT bit (OCxCON<4>) indicates
whether a FAULT condition has occurred. This state will
be maintained until both of the following events have
occurred:
The external FAULT condition has been removed.
The PWM mode has been re-enabled by writing
to the appropriate control bits.
Preliminary
dsPIC30F5011/5013
13.4.2
PWM PERIOD
When the selected TMRx is equal to its respective

period register, PRx, the following four events occur on
the next increment cycle:
The PWM period is specified by writing to the PRx

register. The PWM period can be calculated using
Equation 13-1.
TMRx is cleared.
The OCx pin is set.
- Exception 1: If PWM duty cycle is 0x0000,
the OCx pin will remain low.
- Exception 2: If duty cycle is greater than PRx,
the pin will remain high.
The PWM duty cycle is latched from OCxRS into
OCxR.
The corresponding timer interrupt flag is set.
EQUATION 13-1:
PWM period = [(PRx) + 1] 4 TOSC
(TMRx prescale value)
PWM frequency is defined as 1 / [PWM period].
See Figure 13-2 for key PWM period comparisons.

Timer3 is referred to in Figure 13-2 for clarity.
FIGURE 13-2:
PWM OUTPUT TIMING

Period
Duty Cycle
TMR3 = PR3
T3IF = 1
(Interrupt Flag)
OCxR = OCxRS
TMR3 = PR3
T3IF = 1
(Interrupt Flag)
OCxR = OCxRS
TMR3 = Duty Cycle

(OCxR)
13.5
Output Compare Operation During

CPU Sleep Mode
When the CPU enters Sleep mode, all internal clocks

are stopped. Therefore, when the CPU enters the
Sleep state, the output compare channel will drive the
pin to the active state that was observed prior to
entering the CPU Sleep state.
For example, if the pin was high when the CPU entered
the Sleep state, the pin will remain high. Likewise, if the
pin was low when the CPU entered the Sleep state, the
pin will remain low. In either case, the output compare
module will resume operation when the device wakes
up.
13.6
Output Compare Operation During

CPU Idle Mode
When the CPU enters the Idle mode, the output

compare module can operate with full functionality.
The output compare channel will operate during the
CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at
logic 0 and the selected time base (Timer2 or Timer3)
is enabled and the TSIDL bit of the selected timer is set
to logic 0.
TMR3 = Duty Cycle

(OCxR)
13.7
Output Compare Interrupts
The output compare channels have the ability to generate an interrupt on a compare match, for whichever
Match mode has been selected.
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt will be generated if enabled.
The OCxIF bit is located in the corresponding IFS
Status register and must be cleared in software. The
interrupt is enabled via the respective compare interrupt enable (OCxIE) bit located in the corresponding
IEC Control register.
For the PWM mode, when an event occurs, the respective timer interrupt flag (T2IF or T3IF) is asserted and
an interrupt will be generated if enabled. The IF bit is
located in the IFS0 Status register and must be cleared
in software. The interrupt is enabled via the respective
timer interrupt enable bit (T2IE or T3IE) located in the
IEC0 Control register. The output compare interrupt
flag is never set during the PWM mode of operation.
Preliminary
DS70116D-page 85
0184
0186
0188
018A
018C
018E
0190
0192
0194
0196
0198
019A
019C
019E
01A0
01A2
01A4
01A6
01A8
01AA
01AC
01AE
OC2RS
OC2R
OC2CON
OC3RS
OC3R
OC3CON
DS70116D-page 86
OC4RS
OC4R
OC4CON
OC5RS
OC5R
OC5CON
OC6RS
OC6R
OC6CON
OC7RS
OC7R
OC7CON
OC8RS
OC8R
OC8CON
Legend:
Preliminary
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
Bit 8
Bit 7
Bit 6
Output Compare 1 Main Register
Output Compare 8 Secondary Register
Bit 5
Bit 9
0182
Bit 10
OC1CON
Bit 11
OC1R
Bit 12
0180
Bit 13
Bit 15
Addr.
SFR Name
OC1RS
Bit 14
OUTPUT COMPARE REGISTER MAP
TABLE 13-1:
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
Bit 4
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSE
OCTSEL
Bit 3
Bit 2
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
Bit 1
Bit 0
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
dsPIC30F5011/5013
dsPIC30F5011/5013
14.0
SPI MODULE

Manual (DS70046).
The Serial Peripheral Interface (SPI) module is a synchronous serial interface. It is useful for communicating
with other peripheral devices, such as EEPROMs, shift
registers, display drivers and A/D converters, or other
microcontrollers. It is compatible with Motorola's SPI
and SIOP interfaces.
14.1
Operating Function Description
Each SPI module consists of a 16-bit shift register,

SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates various status conditions.
The serial interface consists of 4 pins: SDIx (serial data
input), SDOx (serial data output), SCKx (shift clock
input or output), and SSx (active low slave select).
In Master mode operation, SCK is a clock output but in
Slave mode, it is a clock input.
A series of eight (8) or sixteen (16) clock pulses shift
out bits from the SPIxSR to SDOx pin and simultaneously shift in data from SDIx pin. An interrupt is generated when the transfer is complete and the
corresponding interrupt flag bit (SPI1IF or SPI2IF) is
set. This interrupt can be disabled through an interrupt
enable bit (SPI1IE or SPI2IE).
The receive operation is double-buffered. When a complete byte is received, it is transferred from SPIxSR to
SPIxBUF.
If the receive buffer is full when new data is being transferred from SPIxSR to SPIxBUF, the module will set the
SPIROV bit indicating an overflow condition. The transfer of the data from SPIxSR to SPIxBUF will not be
completed and the new data will be lost. The module
will not respond to SCL transitions while SPIROV is 1,
effectively disabling the module until SPIxBUF is read
by user software.
Transmit writes are also double-buffered. The user
writes to SPIxBUF. When the master or slave transfer
is completed, the contents of the shift register (SPIxSR)
are moved to the receive buffer. If any transmit data has
been written to the buffer register, the contents of the
transmit buffer are moved to SPIxSR. The received
data is thus placed in SPIxBUF and the transmit data in
SPIxSR is ready for the next transfer.
Note:
In Master mode, the clock is generated by prescaling

the system clock. Data is transmitted as soon as a
value is written to SPIxBUF. The interrupt is generated
at the middle of the transfer of the last bit.
In Slave mode, data is transmitted and received as
external clock pulses appear on SCK. Again, the interrupt is generated when the last bit is latched. If SSx
control is enabled, then transmission and reception are
enabled only when SSx = low. The SDOx output will be
disabled in SSx mode with SSx high.
The clock provided to the module is (FOSC/4). This
clock is then prescaled by the primary (PPRE<1:0>)
and the secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on transition from active clock state to Idle clock state, or vice
versa. The CKP bit selects the Idle state (high or low)
for the clock.
14.1.1
WORD AND BYTE

COMMUNICATION
A control bit, MODE16 (SPIxCON<10>), allows the

module to communicate in either 16-bit or 8-bit mode.
16-bit operation is identical to 8-bit operation except
that the number of bits transmitted is 16 instead of 8.
The user software must disable the module prior to
changing the MODE16 bit. The SPI module is reset
when the MODE16 bit is changed by the user.
A basic difference between 8-bit and 16-bit operation is
that the data is transmitted out of bit 7 of the SPIxSR for
8-bit operation, and data is transmitted out of bit15 of
the SPIxSR for 16-bit operation. In both modes, data is
shifted into bit 0 of the SPIxSR.
14.1.2
SDOx DISABLE
A control bit, DISSDO, is provided to the SPIxCON register to allow the SDOx output to be disabled. This will
allow the SPI module to be connected in an input only
configuration. SDO can also be used for general
purpose I/O.
14.2
Framed SPI Support
The module supports a basic framed SPI protocol in

Master or Slave mode. The control bit FRMEN enables
framed SPI support and causes the SSx pin to perform
the frame synchronization pulse (FSYNC) function.
The control bit SPIFSD determines whether the SSx
pin is an input or an output (i.e., whether the module
receives or generates the frame synchronization
pulse). The frame pulse is an active high pulse for a
single SPI clock cycle. When frame synchronization is
enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
Both the transmit buffer (SPIxTXB) and

the receive buffer (SPIxRXB) are mapped
to the same register address, SPIxBUF.
Preliminary
DS70116D-page 87
dsPIC30F5011/5013
FIGURE 14-1:
SPI BLOCK DIAGRAM

Internal
Data Bus
Read
Write
SPIxBUF
SPIxBUF
Receive
Transmit
SPIxSR
SDIx
bit 0
SDOx
SSx
Shift
Clock
Clock
Control
SS & FSYNC
Control
Edge
Select
Secondary
Prescaler
1, 2, 4, 6, 8
SCKx
Primary
Prescaler
1, 4, 16, 64
FCY
Enable Master Clock

Note: x = 1 or 2.
FIGURE 14-2:
SPI MASTER/SLAVE CONNECTION
SPI Master
SPI Slave
SDOx
SDIy
Serial Input Buffer

(SPIxBUF)
SDIx
Shift Register
(SPIxSR)
MSb
Serial Input Buffer

(SPIyBUF)
SDOy
LSb
Shift Register
(SPIySR)
MSb
SCKx
Serial Clock
PROCESSOR 1
LSb
SCKy
PROCESSOR 2
Note: x = 1 or 2, y = 1 or 2.
DS70116D-page 88
Preliminary
dsPIC30F5011/5013
14.3
Slave Select Synchronization
14.5
The SSx pin allows a Synchronous Slave mode. The

SPI must be configured in SPI Slave mode with SSx pin
control enabled (SSEN = 1). When the SSx pin is low,
transmission and reception are enabled and the SDOx
pin is driven. When SSx pin goes high, the SDOx pin is
no longer driven. Also, the SPI module is resynchronized, and all counters/control circuitry are
reset. Therefore, when the SSx pin is asserted low
again, transmission/reception will begin at the MS bit
even if SSx had been de-asserted in the middle of a
transmit/receive.
14.4
SPI Operation During CPU Idle

Mode
When the device enters Idle mode, all clock sources

remain functional. The SPISIDL bit (SPIxSTAT<13>)
selects if the SPI module will stop or continue on Idle. If
SPISIDL = 0, the module will continue to operate when
the CPU enters Idle mode. If SPISIDL = 1, the module
will stop when the CPU enters Idle mode.
SPI Operation During CPU Sleep

Mode
During Sleep mode, the SPI module is shutdown. If the

CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by entering
or exiting Sleep mode.
Preliminary
DS70116D-page 89
DS70116D-page 90
Legend:
0228
022A
SPI2CON
SPI2BUF
SPIFSD
SPISIDL
Bit 13
Bit 12
FRMEN
Bit 14
SPIEN
Bit 15
Bit 12
Bit 10
Bit 10
DISSDO MODE16
Bit 11
DISSDO MODE16
Bit 11
CKE
Bit 8
SSEN
Bit 7
CKP
SPIROV
Bit 6
CKE
Bit 8
SSEN
Bit 7
Bit 6
CKP
SPIROV
Transmit and Receive Buffer
SMP
Bit 9
Transmit and Receive Buffer
SMP
Bit 9
MSTEN
Bit 5
MSTEN
Bit 5
SPIFSD
SPISIDL
Bit 13
SPI2 REGISTER MAP
0226
Legend:
Addr.
SFR Name
SPI2STAT
TABLE 14-2:
0224
SPI1BUF
FRMEN
0222
SPIEN
0220
SPI1STAT
Bit 14
SPI1CON
Bit 15
Addr.
SPI1 REGISTER MAP
SFR
Name
TABLE 14-1:
SPRE2
Bit 4
SPRE2
Bit 4
Bit 2
SPRE0
Bit 2
SPRE1 SPRE0
Bit 3
SPRE1
Bit 3
PPRE1
SPITBF
Bit 1
PPRE1
SPITBF
Bit 1
Reset State
PPRE0
SPIRBF
Bit 0
PPRE0
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
SPIRBF 0000 0000 0000 0000
Bit 0
dsPIC30F5011/5013
Preliminary
dsPIC30F5011/5013
15.0
I2C MODULE
15.1.1

Manual (DS70046).
2
The following types of I2C operation are supported:
I2C slave operation with 7-bit address

I2C slave operation with 10-bit address
I2C master operation with 7 or 10-bit address
See the I2C programmers model in Figure 15-1.
TM
The Inter-Integrated Circuit (I C ) module provides

complete hardware support for both Slave and MultiMaster modes of the I2C serial communication
standard, with a 16-bit interface.
This module offers the following key features:
I2C interface supporting both master and slave
operation.
I2C Slave mode supports 7 and 10-bit address.
I2C Master mode supports 7 and 10-bit address.
I2C port allows bidirectional transfers between
master and slaves.
Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
I2C supports multi-master operation; detects bus
collision and will arbitrate accordingly.
15.1
Operating Function Description
The hardware fully implements all the master and slave

functions of the I2C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
Thus, the I2C module can operate either as a slave or
a master on an I2C bus.
15.1.2
PIN CONFIGURATION IN I2C MODE
I2C has a 2-pin interface: the SCL pin is clock and the
SDA pin is data.
15.1.3
I2C REGISTERS
I2CCON and I2CSTAT are control and status registers,

respectively. The I2CCON register is readable and writable. The lower 6 bits of I2CSTAT are read only. The
remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer as shown in Figure 15-1.
I2CTRN is the transmit register to which bytes are
written during a transmit operation, as shown in
Figure 15-2.
The I2CADD register holds the slave address. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the baud rate generator reload value.
In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and an interrupt pulse is generated. During
transmission, the I2CTRN is not double-buffered.
Note:
FIGURE 15-1:
VARIOUS I2C MODES
Following a RESTART condition in 10-bit

mode, the user only needs to match the
first 7-bit address.
PROGRAMMERS MODEL
I2CRCV (8 bits)
Bit 7
Bit 0
Bit 7
Bit 0
I2CTRN (8 bits)
I2CBRG (9 bits)
Bit 8
Bit 0
I2CCON (16 bits)
Bit 15
Bit 0
Bit 15
Bit 0
I2CSTAT (16 bits)

I2CADD (10 bits)
Bit 9
Bit 0
Preliminary
DS70116D-page 91
dsPIC30F5011/5013
FIGURE 15-2:
I2C BLOCK DIAGRAM

Internal
Data Bus
I2CRCV
Read
SCL
Shift
Clock
I2CRSR
LSB
SDA
Addr_Match
Match Detect
Write
I2CADD
Read
Start and
Stop bit Detect
I2CSTAT
Write
Control Logic
Start, RESTART,
Stop bit Generate
Write
I2CCON
Collision
Detect
Acknowledge
Generation
Clock
Stretching
Read
Read
Write
I2CTRN
LSB
Shift
Clock
Read
Reload
Control
BRG Down
Counter
DS70116D-page 92
Write
I2CBRG
FCY
Preliminary
Read
dsPIC30F5011/5013
15.2
I2C Module Addresses
15.3.2
The I2CADD register contains the Slave mode

addresses. The register is a 10-bit register.
If the A10M bit (I2CCON<10>) is 0, the address is
interpreted by the module as a 7-bit address. When an
address is received, it is compared to the 7 LS bits of
the I2CADD register.
If the A10M bit is 1, the address is assumed to be a
10-bit address. When an address is received, it will be
compared with the binary value 11110 A9 A8 (where
A9 and A8 are two Most Significant bits of I2CADD). If
that value matches, the next address will be compared
with the Least Significant 8 bits of I2CADD, as specified
in the 10-bit addressing protocol.
TABLE 15-1:
0x00
Reserved
Valid 7-bit addresses
0x78-0x7b
Valid 10-bit addresses (lower 7 bits)
0x7c-0x7f
Reserved
Note:
I C 7-bit Slave Mode Operation
If an address match occurs, an Acknowledgement will

be sent, and the slave event interrupt flag (SI2CIF) is
set on the falling edge of the ninth (ACK) bit. The
address match does not affect the contents of the
I2CRCV buffer or the RBF bit.
SLAVE TRANSMISSION
If the R_W bit received is a 1, then the serial port will

go into Transmit mode. It will send ACK on the ninth bit
and then hold SCL to 0 until the CPU responds by writing to I2CTRN. SCL is released by setting the SCLREL
bit, and 8 bits of data are shifted out. Data bits are
shifted out on the falling edge of SCL, such that SDA is
valid during SCL high. The interrupt pulse is sent on the
falling edge of the ninth clock pulse, regardless of the
status of the ACK received from the master.
15.4
The I2CRCV will be loaded if the I2COV

bit = 1 and the RBF flag = 0. In this case,
a read of the I2CRCV was performed but
the user did not clear the state of the
I2COV bit before the next receive
occurred. The Acknowledgement is not
sent (ACK = 1) and the I2CRCV is
updated.
I2C 10-bit Slave Mode Operation
In 10-bit mode, the basic receive and transmit operations are the same as in the 7-bit mode. However, the
criteria for address match is more complex.
Once enabled (I2CEN = 1), the slave module will wait

for a Start bit to occur (i.e., the I2C module is Idle). Following the detection of a Start bit, 8 bits are shifted into
I2CRSR and the address is compared against
I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>
are compared against I2CRSR<7:1> and I2CRSR<0>
is the R_W bit. All incoming bits are sampled on the rising edge of SCL.
15.3.1
If the RBF flag is set, indicating that I2CRCV is still

holding data from a previous operation (RBF = 1), then
ACK is not sent; however, the interrupt pulse is generated. In the case of an overflow, the contents of the
I2CRSR are not loaded into the I2CRCV.
General call address or start byte
0x04-0x77
15.3
If the R_W bit received is a 0 during an address

match, then Receive mode is initiated. Incoming bits
are sampled on the rising edge of SCL. After 8 bits are
received, if I2CRCV is not full or I2COV is not set,
I2CRSR is transferred to I2CRCV. ACK is sent on the
ninth clock.
7-BIT I2C SLAVE ADDRESSES

SUPPORTED BY dsPIC30F
0x01-0x03
SLAVE RECEPTION
The I2C specification dictates that a slave must be

addressed for a write operation with two address bytes
following a Start bit.
The A10M bit is a control bit that signifies that the
address in I2CADD is a 10-bit address rather than a 7-bit
address. The address detection protocol for the first byte
of a message address is identical for 7-bit and 10-bit
messages, but the bits being compared are different.
I2CADD holds the entire 10-bit address. Upon receiving an address following a Start bit, I2CRSR <7:3> is
compared against a literal 11110 (the default 10-bit
address) and I2CRSR<2:1> are compared against
I2CADD<9:8>. If a match occurs and if R_W = 0, the
interrupt pulse is sent. The ADD10 bit will be cleared to
indicate a partial address match. If a match fails or
R_W = 1, the ADD10 bit is cleared and the module
returns to the Idle state.
The low byte of the address is then received and compared with I2CADD<7:0>. If an address match occurs,
the interrupt pulse is generated and the ADD10 bit is
set, indicating a complete 10-bit address match. If an
address match did not occur, the ADD10 bit is cleared
and the module returns to the Idle state.
Preliminary
DS70116D-page 93
dsPIC30F5011/5013
15.4.1
10-BIT MODE SLAVE

TRANSMISSION
Once a slave is addressed in this fashion with the full

10-bit address (we will refer to this state as
PRIOR_ADDR_MATCH), the master can begin
sending data bytes for a slave reception operation.
15.4.2
10-BIT MODE SLAVE RECEPTION
Once addressed, the master can generate a Repeated

Start, reset the high byte of the address and set the
R_W bit without generating a Stop bit, thus initiating a
slave transmit operation.
15.5
Automatic Clock Stretch
In the Slave modes, the module can synchronize buffer

reads and write to the master device by clock stretching.
15.5.1
Clock stretching takes place following the ninth clock of

the receive sequence. On the falling edge of the ninth
clock at the end of the ACK sequence, if the RBF bit is
set, the SCLREL bit is automatically cleared, forcing
the SCL output to be held low. The users ISR must set
the SCLREL bit before reception is allowed to continue.
By holding the SCL line low, the user has time to service the ISR and read the contents of the I2CRCV
before the master device can initiate another receive
sequence. This will prevent buffer overruns from
occurring.
Note 1: If the user reads the contents of the
I2CRCV, clearing the RBF bit before the
falling edge of the ninth clock, the
SCLREL bit will not be cleared and clock
stretching will not occur.
2: The SCLREL bit can be set in software
regardless of the state of the RBF bit. The
user should be careful to clear the RBF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
TRANSMIT CLOCK STRETCHING
Both 10-bit and 7-bit Transmit modes implement clock

stretching by asserting the SCLREL bit after the falling
edge of the ninth clock, if the TBF bit is cleared, indicating the buffer is empty.
In Slave Transmit modes, clock stretching is always
performed irrespective of the STREN bit.
15.5.4
Clock synchronization takes place following the ninth

clock of the transmit sequence. If the device samples
an ACK on the falling edge of the ninth clock and if the
TBF bit is still clear, then the SCLREL bit is automatically cleared. The SCLREL being cleared to 0 will
assert the SCL line low. The users ISR must set the
SCLREL bit before transmission is allowed to continue.
By holding the SCL line low, the user has time to service the ISR and load the contents of the I2CTRN
before the master device can initiate another transmit
sequence.
Clock stretching takes place automatically during the

addressing sequence. Because this module has a
register for the entire address, it is not necessary for
the protocol to wait for the address to be updated.
Note 1: If the user loads the contents of I2CTRN,

setting the TBF bit before the falling edge
of the ninth clock, the SCLREL bit will not
be cleared and clock stretching will not
occur.
2: The SCLREL bit can be set in software,
regardless of the state of the TBF bit.
15.5.2
RECEIVE CLOCK STRETCHING
The STREN bit in the I2CCON register can be used to

enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCL pin will be held low at the
end of each data receive sequence.
15.5.3
CLOCK STRETCHING DURING

7-BIT ADDRESSING (STREN = 1)
CLOCK STRETCHING DURING

10-BIT ADDRESSING (STREN = 1)
After the address phase is complete, clock stretching

will occur on each data receive or transmit sequence as
was described earlier.
15.6
Software Controlled Clock

Stretching (STREN = 1)
When the STREN bit is 1, the SCLREL bit may be

cleared by software to allow software to control the
clock stretching. The logic will synchronize writes to the
SCLREL bit with the SCL clock. Clearing the SCLREL
bit will not assert the SCL output until the module
detects a falling edge on the SCL output and SCL is
sampled low. If the SCLREL bit is cleared by the user
while the SCL line has been sampled low, the SCL output will be asserted (held low). The SCL output will
remain low until the SCLREL bit is set, and all other
devices on the I2C bus have de-asserted SCL. This
ensures that a write to the SCLREL bit will not violate
the minimum high time requirement for SCL.
If the STREN bit is 0, a software write to the SCLREL
bit will be disregarded and have no effect on the
SCLREL bit.
When the STREN bit is set in Slave Receive mode, the

SCL line is held low when the buffer register is full. The
method for stretching the SCL output is the same for
both 7 and 10-bit Addressing modes.
DS70116D-page 94
Preliminary
dsPIC30F5011/5013
15.7
15.12 I2C Master Operation
Interrupts
The I2C module generates two interrupt flags, MI2CIF

(I2C Master Interrupt Flag) and SI2CIF (I2C Slave Interrupt Flag). The MI2CIF interrupt flag is activated on
completion of a master message event. The SI2CIF
interrupt flag is activated on detection of a message
directed to the slave.
15.8
Slope Control
The I2C standard requires slope control on the SDA

and SCL signals for Fast mode (400 kHz). The control
bit, DISSLW, enables the user to disable slew rate control if desired. It is necessary to disable the slew rate
control for 1 MHz mode.
15.9
IPMI Support
The control bit, IPMIEN, enables the module to support

Intelligent Peripheral Management Interface (IPMI).
When this bit is set, the module accepts and acts upon
all addresses.
15.10 General Call Address Support

The general call address can address all devices.
When this address is used, all devices should, in
theory, respond with an Acknowledgement.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0s with R_W = 0.
The general call address is recognized when the General Call Enable (GCEN) bit is set (I2CCON<15> = 1).
Following a Start bit detection, 8 bits are shifted into
I2CRSR and the address is compared with I2CADD,
and is also compared with the general call address
which is fixed in hardware.
If a general call address match occurs, the I2CRSR is
transferred to the I2CRCV after the eighth clock, the
RBF flag is set and on the falling edge of the ninth bit
(ACK bit), the master event interrupt flag (MI2CIF) is
set.
When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the
I2CRCV to determine if the address was device
specific or a general call address.
15.11 I2C Master Support

As a master device, six operations are supported:
The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the data direction bit. In
this case, the data direction bit (R_W) is logic 0. Serial
data is transmitted 8 bits at a time. After each byte is
transmitted, an ACK bit is received. Start and Stop conditions are output to indicate the beginning and the end
of a serial transfer.
In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device
(7 bits) and the data direction bit. In this case, the data
direction bit (R_W) is logic 1. Thus, the first byte transmitted is a 7-bit slave address, followed by a 1 to indicate receive bit. Serial data is received via SDA while
SCL outputs the serial clock. Serial data is received
8 bits at a time. After each byte is received, an ACK bit
is transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
15.12.1
I2C MASTER TRANSMISSION
Transmission of a data byte, a 7-bit address, or the second half of a 10-bit address is accomplished by simply
writing a value to I2CTRN register. The user should
only write to I2CTRN when the module is in a WAIT
state. This action will set the Buffer Full Flag (TBF) and
allow the baud rate generator to begin counting and
start the next transmission. Each bit of address/data
will be shifted out onto the SDA pin after the falling
edge of SCL is asserted. The Transmit Status Flag,
TRSTAT (I2CSTAT<14>), indicates that a master
transmit is in progress.
15.12.2
I2C MASTER RECEPTION
Master mode reception is enabled by programming the

Receive Enable bit, RCEN (I2CCON<11>). The I2C
module must be Idle before the RCEN bit is set, otherwise the RCEN bit will be disregarded. The baud rate
generator begins counting and on each rollover, the
state of the SCL pin ACK and data are shifted into the
I2CRSR on the rising edge of each clock.
Assert a Start condition on SDA and SCL.

Assert a RESTART condition on SDA and SCL.
Write to the I2CTRN register initiating
transmission of data/address.
Generate a Stop condition on SDA and SCL.
Configure the I2C port to receive data.
Generate an ACK condition at the end of a
received byte of data.
Preliminary
DS70116D-page 95
dsPIC30F5011/5013
15.12.3
BAUD RATE GENERATOR
In I C Master mode, the reload value for the BRG is

located in the I2CBRG register. When the BRG is
loaded with this value, the BRG counts down to 0 and
stops until another reload has taken place. If clock arbitration is taking place, for instance, the BRG is reloaded
when the SCL pin is sampled high.
As per the I2C standard, FSCK may be 100 kHz or
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CBRG values of 0 or 1 are illegal.
EQUATION 15-1:
I2CBRG =
15.12.4
SERIAL CLOCK RATE
CY
( FFSCK
FCY
1,111,111
CLOCK ARBITRATION
Clock arbitration occurs when the master de-asserts

the SCL pin (SCL allowed to float high) during any
receive, transmit, or RESTART/Stop condition. When
the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the
contents of I2CBRG and begins counting. This ensures
that the SCL high time will always be at least one BRG
rollover count in the event that the clock is held low by
an external device.
15.12.5
MULTI-MASTER COMMUNICATION,
BUS COLLISION, AND BUS
ARBITRATION
Multi-master operation support is achieved by bus arbitration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a 1 on SDA by letting SDA float high
while another master asserts a 0. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a 1 and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The
master will set the MI2CIF pulse and reset the master
portion of the I2C port to its Idle state.
If a transmit was in progress when the bus collision

occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are de-asserted and a
value can now be written to I2CTRN. When the user
services the I2C master event Interrupt Service Routine, if the I2C bus is free (i.e., the P bit is set), the user
can resume communication by asserting a Start
condition.
If a Start, RESTART, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deasserted, and the respective control bits in the I2CCON
register are cleared to 0. When the user services the
bus collision Interrupt Service Routine, and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
The master will continue to monitor the SDA and SCL
pins, and if a Stop condition occurs, the MI2CIF bit will
be set.
A write to the I2CTRN will start the transmission of data
at the first data bit regardless of where the transmitter
left off when bus collision occurred.
In a multi-master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.
15.13 I2C Module Operation During CPU

15.13.1
I2C OPERATION DURING CPU

SLEEP MODE
When the device enters Sleep mode, all clock sources

to the module are shutdown and stay at logic 0. If
Sleep occurs in the middle of a transmission and the
state machine is partially into a transmission as the
clocks stop, then the transmission is aborted. Similarly,
if Sleep occurs in the middle of a reception, then the
reception is aborted.
15.13.2
I2C OPERATION DURING CPU IDLE

MODE
For the I2C, the I2CSIDL bit selects if the module will
stop on Idle or continue on Idle. If I2CSIDL = 0, the
module will continue operation on assertion of the Idle
mode. If I2CSIDL = 1, the module will stop on Idle.
DS70116D-page 96
Preliminary
0206
0208
020A
I2CCON
I2CSTAT
I2CADD
Legend:
TRSTAT
Bit 12
Bit 11
I2CSIDL SCLREL IPMIEN
Bit 13
BCL
A10M
Bit 10
GCSTAT
DISSLW
Bit 9
ADD10
SMEN
Bit 8
IWCOL
GCEN
Bit 7
I2COV
STREN
Bit 6
Bit 3
Transmit Register
Receive Register
Bit 4
Address Register
D_A
ACKEN
S
RCEN
Baud Rate Generator
Bit 5
ACKDT
ACKSTAT
I2CEN
0204
I2CBRG
0202
Bit 14
0200
I2CRCV
Bit 15
I2C REGISTER MAP
I2CTRN
SFR Name Addr.
TABLE 15-2:
R_W
PEN
Bit 2
RBF
RSEN
Bit 1
TBF
SEN
Bit 0
0000 0000 0000 0000
0000 0000 0000 0000
0001 0000 0000 0000
0000 0000 0000 0000
0000 0000 1111 1111
0000 0000 0000 0000
Reset State
dsPIC30F5011/5013
Preliminary
DS70116D-page 97
dsPIC30F5011/5013
NOTES:
DS70116D-page 98
Preliminary
dsPIC30F5011/5013
16.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART) MODULE
16.1
The key features of the UART module are:

Manual (DS70046).
This section describes the Universal Asynchronous

Receiver/Transmitter Communications module.
FIGURE 16-1:
UART Module Overview
Full-duplex, 8 or 9-bit data communication

Even, odd or no parity options (for 8-bit data)
One or two Stop bits
Fully integrated baud rate generator with 16-bit
prescaler
Baud rates range from 38 bps to 1.875 Mbps at a
30 MHz instruction rate
4-word deep transmit data buffer
4-word deep receive data buffer
Parity, framing and buffer overrun error detection
Support for interrupt only on address detect
(9th bit = 1)
Separate transmit and receive interrupts
Loopback mode for diagnostic support
UART TRANSMITTER BLOCK DIAGRAM
Internal Data Bus
Control and Status bits

Write
UTX8
Write
UxTXREG Low Byte
Transmit Control
Control TSR
Control Buffer
Generate Flags
Generate Interrupt
Load TSR
UxTXIF
UTXBRK
Data
Transmit Shift Register (UxTSR)
0 (Start)
UxTX
1 (Stop)
Parity
Parity
Generator
16 Divider
16x Baud Clock

from Baud Rate
Generator
Control
Signals
Note:
x = 1 or 2.
Preliminary
DS70116D-page 99
dsPIC30F5011/5013
FIGURE 16-2:
UART RECEIVER BLOCK DIAGRAM

Internal Data Bus
16
Write
Read
Read Read
UxMODE
Write
UxSTA
URX8 UxRXREG Low Byte

Receive Buffer Control
Generate Flags
Generate Interrupt
Shift Data Characters
0
Start bit Detect
Parity Check
Stop bit Detect
Shift Clock Generation
Wake Logic
Load RSR
to Buffer
Receive Shift Register
(UxRSR)
Control
Signals
FERR
UxRX
8-9
PERR
LPBACK
From UxTX
1
16 Divider
16x Baud Clock from

Baud Rate Generator
UxRXIF
DS70116D-page 100
Preliminary
dsPIC30F5011/5013
16.2
16.2.1
Enabling and Setting Up UART
16.3
ENABLING THE UART
16.3.1
The UART module is enabled by setting the UARTEN

bit in the UxMODE register (where x = 1 or 2). Once
enabled, the UxTX and UxRX pins are configured as an
output and an input respectively, overriding the TRIS
and LATCH register bit settings for the corresponding
I/O port pins. The UxTX pin is at logic 1 when no
transmission is taking place.
16.2.2
Disabling the UART module resets the buffers to empty

states. Any data characters in the buffers are lost and
the baud rate counter is reset.
1.
2.
3.
4.
All error and status flags associated with the UART

module are reset when the module is disabled. The
URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and
UTXBF bits are cleared, whereas RIDLE and TRMT
are set. Other control bits, including ADDEN,
URXISEL<1:0>, UTXISEL, as well as the UxMODE
and UxBRG registers, are not affected.
Clearing the UARTEN bit while the UART is active will
abort all pending transmissions and receptions and
reset the module as defined above. Re-enabling the
UART will restart the UART in the same configuration.
16.2.3
SETTING UP DATA, PARITY AND

STOP BIT SELECTIONS
Control bits PDSEL<1:0> in the UxMODE register are

used to select the data length and parity used in the
transmission. The data length may either be 8 bits with
even, odd or no parity, or 9 bits with no parity.
The STSEL bit determines whether one or two Stop bits
will be used during data transmission.
The default (power-on) setting of the UART is 8 bits, no
parity and 1 Stop bit (typically represented as 8, N, 1).
TRANSMITTING IN 8-BIT DATA

MODE
The following steps must be performed in order to

transmit 8-bit data:
DISABLING THE UART
The UART module is disabled by clearing the UARTEN

bit in the UxMODE register. This is the default state
after any Reset. If the UART is disabled, all I/O pins
operate as port pins under the control of the latch and
TRIS bits of the corresponding port pins.
Transmitting Data
5.
Set up the UART:

First, the data length, parity and number of Stop
bits must be selected. Then, the transmit and
receive interrupt enable and priority bits are
setup in the UxMODE and UxSTA registers.
Also, the appropriate baud rate value must be
written to the UxBRG register.
Enable the UART by setting the UARTEN bit
(UxMODE<15>).
Set the UTXEN bit (UxSTA<10>), thereby
enabling a transmission.
Write the byte to be transmitted to the lower byte
of UxTXREG. The value will be transferred to the
Transmit Shift register (UxTSR) immediately
and the serial bit stream will start shifting out
during the next rising edge of the baud clock.
Alternatively, the data byte may be written while
UTXEN = 0, following which, the user may set
UTXEN. This will cause the serial bit stream to
begin immediately because the baud clock will
start from a cleared state.
A transmit interrupt will be generated, depending on the value of the interrupt control bit
UTXISEL (UxSTA<15>).
16.3.2
TRANSMITTING IN 9-BIT DATA

MODE
The sequence of steps involved in the transmission of

9-bit data is similar to 8-bit transmission, except that a
16-bit data word (of which the upper 7 bits are always
clear) must be written to the UxTXREG register.
16.3.3
TRANSMIT BUFFER (UXTXB)
The transmit buffer is 9 bits wide and 4 characters

deep. Including the Transmit Shift register (UxTSR),
the user effectively has a 5-deep FIFO (First-In, FirstOut) buffer. The UTXBF status bit (UxSTA<9>)
indicates whether the transmit buffer is full.
If a user attempts to write to a full buffer, the new data
will not be accepted into the FIFO, and no data shift will
occur within the buffer. This enables recovery from a
buffer overrun condition.
The FIFO is reset during any device Reset but is not
affected when the device enters or wakes up from a
Power Saving mode.
Preliminary
DS70116D-page 101
dsPIC30F5011/5013
16.3.4
TRANSMIT INTERRUPT
16.4.2
The transmit interrupt flag (U1TXIF or U2TXIF) is

located in the corresponding interrupt flag register.
The transmitter generates an edge to set the UxTXIF
bit. The condition for generating the interrupt depends
on the UTXISEL control bit:
a)
b)
If UTXISEL = 0, an interrupt is generated when

a word is transferred from the transmit buffer to
the Transmit Shift register (UxTSR). This implies
that the transmit buffer has at least one empty
word.
If UTXISEL = 1, an interrupt is generated when
a word is transferred from the transmit buffer to
the Transmit Shift register (UxTSR) and the
transmit buffer is empty.
Switching between the two Interrupt modes during

operation is possible and sometimes offers more
flexibility.
16.3.5
TRANSMIT BREAK
RECEIVE BUFFER (UXRXB)
The receive buffer is 4 words deep. Including the

Receive Shift register (UxRSR), the user effectively
has a 5-word deep FIFO buffer.
URXDA (UxSTA<0>) = 1 indicates that the receive
buffer has data available. URXDA = 0 implies that the
buffer is empty. If a user attempts to read an empty
buffer, the old values in the buffer will be read and no
data shift will occur within the FIFO.
The FIFO is reset during any device Reset. It is not
affected when the device enters or wakes up from a
Power Saving mode.
16.4.3
RECEIVE INTERRUPT
The receive interrupt flag (U1RXIF or U2RXIF) can be

read from the corresponding interrupt flag register. The
interrupt flag is set by an edge generated by the
receiver. The condition for setting the receive interrupt
flag depends on the settings specified by the
URXISEL<1:0> (UxSTA<7:6>) control bits.
Setting the UTXBRK bit (UxSTA<11>) will cause the

UxTX line to be driven to logic 0. The UTXBRK bit
overrides all transmission activity. Therefore, the user
should generally wait for the transmitter to be Idle
before setting UTXBRK.
a)
To send a break character, the UTXBRK bit must be set

by software and must remain set for a minimum of 13
baud clock cycles. The UTXBRK bit is then cleared by
software to generate Stop bits. The user must wait for
a duration of at least one or two baud clock cycles in
order to ensure a valid Stop bit(s) before reloading the
UxTXB, or starting other transmitter activity. Transmission of a break character does not generate a transmit
interrupt.
b)
c)
16.4
Switching between the Interrupt modes during operation is possible, though generally not advisable during
normal operation.
16.4.1
Receiving Data
RECEIVING IN 8-BIT OR 9-BIT
DATA MODE
If URXISEL<1:0> = 00 or 01, an interrupt is generated every time a data word is transferred

from the Receive Shift register (UxRSR) to the
receive buffer. There may be one or more
characters in the receive buffer.
If URXISEL<1:0> = 10, an interrupt is generated
when a word is transferred from the Receive Shift
register (UxRSR) to the receive buffer, which as a
result of the transfer, contains 3 characters.
If URXISEL<1:0> = 11, an interrupt is set when
a word is transferred from the Receive Shift register (UxRSR) to the receive buffer, which as a
result of the transfer, contains 4 characters (i.e.,
becomes full).
16.5
Reception Error Handling
The following steps must be performed while receiving

8-bit or 9-bit data:
16.5.1
1.
2.
3.
The OERR bit (UxSTA<1>) is set if all of the following

conditions occur:
4.
5.
Set up the UART (see Section 16.3.1).

Enable the UART (see Section 16.3.1).
A receive interrupt will be generated when one
or more data words have been received,
depending on the receive interrupt settings
specified by the URXISEL bits (UxSTA<7:6>).
Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
Read the received data from UxRXREG. The act
of reading UxRXREG will move the next word to
the top of the receive FIFO, and the PERR and
FERR values will be updated.
DS70116D-page 102
a)
b)
c)
RECEIVE BUFFER OVERRUN

ERROR (OERR BIT)
The receive buffer is full.

The Receive Shift register is full, but unable to
transfer the character to the receive buffer.
The Stop bit of the character in the UxRSR is
detected, indicating that the UxRSR needs to
transfer the character to the buffer.
Once OERR is set, no further data is shifted in UxRSR

(until the OERR bit is cleared in software or a Reset
occurs). The data held in UxRSR and UxRXREG
remains valid.
Preliminary
dsPIC30F5011/5013
16.5.2
FRAMING ERROR (FERR)
16.6
The FERR bit (UxSTA<2>) is set if a 0 is detected

instead of a Stop bit. If two Stop bits are selected, both
Stop bits must be 1, otherwise FERR will be set. The
read only FERR bit is buffered along with the received
data. It is cleared on any Reset.
16.5.3
PARITY ERROR (PERR)
The PERR bit (UxSTA<3>) is set if the parity of the

received word is incorrect. This error bit is applicable
only if a Parity mode (odd or even) is selected. The
read only PERR bit is buffered along with the received
data bytes. It is cleared on any Reset.
16.5.4
IDLE STATUS
When the receiver is active (i.e., between the initial

detection of the Start bit and the completion of the Stop
bit), the RIDLE bit (UxSTA<4>) is 0. Between the completion of the Stop bit and detection of the next Start bit,
the RIDLE bit is 1, indicating that the UART is Idle.
16.5.5
RECEIVE BREAK
The receiver will count and expect a certain number of

bit times based on the values programmed in the
PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>)
bits.
If the break is longer than 13 bit times, the reception is
considered complete after the number of bit times
specified by PDSEL and STSEL. The URXDA bit is set,
FERR is set, zeros are loaded into the receive FIFO,
interrupts are generated if appropriate and the RIDLE
bit is set.
When the module receives a long break signal and the
receiver has detected the Start bit, the data bits and the
invalid Stop bit (which sets the FERR), the receiver
must wait for a valid Stop bit before looking for the next
Start bit. It cannot assume that the break condition on
the line is the next Start bit.
Break is regarded as a character containing all 0s with
the FERR bit set. The break character is loaded into the
buffer. No further reception can occur until a Stop bit is
received. Note that RIDLE goes high when the Stop bit
has not yet been received.
Address Detect Mode
Setting the ADDEN bit (UxSTA<5>) enables this special mode in which a 9th bit (URX8) value of 1 identifies the received word as an address, rather than data.
This mode is only applicable for 9-bit data communication. The URXISEL control bit does not have any
impact on interrupt generation in this mode since an
interrupt (if enabled) will be generated every time the
received word has the 9th bit set.
16.7
Loopback Mode
Setting the LPBACK bit enables this special mode in

which the UxTX pin is internally connected to the UxRX
pin. When configured for the Loopback mode, the
UxRX pin is disconnected from the internal UART
receive logic. However, the UxTX pin still functions as
in a normal operation.
To select this mode:
a)
b)
c)
Configure UART for desired mode of operation.

Set LPBACK = 1 to enable Loopback mode.
Enable transmission as defined in Section 16.3.
16.8
Baud Rate Generator
The UART has a 16-bit baud rate generator to allow

maximum flexibility in baud rate generation. The baud
rate generator register (UxBRG) is readable and
writable. The baud rate is computed as follows:
BRG = 16-bit value held in UxBRG register
(0 through 65535)
FCY = Instruction Clock Rate (1/TCY)
The Baud Rate is given by Equation 16-1.
EQUATION 16-1:
BAUD RATE
Baud Rate = FCY / (16*(BRG+1))

Therefore, the maximum baud rate possible is
FCY /16 (if BRG = 0),
and the minimum baud rate possible is
FCY / (16* 65536).
With a full 16-bit baud rate generator at 30 MIPs
operation, the minimum baud rate achievable is
28.5 bps.
Preliminary
DS70116D-page 103
dsPIC30F5011/5013
16.9
16.10.2
Auto Baud Support
To allow the system to determine baud rates of

received characters, the input can be optionally linked
to a capture input (IC1 for UART1, IC2 for UART2). To
enable this mode, the user must program the input capture module to detect the falling and rising edges of the
Start bit.
UART OPERATION DURING CPU

IDLE MODE
For the UART, the USIDL bit selects if the module will
stop operation when the device enters Idle mode or
whether the module will continue on Idle. If USIDL = 0,
the module will continue operation during Idle mode. If
USIDL = 1, the module will stop on Idle.
16.10 UART Operation During CPU

16.10.1
UART OPERATION DURING CPU

SLEEP MODE

to the module are shutdown and stay at logic 0. If entry
into Sleep mode occurs while a transmission is in
progress, then the transmission is aborted. The UxTX
pin is driven to logic 1. Similarly, if entry into Sleep
mode occurs while a reception is in progress, then the
reception is aborted. The UxSTA, UxMODE, transmit
and receive registers and buffers, and the UxBRG
register are not affected by Sleep mode.
If the WAKE bit (UxSTA<7>) is set before the device
enters Sleep mode, then a falling edge on the UxRX pin
will generate a receive interrupt. The Receive Interrupt
Select mode bit (URXISEL) has no effect for this function. If the receive interrupt is enabled, then this will
wake-up the device from Sleep. The UARTEN bit must
be set in order to generate a wake-up interrupt.
DS70116D-page 104
Preliminary
0212
0214
U1RXREG
U1BRG
Legend:
Bit 12
021E
U2BRG
Legend:
Bit 12
Bit 10
Bit 10
UTXBRK UTXEN
Bit 11
UTXBRK UTXEN
Bit 11
UTXBF
Bit 9
URX8
UTX8
TRMT
Bit 8
LPBACK
Bit 6
LPBACK
Bit 6
ABAUD
Bit 5
PERR
Bit 3
RIDLE
Bit 4
PERR
Bit 3
Receive Register
Transmit Register
RIDLE
Bit 4
Receive Register
Transmit Register
URXISEL1 URXISEL0 ADDEN
WAKE
Bit 7
Baud Rate Generator Prescaler
URX8
UTX8
TRMT
Bit 8
ABAUD
Bit 5
URXISEL1 URXISEL0 ADDEN
WAKE
Bit 7
Baud Rate Generator Prescaler
UTXBF
Bit 9
021A
021C
U2RXREG
USIDL
UARTEN
Bit 13
Bit 14
UTXISEL
Bit 15
UART2 REGISTER MAP
USIDL
U2TXREG
0216
0218
U2MODE
U2STA
Addr.
SFR
Name
TABLE 16-2:
0210
U1TXREG
UARTEN
020E
UTXISEL
020C
U1MODE
U1STA
Bit 13
Bit 15
SFR Name Addr.
Bit 14
UART1 REGISTER MAP
TABLE 16-1:
Bit 1
Bit 0
Reset State
Bit 1
OERR
FERR
OERR
PDSEL1 PDSEL0
Bit 2
FERR
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 000u uuuu uuuu
URXDA 0000 0001 0001 0000
STSEL 0000 0000 0000 0000
Bit 0
0000 0000 0000 0000
0000 0000 0000 0000
0000 000u uuuu uuuu
URXDA 0000 0001 0001 0000
PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
Bit 2
dsPIC30F5011/5013
Preliminary
DS70116D-page 105
dsPIC30F5011/5013
NOTES:
DS70116D-page 106
Preliminary
dsPIC30F5011/5013
17.0
CAN MODULE

Manual (DS70046).
17.1
Overview
The Controller Area Network (CAN) module is a serial

interface, useful for communicating with other CAN
modules or microcontroller devices. This interface/
protocol was designed to allow communications within
noisy environments.
The CAN module is a communication controller implementing the CAN 2.0 A/B protocol, as defined in the
BOSCH specification. The module will support
CAN 1.2, CAN 2.0A, CAN 2.0B Passive, and CAN 2.0B
Active versions of the protocol. The module implementation is a full CAN system. The CAN specification is
not covered within this data sheet. The reader may
refer to the BOSCH CAN specification for further
details.
The module features are as follows:
Implementation of the CAN protocol CAN 1.2,
CAN 2.0A and CAN 2.0B
Standard and extended data frames
0-8 bytes data length
Programmable bit rate up to 1 Mbit/sec
Support for remote frames
Double-buffered receiver with two prioritized
received message storage buffers (each buffer
may contain up to 8 bytes of data)
6 full (standard/extended identifier) acceptance
filters, 2 associated with the high priority receive
buffer and 4 associated with the low priority
receive buffer
2 full acceptance filter masks, one each
associated with the high and low priority receive
buffers
Three transmit buffers with application specified
prioritization and abort capability (each buffer may
contain up to 8 bytes of data)
Programmable wake-up functionality with
integrated low-pass filter
Programmable Loopback mode supports self-test
operation
Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
Programmable clock source
Programmable link to Input Capture module (IC2,
for both CAN1 and CAN2) for time-stamping and
network synchronization
Low power Sleep and Idle mode
The CAN bus module consists of a protocol engine and

message buffering/control. The CAN protocol engine
handles all functions for receiving and transmitting
messages on the CAN bus. Messages are transmitted
by first loading the appropriate data registers. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against filters to
see if it should be received and stored in one of the
receive registers.
17.2
Frame Types
The CAN module transmits various types of frames

which include data messages or remote transmission
requests initiated by the user, as other frames that are
automatically generated for control purposes. The
following frame types are supported:
Standard Data Frame:
A standard data frame is generated by a node
when the node wishes to transmit data. It includes
an 11-bit standard identifier (SID) but not an 18-bit
extended identifier (EID).
Extended Data Frame:
An extended data frame is similar to a standard
data frame but includes an extended identifier as
well.
Remote Frame:
It is possible for a destination node to request the
data from the source. For this purpose, the destination node sends a remote frame with an identifier that matches the identifier of the required data
frame. The appropriate data source node will then
send a data frame as a response to this remote
request.
Error Frame:
An error frame is generated by any node that
detects a bus error. An error frame consists of 2
fields: an error flag field and an error delimiter
field.
Overload Frame:
An overload frame can be generated by a node as
a result of 2 conditions. First, the node detects a
dominant bit during interframe space which is an
illegal condition. Second, due to internal conditions, the node is not yet able to start reception of
the next message. A node may generate a maximum of 2 sequential overload frames to delay the
start of the next message.
Interframe Space:
Interframe space separates a proceeding frame
(of whatever type) from a following data or remote
frame.
Preliminary
DS70116D-page 107
dsPIC30F5011/5013
FIGURE 17-1:
CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM

Acceptance Mask
RXM1
BUFFERS
Acceptance Filter
RXF2
MESSAGE
MSGREQ
TXABT
TXLARB
TXERR
MTXBUFF
TXB2
MESSAGE
MSGREQ
TXABT
TXLARB
TXERR
MTXBUFF
MESSAGE
TXB1
MSGREQ
TXABT
TXLARB
TXERR
MTXBUFF
TXB0
A
c
c
e
p
t
R
X
B
0
Message
Queue
Control
Acceptance Mask
RXM0
Acceptance Filter
RXF3
Acceptance Filter
RXF0
Acceptance Filter
RXF4
Acceptance Filter
RXF1
Acceptance Filter
RXF5
Identifier
M
A
B
Data Field
Transmit Byte Sequencer
Data Field
PROTOCOL
ENGINE
Note 1:
RERRCNT
TERRCNT
Transmit
Error
Counter
CRC Generator
R
X
B
1
Identifier
Receive
Error
Counter
Transmit Shift
A
c
c
e
p
t
Err Pas
Bus Off
Receive Shift
Protocol
Finite
State
Machine
CRC Check
Transmit
Logic
Bit
Timing
Logic
CiTX(1)
CiRX(1)
Bit Timing
Generator
i = 1 or 2 refers to a particular CAN module (CAN1 or CAN2).
DS70116D-page 108
Preliminary
dsPIC30F5011/5013
17.3
Modes of Operation
The CAN module can operate in one of several Operation

modes selected by the user. These modes include:
Initialization Mode
Disable Mode
Normal Operation Mode
Listen Only Mode
Loopback Mode
Error Recognition Mode
Note:
Modes are requested by setting the REQOP<2:0> bits

(CiCTRL<10:8>), except the Error Recognition mode
which is requested through the RXM<1:0> bits
(CiRXnCON<6:5>, where n = 0 or 1 represents a particular receive buffer). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits
(CiCTRL<7:5>). The module will not change the mode
and the OPMODE bits until a change in mode is
acceptable, generally during bus Idle time which is
defined as at least 11 consecutive recessive bits.
17.3.1
INITIALIZATION MODE
In the Initialization mode, the module will not transmit or

receive. The error counters are cleared and the interrupt flags remain unchanged. The programmer will
have access to configuration registers that are access
restricted in other modes. The module will protect the
user from accidentally violating the CAN protocol
through programming errors. All registers which control
the configuration of the module can not be modified
while the module is on-line. The CAN module will not
be allowed to enter the Configuration mode while a
transmission is taking place. The Configuration mode
serves as a lock to protect the following registers.
Typically, if the CAN module is allowed to

transmit in a particular mode of operation
and a transmission is requested immediately after the CAN module has been
placed in that mode of operation, the module waits for 11 consecutive recessive bits
on the bus before starting transmission. If
the user switches to Disable Mode within
this 11-bit period, then this transmission is
aborted and the corresponding TXABT bit
is set and TXREQ bit is cleared.
NORMAL OPERATION MODE
Normal Operating mode is selected when

REQOP<2:0> = 000. In this mode, the module is activated and the I/O pins will assume the CAN bus functions. The module will transmit and receive CAN bus
messages via the CxTX and CxRX pins.
17.3.4
LISTEN ONLY MODE
If the Listen Only mode is activated, the module on the

CAN bus is passive. The transmitter buffers revert to
the port I/O function. The receive pins remain inputs.
For the receiver, no error flags or Acknowledge signals
are sent. The error counters are deactivated in this
state. The Listen Only mode can be used for detecting
the baud rate on the CAN bus. To use this, it is necessary that there are at least two further nodes that
communicate with each other.
LISTEN ALL MESSAGES MODE
The module can be set to ignore all errors and receive

any message. The Listen All Messages mode is activated by setting the REQOP<2:0> bits to 111. In this
mode, the data which is in the message assembly
buffer until the time an error occurred, is copied in the
receive buffer and can be read via the CPU interface.
DISABLE MODE
In Disable mode, the module will not transmit or

receive. The module has the ability to set the WAKIF bit
due to bus activity, however, any pending interrupts will
remain and the error counters will retain their value.
If the REQOP<2:0> bits (CiCTRL<10:8>) = 001, the
module will enter the Module Disable mode. If the module
is active, the module will wait for 11 recessive bits on the
CAN bus, detect that condition as an Idle bus, then
accept the module disable command. When the
OPMODE<2:0> bits (CiCTRL<7:5>) = 001, that indicates whether the module successfully went into Module
Disable mode. The I/O pins will revert to normal I/O
function when the module is in the Module Disable mode.
17.3.3
17.3.5
All Module Control Registers

Baud Rate and Interrupt Configuration Registers
Bus Timing Registers
Identifier Acceptance Filter Registers
Identifier Acceptance Mask Registers
17.3.2
The module can be programmed to apply a low-pass

filter function to the CiRX input line while the module or
the CPU is in Sleep mode. The WAKFIL bit
(CiCFG2<14>) enables or disables the filter.
17.3.6
LOOPBACK MODE
If the Loopback mode is activated, the module will connect the internal transmit signal to the internal receive
signal at the module boundary. The transmit and
receive pins revert to their port I/O function.
Preliminary
DS70116D-page 109
dsPIC30F5011/5013
17.4
17.4.1
Message Reception
17.4.4
RECEIVE BUFFERS
The CAN bus module has 3 receive buffers. However,

one of the receive buffers is always committed to monitoring the bus for incoming messages. This buffer is
called the Message Assembly Buffer (MAB). So there
are 2 receive buffers visible, RXB0 and RXB1, that can
essentially instantaneously receive a complete
message from the protocol engine.
All messages are assembled by the MAB and are transferred to the RXBn buffers only if the acceptance filter
criterion are met. When a message is received, the
RXnIF flag (CiINTF<0> or CiINRF<1>) will be set. This
bit can only be set by the module when a message is
received. The bit is cleared by the CPU when it has completed processing the message in the buffer. If the
RXnIE bit (CiINTE<0> or CiINTE<1>) is set, an interrupt
will be generated when a message is received.
RXF0 and RXF1 filters with RXM0 mask are associated
with RXB0. The filters RXF2, RXF3, RXF4, and RXF5
and the mask RXM1 are associated with RXB1.
17.4.2
MESSAGE ACCEPTANCE FILTERS
The message acceptance filters and masks are used to

determine if a message in the message assembly
buffer should be loaded into either of the receive buffers. Once a valid message has been received into the
Message Assembly Buffer (MAB), the identifier fields of
the message are compared to the filter values. If there
is a match, that message will be loaded into the
appropriate receive buffer.
The acceptance filter looks at incoming messages for
the RXIDE bit (CiRXnSID<0>) to determine how to
compare the identifiers. If the RXIDE bit is clear, the
message is a standard frame and only filters with the
EXIDE bit (CiRXFnSID<0>) clear are compared. If the
RXIDE bit is set, the message is an extended frame,
and only filters with the EXIDE bit set are compared.
Configuring the RXM<1:0> bits to 01 or 10 can
override the EXIDE bit.
17.4.3
MESSAGE ACCEPTANCE FILTER

MASKS
The mask bits essentially determine which bits to apply

the filter to. If any mask bit is set to a zero, then that bit
will automatically be accepted regardless of the filter
bit. There are 2 programmable acceptance filter masks
associated with the receive buffers, one for each buffer.
RECEIVE OVERRUN
An overrun condition occurs when the Message

Assembly Buffer (MAB) has assembled a valid
received message, the message is accepted through
the acceptance filters, and when the receive buffer
associated with the filter has not been designated as
clear of the previous message.
The overrun error flag, RXnOVR (CiINTF<15> or
CiINTF<14>), and the ERRIF bit (CiINTF<5>) will be
set and the message in the MAB will be discarded.
If the DBEN bit is clear, RXB1 and RXB0 operate independently. When this is the case, a message intended
for RXB0 will not be diverted into RXB1 if RXB0 contains an unread message and the RX0OVR bit will be
set.
If the DBEN bit is set, the overrun for RXB0 is handled
differently. If a valid message is received for RXB0 and
RXFUL = 1 indicates that RXB0 is full and RXFUL = 0
indicates that RXB1 is empty, the message for RXB0
will be loaded into RXB1. An overrun error will not be
generated for RXB0. If a valid message is received for
RXB0 and RXFUL = 1, indicating that both RXB0 and
RXB1 are full, the message will be lost and an overrun
will be indicated for RXB1.
17.4.5
RECEIVE ERRORS
The CAN module will detect the following receive

errors:
Cyclic Redundancy Check (CRC) Error
Bit Stuffing Error
Invalid Message Receive Error
These receive errors do not generate an interrupt.
However, the receive error counter is incremented by
one in case one of these errors occur. The RXWAR bit
(CiINTF<9>) indicates that the receive error counter
has reached the CPU warning limit of 96 and an
interrupt is generated.
17.4.6
RECEIVE INTERRUPTS
Receive interrupts can be divided into 3 major groups,

each including various conditions that generate
interrupts:
Receive Interrupt:
A message has been successfully received and
loaded into one of the receive buffers. This interrupt is activated immediately after receiving the
End of Frame (EOF) field. Reading the RXnIF flag
will indicate which receive buffer caused the
interrupt.
Wake-up Interrupt:
The CAN module has woken up from Disable
mode or the device has woken up from Sleep
mode.
DS70116D-page 110
Preliminary
dsPIC30F5011/5013
Receive Error Interrupts:
A receive error interrupt will be indicated by the
ERRIF bit. This bit shows that an error condition
occurred. The source of the error can be determined by checking the bits in the CAN Interrupt
Status register, CiINTF.
- Invalid Message Received:
If any type of error occurred during reception of
the last message, an error will be indicated by
the IVRIF bit.
- Receiver Overrun:
The RXnOVR bit indicates that an overrun
condition occurred.
- Receiver Warning:
The RXWAR bit indicates that the receive error
counter (RERRCNT<7:0>) has reached the
warning limit of 96.
- Receiver Error Passive:
The RXEP bit indicates that the receive error
counter has exceeded the error passive limit of
127 and the module has gone into error passive
state.
17.5
17.5.1
Message Transmission
TRANSMIT BUFFERS
The CAN module has three transmit buffers. Each of

the three buffers occupies 14 bytes of data. Eight of the
bytes are the maximum 8 bytes of the transmitted message. Five bytes hold the standard and extended
identifiers and other message arbitration information.
17.5.2
TRANSMIT MESSAGE PRIORITY
Transmit priority is a prioritization within each node of

the pending transmittable messages. There are
4 levels of transmit priority. If TXPRI<1:0>
(CiTXnCON<1:0>, where n = 0, 1 or 2 represents a particular transmit buffer) for a particular message buffer is
set to 11, that buffer has the highest priority. If
TXPRI<1:0> for a particular message buffer is set to
10 or 01, that buffer has an intermediate priority. If
TXPRI<1:0> for a particular message buffer is 00, that
buffer has the lowest priority.
17.5.3
Setting TXREQ bit simply flags a message buffer as

enqueued for transmission. When the module detects
an available bus, it begins transmitting the message
which has been determined to have the highest priority.
If the transmission completes successfully on the first
attempt, the TXREQ bit is cleared automatically, and an
interrupt is generated if TXIE was set.
If the message transmission fails, one of the error condition flags will be set, and the TXREQ bit will remain
set indicating that the message is still pending for transmission. If the message encountered an error condition
during the transmission attempt, the TXERR bit will be
set, and the error condition may cause an interrupt. If
the message loses arbitration during the transmission
attempt, the TXLARB bit is set. No interrupt is
generated to signal the loss of arbitration.
17.5.4
ABORTING MESSAGE
TRANSMISSION
The system can also abort a message by clearing the

TXREQ bit associated with each message buffer. Setting the ABAT bit (CiCTRL<12>) will request an abort of
all pending messages. If the message has not yet
started transmission, or if the message started but is
interrupted by loss of arbitration or an error, the abort
will be processed. The abort is indicated when the
module sets the TXABT bit and the TXnIF flag is not
automatically set.
17.5.5
TRANSMISSION ERRORS
The CAN module will detect the following transmission

errors:
Acknowledge Error
Form Error
Bit Error
These transmission errors will not necessarily generate
an interrupt but are indicated by the transmission error
counter. However, each of these errors will cause the
transmission error counter to be incremented by one.
Once the value of the error counter exceeds the value
of 96, the ERRIF (CiINTF<5>) and the TXWAR bit
(CiINTF<10>) are set. Once the value of the error
counter exceeds the value of 96, an interrupt is
generated and the TXWAR bit in the Error Flag register
is set.
TRANSMISSION SEQUENCE
To initiate transmission of the message, the TXREQ bit

(CiTXnCON<3>) must be set. The CAN bus module
resolves any timing conflicts between setting of the
TXREQ bit and the Start of Frame (SOF), ensuring that if
the priority was changed, it is resolved correctly before the
SOF occurs. When TXREQ is set, the TXABT
(CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR
(CiTXnCON<4>) flag bits are automatically cleared.
Preliminary
DS70116D-page 111
dsPIC30F5011/5013
17.5.6
17.6
TRANSMIT INTERRUPTS
Baud Rate Setting
Transmit interrupts can be divided into 2 major groups,

each including various conditions that generate
interrupts:
All nodes on any particular CAN bus must have the

same nominal bit rate. In order to set the baud rate, the
following parameters have to be initialized:
Transmit Interrupt:
At least one of the three transmit buffers is empty
(not scheduled) and can be loaded to schedule a
message for transmission. Reading the TXnIF
flags will indicate which transmit buffer is available
and caused the interrupt.
Transmit Error Interrupts:

A transmission error interrupt will be indicated by
the ERRIF flag. This flag shows that an error condition occurred. The source of the error can be
determined by checking the error flags in the CAN
Interrupt Status register, CiINTF. The flags in this
register are related to receive and transmit errors.
- Transmitter Warning Interrupt:
The TXWAR bit indicates that the transmit error
counter has reached the CPU warning limit of
96.
- Transmitter Error Passive:
The TXEP bit (CiINTF<12>) indicates that the
transmit error counter has exceeded the error
passive limit of 127 and the module has gone to
error passive state.
- Bus Off:
The TXBO bit (CiINTF<13>) indicates that the
transmit error counter has exceeded 255 and
the module has gone to the bus off state.
FIGURE 17-2:
Synchronization Jump Width

Baud Rate Prescaler
Phase Segments
Length determination of Phase Segment 2
Sample Point
Propagation Segment bits
17.6.1
BIT TIMING
All controllers on the CAN bus must have the same

baud rate and bit length. However, different controllers
are not required to have the same master oscillator
clock. At different clock frequencies of the individual
controllers, the baud rate has to be adjusted by
adjusting the number of time quanta in each segment.
The nominal bit time can be thought of as being divided
into separate non-overlapping time segments. These
segments are shown in Figure 17-2.
Synchronization Segment (Sync Seg)

Propagation Time Segment (Prop Seg)
Phase Segment 1 (Phase1 Seg)
Phase Segment 2 (Phase2 Seg)
The time segments and also the nominal bit time are
made up of integer units of time called time quanta or
TQ. By definition, the nominal bit time has a minimum
of 8 TQ and a maximum of 25 TQ. Also, by definition,
the minimum nominal bit time is 1 sec corresponding
to a maximum bit rate of 1 MHz.
CAN BIT TIMING
Input Signal
Sync
Prop
Segment
Phase
Segment 1
Phase
Segment 2
Sync
Sample Point
TQ
DS70116D-page 112
Preliminary
dsPIC30F5011/5013
17.6.2
PRESCALER SETTING
17.6.5
There is a programmable prescaler with integral values

ranging from 1 to 64, in addition to a fixed divide-by-2
for clock generation. The time quantum (TQ) is a fixed
unit of time derived from the oscillator period, and is
given by Equation 17-1, where FCAN is FCY (if the
CANCKS bit is set) or 4FCY (if CANCKS is clear).
Note:
FCAN must not exceed 30 MHz. If

CANCKS = 0, then FCY must not exceed
7.5 MHz.
EQUATION 17-1:
TIME QUANTUM FOR

CLOCK GENERATION
17.6.6
PROPAGATION SEGMENT
This part of the bit time is used to compensate physical

delay times within the network. These delay times consist of the signal propagation time on the bus line and
the internal delay time of the nodes. The Prop Seg can
be programmed from 1 TQ to 8 TQ by setting the
PRSEG<2:0> bits (CiCFG2<2:0>).
17.6.4
PHASE SEGMENTS
The phase segments are used to optimally locate the

sampling of the received bit within the transmitted bit
time. The sampling point is between Phase1 Seg and
Phase2 Seg. These segments are lengthened or shortened by resynchronization. The end of the Phase1 Seg
determines the sampling point within a bit period. The
segment is programmable from 1 TQ to 8 TQ. Phase2
Seg provides delay to the next transmitted data transition. The segment is programmable from 1 TQ to 8 TQ,
or it may be defined to be equal to the greater of
Phase1 Seg or the information processing time (2 TQ).
The Phase1 Seg is initialized by setting bits
SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is
initialized by setting SEG2PH<2:0> (CiCFG2<10:8>).
The following requirement must be fulfilled while setting
the lengths of the phase segments:
Prop Seg + Phase1 Seg > = Phase2 Seg
The sample point is the point of time at which the bus

level is read and interpreted as the value of that respective bit. The location is at the end of Phase1 Seg. If the
bit timing is slow and contains many TQ, it is possible to
specify multiple sampling of the bus line at the sample
point. The level determined by the CAN bus then corresponds to the result from the majority decision of three
values. The majority samples are taken at the sample
point and twice before with a distance of TQ/2. The
CAN module allows the user to choose between sampling three times at the same point or once at the same
point, by setting or clearing the SAM bit (CiCFG2<6>).
Typically, the sampling of the bit should take place at
about 60 - 70% through the bit time, depending on the
system parameters.
TQ = 2 (BRP<5:0> + 1) / FCAN
17.6.3
SAMPLE POINT
SYNCHRONIZATION
To compensate for phase shifts between the oscillator

frequencies of the different bus stations, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time (Synchronous Segment). The circuit will then adjust the values
of Phase1 Seg and Phase2 Seg. There are 2
mechanisms used to synchronize.
17.6.6.1
Hard Synchronization
Hard synchronization is only done whenever there is a

recessive to dominant edge during bus Idle indicating
the start of a message. After hard synchronization, the
bit time counters are restarted with the Sync Seg. Hard
synchronization forces the edge which has caused the
hard synchronization to lie within the synchronization
segment of the restarted bit time. If a hard synchronization is done, there will not be a resynchronization within
that bit time.
17.6.6.2
Resynchronization
As a result of resynchronization, Phase1 Seg may be

lengthened or Phase2 Seg may be shortened. The
amount of lengthening or shortening of the phase
buffer segment has an upper bound known as the synchronization jump width, and is specified by the
SJW<1:0> bits (CiCFG1<7:6>). The value of the synchronization jump width will be added to Phase1 Seg or
subtracted from Phase2 Seg. The resynchronization
jump width is programmable between 1 TQ and 4 TQ.
The following requirement must be fulfilled while setting
the SJW<1:0> bits:
Phase2 Seg > Synchronization Jump Width
Preliminary
DS70116D-page 113
DS70116D-page 114
Preliminary
0324
0328
0330
0338
0344
C1RXM0EIDL
C1RXM1SID
C1RXM1EIDL 033C
0342
C1RXM0SID
C1RXM1EIDH 033A
0340
C1RXF5EIDL
C1RXM0EIDH 0332
0334
C1RXF5SID
C1RXF5EIDH 032A
032C
C1RXF4EIDL
C1TX2SID
C1TX2EID
C1TX2DLC
0356
C1TX1DLC
C1TX1B1
Transmit Buffer 1 Byte 1
Transmit Buffer 1 Extended Identifier <5:0>
Transmit Buffer 1 Extended Identifier

<17:14>
Transmit Buffer 1 Standard Identifier <10:6>

<17:14>
Receive Acceptance Filter 4 Extended Identifier <5:0>
0354
C1TX1EID
Legend:
0350
0352
C1TX1SID
034E
0322
C1RXF4EIDH
C1TX2CON
0320
C1RXF4SID
034C
031C
C1RXF3EIDL
C1TX2B4
Receive Acceptance Mask 1 Extended Identifier <5:0>
C1RXF3EIDH 031A
034A
0318
C1RXF3SID
C1TX2B3
0314
C1RXF2EIDL
0348
0312
C1RXF2EIDH
C1TX2B2
0310
C1RXF2SID
0346
030C
C1RXF1EIDL
C1TX2B1
0308
C1RXF1EIDH 030A
C1RXF1SID
0304
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
TXRTR
TXRTR
TXRB1
TXRB1
Bit 2
TXABT TXLARB TXERR
TXREQ
DLC<3:0>
DLC<3:0>
TXRB0
TXRB0
Receive Acceptance Mask 1 Standard Identifier <10:0>
Receive Acceptance Filter 5 Standard Identifier <10:0>
Bit 3
Bit 4
Bit 10
C1RXF0EIDL
Bit 11
0300
Bit 12
0302
Bit 13
C1RXF0SID
Bit 14
Bit 15
CAN1 REGISTER MAP
Addr.
C1RXF0EIDH
SFR Name
TABLE 17-1:
SRR
Reset State
0000 uuuu uuuu uuuu

uuuu uu00 0000 0000
0000 uuuu uuuu uuuu

uuuu uu00 0000 0000
0000 uuuu uuuu uuuu

uuuu uu00 0000 0000
0000 uuuu uuuu uuuu

uuuu uu00 0000 0000
0000 uuuu uuuu uuuu

uuuu uu00 0000 0000
0000 uuuu uuuu uuuu
uuuu uu00 0000 0000
0000 uuuu uuuu uuuu
000u uuuu uuuu uu0u
uuuu uu00 0000 0000
0000 uuuu uuuu uuuu
000u uuuu uuuu uu0u
uuuu uu00 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu u000
uuuu 0000 uuuu uuuu
TXIDE uuuu u000 uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu u000
uuuu 0000 uuuu uuuu
MIDE
MIDE
EXIDE 000u uuuu uuuu uu0u
Bit 0
TXPRI<1:0>
SRR
Bit 1
dsPIC30F5011/5013
Preliminary
RX1OVR
CANCAP
RX0OVR
0384
0386
0388
038A
038C
038E
0390
0392
0394
0396
0398
039A
C1RX0B1
C1RX0B2
C1RX0B3
C1RX0B4
C1RX0CON
C1CTRL
C1CFG1
C1CFG2
C1INTF
C1INTE
C1EC
Receive Buffer 1 Byte 7
TXEP
ABAT
RXEP
CANCKS
SEG2PH<2:0>
REQOP<2:0>
DLC<3:0>
TXABT TXLARB TXERR
RXFUL
RXRTRRO
RXRB0
IVRIE
IVRIF
SEG2PHTS
WAKIE
WAKIF
SAM
SJW<1:0>
RXRB0
TX2IF
TX2IE
SRR
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu u000
uuuu 0000 uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu 000u uuuu
0000 uuuu uuuu uuuu
RXIDE 000u uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu 000u uuuu
0000 uuuu uuuu uuuu
RXIDE 000u uuuu uuuu uuuu
FILHIT<2:0>
DLC<3:0>
TX1IF
TX1IE
TX0IE
TX0IF
RX1E
RX1IF
0u00 0uuu uuuu uuuu
0000 0000 0000 0000
0000 0100 1000 0000
0000 0000 0000 0000
RX0IE 0000 0000 0000 0000
RX0IF 0000 0000 0000 0000
PRSEG<2:0>
ICODE<2:0>
BRP<5:0>
Receive Error Count Register
ERRIE
SRR
Reset State
uuuu uuuu uuuu uuuu
TXPRI<1:0>
SRR
DLC<3:0>
Bit 0
TXPRI<1:0>
Bit 1
RXRTRRO DBEN JTOFF FILHIT0 0000 0000 0000 0000
SEG1PH<2:0>
ERRIF
OPMODE<2:0>
RXFUL
TXREQ
Receive Buffer 0 Extended Identifier <17:6>

RXRTR RXRB1
TXREQ
Bit 2
Receive Buffer 0 Standard Identifier <10:0>
Bit 3

RXRTR RXRB1
Bit 4
Bit 5
TXABT TXLARB TXERR
Bit 6
TXRB0
Bit 7
TXRB1
Bit 8
TXWAR RXWAR EWARN
Transmit Error Count Register
TXBO
CSIDLE
TXRTR
Bit 9
Bit 10
WAKFIL
C1RX0DLC
0382
0380
C1RX0EID
C1RX0SID
Legend:
037E
0372
C1RX1EID
C1RX1CON
0370
C1RX1SID
037C
036E
C1TX0CON
C1RX1B4
036C
C1TX0B4
037A
036A
C1TX0B3
C1RX1B3
0368
C1TX0B2
Bit 11
0378
0366
C1TX0DLC
C1TX0B1
Bit 12
Bit 13

<17:14>
0376
0364
C1TX0EID
C1RX1B2
0362
C1TX0SID
C1RX1B1
0360
C1TX1CON
Bit 14
0374
035E
C1TX1B4
Bit 15
CAN1 REGISTER MAP (CONTINUED)
C1RX1DLC
035A
035C
C1TX1B3
0358
Addr.
C1TX1B2
SFR Name
TABLE 17-1:
dsPIC30F5011/5013
DS70116D-page 115
DS70116D-page 116
03E0
03E2
03E4
C2RXF3EIDL
C2RXF4SID
C2RXF4EIDH
C2RXF4EIDL
Preliminary
Bit 13
Bit 12
Bit 11
Bit 10

<17:14>

<17:14>
Bit 7
Bit 6
Bit 5
TXRTR
TXRTR
TXRB1
TXRB1
TXRB0
TXRB0
Bit 2
TXLARB
TXERR
TXREQ
DLC<3:0>
TXABT
DLC<3:0>
Bit 3
Bit 4
Bit 8
Bit 9
Bit 14
Bit 15
CAN2 REGISTER MAP
0414
Legend:
C2TX1DLC
040E
C2TX2CON
0410
040C
C2TX2B4
0412
040A
C2TX2B3
C2TX1SID
0408
C2TX2B2
C2TX1EID
0404
0406
0402
C2TX2EID
C2TX2B1
0400
C2TX2SID
C2TX2DLC
03FA
03FC
C2RXM1EIDH
03F8
C2RXM1SID
C2RXM1EIDL
03F2
03F4
C2RXM0EIDH
03F0
C2RXM0SID
C2RXM0EIDL
03EA
03EC
C2RXF5EIDH
C2RXF5EIDL
03E8
03DC
C2RXF3EIDH
C2RXF5SID
03D8
03DA
C2RXF3SID
03D2
03D4
C2RXF2EIDH
03D0
C2RXF2SID
C2RXF2EIDL
03CA
03CC
C2RXF1EIDH
C2RXF1EIDL
03C4
03C8
03C2
C2RXF0EIDH
C2RXF1SID
03C0
C2RXF0SID
C2RXF0EIDL
Addr.
SFR Name
TABLE 17-2:
TXIDE
MIDE
MIDE
EXIDE
EXIDE
EXIDE
EXIDE
EXIDE
EXIDE
Bit 0
SRR
TXIDE
TXPRI<1:0>
SRR
Bit 1
uuuu uuuu uuuu u000
uuuu 0000 uuuu uuuu
uuuu u000 uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu u000
uuuu 0000 uuuu uuuu
uuuu u000 uuuu uuuu
uuuu uu00 0000 0000
0000 uuuu uuuu uuuu
000u uuuu uuuu uu0u
uuuu uu00 0000 0000
0000 uuuu uuuu uuuu
000u uuuu uuuu uu0u
uuuu uu00 0000 0000
0000 uuuu uuuu uuuu
000u uuuu uuuu uu0u
uuuu uu00 0000 0000
0000 uuuu uuuu uuuu
000u uuuu uuuu uu0u
uuuu uu00 0000 0000
0000 uuuu uuuu uuuu
000u uuuu uuuu uu0u
uuuu uu00 0000 0000
0000 uuuu uuuu uuuu
000u uuuu uuuu uu0u
uuuu uu00 0000 0000
0000 uuuu uuuu uuuu
000u uuuu uuuu uu0u
uuuu uu00 0000 0000
0000 uuuu uuuu uuuu
000u uuuu uuuu uu0u
Reset State
dsPIC30F5011/5013
Preliminary
Bit 14
Bit 12
Bit 11
Bit 13
RX0OVR
CANCAP
TXEP
ABAT
RXEP
CANCKS
RXWAR
RXRB1
EWARN
RXRB1
SEG2PH<2:0>
TXRB0
Bit 7
Bit 4
TXLARB
TXERR
RXFUL
TXABT
TXERR
SEG2PHTS
IVRIE
WAKIE
WAKIF
SAM
SJW<1:0>
IVRIF
RXRB0
TX2IE
TX1IE
TX1IF
Receive Error Count Register
ERRIE
TX2IF
SRR
SRR
TX0IE
RXIDE
RX1E
RX1IF
RX0IE
RX0IF
FILHIT0
RXIDE
PRSEG<2:0>
JTOFF
DLC<3:0>
TX0IF
BRP<5:0>
TXIDE
TXPRI<1:0>
SRR
FILHIT<2:0>
ICODE<2:0>
Bit 0
TXPRI<1:0>
Bit 1
DLC<3:0>
RXRTRRO DBEN
SEG1PH<2:0>
ERRIF
RXRTRRO
RXRB0
TXREQ
DLC<3:0>
TXLARB
OPMODE<2:0>
RXFUL
Bit 2
TXREQ
Bit 3
Bit 5
TXABT
Bit 6
RXRTR
TXRB1
Bit 8
RXRTR
TXRTR
Bit 9
REQOP<2:0>
TXWAR
Transmit Error Count Register
TXBO
CSIDLE
Bit 10
RX1OVR
WAKFIL

<17:14>
Bit 15
CAN2 REGISTER MAP (CONTINUED)
045A
C2EC
Legend:
0458
0452
C2CFG1
C2INTE
0450
C2CTRL
0454
044E
C2RX0CON
0456
044C
C2RX0B4
C2CFG2
044A
C2RX0B3
C2INTF
0448
0440
C2RX0SID
C2RX0B2
043E
C2RX1CON
0446
043C
C2RX1B4
C2RX0B1
043A
C2RX1B3
0442
0438
C2RX1B2
0444
0436
C2RX1B1
C2RX0DLC
0434
C2RX1DLC
C2RX0EID
0430
042E
C2TX0CON
0432
042C
C2TX0B4
C2RX1SID
042A
C2TX0B3
C2RX1EID
0428
C2TX0EID
C2TX0B2
0422
C2TX0SID
0424
0420
C2TX1CON
0426
041E
C2TX1B4
C2TX0B1
041C
C2TX1B3
C2TX0DLC
0418
041A
C2TX1B2
0416
Addr.
C2TX1B1
SFR Name
TABLE 17-2:
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0u00 0uuu uuuu uuuu
0000 0000 0000 0000
0000 0100 1000 0000
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu 000u uuuu
0000 uuuu uuuu uuuu
000u uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu 000u uuuu
0000 uuuu uuuu uuuu
000u uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu u000
uuuu 0000 uuuu uuuu
uuuu u000 uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
dsPIC30F5011/5013
DS70116D-page 117
dsPIC30F5011/5013
NOTES:
DS70116D-page 118
Preliminary
dsPIC30F5011/5013
18.0
DATA CONVERTER
INTERFACE (DCI) MODULE
18.2.3

Manual (DS70046).
18.1
Module Introduction
The dsPIC30F Data Converter Interface (DCI) module

allows simple interfacing of devices, such as audio
coder/decoders (Codecs), A/D converters and D/A
converters. The following interfaces are supported:
Framed Synchronous Serial Transfer (Single or
Multi-Channel)
Inter-IC Sound (I2S) Interface
AC-Link Compliant mode
Programmable word size up to 16 bits

Support for up to 16 time slots, for a maximum
frame size of 256 bits
Data buffering for up to 4 samples without CPU
overhead
18.2
The serial data input (CSDI) pin is configured as an

input only pin when the module is enabled.
18.2.3.1
The DCI module accesses the shadow registers while

the CPU is in the process of accessing the memory
mapped buffer registers.
BUFFER DATA ALIGNMENT
Data values are always stored left justified in the buffers since most Codec data is represented as a signed
2s complement fractional number. If the received word
length is less than 16 bits, the unused LS bits in the
receive buffer registers are set to 0 by the module. If
the transmitted word length is less than 16 bits, the
unused LS bits in the transmit buffer register are
ignored by the module. The word length setup is
described in subsequent sections of this document.
18.2.5
Module I/O Pins
COFS PIN
The Codec frame synchronization (COFS) pin is used

to synchronize data transfers that occur on the CSDO
and CSDI pins. The COFS pin may be configured as an
input or an output. The data direction for the COFS pin
is determined by the COFSD control bit in the
DCICON1 register.
18.2.4
The DCI module provides the following general

features:
CSDI PIN
TRANSMIT/RECEIVE SHIFT
REGISTER
There are four I/O pins associated with the module.

When enabled, the module controls the data direction
of each of the four pins.
The DCI module has a 16-bit shift register for shifting

serial data in and out of the module. Data is shifted in/
out of the shift register MS bit first, since audio PCM
data is transmitted in signed 2s complement format.
18.2.1
18.2.6
CSCK PIN
The CSCK pin provides the serial clock for the DCI
module. The CSCK pin may be configured as an input
or output using the CSCKD control bit in the DCICON2
SFR. When configured as an output, the serial clock is
provided by the dsPIC30F. When configured as an
input, the serial clock must be provided by an external
device.
18.2.2
CSDO PIN
The serial data output (CSDO) pin is configured as an

output only pin when the module is enabled. The
CSDO pin drives the serial bus whenever data is to be
transmitted. The CSDO pin is tri-stated or driven to 0
during CSCK periods when data is not transmitted,
depending on the state of the CSDOM control bit. This
allows other devices to place data on the serial bus
during transmission periods not used by the DCI
module.
DCI BUFFER CONTROL
The DCI module contains a buffer control unit for transferring data between the shadow buffer memory and
the serial shift register. The buffer control unit is a simple 2-bit address counter that points to word locations
in the shadow buffer memory. For the receive memory
space (high address portion of DCI buffer memory), the
address counter is concatenated with a 0 in the MSb
location to form a 3-bit address. For the transmit memory space (high portion of DCI buffer memory), the
address counter is concatenated with a 1 in the MSb
location.
Note:
Preliminary
The DCI buffer control unit always

accesses the same relative location in the
transmit and receive buffers, so only one
address counter is provided.
DS70116D-page 119
dsPIC30F5011/5013
FIGURE 18-1:
DCI MODULE BLOCK DIAGRAM
BCG Control bits

SCKD
FOSC/4
Sample Rate
CSCK
Generator
FSD
Word Size Selection bits
16-bit Data Bus
Frame Length Selection bits

DCI Mode Selection bits
Frame
Synchronization
Generator
COFS
Receive Buffer
Registers w/Shadow
DCI Buffer
Control Unit
15
Transmit Buffer
Registers w/Shadow
0
DCI Shift Register
CSDI
CSDO
DS70116D-page 120
Preliminary
dsPIC30F5011/5013
18.3
18.3.1
18.3.4
DCI Module Operation

MODULE ENABLE
The DCI module is enabled or disabled by setting/

clearing the DCIEN control bit in the DCICON1 SFR.
Clearing the DCIEN control bit has the effect of resetting the module. In particular, all counters associated
with CSCK generation, frame sync, and the DCI buffer
control unit are reset.
FRAME SYNC MODE

CONTROL BITS
The type of frame sync signal is selected using the

Frame
Synchronization
mode
control
bits
(COFSM<1:0>) in the DCICON1 SFR. The following
operating modes can be selected:
The DCI clocks are shutdown when the DCIEN bit is

cleared.
When enabled, the DCI controls the data direction for

the four I/O pins associated with the module. The Port,
LAT and TRIS register values for these I/O pins are
overridden by the DCI module when the DCIEN bit is set.
The operation of the COFSM control bits depends on

whether the DCI module generates the frame sync
signal as a master device, or receives the frame sync
signal as a slave device.
It is also possible to override the CSCK pin separately

when the bit clock generator is enabled. This permits
the bit clock generator to operate without enabling the
rest of the DCI module.
The master device in a DSP/Codec pair is the device

that generates the frame sync signal. The frame sync
signal initiates data transfers on the CSDI and CSDO
pins and usually has the same frequency as the data
sample rate (COFS).
18.3.2
The DCI module is a frame sync master if the COFSD

control bit is cleared and is a frame sync slave if the
COFSD control bit is set.
WORD SIZE SELECTION BITS
The WS<3:0> word size selection bits in the DCICON2

SFR determine the number of bits in each DCI data
word. Essentially, the WS<3:0> bits determine the
counting period for a 4-bit counter clocked from the
CSCK signal.
Any data length, up to 16-bits, may be selected. The
value loaded into the WS<3:0> bits is one less the
desired word length. For example, a 16-bit data word
size is selected when WS<3:0> = 1111.
Note:
18.3.3
These WS<3:0> control bits are used only

in the Multi-Channel and I2S modes. These
bits have no effect in AC-Link mode since
the data slot sizes are fixed by the protocol.
FRAME SYNC GENERATOR
The frame sync generator (COFSG) is a 4-bit counter

that sets the frame length in data words. The frame
sync generator is incremented each time the word size
counter is reset (refer to Section 18.3.2). The period for
the frame synchronization generator is set by writing
the COFSG<3:0> control bits in the DCICON2 SFR.
The COFSG period in clock cycles is determined by the
following formula:
EQUATION 18-1:
COFSG PERIOD
Frame Length = Word Length (FSG Value + 1)

Frame lengths, up to 16 data words, may be selected.
The frame length in CSCK periods can vary up to a
maximum of 256 depending on the word size that is
selected.
Note:
Multi-Channel mode
I2S mode
AC-Link mode (16-bit)
AC-Link mode (20-bit)
18.3.5
MASTER FRAME SYNC

OPERATION
When the DCI module is operating as a frame sync

master device (COFSD = 0), the COFSM mode bits
determine the type of frame sync pulse that is
generated by the frame sync generator logic.
A new COFS signal is generated when the frame sync
generator resets to 0.
In the Multi-Channel mode, the frame sync pulse is
driven high for the CSCK period to initiate a data transfer. The number of CSCK cycles between successive
frame sync pulses will depend on the word size and
frame sync generator control bits. A timing diagram for
the frame sync signal in Multi-Channel mode is shown
in Figure 18-2.
In the AC-Link mode of operation, the frame sync signal has a fixed period and duty cycle. The AC-Link
frame sync signal is high for 16 CSCK cycles and is low
for 240 CSCK cycles. A timing diagram with the timing
details at the start of an AC-Link frame is shown in
Figure 18-3.
In the I2S mode, a frame sync signal having a 50% duty
cycle is generated. The period of the I2S frame sync
signal in CSCK cycles is determined by the word size
and frame sync generator control bits. A new I2S data
transfer boundary is marked by a high-to-low or a
low-to-high transition edge on the COFS pin.
The COFSG control bits will have no effect

in AC-Link mode since the frame length is
set to 256 CSCK periods by the protocol.
Preliminary
DS70116D-page 121
dsPIC30F5011/5013
18.3.6
SLAVE FRAME SYNC OPERATION
When the DCI module is operating as a frame sync

slave (COFSD = 1), data transfers are controlled by the
Codec device attached to the DCI module. The
COFSM control bits control how the DCI module
responds to incoming COFS signals.
In the Multi-Channel mode, a new data frame transfer
will begin one CSCK cycle after the COFS pin is sampled high (see Figure 18-2). The pulse on the COFS
pin resets the frame sync generator logic.
FIGURE 18-2:
In the I2S mode, a new data word will be transferred

one CSCK cycle after a low-to-high or a high-to-low
transition is sampled on the COFS pin. A rising or falling edge on the COFS pin resets the frame sync
generator logic.
In the AC-Link mode, the tag slot and subsequent data
slots for the next frame will be transferred one CSCK
cycle after the COFS pin is sampled high.
The COFSG and WS bits must be configured to provide the proper frame length when the module is operating in the Slave mode. Once a valid frame sync pulse
has been sampled by the module on the COFS pin, an
entire data frame transfer will take place. The module
will not respond to further frame sync pulses until the
data frame transfer has completed.
FRAME SYNC TIMING, MULTI-CHANNEL MODE

CSCK
COFS
CSDI/CSDO
FIGURE 18-3:
MSB
LSB
FRAME SYNC TIMING, AC-LINK START OF FRAME

BIT_CLK
CSDO or CSDI
S12 S12 S12 Tag Tag Tag

bit 2 bit 1 LSb MSb bit 14 bit 13
SYNC
FIGURE 18-4:
I2S INTERFACE FRAME SYNC TIMING
CSCK
CSDI or CSDO
MSB
LSB MSB
LSB
WS
Note:
A 5-bit transfer is shown here for illustration purposes. The I2S protocol does not specify word length - this will
be system dependent.
DS70116D-page 122
Preliminary
dsPIC30F5011/5013
18.3.7
18.3.8
BIT CLOCK GENERATOR
The DCI module has a dedicated 12-bit time base that

produces the bit clock. The bit clock rate (period) is set
by writing a non-zero 12-bit value to the BCG<11:0>
control bits in the DCICON1 SFR.
When the BCG<11:0> bits are set to zero, the bit clock
will be disabled. If the BCG<11:0> bits are set to a nonzero value, the bit clock generator is enabled. These
bits should be set to 0 and the CSCKD bit set to 1 if
the serial clock for the DCI is received from an external
device.
SAMPLE CLOCK EDGE

CONTROL BIT
The sample clock edge (CSCKE) control bit determines

the sampling edge for the CSCK signal. If the CSCK bit
is cleared (default), data will be sampled on the falling
edge of the CSCK signal. The AC-Link protocols and
most Multi-Channel formats require that data be sampled on the falling edge of the CSCK signal. If the
CSCK bit is set, data will be sampled on the rising edge
of CSCK. The I2S protocol requires that data be
sampled on the rising edge of the CSCK signal.
The formula for the bit clock frequency is given in

Equation 18-2.
18.3.9
EQUATION 18-2:
In most applications, the data transfer begins one

CSCK cycle after the COFS signal is sampled active.
This is the default configuration of the DCI module. An
alternate data alignment can be selected by setting the
DJST control bit in the DCICON2 SFR. When DJST = 1,
data transfers will begin during the same CSCK cycle
when the COFS signal is sampled active.
BIT CLOCK FREQUENCY
FBCK =
FCY
2 (BCG + 1)
The required bit clock frequency will be determined by

the system sampling rate and frame size. Typical bit
clock frequencies range from 16x to 512x the converter
sample rate depending on the data converter and the
communication protocol that is used.
To achieve bit clock frequencies associated with common audio sampling rates, the user will need to select
a crystal frequency that has an even binary value.
Examples of such crystal frequencies are listed in
Table 18-1.
TABLE 18-1:
DEVICE FREQUENCIES FOR

COMMON CODEC CSCK
FREQUENCIES
FOSC
PLL
FCYC
2.048 MHz
16x
32.768 MIPs
4.096 MHz
8x
32.768 MIPs
4.800 MHz
8x
38.4 MIPs
9.600 MHz
4x
38.4 MIPs
Note 1: When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits
have no effect on the operation of the DCI
module.
2: When the CSCK signal is applied externally (CSCKD = 1), the external clock
high and low times must meet the device
timing requirements.
18.3.10
DATA JUSTIFICATION
CONTROL BIT
TRANSMIT SLOT ENABLE BITS
The TSCON SFR has control bits that are used to

enable up to 16 time slots for transmission. These control bits are the TSE<15:0> bits. The size of each time
slot is determined by the WS<3:0> word size selection
bits and can vary up to 16 bits.
If a transmit time slot is enabled via one of the TSE bits
(TSEx = 1), the contents of the current transmit shadow
buffer location will be loaded into the CSDO Shift register and the DCI buffer control unit is incremented to
point to the next location.
During an unused transmit time slot, the CSDO pin will
drive 0s or will be tri-stated during all disabled time
slots depending on the state of the CSDOM bit in the
DCICON1 SFR.
The data frame size in bits is determined by the chosen
data word size and the number of data word elements
in the frame. If the chosen frame size has less than 16
elements, the additional slot enable bits will have no
effect.
Each transmit data word is written to the 16-bit transmit
buffer as left justified data. If the selected word size is
less than 16 bits, then the LS bits of the transmit buffer
memory will have no effect on the transmitted data. The
user should write 0s to the unused LS bits of each
transmit buffer location.
Preliminary
DS70116D-page 123
dsPIC30F5011/5013
18.3.11
RECEIVE SLOT ENABLE BITS
18.3.14
The RSCON SFR contains control bits that are used to

enable up to 16 time slots for reception. These control
bits are the RSE<15:0> bits. The size of each receive
time slot is determined by the WS<3:0> word size
selection bits and can vary from 1 to 16 bits.
If a receive time slot is enabled via one of the RSE bits
(RSEx = 1), the shift register contents will be written to
the current DCI receive shadow buffer location and the
buffer control unit will be incremented to point to the
next buffer location.
Data is not packed in the receive memory buffer locations if the selected word size is less than 16 bits. Each
received slot data word is stored in a separate 16-bit
buffer location. Data is always stored in a left justified
format in the receive memory buffer.
18.3.12
SLOT ENABLE BITS OPERATION

WITH FRAME SYNC
The TSE and RSE control bits operate in concert with

the DCI frame sync generator. In the Master mode, a
COFS signal is generated whenever the frame sync
generator is reset. In the Slave mode, the frame sync
generator is reset whenever a COFS pulse is received.
The TSE and RSE control bits allow up to 16 consecutive time slots to be enabled for transmit or receive.
After the last enabled time slot has been transmitted/
received, the DCI will stop buffering data until the next
occurring COFS pulse.
18.3.13
SYNCHRONOUS DATA
TRANSFERS
The amount of data that is buffered between interrupts

is determined by the buffer length (BLEN<1:0>) control
bits in the DCISTAT SFR. The size of the transmit and
receive buffers may be varied from 1 to 4 data words
using the BLEN control bits. The BLEN control bits are
compared to the current value of the DCI buffer control
unit address counter. When the 2 LS bits of the DCI
address counter match the BLEN<1:0> value, the
buffer control unit will be reset to 0. In addition, the
contents of the receive shadow registers are transferred to the receive buffer registers and the contents
of the transmit buffer registers are transferred to the
transmit shadow registers.
18.3.15
BUFFER ALIGNMENT WITH DATA

FRAMES
There is no direct coupling between the position of the

AGU address pointer and the data frame boundaries.
This means that there will be an implied assignment of
each transmit and receive buffer that is a function of the
BLEN control bits and the number of enabled data slots
via the TSE and RSE control bits.
As an example, assume that a 4-word data frame is
chosen and that we want to transmit on all four time
slots in the frame. This configuration would be established by setting the TSE0, TSE1, TSE2, and TSE3
control bits in the TSCON SFR. With this module setup,
the TXBUF0 register would be naturally assigned to
slot #0, the TXBUF1 register would be naturally
assigned to slot #1, and so on.
Note:
The DCI buffer control unit will be incremented by one

word location whenever a given time slot has been
enabled for transmission or reception. In most cases,
data input and output transfers will be synchronized,
which means that a data sample is received for a given
channel at the same time a data sample is transmitted.
Therefore, the transmit and receive buffers will be filled
with equal amounts of data when a DCI interrupt is
generated.
In some cases, the amount of data transmitted and
received during a data frame may not be equal. As an
example, assume a two-word data frame is used. Furthermore, assume that data is only received during
slot #0 but is transmitted during slot #0 and slot #1. In
this case, the buffer control unit counter would be incremented twice during a data frame but only one receive
register location would be filled with data.
DS70116D-page 124
BUFFER LENGTH CONTROL
Preliminary
When more than four time slots are active

within a data frame, the user code must
keep track of which time slots are to be
read/written at each interrupt. In some
cases, the alignment between transmit/
receive buffers and their respective slot
assignments could be lost. Examples of
such cases include an emulation breakpoint or a hardware trap. In these situations, the user should poll the SLOT status
bits to determine what data should be
loaded into the buffer registers to
resynchronize the software with the DCI
module.
dsPIC30F5011/5013
18.3.16
TRANSMIT STATUS BITS
18.3.19
There are two transmit status bits in the DCISTAT SFR.

The TMPTY bit is set when the contents of the transmit
buffer registers are transferred to the transmit shadow
registers. The TMPTY bit may be polled in software to
determine when the transmit buffer registers may be
written. The TMPTY bit is cleared automatically by the
hardware when a write to one of the four transmit
buffers occurs.
The TUNF bit is read only and indicates that a transmit
underflow has occurred for at least one of the transmit
buffer registers that is in use. The TUNF bit is set at the
time the transmit buffer registers are transferred to the
transmit shadow registers. The TUNF status bit is
cleared automatically when the buffer register that
underflowed is written by the CPU.
Note:
18.3.17
The transmit status bits only indicate status for buffer locations that are used by the
module. If the buffer length is set to less
than four words, for example, the unused
buffer locations will not affect the transmit
status bits.
RECEIVE STATUS BITS
There are two receive status bits in the DCISTAT SFR.
CSDO MODE BIT
The CSDOM control bit controls the behavior of the

CSDO pin during unused transmit slots. A given transmit time slot is unused if its corresponding TSEx bit in
the TSCON SFR is cleared.
If the CSDOM bit is cleared (default), the CSDO pin will
be low during unused time slot periods. This mode will
be used when there are only two devices attached to
the serial bus.
If the CSDOM bit is set, the CSDO pin will be tri-stated
during unused time slot periods. This mode allows multiple devices to share the same CSDO line in a multichannel application. Each device on the CSDO line is
configured so that it will only transmit data during
specific time slots. No two devices will transmit data
during the same time slot.
18.3.20
DIGITAL LOOPBACK MODE
Digital Loopback mode is enabled by setting the

DLOOP control bit in the DCISTAT SFR. When the
DLOOP bit is set, the module internally connects the
CSDO signal to CSDI. The actual data input on the
CSDI I/O pin will be ignored in Digital Loopback mode.
18.3.21
UNDERFLOW MODE CONTROL BIT
The ROV status bit is read only and indicates that a

receive overflow has occurred for at least one of the
receive buffer locations. A receive overflow occurs
when the buffer location is not read by the CPU before
new data is transferred from the shadow registers. The
ROV status bit is cleared automatically when the buffer
register that caused the overflow is read by the CPU.
When an underflow occurs, one of two actions may

occur depending on the state of the Underflow mode
(UNFM) control bit in the DCICON2 SFR. If the UNFM
bit is cleared (default), the module will transmit 0s on
the CSDO pin during the active time slot for the buffer
location. In this Operating mode, the Codec device
attached to the DCI module will simply be fed digital
silence. If the UNFM control bit is set, the module will
transmit the last data written to the buffer location. This
Operating mode permits the user to send continuous
data to the Codec device without consuming CPU
overhead.
When a receive overflow occurs for a specific buffer

location, the old contents of the buffer are overwritten.
18.4
The RFUL status bit is read only and indicates that new
data is available in the receive buffers. The RFUL bit is
cleared automatically when all receive buffers in use
have been read by the CPU.
Note:
18.3.18
The receive status bits only indicate status

for buffer locations that are used by the
module. If the buffer length is set to less
than four words, for example, the unused
buffer locations will not affect the transmit
status bits.
SLOT STATUS BITS
The SLOT<3:0> status bits in the DCISTAT SFR indicate the current active time slot. These bits will correspond to the value of the frame sync generator counter.
The user may poll these status bits in software when a
DCI interrupt occurs to determine what time slot data
was last received and which time slot data should be
loaded into the TXBUF registers.
DCI Module Interrupts
The frequency of DCI module interrupts is dependent

on the BLEN<1:0> control bits in the DCICON2 SFR.
An interrupt to the CPU is generated each time the set
buffer length has been reached and a shadow register
transfer takes place. A shadow register transfer is
defined as the time when the previously written TXBUF
values are transferred to the transmit shadow registers
and new received values in the receive shadow
registers are transferred into the RXBUF registers.
Preliminary
DS70116D-page 125
dsPIC30F5011/5013
18.5
18.5.1
DCI Module Operation During CPU

DCI MODULE OPERATION DURING
CPU SLEEP MODE
The DCI module has the ability to operate while in

Sleep mode and wake the CPU when the CSCK signal
is supplied by an external device (CSCKD = 1). The
DCI module will generate an asynchronous interrupt
when a DCI buffer transfer has completed and the CPU
is in Sleep mode.
18.5.2
DCI MODULE OPERATION DURING

CPU IDLE MODE
If the DCISIDL control bit is cleared (default), the module will continue to operate normally even in Idle mode.
If the DCISIDL bit is set, the module will halt when Idle
mode is asserted.
18.6
AC-Link Mode Operation
The AC-Link protocol is a 256-bit frame with one 16-bit

data slot, followed by twelve 20-bit data slots. The DCI
module has two Operating modes for the AC-Link protocol. These Operating modes are selected by the
COFSM<1:0> control bits in the DCICON1 SFR. The
first AC-Link mode is called 16-bit AC-Link mode and
is selected by setting COFSM<1:0> = 10. The second
AC-Link mode is called 20-bit AC-Link mode and is
selected by setting COFSM<1:0> = 11.
18.6.1
16-BIT AC-LINK MODE
In the 16-bit AC-Link mode, data word lengths are

restricted to 16 bits. Note that this restriction only
affects the 20-bit data time slots of the AC-Link protocol. For received time slots, the incoming data is simply
truncated to 16 bits. For outgoing time slots, the 4 LS
bits of the data word are set to 0 by the module. This
truncation of the time slots limits the A/D and DAC data
to 16 bits but permits proper data alignment in the
TXBUF and RXBUF registers. Each RXBUF and
TXBUF register will contain one data time slot value.
18.6.2
20-BIT AC-LINK MODE
The 20-bit AC-Link mode allows all bits in the data time
slots to be transmitted and received but does not maintain data alignment in the TXBUF and RXBUF
registers.
The 20-bit mode treats each 256-bit AC-Link frame as

sixteen, 16-bit time slots. In the 20-bit AC-Link mode,
the module operates as if COFSG<3:0> = 1111 and
WS<3:0> = 1111. The data alignment for 20-bit data
slots is ignored. For example, an entire AC-Link data
frame can be transmitted and received in a packed
fashion by setting all bits in the TSCON and RSCON
SFRs. Since the total available buffer length is 64 bits,
it would take 4 consecutive interrupts to transfer the
AC-Link frame. The application software must keep
track of the current AC-Link frame segment.
18.7
I2S Mode Operation
The DCI module is configured for I2S mode by writing

a value of 01 to the COFSM<1:0> control bits in the
DCICON1 SFR. When operating in the I2S mode, the
DCI module will generate frame synchronization signals with a 50% duty cycle. Each edge of the frame
synchronization signal marks the boundary of a new
data word transfer.
The user must also select the frame length and data
word size using the COFSG and WS control bits in the
DCICON2 SFR.
18.7.1
I2S FRAME AND DATA WORD

LENGTH SELECTION
The WS and COFSG control bits are set to produce the

period for one half of an I2S data frame. That is, the
frame length is the total number of CSCK cycles
required for a left or a right data word transfer.
The BLEN bits must be set for the desired buffer length.
Setting BLEN<1:0> = 01 will produce a CPU interrupt,
once per I2S frame.
18.7.2
I2S DATA JUSTIFICATION
As per the I2S specification, a data word transfer will, by

default, begin one CSCK cycle after a transition of the
WS signal. A MS bit left justified option can be
selected using the DJST control bit in the DCICON2
SFR.
If DJST = 1, the I2S data transfers will be MS bit left justified. The MS bit of the data word will be presented on
the CSDO pin during the same CSCK cycle as the rising or falling edge of the COFS signal. The CSDO pin
is tri-stated after the data word has been sent.
The 20-bit AC-Link mode functions similar to the MultiChannel mode of the DCI module, except for the duty
cycle of the frame synchronization signal. The AC-Link
frame synchronization signal should remain high for 16
CSCK cycles and should be low for the following
240 cycles.
DS70116D-page 126
Preliminary
DCIEN
0240
0242
0244
DCICON1
DCICON2
DCICON3
DCISTAT
0250
0252
0254
0256
0258
025A
025C
025E
RXBUF0
RXBUF1
RXBUF2
RXBUF3
TXBUF0
TXBUF1
TXBUF2
TXBUF3
Legend:

RSE13
TSE13
RSE12
TSE12
Bit 12
RSE11
TSE11
SLOT3
BLEN1
DLOOP
Bit 11
RSE10
TSE10
SLOT2
BLEN0
CSCKD
Bit 10
Bit 7
RSE8
TSE8
SLOT0
CSDOM
Bit 6
RSE7
TSE7
DJST
Bit 5
RSE6
TSE6
Transmit Buffer #3 Data Register
Receive Buffer #3 Data Register
RSE5
TSE5
BCG<11:0>
COFSG<3:0>
COFSD UNFM
Bit 8
RSE9
TSE9
SLOT1
CSCKE
Bit 9
RSE14
TSE14
TSE15
RSE15
0248
024C
TSCON
0246
RSCON
DCISIDL
Bit 13
Bit 15
Addr.
SFR Name
Bit 14
DCI REGISTER MAP
TABLE 18-2:
TSE3
ROV
Bit 3
RSE4 RSE3
TSE4
Bit 4
RSE2
TSE2
RFUL
Bit 2
RSE1
TSE1
TUNF
WS<3:0>
COFSM1
Bit 1
Reset State
RSE0
TSE0
TMPTY
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
COFSM0 0000 0000 0000 0000
Bit 0
dsPIC30F5011/5013
Preliminary
DS70116D-page 127
dsPIC30F5011/5013
NOTES:
DS70116D-page 128
Preliminary
dsPIC30F5011/5013
19.0
12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The A/D module has six 16-bit registers:

Manual (DS70046).
The ADCON1, ADCON2 and ADCON3 registers

control the operation of the A/D module. The ADCHS
register selects the input channels to be converted. The
ADPCFG register configures the port pins as analog
inputs or as digital I/O. The ADCSSL register selects
inputs for scanning.
The 12-bit Analog-to-Digital converter (A/D) allows

conversion of an analog input signal to a 12-bit digital
number. This module is based on a Successive
Approximation Register (SAR) architecture and provides a maximum sampling rate of 100 ksps. The A/D
module has up to 16 analog inputs which are multiplexed into a sample and hold amplifier. The output of
the sample and hold is the input into the converter
which generates the result. The analog reference voltage is software selectable to either the device supply
voltage (AVDD/AVSS) or the voltage level on the
(VREF+/VREF-) pin. The A/D converter has a unique
feature of being able to operate while the device is in
Sleep mode with RC oscillator selection.
FIGURE 19-1:
A/D Control Register 1 (ADCON1)

A/D Input Select Register (ADCHS)
A/D Port Configuration Register (ADPCFG)
A/D Input Scan Selection Register (ADCSSL)
Note:
The SSRC<2:0>, ASAM, SMPI<3:0>,

BUFM and ALTS bits, as well as the
ADCON3 and ADCSSL registers, must
not be written to while ADON = 1. This
would lead to indeterminate results.
The block diagram of the 12-bit A/D module is shown in

Figure 19-1.
12-BIT A/D FUNCTIONAL BLOCK DIAGRAM

AVDD
AVSS
VREF+
VREF-
0001
AN2
0010
AN3
0011
AN4
0100
AN5
0101
AN6
0110
AN7
0111
AN9
AN10
AN11
AN12
AN13
AN14
AN15
1000
12-bit SAR
Conversion Logic
16-word, 12-bit
Dual Port
RAM
Sample/Sequence
Control
Sample
1001
1010
Input
Switches
1011
Input MUX
Control
1100
1101
1110
1111
VREFAN1
DAC
Bus Interface
AN1
AN8
Comparator
0000
Data
Format
AN0
S/H
CH0
Preliminary
DS70116D-page 129
dsPIC30F5011/5013
19.1
A/D Result Buffer
19.3
Selecting the Conversion

Sequence
The module contains a 16-word dual port read only

buffer, called ADCBUF0...ADCBUFF, to buffer the A/D
results. The RAM is 12 bits wide but the data obtained
is represented in one of four different 16-bit data formats. The contents of the sixteen A/D Conversion
Result Buffer registers, ADCBUF0 through ADCBUFF,
cannot be written by user software.
Several groups of control bits select the sequence in

which the A/D connects inputs to the sample/hold
channel, converts a channel, writes the buffer memory
and generates interrupts.
19.2
The SMPI bits select the number of acquisition/

conversion sequences that would be performed before
an interrupt occurs. This can vary from 1 sample per
interrupt to 16 samples per interrupt.
Conversion Operation
After the A/D module has been configured, the sample

acquisition is started by setting the SAMP bit. Various
sources, such as a programmable bit, timer time-outs
and external events, will terminate acquisition and start
a conversion. When the A/D conversion is complete,
the result is loaded into ADCBUF0...ADCBUFF, and
the DONE bit and the A/D interrupt flag ADIF are set after
the number of samples specified by the SMPI bit. The
ADC module can be configured for different interrupt
rates as described in Section 19.3.
The following steps should be followed for doing an
A/D conversion:
1.
2.
3.
4.
5.
6.
7.
Configure the A/D module:

Configure analog pins, voltage reference and
digital I/O
Select A/D input channels
Select A/D conversion clock
Select A/D conversion trigger
Turn on A/D module
Configure A/D interrupt (if required):
Clear ADIF bit
Select A/D interrupt priority
Start sampling.
Wait the required acquisition time.
Trigger acquisition end, start conversion:
Wait for A/D conversion to complete, by either:
Waiting for the A/D interrupt, or
Waiting for the DONE bit to get set.
Read A/D result buffer, clear ADIF if required.
The sequence is controlled by the sampling clocks.
The BUFM bit will split the 16-word results buffer into
two 8-word groups. Writing to the 8-word buffers will be
alternated on each interrupt event.
Use of the BUFM bit will depend on how much time is
available for the moving of the buffers after the
interrupt.
If the processor can quickly unload a full buffer within
the time it takes to acquire and convert one channel,
the BUFM bit can be 0 and up to 16 conversions (corresponding to the 16 input channels) may be done per
interrupt. The processor will have one acquisition and
conversion time to move the sixteen conversions.
If the processor cannot unload the buffer within the
acquisition and conversion time, the BUFM bit should be
1. For example, if SMPI<3:0> (ADCON2<5:2>) = 0111,
then eight conversions will be loaded into 1/2 of the
buffer, following which an interrupt occurs. The next
eight conversions will be loaded into the other 1/2 of the
buffer. The processor will have the entire time between
interrupts to move the eight conversions.
The ALTS bit can be used to alternate the inputs
selected during the sampling sequence. The input
multiplexer has two sets of sample inputs: MUX A and
MUX B. If the ALTS bit is 0, only the MUX A inputs are
selected for sampling. If the ALTS bit is 1 and
SMPI<3:0> = 0000 on the first sample/convert
sequence, the MUX A inputs are selected and on the
next acquire/convert sequence, the MUX B inputs are
selected.
The CSCNA bit (ADCON2<10>) will allow the multiplexer input to be alternately scanned across a
selected number of analog inputs for the MUX A group.
The inputs are selected by the ADCSSL register. If a
particular bit in the ADCSSL register is 1, the corresponding input is selected. The inputs are always
scanned from lower to higher numbered inputs, starting
after each interrupt. If the number of inputs selected is
greater than the number of samples taken per interrupt,
the higher numbered inputs are unused.
DS70116D-page 130
Preliminary
dsPIC30F5011/5013
19.4
EXAMPLE 19-1:
Programming the Start of

Conversion Trigger
The conversion trigger will terminate acquisition and

start the requested conversions.
Minimum TAD = 667 nsec

TCY = 33 nsec (30 MIPS)
The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to 4 alternate
sources of conversion trigger.
TAD
1
TCY
667 nsec
=2
1
33 nsec
= 39.4
ADCS<5:0> = 2
When SSRC<2:0> = 000, the conversion trigger is

under software control. Clearing the SAMP bit will
cause the conversion trigger.
Therefore,
Set ADCS<5:0> = 40
When SSRC<2:0> = 111 (Auto-Start mode), the conversion trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least 1 clock cycle.
TCY
(ADCS<5:0> + 1)
2
33 nsec
=
(40 + 1)
2
Actual TAD =
Other trigger sources can come from timer modules or

external interrupts.
19.5
Aborting a Conversion
If the clearing of the ADON bit coincides with an autostart, the clearing has a higher priority and a new
conversion will not start.
19.6
Selecting the A/D Conversion

Clock
The A/D conversion requires 15 TAD. The source of the

A/D conversion clock is software selected, using a
six-bit counter. There are 64 possible options for TAD.
EQUATION 19-1:
= 677 nsec
19.7
Clearing the ADON bit during a conversion will abort

the current conversion and stop the sampling sequencing until the next sampling trigger. The ADCBUF will not
be updated with the partially completed A/D conversion
sample. That is, the ADCBUF will continue to contain
the value of the last completed conversion (or the last
value written to the ADCBUF register).
A/D CONVERSION CLOCK
TAD = TCY * (0.5*(ADCS<5:0> + 1))
A/D CONVERSION CLOCK

CALCULATION
A/D Acquisition Requirements
The analog input model of the 12-bit A/D converter

is shown in Figure 19-2. The total sampling time for the
A/D is a function of the internal amplifier settling time
and the holding capacitor charge time.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the voltage level on the analog input
pin. The source impedance (RS), the interconnect
impedance (RIC), and the internal sampling switch
(RSS) impedance combine to directly affect the time
required to charge the capacitor CHOLD. The combined
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the A/D converter, the maximum recommended source impedance, RS, is 2.5 k. After the analog input channel is
selected (changed), this sampling function must be
completed prior to starting the conversion. The internal
holding capacitor will be in a discharged state prior to
each sample operation.
The internal RC oscillator is selected by setting the

ADRC bit.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 667 nsec (for VDD = 5V). Refer to the Electrical
Specifications section for minimum TAD under other
operating conditions.
Example 19-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
Preliminary
DS70116D-page 131
dsPIC30F5011/5013
FIGURE 19-2:
12-BIT A/D CONVERTER ANALOG INPUT MODEL

VDD
Rs
VA
ANx
CPIN
RIC 250
VT = 0.6V
Sampling
Switch
RSS 3 k
RSS
VT = 0.6V
I leakage
500 nA
CHOLD
= DAC capacitance
= 18 pF
VSS
Legend: CPIN
= input capacitance
VT
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
RSS
= sampling switch resistance
CHOLD
= sample/hold capacitance (from DAC)
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs 2.5 k.
19.8
Module Power-down Modes
The module has 2 internal Power modes.

When the ADON bit is 1, the module is in Active mode;
it is fully powered and functional.
When ADON is 0, the module is in Off mode. The digital and analog portions of the circuit are disabled for
maximum current savings.
In order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize.
19.9
19.9.1
A/D Operation During CPU Sleep

and Idle Modes
A/D OPERATION DURING CPU
SLEEP MODE

to the module are shutdown and stay at logic 0.
If Sleep occurs in the middle of a conversion, the conversion is aborted. The converter will not continue with
a partially completed conversion on exit from Sleep
mode.
Register contents are not affected by the device
entering or leaving Sleep mode.
The A/D module can operate during Sleep mode if the
A/D clock source is set to RC (ADRC = 1). When the RC
clock source is selected, the A/D module waits one
instruction cycle before starting the conversion. This
allows the SLEEP instruction to be executed which eliminates all digital switching noise from the conversion.
When the conversion is complete, the CONV bit will be
cleared and the result loaded into the ADCBUF register.
DS70116D-page 132
If the A/D interrupt is enabled, the device will wake-up

from Sleep. If the A/D interrupt is not enabled, the A/
D module will then be turned off, although the ADON bit
will remain set.
19.9.2
A/D OPERATION DURING CPU IDLE

MODE
The ADSIDL bit selects if the module will stop on Idle or

continue on Idle. If ADSIDL = 0, the module will continue operation on assertion of Idle mode. If ADSIDL =
1, the module will stop on Idle.
19.10 Effects of a Reset

A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off, and any
conversion and sampling sequence is aborted. The values that are in the ADCBUF registers are not modified.
The A/D Result register will contain unknown data after
a Power-on Reset.
19.11 Output Formats

The A/D result is 12 bits wide. The data buffer RAM is
also 12 bits wide. The 12-bit data can be read in one of
four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
Preliminary
dsPIC30F5011/5013
FIGURE 19-3:
A/D OUTPUT DATA FORMATS
RAM Contents:
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Fractional
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Signed Integer
Integer
d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
19.12 Configuring Analog Port Pins
19.13 Connection Considerations
The use of the ADPCFG and TRIS registers control the

operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be
converted.
The analog inputs have diodes to VDD and VSS as ESD

protection. This requires that the analog input be
between VDD and VSS. If the input voltage exceeds this
range by greater than 0.3V (either direction), one of the
diodes becomes forward biased and it may damage the
device if the input current specification is exceeded.
The A/D operation is independent of the state of the

CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits.
An external RC filter is sometimes added for antialiasing of the input signal. The R component should be
selected to ensure that the sampling time requirements
are satisfied. Any external components connected (via
high impedance) to an analog input pin (capacitor,
zener diode, etc.) should have very little leakage
current at the pin.
When reading the Port register, all pins configured as

analog input channels will read as cleared.
Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a
digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
Preliminary
DS70116D-page 133
DS70116D-page 134
Preliminary
CSSL12
Bit 8
FORM<1:0>
Bit 9
CH0SB<3:0>
SAMC<4:0>
CSCNA
Bit 10
ADRC
BUFS
Bit 7
CSSL11
CSSL10 CSSL9
CSSL8
CSSL7
Bit 5
CSSL6
CSSL5
PCFG6 PCFG5
ADC Data Buffer 15
ADC Data Buffer 14
ADC Data Buffer 13
ADC Data Buffer 12
ADC Data Buffer 11
ADC Data Buffer 10
ADC Data Buffer 9
ADC Data Buffer 8
ADC Data Buffer 7
ADC Data Buffer 6
ADC Data Buffer 5
ADC Data Buffer 4
ADC Data Buffer 3
ADC Data Buffer 2
ADC Data Buffer 1
ADC Data Buffer 0
Bit 6
SSRC<2:0>
PCFG11 PCFG10 PCFG9 PCFG8 PCFG7
CH0NB
Bit 11
Bit 12
CSSL15 CSSL14 CSSL13
Legend:
ADSIDL
Bit 13
PCFG15 PCFG14 PCFG13 PCFG12
02A8
02AA
ADCSSL
02A6
ADCHS
VCFG<2:0>
ADPCFG
02A2
02A4
ADCON2
ADCON3
02A0
ADCON1
029E
ADCBUFF
ADON
ADCBUFE 029C
ADCBUFB
0294
ADCBUFA
ADCBUFD 029A
0292
ADCBUF9
0290
ADCBUF8
028E
ADCBUF7
ADCBUFC 0298
028C
ADCBUF6
028A
ADCBUF5
0288
ADCBUF4
0296
0286
ADCBUF3
0284
ADCBUF2
Bit 14
Bit 15
A/D CONVERTER REGISTER MAP
0280
0282
ADCBUF0
ADCBUF1
Addr.
SFR
Name
TABLE 19-1:
Bit 3
CSSL4
PCFG4
CH0NA
ASAM
Bit 2
BUFM
SAMP
Bit 1
CSSL3
CSSL2
CSSL1
PCFG3 PCFG2 PCFG1
CH0SA<3:0>
ADCS<5:0>
SMPI<3:0>
Bit 4
CSSL0
PCFG0
ALTS
DONE
Bit 0
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
0000 uuuu uuuu uuuu
Reset State
dsPIC30F5011/5013
dsPIC30F5011/5013
20.0
SYSTEM INTEGRATION
20.1

There are several features intended to maximize system reliability, minimize cost through elimination of
external components, provide Power Saving Operating
modes and offer code protection:
Oscillator Selection
Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Programmable Brown-out Reset (BOR)
Watchdog Timer (WDT)
Power Saving Modes (Sleep and Idle)
Code Protection
Unit ID Locations
Oscillator System Overview
The dsPIC30F oscillator system has the following

modules and features:
Various external and internal oscillator options as
clock sources
An on-chip PLL to boost internal operating
frequency
A clock switching mechanism between various
clock sources
Programmable clock postscaler for system power
savings
A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
Clock Control register (OSCCON)
Configuration bits for main oscillator selection
Configuration bits determine the clock source upon
Power-on Reset (POR) and Brown-out Reset (BOR).
Thereafter, the clock source can be changed between
permissible clock sources. The OSCCON register controls the clock switching and reflects system clock
related status bits.
Table 20-1 provides a summary of the dsPIC30F Oscillator Operating modes. A simplified diagram of the
oscillator system is shown in Figure 20-1.
dsPIC30F devices have a Watchdog Timer which is

permanently enabled via the configuration bits or can
be software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer
necessary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
Reset until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT) which provides a delay on
power-up only, designed to keep the part in Reset while
the power supply stabilizes. With these two timers
on-chip, most applications need no external Reset
circuitry.
Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit a wide variety of
applications. In the Idle mode, the clock sources are
still active but the CPU is shut-off. The RC oscillator
option saves system cost while the LP crystal option
saves power.
Preliminary
DS70116D-page 135
dsPIC30F5011/5013
TABLE 20-1:
OSCILLATOR OPERATING MODES
Oscillator Mode
Description
XTL
200 kHz-4 MHz crystal on OSC1:OSC2.
XT
4 MHz-10 MHz crystal on OSC1:OSC2.
XT w/ PLL 4x
4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled.
XT w/ PLL 8x
4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled.
XT w/ PLL 16x
4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled(1).
LP
32 kHz crystal on SOSCO:SOSCI(2).
HS
10 MHz-25 MHz crystal.
EC
External clock input (0-40 MHz).
ECIO
External clock input (0-40 MHz), OSC2 pin is I/O.
EC w/ PLL 4x
External clock input (0-40 MHz), OSC2 pin is I/O, 4x PLL enabled(1).
EC w/ PLL 8x
EC w/ PLL 16x
ERC
External RC oscillator, OSC2 pin is FOSC/4 output(3).
ERCIO
External RC oscillator, OSC2 pin is I/O(3).
FRC
8 MHz internal RC oscillator.
FRC w/ PLL 4x
8 MHz Internal RC oscillator, 4x PLL enabled.
FRC w/ PLL 8x
8 MHz Internal RC oscillator, 8x PLL enabled.
FRC w/ PLL 16x
7.5 MHz Internal RC oscillator, 16x PLL enabled.
LPRC
512 kHz internal RC oscillator.
Note 1:
2:
3:
dsPIC30F maximum operating frequency of 120 MHz must be met.

LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1.
Requires external R and C. Frequency operation up to 4 MHz.
DS70116D-page 136
Preliminary
dsPIC30F5011/5013
FIGURE 20-1:
OSCILLATOR SYSTEM BLOCK DIAGRAM

Oscillator Configuration bits
PWRSAV Instruction
Wake-up Request
OSC1
OSC2
FPLL
Primary
Oscillator
PLL
PLL
x4, x8, x16
Lock
COSC<1:0>
Primary Osc
NOSC<1:0>
Primary
Oscillator
OSWEN
Stability Detector
POR Done
Oscillator
Start-up
Timer
Clock
Secondary Osc
Switching
and Control
Block
SOSCO
SOSCI
32 kHz LP
Oscillator
Secondary
Oscillator
Stability Detector
Programmable
Clock Divider System
Clock
2
POST<1:0>
Internal Fast RC
Oscillator (FRC)
Internal Low
Power RC
Oscillator (LPRC)
LPRC
FCKSM<1:0>
2
Fail-Safe Clock
Monitor (FSCM)
CF
Oscillator Trap
To Timer1
Preliminary
DS70116D-page 137
dsPIC30F5011/5013
20.2
20.2.1
Oscillator Configurations
INITIAL CLOCK SOURCE
SELECTION
While coming out of Power-on Reset or Brown-out

Reset, the device selects its clock source based on:
a)
b)
FOS<1:0> configuration bits that select one of

four oscillator groups,
and FPR<3:0> configuration bits that select one
of 13 oscillator choices within the primary group.
The selection is as shown in Table 20-2.
TABLE 20-2:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator
Source
FOS1
FOS0
FPR3
FPR2
FPR1
FPR0
OSC2
Function
1
1
1
0
1
1
CLKO
EC
Primary
1
1
1
1
0
0
I/O
ECIO
Primary
EC w/ PLL 4x
Primary
1
1
1
1
0
1
I/O
EC w/ PLL 8x
Primary
1
1
1
1
1
0
I/O
1
1
1
1
1
1
I/O
EC w/ PLL 16x
Primary
ERC
Primary
1
1
1
0
0
1
CLKO
ERCIO
Primary
1
1
1
0
0
0
I/O
1
1
0
1
0
0
OSC2
XT
Primary
XT w/ PLL 4x
Primary
1
1
0
1
0
1
OSC2
XT w/ PLL 8x
Primary
1
1
0
1
1
0
OSC2
1
1
0
1
1
1
OSC2
XT w/ PLL 16x
Primary
XTL
Primary
1
1
0
0
0
0
OSC2
FRC w/ PLL 4x
Internal FRC
1
1
0
0
0
1
I/O
FRC w/ PLL 8x
Internal FRC
1
1
1
0
1
0
I/O
1
1
0
0
1
1
I/O
FRC w/ PLL 16x
Internal FRC
HS
Primary
1
1
0
0
1
0
OSC2
LP
Secondary
0
0
(Notes 1, 2)
FRC
Internal FRC
0
1
x
x
x
x
(Notes 1, 2)
LPRC
Internal LPRC
1
0
(Notes 1, 2)
Note 1: OSC2 pin function is determined by the Primary Oscillator mode selection (FPR<3:0>).
2: OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock source is
selected at all times.
20.2.2
20.2.3
OSCILLATOR START-UP TIMER

(OST)
Enabling the LP oscillator is controlled with two elements:
In order to ensure that a crystal oscillator (or ceramic

resonator) has started and stabilized, an Oscillator
Start-up Timer is included. It is a simple 10-bit counter
that counts 1024 TOSC cycles before releasing the
oscillator clock to the rest of the system. The time-out
period is designated as TOST. The TOST time is involved
every time the oscillator has to restart (i.e., on POR,
BOR and wake-up from Sleep). The Oscillator Start-up
Timer is applied to the LP oscillator, XT, XTL, and HS
modes (upon wake-up from Sleep, POR and BOR) for
the primary oscillator.
DS70116D-page 138
LP OSCILLATOR CONTROL
1.
2.
The current oscillator group bits COSC<1:0>.

The LPOSCEN bit (OSCON register).
The LP oscillator is on (even during Sleep mode) if

LPOSCEN = 1. The LP oscillator is the device clock if:
COSC<1:0> = 00 (LP selected as main oscillator)
and
LPOSCEN = 1
Keeping the LP oscillator on at all times allows for a fast
switch to the 32 kHz system clock for lower power operation. Returning to the faster main oscillator will still
require a start-up time
Preliminary
dsPIC30F5011/5013
20.2.4
TABLE 20-4:
PHASE LOCKED LOOP (PLL)
The PLL multiplies the clock which is generated by the

primary oscillator or Fast RC oscillator. The PLL is
selectable to have either gains of x4, x8, and x16. Input
and output frequency ranges are summarized in
Table 20-3.
TABLE 20-3:
TUN<3:0>
Bits
0111
0110
0101
0100
0011
0010
0001
0000
PLL FREQUENCY RANGE
FIN
PLL
Multiplier
FOUT
4 MHz-10 MHz
x4
16 MHz-40 MHz
4 MHz-10 MHz
x8
32 MHz-80 MHz
4 MHz-7.5 MHz
x16
64 MHz-120 MHz
1111
1110
1101
1100
1011
1010
1001
1000
The PLL features a lock output which is asserted when

the PLL enters a phase locked state. Should the loop
fall out of lock (e.g., due to noise), the lock signal will be
rescinded. The state of this signal is reflected in the
read only LOCK bit in the OSCCON register.
20.2.5
FAST RC OSCILLATOR (FRC)
The FRC oscillator is a fast (8 MHz nominal) internal

RC oscillator. This oscillator is intended to provide
reasonable device operating speeds without the use of
an external crystal, ceramic resonator, or RC network.
The FRC oscillator can be used with the PLL to obtain
higher clock frequencies.
The dsPIC30F operates from the FRC oscillator whenever the current oscillator selection control bits in the
OSCCON register (OSCCON<13:12>) are set to 01.
The four bit field specified by TUN<3:0> (OSCON
<15:14> and OSCON<11:10>) allows the user to tune
the internal fast RC oscillator (nominal 8.0 MHz). The
user can tune the FRC oscillator within a range of
+10.5% (840 kHz) and -12% (960 kHz) in steps of
1.50% around the factory-calibrated setting, see
Table 20-4.
If OSCCON<13:12> are set to 11 and FPR<3:0> are
set to 0001, 1010 or 0011, then a PLL multiplier of 4,
8 or 16 (respectively) is applied.
Note:
When a 16x PLL is used, the FRC frequency must not be tuned to a frequency
greater than 7.5 MHz.
20.2.6
FRC TUNING
FRC Frequency
+ 10.5%
+ 9.0%
+ 7.5%
+ 6.0%
+ 4.5%
+ 3.0%
+ 1.5%
Center Frequency (oscillator is
running at calibrated frequency)
- 1.5%
- 3.0%
- 4.5%
- 6.0%
- 7.5%
- 9.0%
- 10.5%
- 12.0%
LOW POWER RC OSCILLATOR

(LPRC)
The LPRC oscillator is a component of the Watchdog

Timer (WDT) and oscillates at a nominal frequency of
512 kHz. The LPRC oscillator is the clock source for
the Power-up Timer (PWRT) circuit, WDT, and clock
monitor circuits. It may also be used to provide a low
frequency clock source option for applications where
power consumption is critical and timing accuracy is
not required
The LPRC oscillator is always enabled at a Power-on
Reset because it is the clock source for the PWRT.
After the PWRT expires, the LPRC oscillator will
remain on if one of the following is true:
The Fail-Safe Clock Monitor is enabled
The WDT is enabled
The LPRC oscillator is selected as the system
clock via the COSC<1:0> control bits in the
OSCCON register
If one of the above conditions is not true, the LPRC will
shut-off after the PWRT expires.
Note 1: OSC2 pin function is determined by the
Primary Oscillator mode selection
(FPR<3:0>).
2: OSC1 pin cannot be used as an I/O pin
even if the secondary oscillator or an
internal clock source is selected at all
times.
Preliminary
DS70116D-page 139
dsPIC30F5011/5013
20.2.7
FAIL-SAFE CLOCK MONITOR
The Fail-Safe Clock Monitor (FSCM) allows the device

to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by appropriately
programming the FCKSM configuration bits (clock
switch and monitor selection bits) in the FOSC Device
Configuration register. If the FSCM function is enabled,
the LPRC internal oscillator will run at all times (except
during Sleep mode) and will not be subject to control by
the SWDTEN bit.
In the event of an oscillator failure, the FSCM will generate a clock failure trap event and will switch the system clock over to the FRC oscillator. The user will then
have the option to either attempt to restart the oscillator
or execute a controlled shutdown. The user may decide
to treat the trap as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector. In this
event, the CF (Clock Fail) status bit (OSCCON<3>) is
also set whenever a clock failure is recognized.
In the event of a clock failure, the WDT is unaffected
and continues to run on the LPRC clock.
If the oscillator has a very slow start-up time coming out
of POR, BOR or Sleep, it is possible that the PWRT
timer will expire before the oscillator has started. In
such cases, the FSCM will be activated and the FSCM
will initiate a clock failure trap, and the COSC<1:0> bits
are loaded with FRC oscillator selection. This will effectively shut-off the original oscillator that was trying to
start.
The OSCCON register holds the control and status bits

related to clock switching.
COSC<1:0>: Read only status bits always reflect
the current oscillator group in effect.
NOSC<1:0>: Control bits which are written to
indicate the new oscillator group of choice.
- On POR and BOR, COSC<1:0> and
NOSC<1:0> are both loaded with the
configuration bit values FOS<1:0>.
LOCK: The LOCK status bit indicates a PLL lock.
CF: Read only status bit indicating if a clock fail
detect has occurred.
OSWEN: Control bit changes from a 0 to a 1
when a clock transition sequence is initiated.
Clearing the OSWEN control bit will abort a clock
transition in progress (used for hang-up
situations).
If configuration bits FCKSM<1:0> = 1x, then the clock
switching and Fail-Safe Clock monitoring functions are
disabled. This is the default configuration bit setting.
If clock switching is disabled, then the FOS<1:0> and
FPR<3:0> bits directly control the oscillator selection
and the COSC<1:0> bits do not control the clock selection. However, these bits will reflect the clock source
selection.
Note:
The user may detect this situation and restart the

oscillator in the clock fail trap ISR.
Upon a clock failure detection, the FSCM module will
initiate a clock switch to the FRC oscillator as follows:
1.
2.
3.
The COSC bits (OSCCON<13:12>) are loaded

with the FRC oscillator selection value.
CF bit is set (OSCCON<3>).
OSWEN control bit (OSCCON<0>) is cleared.
For the purpose of clock switching, the clock sources

are sectioned into four groups:
1.
2.
3.
4.
Primary
Secondary
Internal FRC
Internal LPRC
20.2.8
The application should not attempt to

switch to a clock of frequency lower than
100 KHz when the fail-safe clock monitor is
enabled. If such clock switching is
performed, the device may generate an
oscillator fail trap and switch to the Fast RC
oscillator.
PROTECTION AGAINST
ACCIDENTAL WRITES TO OSCCON
A write to the OSCCON register is intentionally made

difficult because it controls clock switching and clock
scaling.
To write to the OSCCON low byte, the following code
sequence must be executed without any other
instructions in between:
Byte Write 0x46 to OSCCON low
Byte Write 0x57 to OSCCON low
The user can switch between these functional groups

but cannot switch between options within a group. If the
primary group is selected, then the choice within the
group is always determined by the FPR<3:0>
configuration bits.
Byte write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.
To write to the OSCCON high byte, the following
instructions must be executed without any other
instructions in between:
Byte Write 0x78 to OSCCON high
Byte Write 0x9A to OSCCON high
Byte write is allowed for one instruction cycle. Write the
desired value or use bit manipulation instruction.
DS70116D-page 140
Preliminary
dsPIC30F5011/5013
20.3
Reset
The dsPIC30F differentiates between various kinds of

Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Power-on Reset (POR)

MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset caused by trap lockup (TRAPR)
Reset caused by illegal opcode or by using an
uninitialized W register as an address pointer
(IOPUWR)
FIGURE 20-2:
Different registers are affected in different ways by various Reset conditions. Most registers are not affected
by a WDT wake-up since this is viewed as the resumption of normal operation. Status bits from the RCON
register are set or cleared differently in different Reset
situations, as indicated in Table 20-5. These bits are
used in software to determine the nature of the Reset.
A block diagram of the On-Chip Reset Circuit is shown
in Figure 20-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
Digital
Glitch Filter
MCLR
Sleep or Idle
WDT
Module
VDD Rise
Detect
POR
VDD
Brown-out
Reset
BOR
BOREN
R
SYSRST
Trap Conflict
Illegal Opcode/
Uninitialized W Register
20.3.1
POR: POWER-ON RESET
A power-on event will generate an internal POR pulse

when a VDD rise is detected. The Reset pulse will occur
at the POR circuit threshold voltage (VPOR) which is
nominally 1.85V. The device supply voltage characteristics must meet specified starting voltage and rise rate
requirements. The POR pulse will reset a POR timer
and place the device in the Reset state. The POR also
selects the device clock source identified by the oscillator configuration fuses.
The POR circuit inserts a small delay, TPOR, which is

nominally 10 s and ensures that the device bias circuits are stable. Furthermore, a user selected powerup time-out (TPWRT) is applied. The TPWRT parameter
is based on device configuration bits and can be 0 ms
(no delay), 4 ms, 16 ms, or 64 ms. The total delay is at
device power-up, TPOR + TPWRT. When these delays
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock and the PC will jump to the
Reset vector.
The timing for the SYSRST signal is shown in
Figure 20-3 through Figure 20-5.
Preliminary
DS70116D-page 141
dsPIC30F5011/5013
FIGURE 20-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 20-4:
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 20-5:
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
DS70116D-page 142
Preliminary
dsPIC30F5011/5013
20.3.1.1
POR with Long Crystal Start-up Time

(with FSCM Enabled)
The oscillator start-up circuitry is not linked to the POR

circuitry. Some crystal circuits (especially low frequency crystals) will have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after the POR timer and the PWRT have
expired:
The oscillator circuit has not begun to oscillate.
The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).
The PLL has not achieved a LOCK (if PLL is
used).
If the FSCM is enabled and one of the above conditions
is true, then a clock failure trap will occur. The device
will automatically switch to the FRC oscillator and the
user can switch to the desired crystal oscillator in the
trap ISR.
20.3.1.2
Operating without FSCM and PWRT
A BOR will generate a Reset pulse which will reset the

device. The BOR will select the clock source based on
the device configuration bit values (FOS<1:0> and
FPR<3:0>). Furthermore, if an Oscillator mode is
selected, the BOR will activate the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
until the LOCK bit (OSCCON<5>) is 1.
Concurrently, the POR time-out (TPOR) and the PWRT
time-out (TPWRT) will be applied before the internal Reset
is released. If TPWRT = 0 and a crystal oscillator is being
used, then a nominal delay of TFSCM = 100 s is applied.
The total delay in this case is (TPOR + TFSCM).
The BOR status bit (RCON<1>) will be set to indicate
that a BOR has occurred. The BOR circuit, if enabled,
will continue to operate while in Sleep or Idle modes
and will reset the device should VDD fall below the BOR
threshold voltage.
FIGURE 20-6:
If the FSCM is disabled and the Power-up Timer

(PWRT) is also disabled, then the device will exit rapidly from Reset on power-up. If the clock source is
FRC, LPRC, EXTRC or EC, it will be active
immediately.
If the FSCM is disabled and the system clock has not
started, the device will be in a frozen state at the Reset
vector until the system clock starts. From the users
perspective, the device will appear to be in Reset until
a system clock is available.
20.3.2
VDD
D
Note 1:
The BOR (Brown-out Reset) module is based on an

internal voltage reference circuit. The main purpose of
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (i.e.,
missing portions of the AC cycle waveform due to bad
power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned
on).
2:
3:
Note:
2.0V
2.7V
4.2V
4.5V
Note:
R
R1
BOR: PROGRAMMABLE
BROWN-OUT RESET
The BOR module allows selection of one of the

following voltage trip points:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
MCLR
dsPIC30F
External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
R should be suitably chosen so as to make
sure that the voltage drop across R does not
violate the devices electrical specifications.
R1 should be suitably chosen so as to limit
any current flowing into MCLR from external
capacitor C, in the event of MCLR/VPP pin
breakdown due to Electrostatic Discharge
(ESD), or Electrical Overstress (EOS).
Dedicated supervisory devices, such as

the MCP1XX and MCP8XX, may also be
used as an external Power-on Reset
circuit.
The BOR voltage trip points indicated here

are nominal values provided for design
guidance only. Refer to the Electrical
Specifications in the specific device data
sheet for BOR voltage limit specifications.
Preliminary
DS70116D-page 143
dsPIC30F5011/5013
Table 20-5 shows the Reset conditions for the RCON
register. Since the control bits within the RCON register
are R/W, the information in the table implies that all the
bits are negated prior to the action specified in the
condition column.
TABLE 20-5:
INITIALIZATION CONDITION FOR RCON REGISTER: CASE 1
Condition
Program
Counter
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Power-on Reset
0x000000
Brown-out Reset
0x000000
MCLR Reset during normal

operation
0x000000
Software Reset during

normal operation
0x000000
0x000000
MCLR Reset during Idle
0x000000
WDT Time-out Reset
0x000000
PC + 2
WDT Wake-up
Interrupt Wake-up from

Sleep
PC + 2
(1)
Clock Failure Trap
0x000004
Trap Reset
0x000000
Illegal Operation Trap
0x000000
Legend:
Note 1:
u = unchanged, x = unknown, - = unimplemented bit, read as 0

When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
DS70116D-page 144
Preliminary
dsPIC30F5011/5013
Table 20-6 shows a second example of the bit
conditions for the RCON register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 20-6:
INITIALIZATION CONDITION FOR RCON REGISTER: CASE 2
Condition
Program
Counter
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Power-on Reset
0x000000
Brown-out Reset
0x000000
MCLR Reset during normal

operation
0x000000
Software Reset during

normal operation
0x000000
0x000000
MCLR Reset during Idle
0x000000
WDT Time-out Reset
0x000000
PC + 2
WDT Wake-up
Interrupt Wake-up from

Sleep
(1)
PC + 2
Clock Failure Trap
0x000004
Trap Reset
0x000000
Illegal Operation Reset
0x000000
Legend:
Note 1:
u = unchanged, x = unknown, - = unimplemented bit, read as 0

When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
Preliminary
DS70116D-page 145
dsPIC30F5011/5013
20.4
20.4.1
Watchdog Timer (WDT)
20.6
WATCHDOG TIMER OPERATION
The primary function of the Watchdog Timer (WDT) is

to reset the processor in the event of a software malfunction. The WDT is a free-running timer which runs
off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer will continue to operate even if the main processor clock (e.g., the crystal
oscillator) fails.
20.4.2
There are two power saving states that can be entered

through the execution of a special instruction, PWRSAV;
these are Sleep and Idle.
The format of the PWRSAV instruction is as follows:
PWRSAV <parameter>, where parameter defines
Idle or Sleep mode.
20.6.1
ENABLING AND DISABLING

THE WDT
Setting FWDTEN = 1 enables the Watchdog Timer. The

enabling is done when programming the device. By
default, after chip erase, FWDTEN bit = 1. Any device
programmer capable of programming dsPIC30F
devices allows programming of this and other
configuration bits.
If enabled, the WDT will increment until it overflows or
times out. A WDT time-out will force a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a CLRWDT
instruction.
If a WDT times out during Sleep, the device will wakeup. The WDTO bit in the RCON register will be cleared
to indicate a wake-up resulting from a WDT time-out.
Setting FWDTEN = 0 allows user software to enable/
disable the Watchdog Timer via the SWDTEN
(RCON<5>) control bit.
The Fail-Safe Clock Monitor is not functional during

Sleep since there is no clock to monitor. However,
LPRC clock remains active if WDT is operational during
Sleep.
The brown-out protection circuit and the Low Voltage
Detect circuit, if enabled, will remain functional during
Sleep.
The processor wakes up from Sleep if at least one of
the following conditions has occurred:
any interrupt that is individually enabled and
meets the required priority level
any Reset (POR, BOR and MCLR)
WDT time-out
On waking up from Sleep mode, the processor will
restart the same clock that was active prior to entry into
Sleep mode. When clock switching is enabled, bits
COSC<1:0> will determine the oscillator source that
will be used on wake-up. If clock switch is disabled,
then there is only one system clock.
Note:
Low Voltage Detect
The Low Voltage Detect (LVD) module is used to detect

when the VDD of the device drops below a threshold
value, VLVD, which is determined by the LVDL<3:0>
bits (RCON<11:8>) and is thus user programmable.
The internal voltage reference circuitry requires a nominal amount of time to stabilize, and the BGST bit
(RCON<13>) indicates when the voltage reference has
stabilized.
In some devices, the LVD threshold voltage may be
applied externally on the LVDIN pin.
The LVD module is enabled by setting the LVDEN bit
(RCON<12>).
DS70116D-page 146
SLEEP MODE
In Sleep mode, the clock to the CPU and peripherals is

shutdown. If an on-chip oscillator is being used, it is
shutdown.
The Watchdog Timer can be Enabled or Disabled

only through a configuration bit (FWDTEN) in the
Configuration register, FWDT.
20.5
Power Saving Modes
If a POR or BOR occurred, the selection of

the oscillator is based on the FOS<1:0>
and FPR<3:0> configuration bits.
If the clock source is an oscillator, the clock to the

device will be held off until OST times out (indicating a
stable oscillator). If PLL is used, the system clock is
held off until LOCK = 1 (indicating that the PLL is
stable). In either case, TPOR, TLOCK and TPWRT delays
are applied.
If EC, FRC, LPRC or EXTRC oscillators are used, then
a delay of TPOR (~ 10 s) is applied. This is the smallest
delay possible on wake-up from Sleep.
Moreover, if LP oscillator was active during Sleep and
LP is the oscillator used on wake-up, then the start-up
delay will be equal to TPOR. PWRT delay and OST
timer delay are not applied. In order to have -the smallest possible start-up delay when waking up from Sleep,
one of these faster wake-up options should be selected
before entering Sleep.
Preliminary
dsPIC30F5011/5013
Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level
will be able to wake-up the processor. The processor will
process the interrupt and branch to the ISR. The Sleep
status bit in the RCON register is set upon wake-up.
Note:
In spite of various delays applied (TPOR,

TLOCK and TPWRT), the crystal oscillator
(and PLL) may not be active at the end of
the time-out (e.g., for low frequency crystals). In such cases, if FSCM is enabled,
then the device will detect this as a clock
failure and process the clock failure trap, the
FRC oscillator will be enabled and the user
will have to re-enable the crystal oscillator. If
FSCM is not enabled, then the device will
simply suspend execution of code until the
clock is stable and will remain in Sleep until
the oscillator clock has started.
All Resets will wake-up the processor from Sleep

mode. Any Reset, other than POR, will set the Sleep
status bit. In a POR, the Sleep bit is cleared.
If the Watchdog Timer is enabled, then the processor
will wake-up from Sleep mode upon WDT time-out. The
Sleep and WDTO status bits are both set.
20.6.2
IDLE MODE
Any interrupt that is individually enabled (using IE bit)

and meets the prevailing priority level will be able to
wake-up the processor. The processor will process the
interrupt and branch to the ISR. The Idle status bit in
the RCON register is set upon wake-up.
Any Reset other than POR will set the Idle status bit.
On a POR, the Idle bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Idle mode upon WDT time-out. The Idle
and WDTO status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involved in wake-up from Idle.
20.7
The configuration bits in each device configuration register specify some of the Device modes and are
programmed by a device programmer, or by using the
In-Circuit Serial Programming (ICSP) feature of
the device. Each device configuration register is a
24-bit register, but only the lower 16 bits of each register are used to hold configuration data. There are four
device configuration registers available to the user:
FOSC (0xF80000): Oscillator Configuration
Register
FWDT (0xF80002): Watchdog Timer
Configuration Register
FBORPOR (0xF80004): BOR and POR
FGS (0xF8000A): General Code Segment
1.
2.
In Idle mode, the clock to the CPU is shutdown while

peripherals keep running. Unlike Sleep mode, the clock
source remains active.
Device Configuration Registers
3.
Several peripherals have a control bit in each module

that allows them to operate during Idle.
4.
LPRC Fail-Safe Clock remains active if clock failure

detect is enabled.
The placement of the configuration bits is automatically

handled when you select the device in your device programmer. The desired state of the configuration bits
may be specified in the source code (dependent on the
language tool used), or through the programming interface. After the device has been programmed, the application software may read the configuration bit values
through the table read instructions. For additional information, please refer to the Programming Specifications
of the device.
The processor wakes up from Idle if at least one of the

following conditions has occurred:
any interrupt that is individually enabled (IE bit is
1) and meets the required priority level
any Reset (POR, BOR, MCLR)
WDT time-out
Upon wake-up from Idle mode, the clock is re-applied
to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV
instruction.
Note:
Preliminary
If the code protection configuration fuse

bits (FGS<GCP> and FGS<GWRP>)
have been programmed, an erase of the
entire code-protected device is only
possible at voltages VDD 4.5V.
DS70116D-page 147
dsPIC30F5011/5013
20.8
Peripheral Module Disable (PMD)

Registers
The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a
peripheral is disabled via the appropriate PMD control
bit, the peripheral is in a minimum power consumption
state. The control and status registers associated with
the peripheral will also be disabled so writes to those
registers will have no effect and read values will be
invalid.
A peripheral module will only be enabled if both the
associated bit in the the PMD register is cleared and
the peripheral is supported by the specific dsPIC variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
Note:
If a PMD bit is set, the corresponding module is disabled after a delay of 1 instruction
cycle. Similarly, if a PMD bit is cleared, the
corresponding module is enabled after a
delay of 1 instruction cycle (assuming the
module control registers are already
configured to enable module operation).
20.9
When MPLAB ICD2 is selected as a Debugger, the InCircuit Debugging functionality is enabled. This function allows simple debugging functions when used with
MPLAB IDE. When the device has this feature enabled,
some of the resources are not available for general
use. These resources include the first 80 bytes of Data
RAM and two I/O pins.
One of four pairs of Debug I/O pins may be selected by
the user using configuration options in MPLAB IDE.
These pin pairs are named EMUD/EMUC, EMUD1/
EMUC1, EMUD2/EMUC2 and MUD3/EMUC3.
In each case, the selected EMUD pin is the Emulation/
Debug Data line, and the EMUC pin is the Emulation/
Debug Clock line. These pins will interface to the
MPLAB ICD 2 module available from Microchip. The
selected pair of Debug I/O pins is used by MPLAB
ICD 2 to send commands and receive responses, as
well as to send and receive data. To use the In-Circuit
Debugger function of the device, the design must
implement ICSP connections to MCLR, VDD, VSS,
PGC, PGD, and the selected EMUDx/EMUCx pin pair.
This gives rise to two possibilities:
1.
2.
DS70116D-page 148
In-Circuit Debugger
Preliminary
If EMUD/EMUC is selected as the Debug I/O pin

pair, then only a 5-pin interface is required, as
the EMUD and EMUC pin functions are multiplexed with the PGD and PGC pin functions in
all dsPIC30F devices.
If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/
EMUC3 is selected as the Debug I/O pin pair,
then a 7-pin interface is required, as the
EMUDx/EMUCx pin functions (x = 1, 2 or 3) are
not multiplexed with the PGD and PGC pin
functions.
1:
2:
T4MD
IC7MD
T3MD
IC6MD
T2MD
IC5MD
IC4MD
T1MD
TUN1
Bit 11
Bit 9
IC3MD
TUN0
IC2MD
MCLREN
F80004
F8000A
FGS
Bit 13
Bit 12
Bit 11
IC1MD
DCIMD
SWR
Bit 6
U2MD
Bit 10
Bit 8
OC6MD
U1MD
LOCK
SWDTEN
Bit 5
FOS<1:0>
Bit 9
OC8MD OC7MD
I2CMD
POST<1:0>
EXTR
Bit 7
FWDTEN
F80002
FWDT
Bit 14
FCKSM<1:0>
Bit 15
FBORPOR
Bits 23-16
Addr.
Bit 8
NOSC<1:0>
LVDL<3:0>
Bit 10
DEVICE CONFIGURATION REGISTER MAP
F80000
File Name
FOSC
T5MD
IC8MD
Reset state depends on type of Reset.

Reset state depends on configuration bits.
TABLE 20-8:
Note
0770
0772
PMD2
LVDEN
Bit 12
COSC<1:0>
PMD1
TUN2
0742
TUN3
TRAPR IOPUWR BGST
0740
RCON
OSCCON
Bit 13
Bit 15
Bit 14
SYSTEM INTEGRATION REGISTER MAP
Addr.
SFR
Name
TABLE 20-7:
CF
BOREN
Bit 7
OC5MD
C2MD
IDLE
Bit 2
Bit 6
C1MD
Bit 4
OC2MD
BORV<1:0>
POR
Bit 0
(Note 2)
(Note 1)
Reset State
Bit 3
Bit 1
Bit 0
GCP
GWRP
FPWRT<1:0>
FWPSB<3:0>
FPR<3:0>
Bit 2
OC1MD 0000 0000 0000 0000
ADCMD 0000 0000 0000 0000
LPOSCEN OSWEN
BOR
Bit 1
FWPSA<1:0>
Bit 5
OC4MD OC3MD
SPI2MD SPI1MD
SLEEP
Bit 3
WDTO
Bit 4
dsPIC30F5011/5013
Preliminary
DS70116D-page 149
dsPIC30F5011/5013
NOTES:
DS70116D-page 150
Preliminary
dsPIC30F5011/5013
21.0
INSTRUCTION SET SUMMARY

The dsPIC30F instruction set adds many

enhancements to the previous PICmicro instruction
sets, while maintaining an easy migration from
PICmicro instruction sets.
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Each single word instruction is a 24-bit word divided
into an 8-bit opcode which specifies the instruction
type, and one or more operands which further specify
the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into five basic categories:
Word or byte-oriented operations

Bit-oriented operations
Literal operations
DSP operations
Control operations
The W register (with or without an address

modifier) or file register (specified by the value of
Ws or f)
The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register Wb)
The literal instructions that involve data movement may
use some of the following operands:
A literal value to be loaded into a W register or file
register (specified by the value of k)
The W register or file register where the literal
value is to be loaded (specified by Wb or f)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
The first source operand which is a register Wb
without any address modifier
The second source operand which is a literal
value
The destination of the result (only if not the same
as the first source operand) which is typically a
register Wd with or without an address modifier
The MAC class of DSP instructions may use some of the
following operands:
Table 21-1 shows the general symbols used in

describing the instructions.
The dsPIC30F instruction set summary in Table 21-2
lists all the instructions, along with the status flags
affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
The first source operand which is typically a
register Wb without any address modifier
The second source operand which is typically a
register Ws with or without an address modifier
The destination of the result which is typically a
register Wd with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
The file register specified by the value f
The destination, which could either be the file
register f or the W0 register, which is denoted as
WREG
Most bit-oriented instructions (including simple rotate/

shift instructions) have two operands:
The accumulator (A or B) to be used (required

operand)
The W registers to be used as the two operands
The X and Y address space pre-fetch operations
The X and Y address space pre-fetch destinations
The accumulator write back destination
The other DSP instructions do not involve any
multiplication, and may include:
The accumulator to be used (required)
The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
The amount of shift specified by a W register Wn
or a literal value
The control instructions may use some of the following
operands:
A program memory address
The mode of the table read and table write
instructions
Preliminary
DS70116D-page 151
dsPIC30F5011/5013
All instructions are a single word, except for certain
double-word instructions, which were made doubleword instructions so that all the required information is
available in these 48 bits. In the second word, the
8 MSbs are 0s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
Most single word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table
reads and writes, and RETURN/RETFIE instructions,
TABLE 21-1:
which are single word instructions but take two or three

cycles. Certain instructions that involve skipping over
the subsequent instruction require either two or three
cycles if the skip is performed, depending on whether
the instruction being skipped is a single word or twoword instruction. Moreover, double-word moves
require two cycles. The double-word instructions
execute in two instruction cycles.
Note:
For more details on the instruction set,

refer to the Programmers Reference
Manual.
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
Means literal defined by text
(text)
Means content of text
[text]
Means the location addressed by text
{ }
Optional field or operation
<n:m>
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
Acc
One of two accumulators {A, B}
AWB
Accumulator write back destination address register {W13, [W13]+=2}
bit4
4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z
MCU status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
File register address {0x0000...0x1FFF}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
lit8
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
lit16
lit23
23-bit unsigned literal {0...8388608}; LSB must be 0
None
Field does not require an entry, may be blank
OA, OB, SA, SB
DSP status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
Slit6
DS70116D-page 152
Preliminary
dsPIC30F5011/5013
TABLE 21-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wb
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor working register pair (direct addressing)
Wm*Wm
Multiplicand and Multiplier working register pair for Square instructions

{W4*W4,W5*W5,W6*W6,W7*W7}
Wm*Wn
Multiplicand and Multiplier working register pair for DSP instructions

{W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7}
Wn
One of 16 working registers {W0..W15}
Wnd
One of 16 destination working registers {W0..W15}
Wns
One of 16 source working registers {W0..W15}
WREG
W0 (working register used in file register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X data space pre-fetch address register for DSP instructions

{[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2,
[W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2,
[W9+W12],none}
Wxd
X data space pre-fetch destination register for DSP instructions {W4..W7}
Wy
Y data space pre-fetch address register for DSP instructions

{[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2,
[W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2,
[W11+W12], none}
Wyd
Y data space pre-fetch destination register for DSP instructions {W4..W7}
Preliminary
DS70116D-page 153
dsPIC30F5011/5013
TABLE 21-2:
Base
Instr
#
1
Assembly
Mnemonic
ADD
ADDC
AND
ASR
BCLR
BRA
INSTRUCTION SET OVERVIEW
BSET
BSW
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
ADD
Acc
Add Accumulators
ADD
f = f + WREG
OA,OB,SA,SB
C,DC,N,OV,Z
ADD
f,WREG
WREG = f + WREG
C,DC,N,OV,Z
ADD
#lit10,Wn
Wd = lit10 + Wd
C,DC,N,OV,Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
C,DC,N,OV,Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
C,DC,N,OV,Z
ADD
Wso,#Slit4,Acc
16-bit Signed Add to Accumulator
OA,OB,SA,SB
ADDC
f = f + WREG + (C)
C,DC,N,OV,Z
ADDC
f,WREG
WREG = f + WREG + (C)
C,DC,N,OV,Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
C,DC,N,OV,Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
C,DC,N,OV,Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
C,DC,N,OV,Z
AND
f = f .AND. WREG
N,Z
AND
f,WREG
WREG = f .AND. WREG
N,Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
N,Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
N,Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
N,Z
ASR
f = Arithmetic Right Shift f
C,N,OV,Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
C,N,OV,Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
C,N,OV,Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
N,Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
N,Z
BCLR
f,#bit4
Bit Clear f
None
BCLR
Ws,#bit4
Bit Clear Ws
None
BRA
C,Expr
Branch if Carry
1 (2)
None
None
BRA
GE,Expr
Branch if greater than or equal
1 (2)
BRA
GEU,Expr
Branch if unsigned greater than or equal
1 (2)
None
BRA
GT,Expr
Branch if greater than
1 (2)
None
BRA
GTU,Expr
Branch if unsigned greater than
1 (2)
None
BRA
LE,Expr
Branch if less than or equal
1 (2)
None
BRA
LEU,Expr
Branch if unsigned less than or equal
1 (2)
None
BRA
LT,Expr
Branch if less than
1 (2)
None
BRA
LTU,Expr
Branch if unsigned less than
1 (2)
None
BRA
N,Expr
Branch if Negative
1 (2)
None
BRA
NC,Expr
Branch if Not Carry
1 (2)
None
BRA
NN,Expr
Branch if Not Negative
1 (2)
None
BRA
NOV,Expr
Branch if Not Overflow
1 (2)
None
BRA
NZ,Expr
Branch if Not Zero
1 (2)
None
BRA
OA,Expr
Branch if Accumulator A overflow
1 (2)
None
BRA
OB,Expr
Branch if Accumulator B overflow
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1 (2)
None
BRA
SA,Expr
Branch if Accumulator A saturated
1 (2)
None
BRA
SB,Expr
Branch if Accumulator B saturated
1 (2)
None
BRA
Expr
Branch Unconditionally
None
BRA
Z,Expr
Branch if Zero
1 (2)
None
BRA
Wn
Computed Branch
None
BSET
f,#bit4
Bit Set f
None
BSET
Ws,#bit4
Bit Set Ws
None
BSW.C
Ws,Wb
Write C bit to Ws<Wb>
None
BSW.Z
Ws,Wb
Write Z bit to Ws<Wb>
None
DS70116D-page 154
Preliminary
dsPIC30F5011/5013
TABLE 21-2:
Base
Instr
#
9
10
11
12
13
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
BTG
BTSC
BTSS
BTST
BTSTS
14
CALL
15
CLR
Assembly Syntax
f,#bit4
Bit Toggle f
Ws,#bit4
Bit Toggle Ws
None
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
(2 or 3)
None
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
(2 or 3)
None
BTSS
f,#bit4
Bit Test f, Skip if Set
1
(2 or 3)
None
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
(2 or 3)
None
BTST
f,#bit4
Bit Test f
Ws,#bit4
Bit Test Ws to C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
BTST.C
Ws,Wb
Bit Test Ws<Wb> to C
BTST.Z
Ws,Wb
Bit Test Ws<Wb> to Z
BTSTS
f,#bit4
Bit Test then Set f
Z
C
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
CALL
lit23
Call subroutine
None
CALL
Wn
Call indirect subroutine
None
CLR
f = 0x0000
None
CLR
WREG
WREG = 0x0000
None
CLR
Ws
Ws = 0x0000
None
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
OA,OB,SA,SB
Clear Watchdog Timer
WDTO,Sleep
f=f
N,Z
COM
f,WREG
WREG = f
N,Z
COM
Ws,Wd
Wd = Ws
N,Z
CP
Compare f with WREG
C,DC,N,OV,Z
17
COM
COM
20
21
CP0
CP1
CPB
None
BTST.C
CLRWDT
19
Status Flags
Affected
BTG
CLRWDT
CP
# of
# of
Words Cycles
BTG
16
18
Description
CP
Wb,#lit5
Compare Wb with lit5
C,DC,N,OV,Z
CP
Wb,Ws
Compare Wb with Ws (Wb - Ws)
C,DC,N,OV,Z
CP0
Compare f with 0x0000
C,DC,N,OV,Z
CP0
Ws
Compare Ws with 0x0000
C,DC,N,OV,Z
C,DC,N,OV,Z
CP1
Compare f with 0xFFFF
CP1
Ws
Compare Ws with 0xFFFF
C,DC,N,OV,Z
CPB
Compare f with WREG, with Borrow
C,DC,N,OV,Z
CPB
Wb,#lit5
Compare Wb with lit5, with Borrow
C,DC,N,OV,Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow

(Wb - Ws - C)
C,DC,N,OV,Z
22
CPSEQ
CPSEQ
Wb, Wn
Compare Wb with Wn, skip if =
1
(2 or 3)
None
23
CPSGT
CPSGT
Wb, Wn
Compare Wb with Wn, skip if >
1
(2 or 3)
None
24
CPSLT
CPSLT
Wb, Wn
Compare Wb with Wn, skip if <
1
(2 or 3)
None
25
CPSNE
CPSNE
Wb, Wn
Compare Wb with Wn, skip if
1
(2 or 3)
None
26
DAW
DAW
Wn
Wn = decimal adjust Wn
27
DEC
DEC
f = f -1
C,DC,N,OV,Z
28
DEC2
DEC
f,WREG
WREG = f -1
C,DC,N,OV,Z
DEC
Ws,Wd
Wd = Ws - 1
C,DC,N,OV,Z
C,DC,N,OV,Z
DEC2
f = f -2
DEC2
f,WREG
WREG = f -2
C,DC,N,OV,Z
DEC2
Ws,Wd
Wd = Ws - 2
C,DC,N,OV,Z
Preliminary
DS70116D-page 155
dsPIC30F5011/5013
TABLE 21-2:
Base
Instr
#
Assembly
Mnemonic
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
29
DISI
DISI
#lit14
Disable Interrupts for k instruction cycles
None
30
DIV
DIV.S
Wm,Wn
Signed 16/16-bit Integer Divide
18
N,Z,C,OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
18
N,Z,C,OV
DIV.U
Wm,Wn
Unsigned 16/16-bit Integer Divide
18
N,Z,C,OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
18
N,Z,C,OV
N,Z,C,OV
31
DIVF
DIVF
Wm,Wn
Signed 16/16-bit Fractional Divide
18
32
DO
DO
#lit14,Expr
Do code to PC+Expr, lit14+1 times
None
DO
Wn,Expr
Do code to PC+Expr, (Wn)+1 times
None
33
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance (no accumulate)
OA,OB,OAB,
SA,SB,SAB
34
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
OA,OB,OAB,
SA,SB,SAB
35
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
None
36
FBCL
FBCL
Ws,Wnd
Find Bit Change from Left (MSb) Side
37
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
38
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
39
GOTO
GOTO
Expr
Go to address
None
GOTO
Wn
Go to indirect
None
40
41
42
INC
INC2
IOR
INC
f=f+1
C,DC,N,OV,Z
INC
f,WREG
WREG = f + 1
C,DC,N,OV,Z
INC
Ws,Wd
Wd = Ws + 1
C,DC,N,OV,Z
INC2
f=f+2
C,DC,N,OV,Z
INC2
f,WREG
WREG = f + 2
C,DC,N,OV,Z
INC2
Ws,Wd
Wd = Ws + 2
C,DC,N,OV,Z
IOR
f = f .IOR. WREG
N,Z
IOR
f,WREG
WREG = f .IOR. WREG
N,Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
N,Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
N,Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
N,Z
LAC
LAC
Wso,#Slit4,Acc
Load Accumulator
OA,OB,OAB,
SA,SB,SAB
44
LNK
LNK
#lit14
Link frame pointer
None
45
LSR
LSR
f = Logical Right Shift f
C,N,OV,Z
LSR
f,WREG
WREG = Logical Right Shift f
C,N,OV,Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
C,N,OV,Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
N,Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
N,Z
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,
AWB
Multiply and Accumulate
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
OA,OB,OAB,
SA,SB,SAB
43
46
47
48
MAC
MOV
MOVSAC
MOV
f,Wn
Move f to Wn
None
MOV
Move f to f
N,Z
MOV
f,WREG
Move f to WREG
N,Z
MOV
#lit16,Wn
Move 16-bit literal to Wn
None
MOV.b
#lit8,Wn
Move 8-bit literal to Wn
None
MOV
Wn,f
Move Wn to f
None
MOV
Wso,Wdo
Move Ws to Wd
None
MOV
WREG,f
Move WREG to f
N,Z
MOV.D
Wns,Wd
Move Double from W(ns):W(ns+1) to Wd
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd+1):W(nd)
None
Pre-fetch and store accumulator
None
MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB
DS70116D-page 156
Preliminary
dsPIC30F5011/5013
TABLE 21-2:
Base
Instr
#
49
Assembly
Mnemonic
MPY
Assembly Syntax
Multiply Wm by Wn to Accumulator
OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator
OA,OB,OAB,
SA,SB,SAB
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
-(Multiply Wm by Wn) to Accumulator
None
Multiply and Subtract from Accumulator
OA,OB,OAB,
SA,SB,SAB
MPY.N
MPY.N
MSC
MSC
52
MUL
54
55
NOP
POP
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,
AWB
MUL.SS
Wb,Ws,Wnd
{Wnd+1, Wnd} = signed(Wb) * signed(Ws)
None
MUL.SU
Wb,Ws,Wnd
{Wnd+1, Wnd} = signed(Wb) * unsigned(Ws)
None
MUL.US
Wb,Ws,Wnd
{Wnd+1, Wnd} = unsigned(Wb) * signed(Ws)
None
MUL.UU
Wb,Ws,Wnd
{Wnd+1, Wnd} = unsigned(Wb) *

unsigned(Ws)
None
MUL.SU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = signed(Wb) * unsigned(lit5)
None
MUL.UU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = unsigned(Wb) *

unsigned(lit5)
None
MUL
W3:W2 = f * WREG
None
NEG
Acc
Negate Accumulator
OA,OB,OAB,
SA,SB,SAB
NEG
f=f+1
C,DC,N,OV,Z
NEG
f,WREG
WREG = f + 1
C,DC,N,OV,Z
NEG
Ws,Wd
C,DC,N,OV,Z
Wd = Ws + 1
NOP
No Operation
None
NOPR
No Operation
None
POP
Pop f from top-of-stack (TOS)
None
POP
Wdo
Pop from top-of-stack (TOS) to Wdo
None
POP.D
Wnd
Pop from top-of-stack (TOS) to

W(nd):W(nd+1)
None
Pop Shadow Registers
All
Push f to top-of-stack (TOS)
None
None
POP.S
56
PUSH
Status Flags
Affected
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
50
NEG
# of
# of
Words Cycles
MPY
51
53
Description
PUSH
PUSH
Wso
Push Wso to top-of-stack (TOS)
PUSH.D
Wns
Push W(ns):W(ns+1) to top-of-stack (TOS)
None
Push Shadow Registers
None
WDTO,Sleep
PUSH.S
57
PWRSAV
PWRSAV
Go into Sleep or Idle mode
58
RCALL
RCALL
Expr
Relative Call
None
RCALL
Wn
Computed Call
None
59
REPEAT
#lit1
REPEAT
#lit14
Repeat Next Instruction lit14+1 times
None
REPEAT
Wn
Repeat Next Instruction (Wn)+1 times
None
60
RESET
RESET
Software device Reset
None
61
RETFIE
RETFIE
Return from interrupt
3 (2)
None
62
RETLW
RETLW
None
63
RETURN
RETURN
64
RLC
RLC
65
66
67
RLNC
RRC
RRNC
#lit10,Wn
Return with literal in Wn
3 (2)
Return from Subroutine
3 (2)
None
f = Rotate Left through Carry f
C,N,Z
RLC
f,WREG
WREG = Rotate Left through Carry f
C,N,Z
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
C,N,Z
N,Z
RLNC
f = Rotate Left (No Carry) f
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
N,Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
N,Z
C,N,Z
RRC
f = Rotate Right through Carry f
RRC
f,WREG
WREG = Rotate Right through Carry f
C,N,Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
C,N,Z
N,Z
RRNC
f = Rotate Right (No Carry) f
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
N,Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
N,Z
Preliminary
DS70116D-page 157
dsPIC30F5011/5013
TABLE 21-2:
Base
Instr
#
68
Assembly
Mnemonic
SAC
69
SE
70
SETM
71
72
73
74
75
76
SFTAC
SL
SUB
SUBB
SUBR
SUBBR
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
SAC
Acc,#Slit4,Wdo
Store Accumulator
SAC.R
Acc,#Slit4,Wdo
Store Rounded Accumulator
None
None
SE
Ws,Wnd
Wnd = sign-extended Ws
C,N,Z
SETM
f = 0xFFFF
None
SETM
WREG
WREG = 0xFFFF
None
SETM
Ws
Ws = 0xFFFF
None
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
OA,OB,OAB,
SA,SB,SAB
SL
f = Left Shift f
C,N,OV,Z
SL
f,WREG
WREG = Left Shift f
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
C,N,OV,Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
N,Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
N,Z
SUB
Acc
Subtract Accumulators
OA,OB,OAB,
SA,SB,SAB
SUB
f = f - WREG
C,DC,N,OV,Z
SUB
f,WREG
WREG = f - WREG
C,DC,N,OV,Z
SUB
#lit10,Wn
Wn = Wn - lit10
C,DC,N,OV,Z
SUB
Wb,Ws,Wd
Wd = Wb - Ws
C,DC,N,OV,Z
SUB
Wb,#lit5,Wd
Wd = Wb - lit5
C,DC,N,OV,Z
SUBB
f = f - WREG - (C)
C,DC,N,OV,Z
SUBB
f,WREG
WREG = f - WREG - (C)
C,DC,N,OV,Z
SUBB
#lit10,Wn
Wn = Wn - lit10 - (C)
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBB
Wb,Ws,Wd
Wd = Wb - Ws - (C)
SUBB
Wb,#lit5,Wd
Wd = Wb - lit5 - (C)
SUBR
f = WREG - f
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBR
f,WREG
WREG = WREG - f
C,DC,N,OV,Z
SUBR
Wb,Ws,Wd
Wd = Ws - Wb
C,DC,N,OV,Z
SUBR
Wb,#lit5,Wd
Wd = lit5 - Wb
C,DC,N,OV,Z
SUBBR
f = WREG - f - (C)
C,DC,N,OV,Z
SUBBR
f,WREG
WREG = WREG -f - (C)
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBBR
Wb,Ws,Wd
Wd = Ws - Wb - (C)
SUBBR
Wb,#lit5,Wd
Wd = lit5 - Wb - (C)
C,DC,N,OV,Z
SWAP.b
Wn
Wn = nibble swap Wn
None
77
SWAP
SWAP
Wn
Wn = byte swap Wn
None
78
TBLRDH
TBLRDH
Ws,Wd
Read Prog<23:16> to Wd<7:0>
None
79
TBLRDL
TBLRDL
Ws,Wd
Read Prog<15:0> to Wd
None
80
TBLWTH
TBLWTH
Ws,Wd
Write Ws<7:0> to Prog<23:16>
None
81
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog<15:0>
None
82
ULNK
ULNK
Unlink frame pointer
None
83
XOR
XOR
f = f .XOR. WREG
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
N,Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
N,Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
N,Z
84
ZE
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
N,Z
ZE
Ws,Wnd
Wnd = Zero-extend Ws
C,Z,N
DS70116D-page 158
Preliminary
dsPIC30F5011/5013
22.0
DEVELOPMENT SUPPORT
22.1
The PICmicro microcontrollers are supported with a

full range of hardware and software development tools:
Integrated Development Environment
- MPLAB IDE Software
Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
Simulators
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
In-Circuit Debugger
- MPLAB ICD 2
Device Programmers
- PRO MATE II Universal Device Programmer
- PICSTART Plus Development Programmer
Low-Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
Evaluation Kits
- KEELOQ
- PICDEM MSC
- microID
- CAN
- PowerSmart
- Analog
MPLAB Integrated Development

Environment Software
The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows
based application that contains:
An interface to debugging tools
- simulator
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
A full-featured editor with color coded context
A multiple project manager
Customizable data windows with direct edit of
contents
High-level source code debugging
Mouse over variable inspection
Extensive on-line help
The MPLAB IDE allows you to:
Edit your source files (either assembly or C)
One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
Debug using:
- source files (assembly or C)
- absolute listing file (mixed assembly and C)
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.
22.2
MPASM Assembler
The MPASM assembler is a full-featured, universal

macro assembler for all PICmicro MCUs.
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel standard HEX
files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
The MPASM assembler features include:
Integration into MPLAB IDE projects
User defined macros to streamline assembly code
Conditional assembly for multi-purpose source
files
Directives that allow complete control over the
assembly process
Preliminary
DS70116D-page 159
dsPIC30F5011/5013
22.3
MPLAB C17 and MPLAB C18

C Compilers
22.6
The MPLAB C17 and MPLAB C18 Code Development

Systems are complete ANSI C compilers for
Microchips PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
22.4
MPLINK Object Linker/

MPLIB Object Librarian
The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB object librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
Efficient linking of single libraries instead of many
smaller files
Enhanced code maintainability by grouping
related modules together
Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
22.5
MPLAB C30 C Compiler
MPLAB C30 is distributed with a complete ANSI C

standard library. All library functions have been validated and conform to the ANSI C library standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, timekeeping and math functions (trigonometric, exponential
and hyperbolic). The compiler provides symbolic
information for high-level source debugging with the
MPLAB IDE.
DS70116D-page 160
MPLAB ASM30 assembler produces relocatable

machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
Support for the entire dsPIC30F instruction set

Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
22.7
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until
Break or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
22.8
The MPLAB C30 C compiler is a full-featured, ANSI

compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command
line options and language extensions to take full
advantage of the dsPIC30F device hardware capabilities and afford fine control of the compiler code
generator.
MPLAB ASM30 Assembler, Linker

and Librarian
MPLAB SIM30 Software Simulator
The MPLAB SIM30 software simulator allows code

development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high-speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
Preliminary
dsPIC30F5011/5013
22.9
MPLAB ICE 2000

High-Performance Universal
In-Circuit Emulator
22.11 MPLAB ICD 2 In-Circuit Debugger
The MPLAB ICE 2000 universal in-circuit emulator is

intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of different processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
22.10 MPLAB ICE 4000

High-Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, up to 2 Mb of emulation memory and the
ability to view variables in real-time.
Microchips In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
Microchips In-Circuit Serial ProgrammingTM (ICSPTM)
protocol, offers cost effective in-circuit Flash debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
22.12 PRO MATE II Universal Device

Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
22.13 PICSTART Plus Development

Programmer
The PICSTART Plus development programmer is an
easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
The MPLAB ICE 4000 in-circuit emulator system has

been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
Preliminary
DS70116D-page 161
dsPIC30F5011/5013
22.14 PICDEM 1 PICmicro
Demonstration Board
22.17 PICDEM 3 PIC16C92X

Demonstration Board
The PICDEM 1 demonstration board demonstrates the

capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can
be programmed with a PRO MATE II device programmer or a PICSTART Plus development programmer.
The PICDEM 1 demonstration board can be connected
to the MPLAB ICE in-circuit emulator for testing. A
prototype area extends the circuitry for additional application components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
The PICDEM 3 demonstration board supports the

PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
22.15 PICDEM.net Internet/Ethernet

Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface and a
16 x 2 LCD display. Also included is the book and
CD-ROM TCP/IP Lean, Web Servers for Embedded
Systems, by Jeremy Bentham
22.16 PICDEM 2 Plus

Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18, 28 and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
DS70116D-page 162
22.18 PICDEM 4 8/14/18-Pin

Demonstration Board
The PICDEM 4 can be used to demonstrate the capabilities of the 8, 14 and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320
family of microcontrollers. PICDEM 4 is intended to
showcase the many features of these low pin count
parts, including LIN and Motor Control using ECCP.
Special provisions are made for low-power operation
with the supercapacitor circuit and jumpers allow onboard hardware to be disabled to eliminate current
draw in this mode. Included on the demo board are provisions for Crystal, RC or Canned Oscillator modes, a
five volt regulator for use with a nine volt wall adapter
or battery, DB-9 RS-232 interface, ICD connector for
programming via ICSP and development with MPLAB
ICD 2, 2 x 16 liquid crystal display, PCB footprints for
H-Bridge motor driver, LIN transceiver and EEPROM.
Also included are: header for expansion, eight LEDs,
four potentiometers, three push buttons and a prototyping area. Included with the kit is a PIC16F627A and
a PIC18F1320. Tutorial firmware is included along with
the Users Guide.
22.19 PICDEM 17 Demonstration Board

The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device
programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous prototype area is available for user hardware
expansion.
Preliminary
dsPIC30F5011/5013
22.20 PICDEM 18R PIC18C601/801
Demonstration Board
22.23 PICDEM USB PIC16C7X5

Demonstration Board
The PICDEM 18R demonstration board serves to assist

development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/Demultiplexed and 16-bit
Memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
The PICDEM USB Demonstration Board shows off the

capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
22.21 PICDEM LIN PIC16C43X

Demonstration Board
The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 Flash
microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide
LIN bus communication.
22.22 PICkitTM 1 Flash Starter Kit

A complete development system in a box, the PICkit
Flash Starter Kit includes a convenient multi-section
board for programming, evaluation and development of
8/14-pin Flash PIC microcontrollers. Powered via
USB, the board operates under a simple Windows GUI.
The PICkit 1 Starter Kit includes the Users Guide (on
CD ROM), PICkit 1 tutorial software and code for
various applications. Also included are MPLAB IDE
(Integrated Development Environment) software,
software and hardware Tips 'n Tricks for 8-pin Flash
PIC Microcontrollers Handbook and a USB interface
cable. Supports all current 8/14-pin Flash PIC
microcontrollers, as well as many future planned
devices.
22.24 Evaluation and

Programming Tools
In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
KEELOQ evaluation and programming tools for
Microchips HCS Secure Data Products
CAN developers kit for automotive network
applications
Analog design boards and filter design software
PowerSmart battery charging evaluation/
calibration kits
IrDA development kit
microID development and rfLabTM development
software
SEEVAL designer kit for memory evaluation and
endurance calculations
PICDEM MSC demo boards for Switching mode
power supply, high-power IR driver, delta sigma
ADC and flow rate sensor
Check the Microchip web page and the latest Product
Selector Guide for the complete list of demonstration
and evaluation kits.
Preliminary
DS70116D-page 163
dsPIC30F5011/5013
NOTES:
DS70116D-page 164
Preliminary
dsPIC30F5011/5013
23.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future
revisions of this document as it becomes available.
For detailed information about the dsPIC30F architecture and core, refer to dsPIC30F Family Reference Manual
(DS70046).
Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for
extended periods may affect device reliability. Functional operation of the device at these or any other conditions above
the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings()

Ambient temperature under bias.............................................................................................................-40C to +125C
Storage temperature .............................................................................................................................. -65C to +150C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Voltage on MCLR with respect to VSS (Note 1) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 2) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ..........................................................................................................20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ................................................................................................... 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup.
Thus, a series resistor of 50-100 should be used when applying a low level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note:
All peripheral electrical characteristics are specified. For exact peripherals available on specific
devices, please refer the the Family Cross Reference Table.
Preliminary
DS70116D-page 165
dsPIC30F5011/5013
23.1
DC Characteristics
TABLE 23-1:
OPERATING MIPS VS. VOLTAGE

Max MIPS
VDD Range
Temp Range
dsPIC30FXXX-30I
dsPIC30FXXX-20I
dsPIC30FXXX-20E
30
20
4.5-5.5V
-40C to 85C
4.5-5.5V
-40C to 125C
20
3.0-3.6V
-40C to 85C
15
10
3.0-3.6V
-40C to 125C
10
2.5-3.0V
-40C to 85C
10
7.5
TABLE 23-2:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
Conditions
Operating Voltage(2)
DC10
VDD
Supply Voltage
2.5
5.5
Industrial temperature
DC11
VDD
Supply Voltage
3.0
5.5
Extended temperature
Voltage(3)
DC12
VDR
RAM Data Retention
1.5
DC16
VPOR
VDD Start Voltage

to ensure internal
Power-on Reset signal
VSS
DC17
SVDD
VDD Rise Rate

to ensure internal
Power-on Reset signal
0.05
Note 1:
2:
3:
V/ms 0-5V in 0.1 sec

0-3V in 60 ms
Data in Typ column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
This is the limit to which VDD can be lowered without losing RAM data.
DS70116D-page 166
Preliminary
dsPIC30F5011/5013
TABLE 23-3:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)

DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
mA
Conditions
Operating Current (IDD)(2)

DC20
-40C
DC20a
3.8
mA
25C
DC20b
mA
85C
DC20c
mA
125C
DC20d
mA
-40C
DC20e
5.7
mA
25C
DC20f
mA
85C
DC20g
mA
125C
DC23
mA
-40C
DC23a
12.3
mA
25C
DC23b
mA
85C
DC23c
mA
125C
DC23d
mA
-40C
DC23e
19.4
mA
25C
DC23f
mA
85C
DC23g
mA
125C
DC24
mA
-40C
DC24a
29.2
mA
25C
DC24b
mA
85C
DC24c
mA
125C
DC24d
mA
-40C
DC24e
45.8
mA
25C
DC24f
mA
85C
DC24g
mA
125C
DC25
mA
-40C
DC25a
24.3
mA
25C
DC25b
mA
85C
DC25c
mA
125C
DC25d
mA
-40C
DC25e
37.6
mA
25C
DC25f
mA
85C
DC25g
mA
125C
Note 1:
2:
3.3V
1 MIPS EC mode
5V
3.3V
4 MIPS EC mode, 4X PLL
5V
3.3V
5V
3.3V
5V
Data in Typical column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD.
MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data
Memory are operational. No peripheral modules are operating.
Preliminary
DS70116D-page 167
dsPIC30F5011/5013
TABLE 23-3:
DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)

DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions

DC27
mA
-40C
DC27a
54.2
mA
25C
DC27b
mA
85C
DC27c
mA
-40C
DC27d
84.4
mA
25C
DC27e
mA
85C
DC27f
mA
125C
DC28
mA
-40C
DC28a
44.3
mA
25C
DC28b
mA
85C
DC28c
mA
-40C
DC28d
70.1
mA
25C
DC28e
mA
85C
DC28f
mA
125C
DC29
mA
-40C
DC29a
116.7
mA
25C
DC29b
mA
85C
DC29c
mA
125C
DC30
mA
-40C
DC30a
6.7
mA
25C
DC30b
mA
85C
DC30c
mA
125C
DC30d
mA
-40C
DC30e
10.05
mA
25C
DC30f
mA
85C
DC30g
mA
125C
Note 1:
2:
3.3V
5V
3.3V
5V
5V
3.3V
FRC (~ 2 MIPS)
5V
and are not tested.
DS70116D-page 168
Preliminary
dsPIC30F5011/5013
TABLE 23-3:
DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)

DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
mA
-40C

DC31
DC31a
1.13
mA
25C
DC31b
mA
85C
DC31c
mA
125C
DC31d
mA
-40C
DC31e
1.4
mA
25C
DC31f
mA
85C
mA
125C
DC31g
Note 1:
2:
3.3V
LPRC (~ 512 kHz)
5V
and are not tested.
Preliminary
DS70116D-page 169
dsPIC30F5011/5013
TABLE 23-4:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core OFF Clock ON Base Current(2)

DC40
mA
-40C
DC40a
2.6
mA
25C
DC40b
mA
85C
DC40c
mA
125C
DC40d
mA
-40C
DC40e
3.9
mA
25C
DC40f
mA
85C
DC40g
mA
125C
DC43
mA
-40C
DC43a
8.2
mA
25C
DC43b
mA
85C
DC43c
mA
125C
DC43d
mA
-40C
DC43e
12.7
mA
25C
DC43f
mA
85C
DC43g
mA
125C
DC44
mA
-40C
DC44a
19.6
mA
25C
DC44b
mA
85C
DC44c
mA
125C
DC44d
mA
-40C
DC44e
30.2
mA
25C
DC44f
mA
85C
DC44g
mA
125C
DC45
mA
-40C
DC45a
16
mA
25C
DC45b
mA
85C
DC45c
mA
125C
DC45d
mA
-40C
DC45e
24.8
mA
25C
DC45f
mA
85C
DC45g
mA
125C
Note 1:
2:
3.3V
1 MIPS EC mode
5V
3.3V
5V
3.3V
5V
3.3V
5V
and are not tested.
Base IIDLE current is measured with Core off, Clock on and all modules turned off.
DS70116D-page 170
Preliminary
dsPIC30F5011/5013
TABLE 23-4:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)

DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core OFF Clock ON Base Current(2)

DC47
DC47a
36.2
DC47b
DC47c
DC47d
56.3
DC47e
DC47f
mA
-40C
mA
25C
mA
85C
mA
-40C
mA
25C
mA
85C
mA
125C
DC48
mA
-40C
DC48a
29.4
mA
25C
DC48b
mA
85C
DC48c
mA
-40C
DC48d
46.5
mA
25C
DC48e
mA
85C
DC48f
mA
125C
DC49
mA
-40C
DC49a
80.1
mA
25C
DC49b
mA
85C
DC49c
mA
125C
DC50
mA
-40C
DC50a
4.38
mA
25C
DC50b
mA
85C
DC50c
mA
125C
DC50d
mA
-40C
DC50e
6.57
mA
25C
DC50f
mA
85C
DC50g
mA
125C
DC51
mA
-40C
DC51a
0.82
mA
25C
DC51b
mA
85C
DC51c
mA
125C
DC51d
mA
-40C
DC51e
1.03
mA
25C
DC51f
mA
85C
DC51g
mA
125C
Note 1:
2:
3.3V
5V
3.3V
5V
5V
3.3V
FRC (~ 2 MIPS)
5V
3.3V
LPRC (~ 512 kHz)
5V
and are not tested.
Base IIDLE current is measured with Core off, Clock on and all modules turned off.
Preliminary
DS70116D-page 171
dsPIC30F5011/5013
TABLE 23-5:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
-40C
DC60a
25C
DC60b
85C
DC60c
125C
DC60d
-40C
DC60e
25C
DC60f
85C
Power Down Current (IPD)(2)

DC60
DC60g
125C
DC61
-40C
DC61a
25C
DC61b
85C
DC61c
125C
DC61d
-40C
DC61e
15
25C
DC61f
85C
DC61g
125C
DC62
-40C
DC62a
25C
DC62b
85C
DC62c
125C
DC62d
-40C
DC62e
25C
DC62f
85C
DC62g
125C
DC63
-40C
DC63a
30
25C
DC63b
85C
DC63c
125C
DC63d
-40C
DC63e
36
25C
DC63f
85C
DC63g
125C
Note 1:
2:
3:
3.3V
Base Power Down Current(3)
5V
3.3V
Watchdog Timer Current: IWDT(3)
5V
3.3V
Timer 1 w/32 kHz Crystal: ITI32(3)
5V
3.3V
BOR On: IBOR(3)
5V
Data in the Typical column is at 5V, 25C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. LVD, BOR, WDT, etc. are all switched off.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
DS70116D-page 172
Preliminary
dsPIC30F5011/5013
TABLE 23-5:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)

DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Power Down Current (IPD)(2)

DC66
-40C
DC66a
30
25C
DC66b
85C
DC66c
125C
DC66d
-40C
DC66e
36
25C
DC66f
85C
125C
DC66g
Note 1:
2:
3:
3.3V
Low Voltage Detect: ILVD(3)
5V
Data in the Typical column is at 5V, 25C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. LVD, BOR, WDT, etc. are all switched off.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
Preliminary
DS70116D-page 173
dsPIC30F5011/5013
TABLE 23-6:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS
Param
Symbol
No.
VIL
DI10
Characteristic
Min
Typ(1)
Max
Units
VSS
0.2 VDD
Conditions
Input Low Voltage(2)

I/O pins:
with Schmitt Trigger buffer
DI15
MCLR
VSS
0.2 VDD
DI16
OSC1 (in XT, HS and LP modes)
VSS
0.2 VDD
(3)
DI17
OSC1 (in RC mode)
VSS
0.3 VDD
DI18
SDA, SCL
TBD
TBD
SM bus disabled
SDA, SCL
TBD
TBD
SM bus enabled
I/O pins:
with Schmitt Trigger buffer
0.8 VDD
VDD
DI25
MCLR
0.8 VDD
VDD
DI26
OSC1 (in XT, HS and LP modes) 0.7 VDD
VDD
DI27
(3)
OSC1 (in RC mode)
0.9 VDD
VDD
DI28
SDA, SCL
TBD
TBD
SM bus disabled
DI29
SDA, SCL
TBD
TBD
SM bus enabled
50
250
400
VDD = 5V, VPIN = VSS
TBD
TBD
TBD
VDD = 3V, VPIN = VSS
DI19
VIH
DI20
ICNPU
Input High Voltage(2)
CNXX Pull-up
Current(2)
DI30
DI31
IIL
Input Leakage Current(2)(4)(5)
DI50
I/O ports
0.01
VSS VPIN VDD,

Pin at hi-impedance
DI51
Analog input pins
0.50
VSS VPIN VDD,

Pin at hi-impedance
DI55
MCLR
0.05
VSS VPIN VDD
DI56
OSC1
0.05
VSS VPIN VDD, XT, HS

and LP Osc mode
Note 1:
2:
3:
4:
5:
are not tested.
In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that
the dsPIC30F device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
DS70116D-page 174
Preliminary
dsPIC30F5011/5013
TABLE 23-7:
DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS
Param
Symbol
No.
VOL
Characteristic
Min
Typ(1)
Max
Units
0.6
IOL = 8.5 mA, VDD = 5V
Conditions
Output Low Voltage(2)
DO10
I/O ports
TBD
DO16
OSC2/CLKOUT
0.6
(RC or EC Osc mode)
TBD
VDD 0.7
IOH = -3.0 mA, VDD = 5V
TBD
IOH = -2.0 mA, VDD = 3V
VOH
DO20
Output High Voltage(2)

I/O ports
DO26
OSC2/CLKOUT
(RC or EC Osc mode)
VDD 0.7
IOH = -1.3 mA, VDD = 5V
TBD
IOH = -2.0 mA, VDD = 3V
Capacitive Loading Specs

on Output Pins(2)
DO50
COSC2
OSC2/SOSC2 pin
15
pF
In XTL, XT, HS and LP modes

when external clock is used to
drive OSC1.
DO56
CIO
All I/O pins and OSC2
50
pF
RC or EC Osc mode
DO58
CB
SCL, SDA
400
pF
In I2C mode
Note 1:
2:
are not tested.
FIGURE 23-1:
LOW-VOLTAGE DETECT CHARACTERISTICS

VDD
LV10
LVDIF
(LVDIF set by hardware)
Preliminary
DS70116D-page 175
dsPIC30F5011/5013
TABLE 23-8:
ELECTRICAL CHARACTERISTICS: LVDL

DC CHARACTERISTICS
Param
No.
LV10
Characteristic(1)
Symbol
VPLVD
Min
Typ
Max
Units
LVDL Voltage on VDD transition LVDL = 0000(2)

high to low
LVDL = 0001(2)
LVDL = 0010(2)
2.50
2.65
LVDL = 0011
(2)
LVDL = 0100
LV15
Note 1:
2:
VLVDIN
External LVD input pin

threshold voltage
LVDL = 0101
2.70
2.86
LVDL = 0110
2.80
2.97
LVDL = 0111
3.00
3.18
LVDL = 1000
3.30
3.50
LVDL = 1001
3.50
3.71
LVDL = 1010
3.60
3.82
LVDL = 1011
3.80
4.03
LVDL = 1100
4.00
4.24
LVDL = 1101
4.20
4.45
LVDL = 1110
4.50
4.77
LVDL = 1111
Conditions

These values not in usable operating range.
FIGURE 23-2:
BROWN-OUT RESET CHARACTERISTICS

VDD
BO10
(Device in Brown-out Reset)
BO15
(Device not in Brown-out Reset)
RESET (due to BOR)

Power Up Time-out
DS70116D-page 176
Preliminary
dsPIC30F5011/5013
TABLE 23-9:
ELECTRICAL CHARACTERISTICS: BOR

DC CHARACTERISTICS
Param
No.
Symbol
VBOR
BO10
Min
Typ(1)
Max
Units
BORV = 00(3)
BORV = 01
2.7
2.86
BORV = 10
4.2
4.46
BORV = 11
4.5
4.78
mV
Characteristic
BOR Voltage(2) on
VDD transition high to
low
Conditions
Not in operating
range
BO15
VBHYS
Note 1:
are not tested.
00 values not in usable operating range.
2:
3:
TABLE 23-10: DC CHARACTERISTICS: PROGRAM AND EEPROM

DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
Data EEPROM Memory(2)

D120
ED
Byte Endurance
100K
1M
E/W
D121
VDRW
VDD for Read/Write
VMIN
5.5
-40C TA +85C
Using EECON to read/write
VMIN = Minimum operating
voltage
D122
TDEW
Erase/Write Cycle Time
ms
D123
TRETD
Characteristic Retention
40
100
Year
Provided no other specifications

are violated
D124
IDEW
IDD During Programming
10
30
mA
Row Erase
-40C TA +85C
(2)
Program FLASH Memory

D130
EP
Cell Endurance
10K
100K
E/W
D131
VPR
VDD for Read
VMIN
5.5
D132
VEB
VDD for Bulk Erase
4.5
5.5
D133
VPEW
VDD for Erase/Write
3.0
5.5
D134
TPEW
Erase/Write Cycle Time
ms
D135
TRETD
Characteristic Retention
40
100
Year
VMIN = Minimum operating

voltage
Provided no other specifications

are violated
D136
TEB
ICSP Block Erase Time
ms
D137
IPEW
10
30
mA
Row Erase
D138
IEB
10
30
mA
Bulk Erase
Note 1:
2:
Data in Typ column is at 5V, 25C unless otherwise stated.

Preliminary
DS70116D-page 177
dsPIC30F5011/5013
23.2
AC Characteristics and Timing Parameters
The information contained in this section defines dsPIC30F AC characteristics and timing parameters.
TABLE 23-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS AC

Operating voltage VDD range as described in DC Spec Section 23.0.
AC CHARACTERISTICS
FIGURE 23-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 - for all pins except OSC2
Load Condition 2 - for OSC2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
5 pF for OSC2 output
VSS
FIGURE 23-4:
EXTERNAL CLOCK TIMING

Q4
Q1
Q2
Q3
Q4
Q1
OSC1
OS20
OS30
OS25
OS30
OS31
OS31
CLKOUT
OS40
DS70116D-page 178
Preliminary
OS41
dsPIC30F5011/5013
TABLE 23-12: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol
No.
FOSC
OS10
Characteristic
Min
Typ(1)
Max
Units
External CLKIN Frequency(2)

(External clocks allowed only
in EC mode)
DC
4
4
4
40
10
10
7.5
MHz
MHz
MHz
MHz
EC
EC with 4x PLL
EC with 8x PLL
EC with 16x PLL
Oscillator Frequency(2)
DC
0.4
4
4
4
4
10
31
8
512
4
4
10
10
10
7.5
25
33
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
MHz
kHz
RC
XTL
XT
XT with 4x PLL
XT with 8x PLL
XT with 16x PLL
HS
LP
FRC internal
LPRC internal
See parameter OS10

for FOSC value
Conditions
OS20
TOSC
TOSC = 1/FOSC
OS25
TCY
Instruction Cycle Time(2)(3)
33
DC
ns
See Table 23-14
OS30
TosL,
TosH
External Clock(2) in (OSC1)

High or Low Time
.45 x TOSC
ns
EC
OS31
TosR,
TosF
External Clock(2) in (OSC1)

Rise or Fall Time
20
ns
EC
OS40
TckR
CLKOUT Rise Time(2)(4)
10
ns
OS41
TckF
CLKOUT Fall Time(2)(4)
10
ns
Note 1:
2:
3:
4:
are not tested.
Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at min.
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
Max. cycle time limit is DC (no clock) for all devices.
Measurements are taken in EC or ERC modes. The CLKOUT signal is measured on the OSC2 pin.
CLKOUT is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
Preliminary
DS70116D-page 179
dsPIC30F5011/5013
TABLE 23-13: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V)
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min
Typ(2)
Max
Units
Conditions
OS50
FPLLI
PLL Input Frequency Range(2)
10
MHz
EC, XT modes with PLL
OS51
FSYS
On-chip PLL Output(2)
16
120
MHz
EC, XT modes with PLL
OS52
TLOC
PLL Start-up Time (Lock Time)
20
50
OS53
DCLK
CLKOUT Stability (Jitter)
TBD
TBD
Note 1:
2:
Measured over 100 ms

period

are not tested.
TABLE 23-14: INTERNAL CLOCK TIMING EXAMPLES

Clock
Oscillator
Mode
FOSC
(MHz)(1)
TCY (sec)(2)
MIPS(3)
w/o PLL
MIPS(3)
w PLL x4
MIPS(3)
w PLL x8
MIPS(3)
w PLL x16
EC
0.200
20.0
0.05
XT
Note 1:
2:
3:
1.0
1.0
4.0
8.0
16.0
10
0.4
2.5
10.0
20.0
25
0.16
25.0
1.0
1.0
4.0
8.0
16.0
10
0.4
2.5
10.0
20.0
Assumption: Oscillator Postscaler is divide by 1.

Instruction Execution Cycle Time: TCY = 1 / MIPS.
Instruction Execution Frequency: MIPS = (FOSC * PLLx) / 4 [since there are 4 Q clocks per instruction
cycle].
TABLE 23-15: INTERNAL RC ACCURACY

AC CHARACTERISTICS
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
F16
TBD
TBD
-40C to +85C
VDD = 3.3V
F19
TBD
TBD
-40C to +85C
VDD = 5V
TBD
TBD
-40C to +85C
VDD = 3V
TBD
TBD
-40C to +85C
VDD = 5V
FRC @ Freq = 8 MHz(1)
LPRC @ Freq = 512 kHz

F20
F21
Note 1:
2:
3:
(2)
Frequency calibrated at 25C and 5V. TUN bits can be used to compensate for temperature drift.
LPRC frequency after calibration.
Change of LPRC frequency as VDD changes.
DS70116D-page 180
Preliminary
dsPIC30F5011/5013
FIGURE 23-5:
CLKOUT AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-16: CLKOUT AND I/O TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Characteristic(1)(2)(3)
Symbol
Min
Typ(4)
Max
Units
Conditions
10
25
ns
DO31
TIOR
DO32
TIOF
Port output fall time
10
25
ns
DI35
TINP
INTx pin high or low time (output)
20
ns
TRBP
CNx high or low time (input)
2 TCY
ns
DI40
Note 1:
2:
3:
4:
Port output rise time
These parameters are asynchronous events not related to any internal clock edges
Measurements are taken in RC mode and EC mode where CLKOUT output is 4 x TOSC.
Preliminary
DS70116D-page 181
dsPIC30F5011/5013
FIGURE 23-6:
VDD
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING CHARACTERISTICS
SY12
MCLR
SY10
Internal
POR
SY11
PWRT
Time-out
OSC
Time-out
SY30
Internal
RESET
Watchdog
Timer
RESET
SY13
SY20
SY13
I/O Pins
SY35
FSCM
Delay
DS70116D-page 182
Preliminary
dsPIC30F5011/5013
TABLE 23-17: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
SY10
TmcL
MCLR Pulse Width (low)
SY11
TPWRT
Power-up Timer Period
Min
Typ(2)
Max
Units
Conditions
-40C to +85C
TBD
TBD
TBD
TBD
0
4
16
64
TBD
TBD
TBD
TBD
ms
-40C to +85C
User programmable
-40C to +85C
SY12
TPOR
Power On Reset Delay
10
30
SY13
TIOZ
I/O Hi-impedance from MCLR

Low or Watchdog Timer Reset
100
ns
SY20
TWDT1
Watchdog Timer Time-out Period

(No Prescaler)
1.8
2.0
2.2
ms
VDD = 5V, -40C to +85C
1.9
2.1
2.3
ms
VDD = 3V, -40C to +85C
SY25
TBOR
Brown-out Reset Pulse Width(3)
100
VDD VBOR (D034)
SY30
TOST
Oscillation Start-up Timer Period
1024 TOSC
TOSC = OSC1 period
SY35
TFSCM
Fail-Safe Clock Monitor Delay
100
-40C to +85C
TWDT2
Note 1:
2:
3:

Refer to Figure 23-2 and Table 23-9 for BOR.
FIGURE 23-7:
BAND GAP START-UP TIME CHARACTERISTICS

VBGAP
0V
Enable Band Gap
(see Note)
Band Gap
Stable
SY40
Note: Set LVDEN bit (RCON<12>) or FBORPOR<7>set.
TABLE 23-18: BAND GAP START-UP TIME REQUIREMENTS

AC CHARACTERISTICS
Param
No.
SY40
Note 1:
2:
Symbol
TBGAP

Characteristic(1)
Min
Typ(2)
Max
Units
Band Gap Start-up Time
20
50
Conditions
Defined as the time between the
instant that the band gap is enabled
and the moment that the band gap
reference voltage is stable.
RCON<13>Status bit

Preliminary
DS70116D-page 183
dsPIC30F5011/5013
FIGURE 23-8:
TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRX
TABLE 23-19: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
TA10
TA11
TA15
Symbol
TTXH
TTXL
TTXP
Characteristic
TxCK High Time
TxCK Low Time
Min
Typ
Max
Units
Conditions
Synchronous,
no prescaler
0.5 TCY + 20
ns
Must also meet

parameter TA15
Synchronous,
with prescaler
10
ns
Asynchronous
10
ns
Synchronous,
no prescaler
0.5 TCY + 20
ns
Synchronous,
with prescaler
10
ns
Asynchronous
10
ns
TCY + 10
ns
Greater of:
20 ns or
(TCY + 40)/N
20
ns
DC
50
kHz
6 TOSC
TxCK Input Period Synchronous,

no prescaler
Synchronous,
with prescaler
Asynchronous
OS60
Ft1
TA20
TCKEXTMRL Delay from External TQCK Clock

Edge to Timer Increment
Note:
SOSC1/T1CK oscillator input

frequency range (oscillator enabled
by setting bit TCS (T1CON, bit 1))
2 TOSC
Must also meet

parameter TA15
N = prescale
value
(1, 8, 64, 256)
Timer1 is a Type A.
DS70116D-page 184
Preliminary
dsPIC30F5011/5013
TABLE 23-20: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
TB10
TB11
TB15
Symbol
TtxH
TtxL
TtxP
Characteristic
TxCK High Time
TxCK Low Time
Min
Typ
Max
Units
Synchronous,
no prescaler
0.5 TCY + 20
ns
Synchronous,
with prescaler
10
ns
Synchronous,
no prescaler
0.5 TCY + 20
ns
Synchronous,
with prescaler
10
ns
TCY + 10
ns
6 TOSC

no prescaler
Synchronous,
with prescaler
TB20
Note:

Greater of:
20 ns or
(TCY + 40)/N
2 TOSC
Conditions
Must also meet
parameter TB15
Must also meet

parameter TB15
N = prescale
value
(1, 8, 64, 256)
Timer2 and Timer4 are Type B.
TABLE 23-21: TYPE C TIMER (TIMER3 AND TIMER5) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
TC10
TtxH
TxCK High Time
Synchronous
0.5 TCY + 20
ns
Must also meet

parameter TC15
TC11
TtxL
TxCK Low Time
Synchronous
0.5 TCY + 20
ns
Must also meet

parameter TC15
TC15
TtxP

no prescaler
TCY + 10
ns
N = prescale
value
(1, 8, 64, 256)
6 TOSC
Synchronous,
with prescaler
TC20
Note:

Greater of:
20 ns or
(TCY + 40)/N
2 TOSC
Timer3 and Timer5 are Type C.
Preliminary
DS70116D-page 185
dsPIC30F5011/5013
FIGURE 23-9:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

ICX
IC10
IC11
IC15
TABLE 23-22: INPUT CAPTURE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
IC10
TccL
ICx Input Low Time
IC11
TccH
ICx Input High Time
IC15
TccP
ICx Input Period
No Prescaler
Min
Max
Units
0.5 TCY + 20
ns
With Prescaler
No Prescaler
10
ns
0.5 TCY + 20
ns
With Prescaler
Note 1:
10
ns
(2 TCY + 40)/N
ns
Conditions
N = prescale
value (1, 4, 16)
FIGURE 23-10:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
TABLE 23-23: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)

Min
Typ(2)
Max
Units
Conditions
OC10
TccF
OCx Output Fall Time
10
25
ns
OC11
TccR
OCx Output Rise Time
10
25
ns
Note 1:
2:

are not tested.
DS70116D-page 186
Preliminary
dsPIC30F5011/5013
FIGURE 23-11:
OC/PWM MODULE TIMING CHARACTERISTICS

OC20
OCFA/OCFB
OC15
OCx
TABLE 23-24: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
25
ns
OC15 TFD
Fault Input to PWM I/O

Change
OC20 TFLT
Fault Input Pulse Width
Note 1:
2:
Conditions
VDD = 3V
TBD
ns
VDD = 5V
50
ns
VDD = 3V
TBD
ns
VDD = 5V
-40C to +85C
-40C to +85C

are not tested.
Preliminary
DS70116D-page 187
dsPIC30F5011/5013
FIGURE 23-12:
DCI MODULE (MULTICHANNEL, I2S MODES) TIMING CHARACTERISTICS
CSCK
(SCKE = 0)
CS11
CS10
CS21
CS20
CS20
CS21
CSCK
(SCKE = 1)
COFS
CS55 CS56
CS35
CS51
CSDO
HIGH-Z
70
CS50
LSb
MSb
CS30
CSDI
HIGH-Z
CS31
LSb IN
MSb IN
CS40 CS41
DS70116D-page 188
Preliminary
dsPIC30F5011/5013
TABLE 23-25: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
TcSCKL
CS10
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
TCY / 2 + 20
ns
30
ns
TCY / 2 + 20
ns
CSCK Output High Time(3)

(CSCK pin is an output)
30
ns
CSCK Input Low Time

(CSCK pin is an input)
CSCK Output Low Time(3)
TcSCKH
CS11
CSCK Input High Time

(CSCK pin is an input)
CS20
TcSCKF
CSCK Output Fall Time(4)

10
25
ns
CS21
TcSCKR
CSCK Output Rise Time(4)

10
25
ns
CS30
TcSDOF
CSDO Data Output Fall Time(4)
10
25
ns
10
25
ns
10
ns
Time(4)
CS31
TcSDOR
CSDO Data Output Rise
CS35
TDV
Clock edge to CSDO data valid
CS36
TDIV
Clock edge to CSDO tri-stated
10
20
ns
CS40
TCSDI
Setup time of CSDI data input to

CSCK edge (CSCK pin is input
or output)
20
ns
CS41
THCSDI
Hold time of CSDI data input to

CSCK edge (CSCK pin is input
or output)
20
ns
CS50
TcoFSF
COFS Fall Time

(COFS pin is output)
10
25
ns
Note 1
CS51
TcoFSR
COFS Rise Time

(COFS pin is output)
10
25
ns
Note 1
CS55
TscoFS
Setup time of COFS data input to

CSCK edge (COFS pin is input)
20
ns
CS56
THCOFS
Hold time of COFS data input to

CSCK edge (COFS pin is input)
20
ns
Note 1:
2:
3:
4:

are not tested.
The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all DCI pins.
Preliminary
DS70116D-page 189
dsPIC30F5011/5013
FIGURE 23-13:
DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS
BIT_CLK
(CSCK)
CS61
CS60
CS62
CS21
CS20
CS71
CS70
CS72
SYNC
(COFS)
CS76
CS75
CS80
SDO
(CSDO)
MSb
LSb
LSb
CS76
CS75
MSb IN
SDI
(CSDI)
CS65 CS66
TABLE 23-26: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
CS60
CS61
CS62
CS65
CS66
CS70
CS71
CS72
CS75
CS76
CS77
CS78
CS80
Note
Symbol
Characteristic(1)(2)
Min
Typ(3)
Max
Units
Conditions
TBCLKL
TBCLKH
TBCLK
TSACL
BIT_CLK Low Time

36
40.7
45
ns
BIT_CLK High Time

36
40.7
45
ns
BIT_CLK Period
81.4
ns
Bit clock is input
Input Setup Time to
10
ns
Falling Edge of BIT_CLK

THACL
Input Hold Time from
10
ns
Falling Edge of BIT_CLK

TSYNCLO SYNC Data Output Low Time
19.5
s
Note 1
1.3
s
Note 1
TSYNCHI SYNC Data Output High Time
SYNC Data Output Period
20.8
s
Note 1
TSYNC
TRACL
Rise Time, SYNC, SDATA_OUT
10
25
ns
CLOAD = 50 pF, VDD = 5V
TFACL
Fall Time, SYNC, SDATA_OUT
10
25
ns
Rise Time, SYNC, SDATA_OUT
TBD
TBD
ns
TRACL
Fall Time, SYNC, SDATA_OUT
TBD
TBD
ns
TFACL
15
ns
TOVDACL Output valid delay from rising

edge of BIT_CLK
1: These parameters are characterized but not tested in manufacturing.
2: These values assume BIT_CLK frequency is 12.288 MHz.
3: Data in Typ column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and
are not tested.
DS70116D-page 190
Preliminary
dsPIC30F5011/5013
FIGURE 23-14:
SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
BIT14 - - - - - -1
MSb
SDOx
SP31
SDIx
LSb
SP30
MSb IN
LSb IN
BIT14 - - - -1
SP40 SP41
TABLE 23-27: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
ns
TscL
SCKX Output Low Time(3)
TCY / 2
SP11
TscH
SCKX Output High
Time(3)
TCY / 2
ns
SP20
TscF
SCKX Output Fall Time(4
10
25
ns
SP21
TscR
SCKX Output Rise Time(4)
10
25
ns
SP30
TdoF
SDOX Data Output Fall Time(4)
10
25
ns
SP10
(4)
SP31
TdoR
SDOX Data Output Rise Time
10
25
ns
SP35
TscH2doV,
TscL2doV
SDOX Data Output Valid after

SCKX Edge
30
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIX Data Input

to SCKX Edge
20
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIX Data Input

to SCKX Edge
20
ns
Note 1:
2:
3:
4:

are not tested.
The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
Assumes 50 pF load on all SPI pins.
Preliminary
DS70116D-page 191
dsPIC30F5011/5013
FIGURE 23-15:
SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS

SP36
SCKX
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKX
(CKP = 1)
SP35
SDOX
BIT14 - - - - - -1
MSb
SP40
SDIX
LSb
SP30,SP31
MSb IN
BIT14 - - - -1
LSb IN
SP41
TABLE 23-28: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
TscL
SCKX output low time(3)
TCY / 2
ns
SP11
TscH
SCKX output high time(3)
TCY / 2
ns
10
25
ns
10
25
ns
10
25
ns
10
25
ns
time(4)
SP20
TscF
SCKX output fall
SP21
TscR
SCKX output rise time(4)

time(4)
SP30
TdoF
SDOX data output fall
SP31
TdoR
SDOX data output rise time(4)
SP35
TscH2doV, SDOX data output valid after

TscL2doV SCKX edge
30
ns
SP36
TdoV2sc, SDOX data output setup to

TdoV2scL first SCKX edge
30
ns
SP40
TdiV2scH, Setup time of SDIX data input

TdiV2scL to SCKX edge
20
ns
SP41
TscH2diL,
TscL2diL
20
ns
Note 1:
2:
3:
4:
Hold time of SDIX data input

to SCKX edge

are not tested.
The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not
DS70116D-page 192
Preliminary
dsPIC30F5011/5013
FIGURE 23-16:
SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP20
SP21
SP20
SP21
SCKX
(CKP = 1)
SP35
MSb
SDOX
LSb
BIT14 - - - - - -1
SP51
SP30,SP31
SDIX
MSb IN
SP40
BIT14 - - - -1
LSb IN
SP41
TABLE 23-29: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SCKX Input Low Time
30
ns
SP70
TscL
SP71
TscH
SCKX Input High Time
30
ns
SP20
TscF
SCKX Output Fall Time(3)
10
25
ns
10
25
ns
10
25
ns
Time(3)
SP21
TscR
SCKX Output Rise
SP30
TdoF
SDOX Data Output Fall Time(3)

SDOX Data Output Rise
Time(3)
SP31
TdoR
10
25
ns
SP35
TscH2doV, SDOX Data Output Valid after

TscL2doV SCKX Edge
30
ns
SP40
TdiV2scH, Setup Time of SDIX Data Input

TdiV2scL to SCKX Edge
20
ns
SP41
TscH2diL, Hold Time of SDIX Data Input

TscL2diL to SCKX Edge
20
ns
SP50
TssL2scH, SSX to SCKX or SCKX Input

TssL2scL
120
ns
SP51
TssH2doZ SSX to SDOX Output

Hi-Impedance(3)
10
50
ns
SP52
TscH2ssH SSX after SCK Edge

TscL2ssH
1.5 TCY +40
ns
Note 1:
2:

are not tested.
3:
Preliminary
DS70116D-page 193
dsPIC30F5011/5013
FIGURE 23-17:
SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS

SP60
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP20
SP21
SP20
SP21
SCKX
(CKP = 1)
SP35
SP52
MSb
SDOX
BIT14 - - - - - -1
LSb
SP30,SP31
SDIX
MSb IN
SP51
BIT14 - - - -1
LSb IN
SP41
SP40
DS70116D-page 194
Preliminary
dsPIC30F5011/5013
TABLE 23-30: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscL
SCKX Input Low Time
30
ns
SP71
TscH
SCKX Input High Time
30
ns
SP20
TscF
SCKX Output Fall Time(3)
10
25
ns
SP21
TscR
SCKX Output Rise Time(3)
10
25
ns
(3)
SP30
TdoF
SDOX Data Output Fall Time
10
25
ns
SP31
TdoR
SDOX Data Output Rise Time(3)
10
25
ns
SP35
TscH2doV, SDOX Data Output Valid after

TscL2doV SCKX Edge
30
ns
SP40
TdiV2scH, Setup Time of SDIX Data Input

TdiV2scL to SCKX Edge
20
ns
SP41
TscH2diL, Hold Time of SDIX Data Input

TscL2diL to SCKX Edge
20
ns
SP50
TssL2scH, SSX to SCKX or SCKX input

TssL2scL
120
ns
SP51
TssH2doZ SS to SDOX Output

Hi-Impedance(4)
10
50
ns
SP52
TscH2ssH SSX after SCKX Edge

TscL2ssH
1.5 TCY + 40
ns
SP60
TssL2doV SDOX Data Output Valid after

SSX Edge
50
ns
Note 1:
2:
3:
4:

are not tested.
The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not
Preliminary
DS70116D-page 195
dsPIC30F5011/5013
FIGURE 23-18:
I2C BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCL
IM31
IM34
IM30
IM33
SDA
Stop
Condition
Start
Condition
FIGURE 23-19:
I2C BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM20
IM21
IM11
IM10
SCL
IM11
IM26
IM10
IM25
IM33
SDA
In
IM40
IM40
IM45
SDA
Out
DS70116D-page 196
Preliminary
dsPIC30F5011/5013
TABLE 23-31: I2C BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Param
Symbol
No.
Min(1)
Max
Units
Conditions
TCY / 2 (BRG + 1)
ms
400 kHz mode
TCY / 2 (BRG + 1)
ms
1 MHz mode(2)
TCY / 2 (BRG + 1)
ms
Clock High Time 100 kHz mode
TCY / 2 (BRG + 1)
ms
400 kHz mode
TCY / 2 (BRG + 1)
ms
Characteristic
TLO:SCL Clock Low Time 100 kHz mode
IM10
THI:SCL
IM11
(2)
TCY / 2 (BRG + 1)
ms
100 kHz mode
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
100
ns
100 kHz mode
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
300
ns
100 kHz mode
250
ns
400 kHz mode
100
ns
1 MHz mode(2)
TBD
ns
100 kHz mode
ns
400 kHz mode
0.9
ms
1 MHz mode(2)
TBD
ns
100 kHz mode
TCY / 2 (BRG + 1)
ms
400 kHz mode
TCY / 2 (BRG + 1)
ms
1 MHz mode(2)
TCY / 2 (BRG + 1)
ms
100 kHz mode
TCY / 2 (BRG + 1)
ms
1 MHz mode
TF:SCL
IM20
TR:SCL
IM21
SDA and SCL

Fall Time
SDA and SCL

Rise Time
TSU:DAT Data Input

Setup Time
IM25
THD:DAT Data Input

Hold Time
IM26
TSU:STA
IM30
Start Condition
Setup Time
THD:STA Start Condition

Hold Time
IM31
TSU:STO Stop Condition

Setup Time
IM33
THD:STO Stop Condition
IM34
Hold Time
TAA:SCL
IM40
Output Valid
From Clock
TBF:SDA Bus Free Time
IM45
CB
IM50
Note 1:
2:
400 kHz mode
TCY / 2 (BRG + 1)
ms
1 MHz mode(2)
TCY / 2 (BRG + 1)
ms
100 kHz mode
TCY / 2 (BRG + 1)
ms
400 kHz mode
TCY / 2 (BRG + 1)
ms
1 MHz mode(2)
TCY / 2 (BRG + 1)
ms
100 kHz mode
TCY / 2 (BRG + 1)
ns
CB is specified to be
from 10 to 400 pF
CB is specified to be
from 10 to 400 pF
Only relevant for

repeated Start
condition
After this period the
first clock pulse is
generated
400 kHz mode
TCY / 2 (BRG + 1)
ns
1 MHz mode(2)
TCY / 2 (BRG + 1)
ns
100 kHz mode
3500
ns
400 kHz mode
1000
ns
(2)
1 MHz mode
ns
100 kHz mode
4.7
ms
400 kHz mode
1.3
ms
1 MHz mode(2)
TBD
ms
400
pF
Bus Capacitive Loading
Time the bus must be

free before a new
transmission can start
BRG is the value of the I2C Baud Rate Generator. Refer to Section 21 Inter-Integrated Circuit (I2C)
in the dsPIC30F Family Reference Manual.
Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
Preliminary
DS70116D-page 197
dsPIC30F5011/5013
FIGURE 23-20:
I2C BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCL
IS34
IS31
IS30
IS33
SDA
Stop
Condition
Start
Condition
FIGURE 23-21:
I2C BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS20
IS21
IS11
IS10
SCL
IS30
IS26
IS31
IS25
IS33
SDA
In
IS40
IS40
IS45
SDA
Out
DS70116D-page 198
Preliminary
dsPIC30F5011/5013
TABLE 23-32: I2C BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Param
No.
IS10
IS11
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
Symbol
TLO:SCL
THI:SCL
TF:SCL
TR:SCL
TSU:DAT
THD:DAT
TSU:STA
THD:STA
TSU:STO
THD:STO
Characteristic
Clock Low Time
Clock High Time
SDA and SCL

Fall Time
SDA and SCL
Rise Time
Data Input
Setup Time
Data Input
Hold Time
Start Condition
Setup Time
Start Condition
Hold Time
Stop Condition
Setup Time
Stop Condition
Hold Time
IS40
IS45
IS50
Note 1:
TAA:SCL
TBF:SDA
CB
Min
Max
Units
100 kHz mode
4.7
Device must operate at a

minimum of 1.5 MHz
400 kHz mode
1.3

minimum of 10 MHz.
1 MHz mode(1)
0.5
100 kHz mode
4.0

minimum of 1.5 MHz
400 kHz mode
0.6

minimum of 10 MHz
1 MHz mode(1)
0.5
100 kHz mode
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
100
ns
100 kHz mode
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
300
ns
100 kHz mode
250
ns
400 kHz mode
100
ns
1 MHz mode(1)
100
ns
100 kHz mode
ns
400 kHz mode
0.9
1 MHz mode(1)
0.3
100 kHz mode
4.7
400 kHz mode
0.6
1 MHz mode(1)
0.25
100 kHz mode
4.0
400 kHz mode
0.6
1 MHz mode(1)
0.25
100 kHz mode
4.7
400 kHz mode
0.6
1 MHz mode(1)
0.6
100 kHz mode
4000
ns
400 kHz mode
600
ns
1 MHz mode(1)
250
0
3500
1000
ns
1 MHz mode(1)
350
ns
100 kHz mode
4.7
400 kHz mode
1.3
1 MHz mode(1)
0.5
400
pF
Bus Capacitive
Loading
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
Only relevant for repeated

Start condition
After this period the first
clock pulse is generated
ns
Output Valid From 100 kHz mode

Clock
400 kHz mode
Bus Free Time
Conditions
ns
Time the bus must be free

before a new transmission
can start
Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
Preliminary
DS70116D-page 199
dsPIC30F5011/5013
FIGURE 23-22:
CXTX Pin
(output)
CAN MODULE I/O TIMING CHARACTERISTICS
New Value
Old Value
CA10 CA11
CXRX Pin
(input)
CA20
TABLE 23-33: CAN MODULE I/O TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol

Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
CA10
TioF
Port Output Fall Time
10
25
ns
CA11
TioR
Port Output Rise Time
10
25
ns
CA20
Tcwf
Pulse Width to Trigger

CAN Wakeup Filter
500
ns
Note 1:
2:

are not tested.
DS70116D-page 200
Preliminary
dsPIC30F5011/5013
TABLE 23-34: 12-BIT A/D MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of
VDD - 0.3
or 2.7
Lesser of
VDD + 0.3
or 5.5
AD02
AVSS
Module VSS Supply
VSS - 0.3
VSS + 0.3
AD05
VREFH
Reference Voltage High
AVDD
Reference Inputs
AD06
VREFL
Reference Voltage Low
AD07
VREF
Absolute Reference
Voltage
AD08
IREF
Current Drain
AD10
VINH-VINL Full-Scale Input Span
AVSS + 2.7
AVSS
AVDD - 2.7
AVSS - 0.3
AVDD + 0.3
200
.001
300
3
A
A
A/D operating
A/D off
VREFH
See Note
Analog Input
VREFL
AD11
VIN
Absolute Input Voltage
AVDD + 0.3
AD12
Leakage Current
AVSS - 0.3
0.001
0.610
VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V
Source Impedance =
2.5 k
AD13
Leakage Current
0.001
0.610

Source Impedance =
2.5 k
AD15
RSS
Switch Resistance
3.2K
AD16
CSAMPLE
Sample Capacitor
18
pF
AD17
RIN
Recommended Impedance
of Analog Voltage Source
AD20
Nr
Resolution
AD21
INL
Integral Nonlinearity
0.75
TBD
LSb

AD21A INL
Integral Nonlinearity
0.75
TBD
LSb

AD22
DNL
Differential Nonlinearity
0.5
< 1
LSb

AD22A DNL
Differential Nonlinearity
0.5
< 1
LSb

GERR
Gain Error
1.25
TBD
LSb

AD23A GERR
Gain Error
1.25
TBD
LSb

2.5K
DC Accuracy
AD23
Note 1:
12 data bits
bits
The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
Preliminary
DS70116D-page 201
dsPIC30F5011/5013
TABLE 23-34: 12-BIT A/D MODULE SPECIFICATIONS (CONTINUED)
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
EOFF
Offset Error
1.25
TBD
LSb

AD24A EOFF
Offset Error
1.25
TBD
LSb

AD25
Monotonicity(1)
AD26
CMRR
Common-Mode Rejection
TBD
dB
AD27
PSRR
Power Supply Rejection

Ratio
TBD
dB
AD28
CTLK
Channel to Channel
Crosstalk
TBD
dB
AD30
THD
Total Harmonic Distortion
dB
AD31
SINAD
Signal to Noise and

Distortion
TBD
dB
AD32
SFDR
Spurious Free Dynamic

Range
TBD
dB
AD33
FNYQ
Input Signal Bandwidth
50
kHz
AD34
ENOB
Effective Number of Bits
TBD
TBD
bits
AD24
Guaranteed
Dynamic Performance
Note 1:
The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
DS70116D-page 202
Preliminary
dsPIC30F5011/5013
FIGURE 23-23:
12-BIT A/D CONVERSION TIMING CHARACTERISTICS

(ASAM = 0, SSRC = 000)
AD50
ADCLK
Instruction
Execution
Set SAMP
Clear SAMP
SAMP
ch0_dischrg
ch0_samp
eoc
AD61
AD60
TSAMP
AD55
DONE
ADIF
ADRES(0)
1 - Software sets ADCON. SAMP to start sampling.

2 - Sampling starts after discharge period.
TSAMP is described in the dsPIC30F Family Reference Manual, Section 18.
3 - Software clears ADCON. SAMP to start conversion.
4 - Sampling ends, conversion sequence starts.
5 - Convert bit 11.
6 - Convert bit 10.
7 - Convert bit 1.
8 - Convert bit 0.
9 - One TAD for end of conversion.
Preliminary
DS70116D-page 203
dsPIC30F5011/5013
TABLE 23-35: 12-BIT A/D CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Clock Parameters
AD50
TAD
A/D Clock Period
AD51
tRC
A/D Internal RC Oscillator Period
667
ns
1.2
1.5
1.8
VDD = 3-5.5V (Note 1)
Conversion Rate
AD55
tCONV
Conversion Time
14 TAD
ns
AD56
FCNV
Throughput Rate
100
ksps
AD57
TSAMP
Sampling Time
1 TAD
ns
AD60
tPCS
Conversion Start from Sample

Trigger
AD61
tPSS
AD62
AD63
VDD = VREF = 5V
VDD = 3-5.5V source
resistance
RS = 0-2.5 k
Timing Parameters
Note 1:
2:
TAD
ns
Sample Start from Setting

Sample (SAMP) Bit
0.5 TAD
1.5 TAD
ns
tCSS
Conversion Completion to
Sample Start (ASAM = 1)
TBD
ns
tDPU
Time to Stabilize Analog Stage

from A/D Off to A/D On
TBD
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
DS70116D-page 204
Preliminary
dsPIC30F5011/5013
24.0
PACKAGING INFORMATION
24.1
Package Marking Information

64-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC30F
5011-30I/PT
0348017
80-Lead TQFP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
Note:
dsPIC30F5013
-30I/PT
0348017
Customer specific information*

Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard device marking consists of Microchip part number, year code, week code, and traceability code.
For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
Preliminary
DS70116D-page 205
dsPIC30F5011/5013
64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
2
1
B
n
CH x 45
A
c
A2
A1
(F)
Units
Dimension Limits
n
p
Number of Pins
Pitch
Pins per Side
Overall Height
Molded Package Thickness
Standoff
Foot Length
Footprint (Reference)
Foot Angle
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
n1
A
A2
A1
L
(F)
E
D
E1
D1
c
B
CH
MIN
.039
.037
.002
.018
0
.463
.463
.390
.390
.005
.007
.025
5
5
INCHES
NOM
64
.020
16
.043
.039
.006
.024
.039
3.5
.472
.472
.394
.394
.007
.009
.035
10
10
MAX
.047
.041
.010
.030
7
.482
.482
.398
.398
.009
.011
.045
15
15
MILLIMETERS*
NOM
64
0.50
16
1.00
1.10
0.95
1.00
0.05
0.15
0.45
0.60
1.00
0
3.5
11.75
12.00
11.75
12.00
9.90
10.00
9.90
10.00
0.13
0.18
0.17
0.22
0.64
0.89
5
10
5
10
MIN
MAX
1.20
1.05
0.25
0.75
7
12.25
12.25
10.10
10.10
0.23
0.27
1.14
15
15
* Controlling Parameter
Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-085
DS70116D-page 206
Preliminary
dsPIC30F5011/5013
80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
2
1
CH x 45
A
A2
A1
(F)
Units
Dimension Limits
n
p
Number of Pins
Pitch
Pins per Side
Overall Height
Molded Package Thickness
Standoff
Foot Length
Footprint (Reference)
Foot Angle
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
n1
A
A2
A1
L
(F)
E
D
E1
D1
c
B
CH
MIN
.039
.037
.002
.018
0
.541
.541
.463
.463
.004
.007
.025
5
5
INCHES
NOM
80
.020
20
.043
.039
.004
.024
.039
3.5
.551
.551
.472
.472
.006
.009
.035
10
10
MAX
.047
.041
.006
.030
7
.561
.561
.482
.482
.008
.011
.045
15
15
MILLIMETERS*
NOM
80
0.50
20
1.00
1.10
0.95
1.00
0.05
0.10
0.45
0.60
1.00
0
3.5
13.75
14.00
13.75
14.00
11.75
12.00
11.75
12.00
0.09
0.15
0.17
0.22
0.64
0.89
5
10
5
10
MIN
MAX
1.20
1.05
0.15
0.75
7
14.25
14.25
12.25
12.25
0.20
0.27
1.14
15
15
* Controlling Parameter
Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-092
Preliminary
DS70116D-page 207
dsPIC30F5011/5013
NOTES:
DS70116D-page 208
Preliminary
dsPIC30F5011/5013
INDEX
Numerics
12-bit Analog-to-Digital Converter (A/D) Module .............. 129
A
A/D .................................................................................... 129
Aborting a Conversion .............................................. 131
ADCHS Register ....................................................... 129
ADCON1 Register..................................................... 129
ADCON2 Register..................................................... 129
ADCON3 Register..................................................... 129
ADCSSL Register ..................................................... 129
ADPCFG Register..................................................... 129
Configuring Analog Port Pins.............................. 60, 133
Connection Considerations....................................... 133
Conversion Operation ............................................... 130
Effects of a Reset...................................................... 132
Operation During CPU Idle Mode ............................. 132
Operation During CPU Sleep Mode.......................... 132
Output Formats ......................................................... 132
Power-down Modes .................................................. 132
Programming the Sample Trigger............................. 131
Register Map............................................................. 134
Result Buffer ............................................................. 130
Sampling Requirements............................................ 131
Selecting the Conversion Clock ................................ 131
Selecting the Conversion Sequence......................... 130
AC Characteristics ............................................................ 178
Load Conditions ........................................................ 178
AC Temperature and Voltage Specifications .................... 178
AC-Link Mode Operation .................................................. 126
16-bit Mode ............................................................... 126
20-bit Mode ............................................................... 126
Address Generator Units .................................................... 35
Alternate Vector Table ........................................................ 45
Analog-to-Digital Converter. See A/D.
Assembler
MPASM Assembler................................................... 159
Automatic Clock Stretch...................................................... 94
During 10-bit Addressing (STREN = 1)....................... 94
During 7-bit Addressing (STREN = 1)......................... 94
Receive Mode ............................................................. 94
Transmit Mode ............................................................ 94
B
Bandgap Start-up Time
Requirements............................................................ 183
Timing Characteristics .............................................. 183
Barrel Shifter ....................................................................... 21
Bit-Reversed Addressing .................................................... 38
Example ...................................................................... 38
Implementation ........................................................... 38
Modifier Values Table ................................................. 39
Sequence Table (16-Entry)......................................... 39
Block Diagrams
12-bit A/D Functional ................................................ 129
16-bit Timer1 Module .................................................. 65
16-bit Timer2............................................................... 71
16-bit Timer3............................................................... 71
16-bit Timer4............................................................... 76
16-bit Timer5............................................................... 76
32-bit Timer2/3............................................................ 70
32-bit Timer4/5............................................................ 75
CAN Buffers and Protocol Engine............................. 108
DCI Module............................................................... 120

Dedicated Port Structure ............................................ 59
DSP Engine ................................................................ 18
dsPIC30F5011.............................................................. 8
dsPIC30F5013.............................................................. 9
External Power-on Reset Circuit .............................. 143
I2C .............................................................................. 92
Input Capture Mode.................................................... 79
Oscillator System...................................................... 137
Output Compare Mode ............................................... 83
Reset System ........................................................... 141
Shared Port Structure................................................. 60
SPI.............................................................................. 88
SPI Master/Slave Connection..................................... 88
UART Receiver......................................................... 100
UART Transmitter....................................................... 99
BOR Characteristics ......................................................... 177
BOR. See Brown-out Reset.
Brown-out Reset
Characteristics.......................................................... 176
Timing Requirements ............................................... 183
C
C Compilers
MPLAB C17.............................................................. 160
MPLAB C18.............................................................. 160
MPLAB C30.............................................................. 160
CAN Module ..................................................................... 107
Baud Rate Setting .................................................... 112
CAN1 Register Map.................................................. 114
CAN2 Register Map.................................................. 116
Frame Types ............................................................ 107
I/O Timing Characteristics ........................................ 200
I/O Timing Requirements.......................................... 200
Message Reception.................................................. 110
Message Transmission............................................. 111
Modes of Operation .................................................. 109
Overview................................................................... 107
CLKOUT and I/O Timing
Characteristics.......................................................... 181
Requirements ........................................................... 181
Code Examples
Data EEPROM Block Erase ....................................... 54
Data EEPROM Block Write ........................................ 56
Data EEPROM Read.................................................. 53
Data EEPROM Word Erase ....................................... 54
Data EEPROM Word Write ........................................ 55
Erasing a Row of Program Memory ........................... 49
Initiating a Programming Sequence ........................... 50
Loading Write Latches................................................ 50
Code Protection ................................................................ 135
Control Registers ................................................................ 48
NVMADR .................................................................... 48
NVMADRU ................................................................. 48
NVMCON.................................................................... 48
NVMKEY .................................................................... 48
Core Architecture
Overview..................................................................... 13
CPU Architecture Overview ................................................ 13
D
Data Accumulators and Adder/Subtractor .......................... 19
Data Space Write Saturation ...................................... 21
Overflow and Saturation ............................................. 19
Round Logic ............................................................... 20
Write Back .................................................................. 20
Preliminary
DS70116D-page 209
dsPIC30F5011/5013
Data Address Space ........................................................... 27
Alignment .................................................................... 30
Alignment (Figure) ...................................................... 30
Effect of Invalid Memory Accesses (Table)................. 30
MCU and DSP (MAC Class) Instructions Example..... 29
Memory Map ......................................................... 27, 28
Near Data Space ........................................................ 31
Software Stack ............................................................ 31
Spaces ........................................................................ 30
Width........................................................................... 30
Data Converter Interface (DCI) Module ............................ 119
Data EEPROM Memory ...................................................... 53
Erasing ........................................................................ 54
Erasing, Block ............................................................. 54
Erasing, Word ............................................................. 54
Protection Against Spurious Write .............................. 57
Reading....................................................................... 53
Write Verify ................................................................. 57
Writing ......................................................................... 55
Writing, Block .............................................................. 56
Writing, Word .............................................................. 55
DC Characteristics ............................................................ 166
BOR .......................................................................... 177
Brown-out Reset ....................................................... 176
I/O Pin Input Specifications ....................................... 174
I/O Pin Output Specifications .................................... 175
Idle Current (IIDLE) .................................................... 170
Low-Voltage Detect................................................... 175
LVDL ......................................................................... 176
Operating Current (IDD)............................................. 167
Power-Down Current (IPD) ........................................ 172
Program and EEPROM............................................. 177
Temperature and Voltage Specifications .................. 166
DCI Module
Bit Clock Generator................................................... 123
Buffer Alignment with Data Frames .......................... 124
Buffer Control ............................................................ 119
Buffer Data Alignment ............................................... 119
Buffer Length Control................................................ 124
COFS Pin.................................................................. 119
CSCK Pin.................................................................. 119
CSDI Pin ................................................................... 119
CSDO Mode Bit ........................................................ 125
CSDO Pin ................................................................. 119
Data Justification Control Bit ..................................... 123
Device Frequencies for Common Codec
CSCK Frequencies (Table)............................... 123
Digital Loopback Mode ............................................. 125
Enable....................................................................... 121
Frame Sync Generator ............................................. 121
Frame Sync Mode Control Bits ................................. 121
I/O Pins ..................................................................... 119
Interrupts ................................................................... 125
Introduction ............................................................... 119
Master Frame Sync Operation .................................. 121
Operation .................................................................. 121
Operation During CPU Idle Mode ............................. 126
Operation During CPU Sleep Mode .......................... 126
Receive Slot Enable Bits........................................... 124
Receive Status Bits ................................................... 125
Register Map............................................................. 127
Sample Clock Edge Control Bit................................. 123
Slave Frame Sync Operation .................................... 122
Slot Enable Bits Operation with Frame Sync ............ 124
Slot Status Bits.......................................................... 125
DS70116D-page 210
Synchronous Data Transfers .................................... 124

Timing Characteristics
AC-Link Mode................................................... 190
Multichannel, I2S Modes................................... 188
Timing Requirements
AC-Link Mode................................................... 190
Transmit Slot Enable Bits ......................................... 123
Transmit Status Bits.................................................. 125
Transmit/Receive Shift Register ............................... 119
Underflow Mode Control Bit...................................... 125
Word Size Selection Bits .......................................... 121
Demonstration Boards
PICDEM 1................................................................. 162
PICDEM 17............................................................... 162
PICDEM 18R ............................................................ 163
PICDEM 2 Plus......................................................... 162
PICDEM 3................................................................. 162
PICDEM 4................................................................. 162
PICDEM LIN ............................................................. 163
PICDEM USB ........................................................... 163
PICDEM.net Internet/Ethernet .................................. 162
Development Support ....................................................... 159
Device Configuration
Register Map ............................................................ 149
Device Configuration Registers
FBORPOR ................................................................ 147
FGS .......................................................................... 147
FOSC........................................................................ 147
FWDT ....................................................................... 147
Device Overview.................................................................. 7
Disabling the UART .......................................................... 101
Divide Support .................................................................... 16
Instructions (Table) ..................................................... 16
DSP Engine ........................................................................ 17
Multiplier ..................................................................... 19
Dual Output Compare Match Mode .................................... 84
Continuous Pulse Mode.............................................. 84
Single Pulse Mode...................................................... 84
E
Electrical Characteristics .................................................. 165
AC............................................................................. 178
DC ............................................................................ 166
Enabling and Setting Up UART
Setting Up Data, Parity and Stop Bit Selections ....... 101
Enabling the UART ........................................................... 101
Equations
A/D Conversion Clock............................................... 131
Baud Rate................................................................. 103
Bit Clock Frequency.................................................. 123
COFSG Period.......................................................... 121
Serial Clock Rate ........................................................ 96
Time Quantum for Clock Generation ........................ 113
Errata .................................................................................... 5
Evaluation and Programming Tools.................................. 163
Exception Sequence
Trap Sources .............................................................. 43
External Clock Timing Characteristics
Type A, B and C Timer ............................................. 184
External Clock Timing Requirements ............................... 179
Type A Timer ............................................................ 184
Type B Timer ............................................................ 185
Type C Timer ............................................................ 185
External Interrupt Requests ................................................ 45
Preliminary
dsPIC30F5011/5013
F
Fast Context Saving............................................................ 45
Flash Program Memory ...................................................... 47
I
I/O Pin Specifications
Input .......................................................................... 174
Output ....................................................................... 175
I/O Ports .............................................................................. 59
Parallel (PIO) .............................................................. 59
I2C 10-bit Slave Mode Operation ........................................ 93
Reception.................................................................... 94
Transmission............................................................... 94
I2C 7-bit Slave Mode Operation .......................................... 93
Reception.................................................................... 93
Transmission............................................................... 93
I2C Master Mode Operation ................................................ 95
Baud Rate Generator.................................................. 96
Clock Arbitration.......................................................... 96
Multi-Master Communication, Bus Collision
and Bus Arbitration ............................................. 96
Reception.................................................................... 95
Transmission............................................................... 95
I2C Master Mode Support ................................................... 95
I2C Module .......................................................................... 91
Addresses ................................................................... 93
Bus Data Timing Characteristics
Master Mode ..................................................... 196
Slave Mode ....................................................... 198
Bus Data Timing Requirements
Master Mode ..................................................... 197
Slave Mode ....................................................... 199
Bus Start/Stop Bits Timing Characteristics
Master Mode ..................................................... 196
Slave Mode ....................................................... 198
General Call Address Support .................................... 95
Interrupts..................................................................... 95
IPMI Support ............................................................... 95
Operating Function Description .................................. 91
Operation During CPU Sleep and Idle Modes ............ 96
Pin Configuration ........................................................ 91
Programmers Model................................................... 91
Register Map............................................................... 97
Registers..................................................................... 91
Slope Control .............................................................. 95
Software Controlled Clock Stretching (STREN = 1).... 94
Various Modes ............................................................ 91
I2S Mode Operation .......................................................... 126
Data Justification....................................................... 126
Frame and Data Word Length Selection................... 126
Idle Current (IIDLE) ............................................................ 170
In-Circuit Serial Programming (ICSP) ......................... 47, 135
Input Capture (CAPX) Timing Characteristics .................. 186
Input Capture Module ......................................................... 79
Interrupts..................................................................... 80
Register Map............................................................... 81
Input Capture Operation During Sleep and Idle Modes ...... 80
CPU Idle Mode............................................................ 80
CPU Sleep Mode ........................................................ 80
Input Capture Timing Requirements ................................. 186
Input Change Notification Module ....................................... 63
dsPIC30F5011 Register Map (Bits 15-8) .................... 63
dsPIC30F5011 Register Map (Bits 7-0) ...................... 63
dsPIC30F5013 Register Map (Bits 15-8) .................... 63
dsPIC30F5013 Register Map (Bits 7-0) ...................... 63
Instruction Addressing Modes ............................................ 35

File Register Instructions ............................................ 35
Fundamental Modes Supported ................................. 35
MAC Instructions ........................................................ 36
MCU Instructions ........................................................ 35
Move and Accumulator Instructions ........................... 36
Other Instructions ....................................................... 36
Instruction Set
Overview................................................................... 154
Summary .................................................................. 151
Internal Clock Timing Examples ....................................... 180
Interrupt Controller
Register Map .............................................................. 46
Interrupt Priority .................................................................. 42
Traps .......................................................................... 43
Interrupt Sequence ............................................................. 45
Interrupt Stack Frame................................................. 45
Interrupts ............................................................................ 41
L
Load Conditions................................................................ 178
Low Voltage Detect (LVD) ................................................ 146
Low-Voltage Detect Characteristics.................................. 175
LVDL Characteristics ........................................................ 176
M
Memory Organization .......................................................... 7
Core Register Map ..................................................... 31
Modes of Operation
Disable...................................................................... 109
Initialization............................................................... 109
Listen All Messages.................................................. 109
Listen Only................................................................ 109
Loopback .................................................................. 109
Normal Operation ..................................................... 109
Modulo Addressing ............................................................. 36
Applicability................................................................. 38
Incrementing Buffer Operation Example .................... 37
Start and End Address ............................................... 37
W Address Register Selection.................................... 37
MPLAB ASM30 Assembler, Linker, Librarian ................... 160
MPLAB ICD 2 In-Circuit Debugger ................................... 161
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator.................................................... 161
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator.................................................... 161
MPLAB Integrated Development Environment Software.. 159
MPLINK Object Linker/MPLIB Object Librarian ................ 160
N
NVM
Register Map .............................................................. 51
O
OC/PWM Module Timing Characteristics ......................... 187
Operating Current (IDD) .................................................... 167
Operating Frequency vs Voltage
dsPIC30FXXXX-20 (Extended) ................................ 166
Oscillator
Configurations .......................................................... 138
Fail-Safe Clock Monitor .................................... 140
Fast RC (FRC).................................................. 139
Initial Clock Source Selection ........................... 138
Low Power RC (LPRC)..................................... 139
LP Oscillator Control......................................... 138
Phase Locked Loop (PLL) ................................ 139
Preliminary
DS70116D-page 211
dsPIC30F5011/5013
Start-up Timer (OST) ........................................ 138
Operating Modes (Table) .......................................... 136
System Overview ...................................................... 135
Oscillator Selection ........................................................... 135
Oscillator Start-up Timer
Timing Requirements ................................................ 183
Output Compare Interrupts ................................................. 85
Output Compare Module..................................................... 83
Register Map............................................................... 86
Output Compare Operation During CPU Idle Mode............ 85
Output Compare Sleep Mode Operation............................. 85
P
Packaging Information ...................................................... 205
Marking ..................................................................... 205
Peripheral Module Disable (PMD) Registers .................... 148
PICkit 1 Flash Starter Kit................................................... 163
PICSTART Plus Development Programmer ..................... 161
Pinout Descriptions ............................................................. 10
PLL Clock Timing Specifications....................................... 180
POR. See Power-on Reset.
Port Write/Read Example.................................................... 60
PORTA
Register Map for dsPIC30F5013 ................................ 61
PORTB
Register Map for dsPIC30F5011/5013 ....................... 61
PORTC
PORTD
PORTF
PORTG
Register Map for dsPIC30F5011/5013 ....................... 62
Power Saving Modes ........................................................ 146
Idle ............................................................................ 147
Sleep......................................................................... 146
Sleep and Idle ........................................................... 135
Power-Down Current (IPD) ................................................ 172
Power-up Timer
PRO MATE II Universal Device Programmer ................... 161
Program Address Space ..................................................... 23
Construction ................................................................ 24
Data Access from Program Memory Using
Program Space Visibility ..................................... 26
Data Access From Program Memory Using
Table Instructions................................................ 25
Data Access from, Address Generation...................... 24
Data Space Window into Operation ............................ 27
Data Table Access (LS Word) .................................... 25
Data Table Access (MS Byte) ..................................... 26
Memory Map ............................................................... 23
Table Instructions
TBLRDH.............................................................. 25
TBLRDL .............................................................. 25
TBLWTH ............................................................. 25
TBLWTL.............................................................. 25
DS70116D-page 212
Program and EEPROM Characteristics............................ 177

Program Counter ................................................................ 14
Programmable .................................................................. 135
Programmers Model .......................................................... 14
Diagram ...................................................................... 15
Programming Operations.................................................... 49
Algorithm for Program Flash....................................... 49
Erasing a Row of Program Memory............................ 49
Initiating the Programming Sequence......................... 50
Loading Write Latches ................................................ 50
Protection Against Accidental Writes to OSCCON ........... 140
R
Reset ........................................................................ 135, 141
BOR, Programmable ................................................ 143
Brown-out Reset (BOR)............................................ 135
Oscillator Start-up Timer (OST) ................................ 135
POR
Operating without FSCM and PWRT................ 143
With Long Crystal Start-up Time ...................... 143
POR (Power-on Reset)............................................. 141
Power-on Reset (POR)............................................. 135
Power-up Timer (PWRT) .......................................... 135
Reset Sequence ................................................................. 43
Reset Sources ............................................................ 43
Reset Sources
Brown-out Reset (BOR).............................................. 43
Illegal Instruction Trap ................................................ 43
Trap Lockout............................................................... 43
Uninitialized W Register Trap ..................................... 43
Watchdog Time-out .................................................... 43
Reset Timing Characteristics............................................ 182
Reset Timing Requirements ............................................. 183
Run-Time Self-Programming (RTSP) ................................. 47
S
Simple Capture Event Mode............................................... 79
Buffer Operation ......................................................... 80
Hall Sensor Mode ....................................................... 80
Prescaler .................................................................... 79
Timer2 and Timer3 Selection Mode............................ 80
Simple OC/PWM Mode Timing Requirements ................. 187
Simple Output Compare Match Mode ................................ 84
Simple PWM Mode ............................................................. 84
Input Pin Fault Protection ........................................... 84
Period ......................................................................... 85
Software Simulator (MPLAB SIM) .................................... 160
Software Simulator (MPLAB SIM30) ................................ 160
Software Stack Pointer, Frame Pointer .............................. 14
CALL Stack Frame ..................................................... 31
SPI Module ......................................................................... 87
Framed SPI Support ................................................... 87
Operating Function Description .................................. 87
Operation During CPU Idle Mode ............................... 89
Operation During CPU Sleep Mode............................ 89
SDOx Disable ............................................................. 87
Slave Select Synchronization ..................................... 89
SPI1 Register Map...................................................... 90
SPI2 Register Map...................................................... 90
Master Mode (CKE = 0).................................... 191
Master Mode (CKE = 1).................................... 192
Slave Mode (CKE = 1).............................. 193, 194
Timing Requirements
Master Mode (CKE = 0).................................... 191
Master Mode (CKE = 1).................................... 192
Preliminary
dsPIC30F5011/5013
Slave Mode (CKE = 0) ...................................... 193
Slave Mode (CKE = 1) ...................................... 195
Word and Byte Communication .................................. 87
Status Bits, Their Significance and the Initialization
Condition for RCON Register, Case 1 ...................... 144
Status Bits, Their Significance and the Initialization
Condition for RCON Register, Case 2 ...................... 145
Status Register ................................................................... 14
Symbols Used in Opcode Descriptions............................. 152
System Integration ............................................................ 135
Register Map............................................................. 149
T
Table Instruction Operation Summary ................................ 47
Temperature and Voltage Specifications
AC ............................................................................. 178
DC............................................................................. 166
Timer1 Module .................................................................... 65
16-bit Asynchronous Counter Mode ........................... 65
16-bit Synchronous Counter Mode ............................. 65
16-bit Timer Mode....................................................... 65
Gate Operation ........................................................... 66
Interrupt....................................................................... 66
Operation During Sleep Mode .................................... 66
Prescaler..................................................................... 66
Real-Time Clock ......................................................... 66
Interrupts............................................................. 67
Oscillator Operation ............................................ 67
Register Map............................................................... 68
Timer2 and Timer3 Selection Mode .................................... 84
Timer2/3 Module ................................................................. 69
16-bit Timer Mode....................................................... 69
32-bit Synchronous Counter Mode ............................. 69
32-bit Timer Mode....................................................... 69
ADC Event Trigger...................................................... 72
Gate Operation ........................................................... 72
Interrupt....................................................................... 72
Operation During Sleep Mode .................................... 72
Register Map............................................................... 73
Timer Prescaler........................................................... 72
Timer4/5 Module ................................................................. 75
Register Map............................................................... 77
A/D Conversion
Low-speed (ASAM = 0, SSRC = 000) .............. 203
Bandgap Start-up Time............................................. 183
CAN Module I/O........................................................ 200
CLKOUT and I/O....................................................... 181
DCI Module
AC-Link Mode ................................................... 190
Multichannel, I2S Modes ................................... 188
External Clock........................................................... 178
I2C Bus Data
Master Mode ..................................................... 196
Slave Mode ....................................................... 198
I2C Bus Start/Stop Bits
Master Mode ..................................................... 196
Slave Mode ....................................................... 198
Input Capture (CAPX) ............................................... 186
OC/PWM Module ...................................................... 187
Oscillator Start-up Timer ........................................... 182
Output Compare Module........................................... 186
Power-up Timer ........................................................ 182
Reset......................................................................... 182
SPI Module
Master Mode (CKE = 0).................................... 191
Master Mode (CKE = 1).................................... 192
Slave Mode (CKE = 0)...................................... 193
Slave Mode (CKE = 1)...................................... 194
Type A, B and C Timer External Clock..................... 184
Watchdog Timer ....................................................... 182
Timing Diagrams
CAN Bit..................................................................... 112
Frame Sync, AC-Link Start of Frame ....................... 122
Frame Sync, Multi-Channel Mode ............................ 122
I2S Interface Frame Sync ......................................... 122
PWM Output ............................................................... 85
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ..................... 142
(MCLR Not Tied to VDD), Case 2 ..................... 142
(MCLR Tied to VDD) ......................................... 142
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy .............. 180
Timing Diagrams.See Timing Characteristics
Timing Requirements
A/D Conversion
Low-speed ........................................................ 204
Bandgap Start-up Time ............................................ 183
Brown-out Reset....................................................... 183
CAN Module I/O ....................................................... 200
CLKOUT and I/O ...................................................... 181
DCI Module
AC-Link Mode................................................... 190
External Clock .......................................................... 179
I2C Bus Data (Master Mode) .................................... 197
I2C Bus Data (Slave Mode) ...................................... 199
Input Capture............................................................ 186
Oscillator Start-up Timer........................................... 183
Output Compare Module .......................................... 186
Power-up Timer ........................................................ 183
Reset ........................................................................ 183
Simple OC/PWM Mode ............................................ 187
SPI Module
Master Mode (CKE = 0).................................... 191
Master Mode (CKE = 1).................................... 192
Slave Mode (CKE = 0)...................................... 193
Slave Mode (CKE = 1)...................................... 195
Type A Timer External Clock.................................... 184
Type B Timer External Clock.................................... 185
Type C Timer External Clock.................................... 185
Watchdog Timer ....................................................... 183
Timing Specifications
PLL Clock ................................................................. 180
Trap Vectors ....................................................................... 44
U
UART Module
Address Detect Mode ............................................... 103
Auto Baud Support ................................................... 104
Baud Rate Generator ............................................... 103
Enabling and Setting Up........................................... 101
Framing Error (FERR) .............................................. 103
Idle Status................................................................. 103
Loopback Mode ........................................................ 103
Operation During CPU Sleep and Idle Modes.......... 104
Preliminary
DS70116D-page 213
dsPIC30F5011/5013
Overview ..................................................................... 99
Parity Error (PERR) .................................................. 103
Receive Break........................................................... 103
Receive Buffer (UxRXB) ........................................... 102
Receive Buffer Overrun Error (OERR Bit) ................ 102
Receive Interrupt....................................................... 102
Receiving Data.......................................................... 102
Receiving in 8-bit or 9-bit Data Mode........................ 102
Reception Error Handling.......................................... 102
Transmit Break.......................................................... 102
Transmit Buffer (UxTXB)........................................... 101
Transmit Interrupt...................................................... 102
Transmitting Data...................................................... 101
Transmitting in 8-bit Data Mode................................ 101
Transmitting in 9-bit Data Mode................................ 101
UART1 Register Map ................................................ 105
UART2 Register Map ................................................ 105
DS70116D-page 214
UART Operation
Idle Mode .................................................................. 104
Sleep Mode .............................................................. 104
Unit ID Locations .............................................................. 135
Universal Asynchronous Receiver Transmitter (UART) Module ............................................................................... 99
W
Wake-up from Sleep ......................................................... 135
Wake-up from Sleep and Idle ............................................. 45
Watchdog Timer
Timing Requirements................................................ 183
Watchdog Timer (WDT)............................................ 135, 146
Enabling and Disabling ............................................. 146
Operation .................................................................. 146
WWW, On-Line Support ....................................................... 5
Preliminary
dsPIC30F5011/5013
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Internet Explorer. Files are also available for FTP
download from our FTP site.
SYSTEMS INFORMATION AND

UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits.The Hot Line
Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet

Web Site
042003
The Microchip web site is available at the following

URL:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Latest Microchip Press Releases
Technical Support Section with Frequently Asked
Questions
Design Tips
Device Errata
Job Postings
Microchip Consultant Program Member Listing
Links to other useful web sites related to
Microchip Products
Conferences for products, Development Systems,
technical information and more
Listing of seminars and events
Preliminary
DS70116D-page 215
dsPIC30F5011/5013
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
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RE:
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Total Pages Sent ________
From: Name
Company
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City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: dsPIC30F5011/5013
N
Literature Number: DS70116D
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS70116D-page 216
Preliminary
dsPIC30F5011/5013
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
d s P I C 3 0 F 5 0 1 3 AT- 3 0 I / P T- E S
Custom ID (3 digits) or
Engineering Sample (ES)
Trademark
Architecture
PT
PT
S
W
Flash
Memory Size in Bytes
0 = ROMless
1 = 1K to 6K
2 = 7K to 12K
3 = 13K to 24K
4 = 25K to 48K
5 = 49K to 96K
6 = 97K to 192K
7 = 193K to 384K
8 = 385K to 768K
9 = 769K and Up
=
=
=
=
Package
TQFP 10x10
TQFP 12x12
Die (Waffle Pack)
Die (Wafers)
Temperature
I = Industrial -40C to +85C
E = Extended High Temp -40C to +125C
Speed
20 = 20 MIPS
30 = 30 MIPS
Device ID
T = Tape and Reel

A,B,C = Revision Level
Example:
dsPIC30F5013AT-30I/PT = 30 MIPS, Industrial temp., TQFP package, Rev. A
Preliminary
DS70116D-page 217
WORLDWIDE SALES AND SERVICE

AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
480-792-7627
Web Address:
www.microchip.com
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
India - New Delhi

Tel: 91-11-5160-8632
Fax: 91-11-5160-8632
Austria - Weis
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark - Ballerup
Tel: 45-4420-9895
Fax: 45-4420-9910
China - Chengdu
Tel: 86-28-8676-6200
Fax: 86-28-8676-6599
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Fax: 81-45-471-6122
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Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
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Tel: 86-591-750-3506
Fax: 86-591-750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Germany - Ismaning
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
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Fax: 978-692-3821
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Tel: 248-538-2250
Fax: 248-538-2260
China - Hong Kong SAR

Tel: 852-2401-1200
Fax: 852-2401-3431
China - Shanghai
Tel: 86-21-6275-5700
Fax: 86-21-6275-5060
China - Shenzhen
Tel: 86-755-8290-1380
Fax: 86-755-8295-1393
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
China - Qingdao
Tel: 86-532-502-7355
Fax: 86-532-502-7205
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Kaohsiung
Tel: 886-7-536-4816
Fax: 886-7-536-4817
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
England - Berkshire
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Taiwan - Hsinchu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
San Jose
Mountain View, CA
Tel: 650-215-1444
Fax: 650-961-0286
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
08/24/04
DS70116D-page 218
Preliminary

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2004 Microchip Technology Inc.

Information contained in this publication regarding device

Microchip received ISO/TS-16949:2002 quality system certification for

2004 Microchip Technology Inc.

High Performance Modified RISC CPU:

Modified Harvard architecture

2004 Microchip Technology Inc.

Special Microcontroller Features:

Fail-Safe Clock Monitor operation:

Low power, high speed Flash technology

dsPIC30F5011/5013 Controller Family

2004 Microchip Technology Inc.

For descriptions of individual pins, see Section 1.0.

2004 Microchip Technology Inc.

For descriptions of individual pins, see Section 1.0.

2004 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

2004 Microchip Technology Inc.

2004 Microchip Technology Inc.

Note: This data sheet summarizes features of this group

2004 Microchip Technology Inc.

This document contains specific information for the

dsPIC30F5011 BLOCK DIAGRAM

PSV & Table

PCU PCH PCL

2004 Microchip Technology Inc.

dsPIC30F5013 BLOCK DIAGRAM

PSV & Table

PCU PCH PCL

2004 Microchip Technology Inc.

PINOUT I/O DESCRIPTIONS

Input change notification inputs.

Data Converter Interface Frame Synchronization pin.

CAN1 Bus Receive pin.

ICD Primary Communication Channel data input/output pin.

Capture inputs 1 through 8.

Master Clear (Reset) input or programming voltage input. This

Compare Fault A input (for Compare channels 1, 2, 3 and 4).

Positive supply for analog module.

Low Voltage Detect Reference Voltage input pin.

CMOS = CMOS compatible input or output

Analog = Analog input

2004 Microchip Technology Inc.

PINOUT I/O DESCRIPTIONS (CONTINUED)

Oscillator crystal input. ST buffer when configured in RC mode;

In-Circuit Serial Programming data input/output pin.

PORTA is a bidirectional I/O port.

PORTB is a bidirectional I/O port.

PORTC is a bidirectional I/O port.

PORTD is a bidirectional I/O port.

PORTF is a bidirectional I/O port.

PORTG is a bidirectional I/O port.

Synchronous serial clock input/output for SPI1.

Synchronous serial clock input/output for I2C.

Timer1 external clock input.

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.