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ClockTree ProgrammingAssignment1

This document provides instructions for programming assignment 1 on constructing a zero skew rectilinear clock tree. Students are asked to implement an algorithm to take as input a 4x3 matrix representing the x,y coordinates and load capacitances of clock sinks. The code should use R.T. Say's exact zero skew clock routing algorithm to plot the optimal clock tree that minimizes total wirelength while ensuring zero skew. It should also calculate and display the clock latency from the root to sinks using the Elmore delay model, as well as the total wirelength of the tree. Sample input and output are provided. Students must submit their code along with a report explaining the algorithm and outputs for test cases.

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soumya
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42 views2 pages

ClockTree ProgrammingAssignment1

This document provides instructions for programming assignment 1 on constructing a zero skew rectilinear clock tree. Students are asked to implement an algorithm to take as input a 4x3 matrix representing the x,y coordinates and load capacitances of clock sinks. The code should use R.T. Say's exact zero skew clock routing algorithm to plot the optimal clock tree that minimizes total wirelength while ensuring zero skew. It should also calculate and display the clock latency from the root to sinks using the Elmore delay model, as well as the total wirelength of the tree. Sample input and output are provided. Students must submit their code along with a report explaining the algorithm and outputs for test cases.

Uploaded by

soumya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Clock Tree synthesis

Fall 2016-17
Issue date: 2nd Sept 2016, submission date: Sept. 18, 2016)

Programming Assignment-1

Construct a zero skew rectilinear clock tree using R.Tsays exact zero skew clock routing algorithm.
Your code will take 4-by-3 matrix as input where each row represents clock sink information-1st column
is x-co-ordinate of sink,2nd column is y-coordinate of sink and 3rd column is load capacitance at sink.
Your code will form the exact zero skew clock tree and plot it.Your code should also find delay(clock
latency) from the root source(Zero skew point) to the sinks using elmore delay-model and display it in
command window.Your code should also display the total length of the clock tree.
Parameters:
Resistance of wire = 0.1 /unit
Capacitance of wire = 0.2 F/unit
Example: Suppose we want to form zero skew clock tree for 4 points
A(8,0) having a capacitance of 16F,
B(22,6) having a capacitance of 10F,
C(0,10) having a capacitance of 1F and
D(5,15) having a capacitance of 2F
Your code when executed should ask for an input matrix.For the above points,input matrix will be
8
0 16
22 6 10
0 10 1
5 15 2
Legal values: Assume a grid size of 25 by 25.i.e the first 2 columns can take values between 1 and 25.
Lets assume capacitance varies between 1F and 25 F i.e legal value for third column is any value between
1 and 25.
When this matrix is given as input, your code should plot the exact zero skew clock tree as shown below:

>> clock latency from root to sinks = __ units

>> Total wirelength= __ units


Note:
1)Your code should use an appropriate algorithm to find the grouping of sinks so that the total wirelength
of the clock tree is minimized. Marks will be reduced for clock trees which are not optimised in terms of
wirelength.
2)Your code should be able to handle highly unbalanced load capacitance using appropriate wire snaking
i.e x<0 and x>1 cases

Submission guidelines:
1.Implement the algorithm in any high level language like MATLAB/C/Python
2.Each student should do the assignment individually.
3. A report(pdf format) should be uploaded with the pseudo code/flowchart i.e the brief sequence of steps
describing how the algorithm is implemented. Also attach the output of your code for some sample
testcases.
Weightage- 10%
Plagiarism in code will be checked by MOSS(Measure of software similarity)

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