EE241 - Spring 2005

Advanced Digital Integrated

Circuits
Lectures 4 and 5:
Delay Modeling

ISSCC 2005
Keynotes (Monday Morning)
Nanoelectronics for the Ubiquitous Information Society,
Daeje Chin, Minister of Information and Communications, Korea
Ambient Intelligence: Broad Dreams and Nanoscale
Realities, Hugo De Man, IMEC, Katholieke Universiteit Leuven,
Belgium
Innovation and Integration in the Nanoelectronics Era, Sunlin
Chou, Intel, Hillsboro, OR

Interesting Short Courses (on Su)

Memory forum
When processors hit the power wall
3d Integration
2

Interesting Sessions
Mo
Non-Volatile Memories
Multimedia Processing

Tu
High-speed links and clock generators
Microprocessors and Signal processing
Low-Power wireless and advanced integration
Clock distribution and power control
High-speed interconnects and building blocks

We
Processor building blocks
PLL, DLL and VCOs
DRAM
SRAM
Clocking and I/O

Some other stuff

Panels:
Mo: Towards the Nanoscale transistor
Tu: SRAM Design in the Nanoscale Era

Th Circuit Design Forum

Robust Design for Nanoscale circuits

Projects
Projects info
Target benchmark: ultra low-power 8051 microcontroller (and its components)
Some interesting projects:
Ultra low-power clock dividers/multipliers
Sub-threshold design versus low-threshold design
Low-current voltage converters/multipliers
Design techniques for self-calibration
Energy recovery and reversible computing
The return of current-driven logic
Error-resilient circuits and architectures
Small-granularity self-timing / asynchronous

Device Models

K(VGS VTHZ) Model

Drain current vs. gate-source voltage
8.0E-04

IDS [A]

6.0E-04

4.0E-04

2.0E-04

0.0E+00
0

0.2

0.4

VTHZ

0.6

0.8

1.2

V GS [V]

Transistor Leakage
-3

log IDS [log A]

-4
-5
-6

Subthreshold slope
-7
-8
-9
0

0.2

0.4

0.6

0.8

V GS [V]

Leakage current is exponential with VGS

1.2

VDS = 1.2V
8

Transistor Leakage

Transistor Leakage
8

IDS [nA]

0
0

0.2

0.4

0.6

0.8

1.2

1.4

V DS [V]

Two effects:
diffusion current (like a bipolar transistor)
exponential increase with VDS (DIBL)

10

Subthreshold Current
Subthreshold behavior can be modeled physically

W
I ds =
L

V V
Vds
2 g Th

kT m kT q
kT q
e
1 e

[Taur, Ning]

Or:
W
10
I ds = I 0
W0

(Vgs VTh )+ Vds

S

11

Leakage Components

Courtesy of IEEE Press, New York. 2000

12

Leakage Components
1.

pn junction reverse bias current

2.

Weak inversion

3.

Drain-induced barrier lowering (DIBL)

4.

Gate-induced drain leakage (GIDL)

5.

Punchthrough

6.

Narrow width effect

7.

Gate oxide tunneling

8.

Hot carrier injection

13

Leakage Components
Drain-induced barrier lowering (DIBL)
Voltage at the drain lowers the source potential barrier
Lowers VTh, no change on S

Gate-induced drain leakage (GIDL)

High field between gate and drain increases injection of carriers
into substrate -> leakage
(band-to-band leakage)

14

DIBL, GIDL, Weak Inversion

15
Courtesy of IEEE Press, New York. 2000

Stack Effect
NAND gate:

Reduction:

16
Courtesy of IEEE Press, New York. 2000

MOS Transistor as a Switch

Discharging a capacitor
Can solve:

iD = iD (vDS )
dV
iD = C DS
dt
Prefer using equivalent
resistances

17

MOS Transistor as a Switch

Traversed path

18

MOS Transistor as a Switch

Solving the integral:

with appropriately calculated Idsat

Averaging resistances:

19

Equivalent Resistance

W/L=1, L=0.25

20

10

CMOS Performance
Propagation delay: t pHL = (ln 2 )ReqnC L

t pLH = (ln 2)ReqpC L

ln2 = 0.7

Short channel

Long channel

Req f (VDD )

Req

1
VDD

for VDD >> VT

21

MOS Capacitances
Gate Capacitance

Overlap Capacitance
CGSO = CGDO
= CoxxdW
= CoW
22

11

MOS Capacitances
Gate capacitance
Non-linear channel capacitance
Linear overlap, fringing capacitances
Miller effect on overlap capacitance

Non-linear drain diffusion capacitance

PN junction

Wiring capacitances
Linear

23

Gate Capacitance

24

12

MOS Capacitances

0.25m process

25

Gate and Drain Capacitances

1.80E-15

0.13um Cgs/um vs. Vgs

1.8E-15

1.60E-15

1.6E-15

Cdb (F)

2.00E-15
2.0E-15

0.13um Cdb/um vs. Vds

NMOS VGS=0
PMOS VGS=0

1.40E-15

1.4E-15

1.20E-15

1.0E-15

1.00E-15
Cgs [F]

1.2E-15

8.0E-16
6.0E-16

8.00E-16
NMOS VDS=VDD

4.0E-16

6.00E-16

PMOS VDS=VDD

4.00E-16

NMOS VDS=0

2.0E-16

Vgs [V]

PMOS VDS=0

2.00E-16

0.0E+00
0.0

0.4

0.8

1.2

Vds (V)

0.00E+00
0.0

Gate capacitance

0.4

0.8

1.2

Drain Capacitance
26

13

Gate Capacitances
Gate capacitance is non-linear
First order approximation with CoxWL (CoxL = 2fF/m)
This is an overestimation

Need to find the actual equivalent capacitance by

simulating it
Since this is a linear approximation of non-linear
function, it is valid only over the certain range
Different capacitances for HL, LH transitions and power
computation

Drain capacitance non-linearity compensates

But this changes with fanout
27

Gate Capacitance vs. VTh, VDD

Nose, Sakurai, ISLPED00

28

14

FO4 Inverter Delay

In

Shapes the
input slope to FO4

tp

FO4 load

Suppresses Miller
kickback

29

Calibrating Delays
Step RC delay model is a good first-order
approximation
Accuracy can be improved by including:
Slope effects
Non-linear capacitive loading
Signal arrival times
Wire models

30

15

Input Slope
Simulated vs. linear model

70

8
4
1

60

Delay [ps]

50

Driving gate
fanout

40
30
20
10
0
0

10

FanOut

31

Input slope
We can model the delay as tp = 0.7*RekvC
When driving with non-step input, the rise/fall time is absorbed
into Rekv
Rekv is different than one extracted straight from I-V

The output delay is linearly dependent on input

rise/fall time tp = 0.7RC + tS
= 0.17 in this example (~1/6)
The model is limited to a range of fanouts

More accurate delay models propagate two

quantities: delay and signal slope
Both can be modeled either as linear or table lookups
32

16

Standard Cell Library

Contains for each cell:
Functional information: cell = a *b * c
Timing information: function of
input slew
intrinsic delay
output capacitance
non-linear models used in tabular approach

Library

Physical footprint (area)

Power characteristics

Wire-load models - function of

Block size
Fan-out

[from K. Keutzer]
33

Synopsys Delay Models

Linear (CMOS2) delay model

34

17

Example Cell Timing

35

Delay Dependency on Edge Rate

36

18

Transition Time

Linear:

Piecewise
linear:

37

Cell Characterization

38

19

Synopsys Nonlinear Delay Model

Delay is a function of:

39

Synopsys Nonlinear Delay Model

40

20

Static Timing Analysis

Combinational
logic

Combinational
logic

Combinational
logic

clk

clk

clk

original circuit

Combinational
logic

[from K. Keutzer]

extracted block

41

Each Combinational Block

Arrival time in
green

.10

.05

f
.15

.20

B
1

Gate delay in
blue

.20

W
0

Interconnect
delay in red

.05 X

.20

.05

Whats the right mathematical

object to use to represent this
physical object?
[from K. Keutzer]
42

21

Problem formulation - 1
Use a labeled
.05
0
directed graph
A
W
G = <V,E>
.10 1
.05
Vertices represent 0 C
gates, primary inputs
.20
and primary outputs
B
1 .05
Edges represent
A
wires
Labels represent
delays
Now what do we do
with this?

X
.20
2
Z

.1

.20

X
2

1
W

.05

.20
2 .15

.2
1

f
.15

0
0

.20

[from K. Keutzer]
43

Problem formulation - Arrival Time

Arrival time A(v) for a node v is time when signal
arrives at node v
X
A(X)

dx z
A(Z)
Z

dY z

A(Y)
Y

A( ) = max (A(u) + du )
uFI( )

where du is delay from to u, FI() = {X,Y}, and = {Z}.

[from K. Keutzer]
44

22

Static Timing Analysis

Computing critical (longest) path delay
Longest path algorithm on DAG [Kirkpatrick, IBM Jo. R&D, 1966]

Used in most ASIC designs today

Limitations
False paths
Simultaneous arrival times

45

Signal Arrival Times

NAND gate:

46

23

Signal Arrival Times

NAND gate:

47

Simultaneous Arrival Times

NAND gate:

48

24

Impact of Arrival Times

Delay

A
B

Up to 25%

A arrives early

B arrives early

tA - tB
49

Optimization for Performance

Performance critical blocks
Start with a synthesized design
Easier to explore architectures
Easy to verify
Provides some level of performance optimization

Understand the limits of synthesized designs

50

25

Optimization for Performance

Options
Technology choice
CMOS, bipolar, BiCMOS, GaAs, Superconducting
Logic level optimizations
logic depth, network topology, fan-out, gate complexity
Circuit optimizations
logic style, transistor sizing
Physical optimization
implementation choice, layout strategy
Do not ignore wiring!!
51

Logic Level Optimizations

Logic Depth
or

Techniques: Restructuring, pipelining, retiming, technology mapping

Well covered by todays logic and sequential synthesis

52

26

Logic Optimizations (2)

Late arriving

Fanout
Tp = O(FO)
also effects wiring capacitance
Technique: Removal of common sub-expression
Start from tree structure/output

53

Logic Optimizations (3)

4.0
tpHL

tp (nsec)

3.0

Fanin
Tp = O(FI2) !

2.0

tp

quadratic

Observation: only true if FI

translates in series devices -

1.0
linear

0.0

5
fan-in

tpLH

otherwise linear
e.g. NAND pull-down

NOR pull-up

AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

54

27

Logic Optimizations (4)

tpNOR

t pINV

tp (psec)

tpNAND

Slope is a function
of driving strength
F(Fan-in)
1

3
4
Fan-out

All the gates have the same drive current

55

Technology Mapping for Performance

Alternative coverings

Use low FI modules on critical path(s)

Library composition?

56

28