1 Leda General Coding Rules
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krishna chaitanya1 Leda General Coding Rules
Uploaded by
krishna chaitanya9/7/2016
1LedaGeneralCodingRules
1
LedaGeneralCodingRules
Introduction
ThischapterpresentsdetailedreferenceinformationabouttherulescontainedintheLedageneral
codingguidelinespolicyfortheLedaCheckertool.Thispolicyspecifiesgeneralpurposerulesand
guidelinesthatcovermanyaspectsofHDLcoding.
Someoftheerrormessageslistedinthischaptercorrespondtotherulesastheyaredeliveredand
configuredbySynopsys.Thesemessagesdonotapplyifyouchangetheconfigurationoftherules.
Thismainlyappliestotherulesfornamingconventions,wheretheerrormessages,assetby
Synopsys,containthenamingconventionsthemselves.Youcanchangetheerrormessageswhen
configuringruleswiththeRuleConfigurationWizard.
FiniteStateMachineRecognition
SeveraloftherulesintheLedapolicyconcernfinitestatemachines.Ledacaninferfinitestate
machines(FSMs)fromadesignandapplyrulestoconstrainthetypeofFSMaccepted.Ledacan
identifyFSMsthataredevelopedusingcasestatementstodefinethestatesandtransitions.Leda
doesnotrecognizeFSMsdefinedusingifstatements.Ledarecognizes1process,2process,and3
processFSMsaslongasallprocessesareinthesameblock(architectureormodule).
Therulesaregroupedintothefollowingrulesets,eachofwhichimposeconstraintsondifferent
aspectsoftheapplicablelanguage:
"DesignStructureRuleset"
"ClocksRuleset"
"ResetsRuleset"
"RTLSynthesisRuleset"
"DataTypesRuleset"
"ExpressionsRuleset"
"StatementsRuleset"
"B_3426"
"HDLLayoutRuleset"
"HDLNamingRuleset"
"RTLNamingRuleset"
"SystemVerilogRuleset"
Therulesprefixedby"B_"areverifiedattheblocklevel,whereastherulesprefixedby"C_"are
verifiedfortheentiredesign.
DesignStructureRuleset
Thefollowingrulesarefromthedesignstructureruleset:
B_1000
Message:Module/unitwithoutI/Os
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Thisrulechecksthatamoduleorunithasatleastoneport(input,outputor
Description inout).Rationale:asthefunctionalityofthismoduleorunitcannotbeused,all
instancesofthisdesignwillberemovedduringsynthesis.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofinvalidVerilogcode:
moduleB_1000_BAD()//FAIL:modulewithoutI/Os
wiretmp
regREG_TMP
endmodule
B_1001
Message:Readingfromanoutputport
TheCheckerverifiesthatnooutputportisusedasadriver.Rationale:whenthe
Description valueofanoutputisalsousedinternally,itisrecommendedtoaddabufferthat
isolatestheinternalloopfromtheoutside.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofinvalidVerilogcode,followedbyacircuitdiagramthatillustratesthe
problem:
moduleB_1001_1(A,B,CLK,A_REG,B_OUT)
inputA,B,CLK
outputA_REG,B_OUT
regA_REG
always@(posedgeCLK)begin
A_REG<=A
end
assignB_OUT=B&A_REG//OutputportsignalA_REGisread
endmodule
B_1002
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Message:Portdeclarationisunusedorpartiallyunused
TheCheckerverifiesthatallportsareusedatleastonetime.Usually,leavingports
Description unusedindicatesadesignerror.Youshouldremoveallunusedports(thiscanbe
acceptedforsomereuseorcompatibilityissues).
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofinvalidVHDLcode,followedbyacircuitdiagramthatillustratestheproblem:
libraryIEEE
useIEEE.std_logic_1164.all
entityB_1002_TESTis
port(CLK,RST,DATA_IN:instd_logic
UNUSED
:instd_logicUNUSEDisanunconnectedport
DATA_OUT:outstd_logic)
end
architectureRTLofB_1002_TESTis
begin
process(CLK,RST)begin
if(RST='0')then
DATA_OUT<='0'
elsif(CLK'eventandCLK='1')then
DATA_OUT<=DATA_IN
endif
endprocess
end
B_1005
Message:Nobidirectionalportallowed
TheCheckerdetectsallbidirectionalportinallmodules.Usingbidirectionalports
Description mayresultsinshortsthataredifficulttodetect.Itisbesttousebidirectionalports
onlywhenneeded.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Blocklevel
Severity
Error
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Example
ThisisanexampleofinvalidVHDLcode,followedbyacircuitdiagramthatillustratestheproblem:
libraryIEEE
useIEEE.std_logic_1164.all
entityB_1005is
port(CLK,RST:instd_logic
DATA_IN:inoutstd_logicDATA_INisdeclaredas
inout
DATA_OUT:outstd_logic)
end
architectureRTLofB_1005is
begin
process(CLK,RST)begin
if(RST='0')then
DATA_OUT<='0'
elsif(CLK'eventandCLK='1')then
DATA_OUT<=DATA_IN
endif
endprocess
end
B_1006
Message:Tristateareonlyallowedinspecifiedmodules/units
TheCheckerdetectsalltristatesdeclaredoutofthespecifiedmodule/unit.To
specifythemodule,usetheRuleConfigurationWizardandsupplythemodule/unit
Description nameinthevaluenodeoftherule.Thedefaultspecifiedmodule/unitnameis
"^TOP".Groupingthetristateelementsinagivenuniteasesthetesttasks(noneed
toparsethewholedesigntodetectthesestructures).
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofinvalidVerilogcode,followedbyacircuitdiagramthatillustratesthe
problem:
moduleB_1006_7(CLK,DATA_IN,EN,DATA_OUT)
inputCLK,DATA_IN,EN
outputDATA_OUT
regtmp
always@(posedgeCLK)begin
tmp<=DATA_IN
end
SUBU1(.A(tmp),.B(DATA_OUT),.EN(EN))
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endmodule
moduleSUB(A,B,EN)
inputA,EN
outputB
assignB=EN?A:1'bZ//Thistristateisnotinthetoplevel
//module
endmodule
B_1007
Message:Tristateportdetected
Description
Alltristateportsarereported.Becausetristateportsrequiremoreattentionduring
testing,reportingtheseportseasesthetestactivity.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofinvalidVHDLcode,followedbyacircuitdiagramthatillustratestheproblem:
libraryIEEE
useIEEE.1164.all
EntityB_1007is
Port(EN,RST,CLK,DATA_IN:std_logic
DATA_OUT:outstd_logic)
End
architectureRTLofB_1007is
signalTMP:std_logic
begin
process(EN,TMP)begin
if(EN='1')then
DATA_OUT<=TMP
else
DATA_OUT<='Z'tristateport(DATA_OUT)detected
endif
endprocess
process(CLK,RST)begin
if(RST='0')then
TMP<='0'
elsif(CLK'eventandCLK='1')then
TMP<=DATA_IN
endif
endprocess
end
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B_1008
Message:Tristatesignaldetected
Description
Alltristatesignalsarereported.Becausetristatesignalsrequiremoreattention
duringtesting,reportingthesesignalseasesthetestactivity.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofinvalidVHDLcode,followedbyacircuitdiagramthatillustratestheproblem:
libraryIEEE
useIEEE.std_logic_1164.all
entityB_1008is
port(DATA_IN,CLK,RST,EN:std_logic
DATA_OUT:outstd_logic)
End
architectureRTLofB_1008is
signalTMP:std_logic
begin
process(EN,DATA_IN)begin
if(EN='1')then
TMP<=DATA_IN
else
TMP<='Z'AssigningTMPto'Z'makeTMPbeinga
tristatesignall
endif
endprocess
process(CLK,RST)begin
if(RST='0')then
DATA_OUT<='0'
elsif(CLK'eventandCLK='1')then
DATA_OUT<=TMP
endif
endprocess
end
B_1009
Message:Tristateoutputdetected
Description
Alltristateoutputsarereported.Becausetristateportsrequiremoreattentionduring
testing,reportingtheseportseasesthetestactivity.
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Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofinvalidVHDLcode,followedbyacircuitdiagramthatillustratestheproblem:
libraryIEEE
useIEEE.std_logic_1164.all
entityB_1009is
port(DATA_IN,CLK,RST,EN:std_logic
DATA_OUT:outstd_logic)
End
architectureRTLofB_1009is
signalTMP:std_logic
begin
process(EN,DATA_IN)begin
if(EN='1')then
DATA_OUT<=TMP
else
DATA_OUT<='Z'AssigningDATA_OUTtoZmakesDATA_OUTbea
tristatesignal
endif
endprocess
process(CLK,RST)begin
if(RST='0')then
TMP<='0'
elsif(CLK'eventandCLK='1')then
TMP<=DATA_IN
endif
endprocess
end
B_1010
Message:Feedthroughdetected
Description
TheCheckerreportsfeedthroughinallunits.Feedthroughcancausetroubleduring
backendsteps.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
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Example
ThisisanexampleofinvalidVHDLcode,followedbyacircuitdiagramthatillustratestheproblem:
libraryIEEE
useIEEE.std_logic_1164.all
entityB_1010is
port(DATA_IN,RST,CLK,A_IN:std_logic
Q_OUT,DATA_OUT:outstd_logic)
End
architectureRTLofB_1010is
begin
DATA_OUT<=DATA_INFeedthroughfromDATA_INtoDATA_OUT
process(CLK,RST)begin
if(RST='0')thenPASS
Q_OUT<='0'
elsif(CLK'eventandCLK='1')then
Q_OUT<=A_IN
endif
endprocess
end
B_1011
Message:Moduleinstantiationisnotfullybounded
Description
TheCheckerverifiesthatduringaninstantiationallofaninstance'spinsare
connected.Leavinginputpinsunconnectedisnotrecommended.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofinvalidVerilogcode:
moduleB_1011_TOP(A,B,C)
inputA,B
outputC
SUB_B_1011U1(.A(A),.C(C))//PortBisnotconnected
endmodule
moduleSUB_B_1011(A,B,C)
inputA,B
output[1:0]C
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assignC=A+B
endmodule
B_1013
Message:Signalshouldnotdrivemultipleports
Description TheCheckerreportsthosesignalsthatdrivemultipleports.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_1014
Message:Parameter%shasbeendefinedbutisnotused
Description Ledaflagsthisrulewhenaparameter%sisdefinedbutisnotused.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
Verilog
Type
Blocklevel
Severity
Warning
B_1017
Message:DBcellshouldhavenamedportassociation
Description LedaflagsthisruleifDBcellsarenotassociatedbyports.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
Verilog
Type
Blocklevel
Severity
Warning
C_1000
Message:Asynchronousfeedbackloopdetected
TheCheckerreportsasynchronousfeedbackloopsinthedesign.Thisisachiplevel
Description check.Tocheckthisruleontheentiredesign,atopdesignunitmustbeprovided.
Asynchronousfeedbackloopscancreateinstabilityindesign.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
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Type
Chiplevel
Severity
Error
Example
Thefollowingcircuitdiagramillustratesanasynchronousfeedbackloopinadesign:
C_1001
Message:Flipflopwithfixedvaluedatainputisdetected
Thisruledetectsiftheinputofaflipflopistiedtoafixedvalue(groundorVCC).To
Description checkthisruleontheentiredesignyoumustspecifyatopdesignunitusingthetop
switch.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
C_1002
Message:Latchwithfixedvaluedatainputisdetected
Thisruledetectsiftheinputofalatchistiedtoafixedvalue(groundorVCC).To
Description checkthisruleontheentiredesignyoumustspecifyatopdesignunitusingthetop
switch.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
C_1003
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Message:Latchdetectedindesign(inferredorinstantiated)
Latchesaregenerallynotrecommendedbecausetheycauseproblemswithscan
insertionandtiminganalysis.Attheblocklevel,Ledaonlydetectslatchesinferredin
theRTLcode.Inotherwords,Ledainfersalatchwhenasignalisnotassignedonall
Description possibleflowsofcontrol.Thisruleworksatthedesign(chip)level,andnotonly
reportslatchesinferredattheblocklevel,butalsothoseinstantiatedin.dblibraries
(forexample).Thechiplevelapplicationofthisruleonlyworksifyouspecifythetop
levelofthedesignusingthetopswitch.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
Example
Thefollowingexamplesshowpoorandrecommendedcodingstylesifyouneedtouselatchesin
yourdesign
Poorcodingstyle:latchinferredbecauseofmissingelsecondition:
EX21_PROC:process(a,b)
begin
if(a='1')then
q<=b
endif
endprocessEX21_PROC
Poorcodingstyle:latchinferredbecauseofmissingzoutputassignment:
libraryIEEE
useIEEE.std_logic_1164.all
useIEEE.std_logic_arith.all
useIEEE.STD_LOGIC_UNSIGNED.conv_integer
entityc_1003is
port(c
:instd_logic
q,z:outstd_logic)
end
architecturearchofc_1003is
begin
EX22_PROC:process(c)begin
casecis
when'0'=>q<='1'z<='0'
whenothers=>q<='0'
endcase
endprocessEX22_PROC
endarchitecture
Poorcodingstyle:latchesinferredbecauseofmissingsoutputassignmentsforthe2'b00and
2'b01conditionsandamissing2'b11condition:
always@(d)
begin
case(d)
2'b00:z<=1'b1
2'b01:z<=1'b0
2'b10:z<=1'b1s<=1'b1
endcase
end
GuidelineYoucanavoidinferredlatchesbyusinganyofthefollowingcodingtechniques:
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Assigndefaultvaluesatthebeginningofaprocess,asshownforVHDLin
ExampleA.
Assignoutputsforallinputconditions,asshowninExampleB.
Useelse(insteadofelsif)forthefinalprioritybranch,asshownin
ExampleC.
ExampleA.Avoidingalatchbyassigningdefaultvalues.
COMBINATIONAL_PROC:process(state,bus_request)
begin
intitializeoutputstoavoidlatches
bus_hold<='0'
bus_interrupt<='0'
case(state)...
.................
.................
endprocessCOMBINATIONAL_PROC
ExampleB.Avoidingalatchbyfullyassigningoutputsforallinputconditions.
Poorcodingstyle:
EX25A_PROC:process(g,a,b)
begin
if(g='1')then
q<=0
elsif(a='1')then
q<=b
endif
endprocessEX25A_PROC
Recommendedcodingstyle:
EX25B_PROC:process(g1,g2,a,b)
begin
q<='0'
if(g1='1')then
q<=a
elsif(g2='1')then
q<=b
endif
endprocessEX25B_PROC
ExampleC.Avoidingalatchbyusingelseforthefinalprioritybranch(VHDL).
Poorcodingstyle:
MUX3_PROC:process(decode,A,B)
begin
if(decode='0')then
C<=A
elsif(decode='1')then
C<=B
endif
endprocessMUX3_PROC
Recommendedcodingstyle:
MUX3_PROC:process(decode,A,B)
begin
if(decode='1')then
C<=A
else
C<=B
endif
endprocessMUX3_PROC
IfyouMustuseaLatch
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Insomedesigns,usingalatchisabsolutelyunavoidable.Forexample,inaPCIdesign,theteam
foundthatitwasimpossibletocomplywiththePCIspecificationforresetbehaviorwithouthaving
alatchinthedesign.Inordertoachievetestability,theteamusedtheapproachshowninthe
followingcircuitdiagram.Theyusedamuxtoprovideeitherthenormalfunctionortheinputfrom
anI/Opadasdatatothemux.Themuxwasselectedbythetestmodepinusedtoenablescan.
Thefollowingcircuitdiagramshowshowtomakealatchtestable:
C_1004
Message:Gluelogicattoplevelisdetected
Description
Adesignhierarchyshouldcontaingatesonlyatleaflevelsofthehierarchytree.This
ruleonlyworksifyouspecifythetoplevelofthedesignusingthetopswitch.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
Example
ThefollowingcircuitdiagramshowsaninvaliddesignwhereaNANDgateexistsatthetoplevel,
betweentwolowerleveldesignblocks.Optimizationislimitedbecausesynthesistoolssuchas
DesignCompilercannotmergetheNANDwiththecombinationallogicinsideblockC.
ThisnextcircuitdiagramshowsavalidsimilardesignwheretheNANDgateisincludedaspartof
thecombinationallogicinblockC.ThisapproacheliminatestheextraCPUcyclesneededto
compilesmallamountsofgluelogicandprovidesforsimplersynthesisscriptdevelopment.An
automatedscriptmechanismonlyneedstocompileandcharacterizetheleaflevelcells.
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C_1005
Message:Topleveloutputsarenotregistered:%s
Registeralltopleveloutputs.Registeringthetopleveloutputsignalssimplifiesthe
synthesisprocessbecauseitmakesoutputdrivestrengthsandinputdelay
predictable.Alltheinputsarrivewiththesamerelativedelay.Outputdrivestrength
isequaltothedrivestrengthoftheaverageflipflop.Anothertechniqueistoregister
Description
thetoplevelinputports(seeruleC_1006).Thisrulefireswhensomecombinatorial
logic(insteadofaflipflop)driveatopleveloutputorantoplevelinputfeeds
directlytoatopleveloutput.Thisruleworksonlyifyouspecifythetoplevelofthe
designusingthetopswitch.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
Example
Thefollowingvalidexampleshowsahierarchicaldesigninwhichalloutputsignalsfromeachblock
areregisteredthatis,thereisnocombinationallogicbetweentheregistersandtheoutputports.
C_1006
Message:Toplevelinputsarenotregistered
Registeralltoplevelinputs.Registeringthetoplevelinputsignalssimplifiesthe
synthesisprocessbecauseitmakesinputcapacitancetheninputdelaypredictable.
Alltheinputsarrivewiththesamerelativedelay.Anothertechniqueistoregister
Description thetopleveloutputports(seeruleC_1005).Thisrulefireswhensomecombinatorial
logic(insteadofaflipflop)aretiedtoatoplevelinputorantoplevelinputfeeds
directlytoatopleveloutput.Thisruleworksonlyifyouspecifythetoplevelofthe
designusingthetopswitch.
Policy
Leda
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Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
Example
Thefollowingvalidexampleshowsahierarchicaldesigninwhichallinputsignalsfromeachblock
areregisteredthatis,thereisnocombinationallogicbetweentheinputportsandtheregisters.
C_1007
Message:PulseGeneratorDetected
Description
Thisruledetectssignalreconvergence,whichcreatesapulsesignalattheoutputof
agate.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Chiplevel
Severity
Warning
Example
Thefollowingcircuitdiagramillustratestheproblem.
C_1008
Message:Multipledriverstoasignaldetected
Eachsignalmusthaveatmostonedriver.Signalswithmultipledriversareoftenthe
resultofadesignerror.Ifneeded,thesesignalsmustbehandledcarefullywithatri
Description
statebuffer.Tocheckthisruleontheentiredesign,youmustspecifyatopdesign
unitusingthetopswitch.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Chiplevel
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Severity
Error
Example
ThisisanexampleofinvalidVHDLcode:
libraryIEEE
useIEEE.std_logic_1164.all
entityC_1008is
port(A,B,CLK,RST,DATA_IN
DATA_OUT
end
:std_logic
:outstd_logic)
architectureRTLofB_1003is
signalTMP:std_logicTMPsignalhasmultipledrivers
begin
TMP<=AandBFirstdriverforTMP
process(CLK,RST)begin
if(RST='0')thenPASS
TMP<='0'
elsif(CLK'eventandCLK='1')then
TMP<=DATA_INSeconddriverforTMP
endif
endprocess
DATA_OUT<=TMP
end
C_1009
Message:Multiplenontristatedriverstoasignaldetected
Eachsignalmusthaveatmostonedriver.Signalswithmultiplenontristatedrivers
areoftentheresultofadesignerror.Ifneeded,thesesignalsmustbehandled
Description
carefullywithatristatebuffer.Tocheckthisruleontheentiredesign.youmust
specifyatopdesignunitusingthetopswitch.
Policy
Leda
Ruleset
DESIGN_STRUCTURE
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
Example
ThisisanexampleofinvalidVHDLcode:
libraryIEEE
useIEEE.std_logic_1164.all
entityC_1009is
port(A,B,RST,CLK,DATA_IN
DATA_OUT
end
:std_logic
:outstd_logic)
architectureRTLofC_1009is
begin
DATA_OUT<=AandBFirstdriverforDATA_OUT
process(CLK,RST)begin
if(RST='0')thenPASS
DATA_OUT<='0'
elsif(CLK'eventandCLK='1')then
DATA_OUT<=DATA_INSeconddriverforDATA_OUT
endif
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endprocess
end
ClocksRuleset
Thefollowingrulesarefromtheclocksruleset:
B_1200
Message:Nestedeventcontrolinatask
Description
TheCheckerreportsanerrorwheneventcontrol(forexample,@(posedgeclk))is
nested.Nestedeventsarenotsupportedbysynthesistools.
Policy
Leda
Ruleset
CLOCKS
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofinvalidVerilogcodewithnestedeventcontrol:
tasktest
inputA,B,CLK_1,CLK_2
outputA_REG,B_REG
begin
@(posedgeCLK_1)begin
A_REG<=A
@(negedgeCLK_2)
B_REG<=B//FAIL:nestedeventintask
end
end
endtask
B_1201
Message:Multipleeventcontrolstatementinatask
Thischeckcontrolsthenumberofeventcontrolsinataskdeclaration.Youcan
Description configurethisrulewiththeRuleConfigurationWizardtoacceptmorethanoneevent
pertask.
Policy
Leda
Ruleset
CLOCKS
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofaVerilogcodewithmorethanoneeventcontrol:
tasktest
inputA,B,CLK_1,CLK_2
outputA_REG,B_REG
begin
@(posedgeCLK_1)
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A_REG<=A
@(negedgeCLK_2)//FAIL:Multipleeventcontrolintask
B_REG<=B
end
endtask
B_1202
Message:Multipleclocksinthisunitdetected
Thischeckcontrolsthenumberofclocksinaunit.Youcanconfigurethisrulewith
Description theRuleConfigurationWizardtoacceptmorethanoneclockperunit.Partitioning
thedesigninclockdomainseasesthesynthesis/timinganalysistask.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_1203
Message:Userisingedgeclockinthisunit
Thisrulechecksthatonlyrisingedgeflipflopareusedintheunit.Youcanconfigure
thisruleusingtheRuleConfigurationWizardinordertoacceptrisingedgeorfalling
Description
edge.Usingonlyoneedgeinthedesigneasesthescaninsertionprocessandgives
moreflexibilityforscanchaindefinition.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Error
B_1204
Message:Multibitexpressionusedasclock
Description
Thisrulechecksthataclocksignalisnotpartofabus.Usinga1bitsignalfora
clockeasestheclockmanagementprocessallalongthedesignflow.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL
Type
Blocklevel
Severity
Warning
B_1205
Message:Theclocksignalisnotcomingdirectlyfromaportofthecurrent
unit
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TheCheckerverifiesthatallclocksinaunitaredeclaredasportsignalsandnot
internallygeneratedeitherviacombinatoriallogicorsequentialpart.Internally
Description
generatedclocksmaynotbecontrollablefromtheboundaryofthechip.Thisreduces
testcoverage.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_1206
Message:Donotuseeventdefinitionsforclocks
Description
Thisrulechecksthateventdefinitionsarenotusedasclocks.Eventdeclarationsare
notsupportedbysynthesistools.
Policy
Leda
Ruleset
CLOCKS
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofinvalidVerilogcodethatusesaneventtogenerateaclock:
...
eventmy_event
...
always@(posedgemy_event)q<=d//Eventusedasaclock
...
B_1220
Message:Clockinconcurrentstatementotherthanprocessmaynotbe
synthesizable
Description
Thisrulechecksforthepresenceofclockinconcurrentstatementsotherthan
processstatements.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofaVerilogcodewithmorethanoneeventcontrol:
libraryieee
useieee.std_logic_1164.all
entityDFFis
Signalsareinitializedto0bydefault.
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TomakeQNa1,ithastobeinitialized
port(D,CLK:instd_logic
Q:outstd_logic
QN:outstd_logic:='1')
endDFF
architecturedata_flipofDFFis
begin
Q<=DwhenCLK'eventandCLK='1'
FAIL:Clockinconcurrentstatement
enddata_flip
B_1221
Message:Aclockingstyleisusedwhichmaynotbesynthesizable
Description ThisruleisflaggedwhenLedafindsaclockingstylethatmaynotbesynthesizable.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofaVerilogcodewithmorethanoneeventcontrol:
libraryieee
useieee.std_logic_1164.all
entityDFFis
Signalsareinitializedto0bydefault.
TomakeQNa1,ithastobeinitialized
port(D,CLK:instd_logic
Q:outstd_logic
QN:outstd_logic:='1')
endDFF
architecturedata_flipofDFFis
begin
process(CLK)
begin
if(CLK'stableandCLK'event)then
FAIL:Cunsynthesizableclockingstyle
Q<=Dafter10ns
QN<=notDafter10ns
endif
endprocess
enddata_flip
B_1222
Message:Multiplewaitstatementusingthesameclockexpression
Description
ThisruleisflaggedwhenLedafindsmultiplewaitstatementsinwhichthesame
clockexpressionisused.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL
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Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofaVerilogcodewithmorethanoneeventcontrol:
libraryIEEE
useIEEE.std_logic_1164.all
entitydffisport(
clk:inbit
Q1,Q2,Q3:inoutbit)
enddff
architecturedff_archofdffis
begin
Output:processbegin
Q1=notQ1
Waituntilclk='1'
Q2=notQ2
Waituntilclk='1'FAIL:Multiplewaitexp.insideaprocess
usingsameclockexpression.
Q3=notQ3
endprocessoutput
enddff_arch
C_1200
Message:Onlyoneclockallowedinthedesign
Thisruleensuresthatonlyoneclockisusedinadesign.Youcanconfigurethisrule
withtheRuleConfigurationWizardtoallowmorethanoneclock.Note:aswithall
Description
chiplevelrules,thisruleworksonlyifyouusethetopswitchtospecifythetop
levelofyourdesign.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
C_1201
Message:Clocksmustnotbeusedasdata
Thisruleverifiesthatnoclocksareconnectedtothedatainputsofaflipflop.
Controllingtheclocktreeseasesthetaskofclocktreesynthesis.Note:aswithall
Description
chiplevelrules,thisruleworksonlyifyouusethetopswitchtospecifythetoplevel
ofyourdesign.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
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C_1202
Message:Datamustberegisteredby2flipflopswhenchangingclock
domain
Whenchangingclockdomains,usetwoflipflopstagesinthedestinationclock
Description domaintoavoidmetastabilityproblems.Note:aswithallchiplevelrules,thisrule
worksonlyifyouusethetopswitchtospecifythetoplevelofyourdesign.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
C_1203
Message:Internallygeneratedclockdetected(chiplevel)
Thisruleverifiesthatallclocksarecontrollablefromthetoplevelofthedesignand
notinternallygeneratedviaasequentialblock.Internallygeneratedclocksmaynot
Description becontrollablefromtheboundaryofthechip.Thisreducestestcoverage.Note:as
withallchiplevelrules,thisruleworksonlyifyouusethetopswitchtospecifytop
levelofyourdesign.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
C_1204
Message:NogatedclockexceptinclockgeneratorCKGEN
Thisruleverifiesthatallclockgatingelements(forexample,and/or/xor/inverter)are
groupedinauniquedesigncalledCKGEN.Isolatingtheclockgatinglogiceasesthe
Description taskofclocktreesynthesis.YoucanconfigurethisruleusingtheRuleConfiguration
Wizard.Note:aswithallchiplevelrules,thisruleworksonlyifyouusethetop
switchtospecifythetoplevelofyourdesign.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
C_1205
Message:Userisingedgeclockinthedesign
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Thisruleensuresthatallflipflopsinthedesignaredrivenbyarisingedge.Mixing
risingedgeandfallingedgeflipflopshasimpactsonscanchains.Ifnecessary,you
Description canconfigurethisruletocheckthatallflipflopsaredrivenbyafallingedge.Note:
aswithallchiplevelrules,thisruleworksonlyifyouusethetopswitchtospecify
thetoplevelofthedesign.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
C_1206
Message:Buffersmustnotbeexplicitlyaddedtoclockpath
Thisruleverifiesthatnobuffershavebeenaddedontheclockpath.Clocktree
synthesistoolsfirstremovebuffersontheclockpathbeforebuildingthetrees.Note:
Description
aswithallchiplevelrules,thisruleworksonlyifyouusethetopswitchtospecify
toplevelofyourdesign.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
C_1207
Message:Avoidgatedclockinthedesign
Thisrulelooksforallgatedclocksinthedesign.ThisruleissimilartoruleC_1204.
Gatedclocksrequireparticularattentionduringtiminganalysisandextraworkduring
Description
clocktreesynthesis.Note:aswithallchiplevelrules,thisruleworksonlyifyouuse
thetopswitchtospecifythetoplevelofthedesign.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
C_1208
Message:Multiplexedclockisdetected
Description
TheCheckerreportsaclocksignalthatismultiplexed.Seethefollowingexampleand
exceptions.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
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Type
Chiplevel
Severity
Warning
Example
FollowingisanexampleofinvalidVerilogcodethatexhibitsthisproblem:
//C_1208:Avoidgatedclockinthedesign
moduleTEST_C_1208_2(SEL,CLK0,CLK1,CLK2,CLK3,D,Q)
input[0:1]SEL
inputCLK0,CLK1,CLK2,CLK3
inputD
outputQ
regQ
regmux_clk
always@(SEL)begin
case(SEL)
2'b00:mux_clk=CLK0
2'b01:mux_clk=CLK1
2'b11:mux_clk=CLK3
2'b10:mux_clk=CLK2//TheCheckerflagsthisline
endcase
end
always@(posedgemux_clk)begin
Q<=D
end
endmodule
CheckerExceptions
Fortheclockgenerator,ifallinputsofamuxareconnectedtoconstantvalue,thentheChecker
doesnotconsidertheclockasmultiplexed.Inthefollowingfigure,Gen_clkisconsideredasan
internallygeneratedclocksoitisnotconsideredasamultiplexedclock
Foragatedclock,ifoneoftheinputsofamuxbutnotallisconnectedtoaconstantvalue,then
theCheckerdoesnotconsidertheclockasmultiplexed.Inthefollowingfigure,CLKisconsidered
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asgatedclockandnotasamultiplexedclock
C_1209
Message:Registerwithfixedvalueclockisdetected
Thisruledetectsiftheclockofaregisteristiedtoafixedvalue(groundorVCC).To
Description checkthisruleontheentiredesignyoumustspecifyatopdesignunitusingthetop
switch.
Policy
Leda
Ruleset
CLOCKS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
ResetsRuleset
Thefollowingrulesarefromtheresetsruleset:
B_1400
Message:Asynchronousreset/set/loadsignal<%item>isnotaprimary
inputtothecurrentunit
ThisruleissimilartoruleB_1205exceptthatitlooksforanasynchronousresets,
sets,orloads.TheCheckerverifiesthatallasynchronousresets,sets,andloadsina
Description unitaredeclaredasportsignals.Ifnot,itmeansthatthereset,set,orloadis
generatedinsidetheunit.Internallygeneratedresets,sets,andloadsmaynotbe
controllablefromtheboundaryofthechip.Thisreducestestcoverage.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofinvalidVHDLcode,followedbyacircuitdiagramthatillustratestheproblem:
libraryIEEE
useIEEE.std_logic_1164.all
entityB_1400is
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port(CLK,A_IN
:std_logic
Q_OUT
:outstd_logic)
End
architectureRTLofB_1400is
signalRST:std_logic
begin
process(CLK)begin
if(CLK'eventandCLK='1')then
RST<=notRST
endif
endprocess
process(CLK,RST)begin
if(RST='0')thenResetisgeneratedinternally(previous
Q_OUT<='0'process)
elsif(CLK'eventandCLK='1')then
Q_OUT<=A_IN
endif
endprocess
end
InvalidExample:
ValidExample:
B_1401
Message:Synchronousreset/set/loadsignal<%item>isnotaprimary
inputtothecurrentunit
ThisruleissimilartoruleB_1205exceptthatitlooksforasynchronousresets,sets,
andloads.TheCheckerverifiesthatallsynchronousresets,sets,andloadsinaunit
Description aredeclaredasportsignals.Ifnot,itmeansthatthereset,sets,orloadis
generatedinsidetheunit.Internallygeneratedresets,sets,andloadsmaynotbe
controllablefromtheboundaryofthechip.Thisreducestestcoverage.
Policy
Leda
Ruleset
RESETS
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Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
Example
ThisisanexampleofinvalidVHDLcode,followedbyacircuitdiagramthatillustratestheproblem:
libraryIEEE
useIEEE.std_logic_1164.all
entityB_1401is
port(CLK,A_IN
:std_logic
Q_OUT
:outstd_logic)
End
architectureRTLofB_1401is
signalRST:std_logic
begin
process(CLK)begin
if(CLK'eventandCLK='1')then
RST<=notRST
endif
endprocess
process(CLK,RST)begin
if(CLK'eventandCLK='1')then
if(RST='0')thenResetisinternallygenerated
Q_OUT<='0'(previousprocess)
else
Q_OUT<=A_IN
endif
endif
endprocess
end
InvalidExample:
ValidExample:
B_1402
Message:Donotuseeventdefinitionsforasynchronousresets/sets/loads
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Description Eventsarenotsupportedbysynthesistools.
Policy
Leda
Ruleset
RESETS
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingareexamplesofvalidandinvalidVHDLcodethatillustratethisproblemandhowto
correctit:
InvalidVerilogCode:
moduleB_1402_bad(clk,data_in,data_out)
inputclk,data_in
outputdata_out
regdata_out
eventrst//FAIL
always@(posedgeclkorposedgerst)begin//Resetdefintiondonevia
if(rst==1'b1)//anevent
data_out<=1'b0
else
data_out<=data_in
end
endmodule
ValidVerilogCode:
moduleB_1402_good(clk,data_in,rst,data_out)
inputclk,data_in
inputrst//PASS
outputdata_out
regdata_out
always@(posedgeclkorposedgerst)begin//Resetdefinitiondonevia
if(rst==1'b1)//aninputport
data_out<=1'b0
else
data_out<=data_in
end
endmodule
B_1403
Message:Flipflopassignedbutnotinitialized
TheCheckersearchesforallflipflopsthathavenoreset.Allsequentialelements
musthavearesetfortestabilitypurposes.Thisruleonlychecksatthe
Description
architecture/modulelevel.ThereisasimilarruleintheLedageneralcoding
guidelinespolicythatyoucanusetochecktheentiredesign.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
Example
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FollowingareexamplesofvalidandinvalidVHDLcodethatillustratethisproblemandhowto
correctit.Thecodesamplesarefollowedbycircuitdiagramsthatalsoillustratetheproblemand
thesolution.
InvalidVHDLCode:
libraryIEEE
useIEEE.std_logic_1164.all
entityb_1403is
port(CLK,RST,DATA_IN
DATA_OUT
)
end
:instd_logic
:outstd_logic
architectureRTLofb_1403is
signaltmp:std_logic
begin
process(CLK,RST)begin
if(RST='0')then
DATA_OUT<='0'
elsif(CLK'eventandCLK='1')then
tmp<=DATA_INtmpisaffectedbutnotinitialized
DATA_OUT<=tmp
endif
endprocess
end
InvalidExample:
ValidVHDLCode:
libraryIEEE
useIEEE.std_logic_1164.all
entityb_1403is
port(CLK,RST,DATA_IN
DATA_OUT
end
:instd_logic
:outstd_logic)
architectureRTLofb_1403is
signaltmp:std_logic
begin
process(CLK,RST)begin
if(RST='0')then
DATA_OUT<='0'
tmp<='0'tmpinitialization
elsif(CLK'eventandCLK='1')then
tmp<=DATA_IN
DATA_OUT<=tmp
endif
endprocess
end
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ValidExample:
B_1404
Message:Asynchronousreset/set/load<%item>existsinmodule/unit
TheCheckerreportsallasynchronousresets,sets,andloads.Somestandardcell
librariesmayhaveonlyflipflopswithsynchronousresets,sets,andloads.Avoiding
Description
asynchronousresets,sets,andloadspreventsyoufromaddingcircuitrythatisnot
usefulwiththeclockonthedataline.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
Example
HereisanexampleofthebasicVerilogcodeforanasynchronousreset:
always@(posedgeCLKornegedgeRST)begin
if(!RST)begin
A_REG<=1'b0
end
elsebegin
A_REG<=A
end
end
HereisanexampleofthebasicVerilogcodeforasynchronousreset:
always@(posedgeCLK)begin
if(!RST)begin
A_REG<=1'b0
end
elsebegin
A_REG<=A
end
end
B_1405
Message:Multipleasynchronousresetsinthisunitdetected
Thisrulecontrolsthemaximumnumberofasynchronousresetsallowedinaunit.The
Description defaultis1.Tochangethisparameter,usetheRuleConfigurationWizardandsupply
thenumberinthevaluenodeoftherule.
Policy
Leda
Ruleset
RESETS
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Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVerilogcode,followedbydiagramsthatillustratevalidand
invalidcircuits:
moduleB_1405_BAD(A,B,CLK,RST_1,RST_2,A_REG,B_REG)
inputA,B,CLK,RST_1,RST_2
outputA_REG,B_REG
regA_REG,B_REG
always@(posedgeCLKornegedgeRST_1)begin
if(!RST_1)//Firstasynchronousreset
A_REG<=1'b0
else
A_REG<=A
end
always@(posedgeCLKornegedgeRST_2)begin
if(!RST_2)//Secondasynchronousresetinthisunit
B_REG<=1'b0
else
B_REG<=B
end
endmodule
InvalidExample:
ValidExample:
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B_1406
Message:Multiplesynchronousresetsinthisunitdetected
Thisrulecontrolsthemaximumnumberofsynchronousresetsallowedinaunit.The
Description defaultis1.Tochangethisparameter,usetheRuleConfigurationWizardandsupply
thenumberinthevaluenodeoftherule.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVerilogcode,followedbydiagramsthatillustratevalidand
invalidcircuits:
moduleb_1406(A,B,CLK,RST_1,RST_2,A_REG,B_REG)
inputA,B,CLK,RST_1,RST_2
outputA_REG,B_REG
regA_REG,B_REG
always@(posedgeCLK)begin
if(!RST_1)//Firstsynchronousreset
A_REG<=1'b0
else
A_REG<=A
end
always@(posedgeCLK)begin
if(!RST_2)//Secondsynchronousresetinthisunit
B_REG<=1'b0
else
B_REG<=B
end
endmodule
InvalidExample:
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ValidExample:
B_1407
Message:Donotuseactivehighasynchronousreset/set/load
Thisrulecontrolstheactivelevelofallasynchronousresets,sets,andloadsinall
units.Thedefaultisactivelow.Tochangetheactiveedge,usetheRuleWizardto
Description selecttheactiveedgeinthevaluenodeoftherule.Usingactivehighasynchronous
resets,sets,andloadswhenthetechnologylibraryonlyhasactivelowasynchronous
resets,sets,andloadsresultsininvertedcircuitryonthereset,set,orloadpath.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Error
Example
ThefollowingexampleofvalidVerilogcodeshowsanactivehighasynchronousreset:
moduleb_1407(CLK,RST,A,A_REG)
inputCLK,RST,A
outputA_REG
regA_REG
always@(posedgeCLKorposedgeRST)begin
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if(RST)begin//Posedgeasynchronousreset
A_REG<=1'b0
end
elsebegin
A_REG<=A
end
end
endmodule
B_1408
Message:Donotuseactivehighsynchronousreset/set/load
Thisrulecontrolstheactivelevelofallsynchronousresets,sets,andloadsinall
units.Thedefaultisactivelow.Tochangetheactiveedge,usetheRuleWizardand
Description selecttheactiveedgeinthevaluenodeoftherule.Usingactivehighsynchronous
resets,sets,andloadswhenthetechnologylibraryhasonlyactivelowsynchronous
resets,sets,andloadsresultsininvertedcircuitryonthereset,set,orloadpath.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Error
Example
ThefollowingexampleofvalidVerilogcodeshowsanactivelowsynchronousreset:
moduleb_1408(CLK,RST,A,A_REG)
inputCLK,RST,A
outputA_REG
regA_REG
always@(posedgeCLK)begin
if(RST)begin//Posedgesynchronousreset
A_REG<=1'b0
end
elsebegin
A_REG<=A
end
end
endmodule
B_1409
Message:Multipleasynchronousresetsinalways/processblock
Thisrulecontrolsthemaximumnumberofasynchronousresetsallowedinaprocess
Description (VHDL)oralways(Verilog).Thedefaultis1.Tochangethisparameter,usetheRule
ConfigurationWizardandsupplythenumberinthevaluenodeoftherule.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
Example
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FollowingareexamplesofinvalidVerilogandVHDLcode,followedbyacircuitdiagramthat
illustratesaninvalidexample:
InvalidVerilogCode:
always@(posedgeCLKornegedgeRSTornegedgeSET)begin
if(!RST)//Firstresetsignal
A_REG<=1'b0
elseif(!SET)//Secondresetsignalinsameunit
A_REG<=1'b1
else
A_REG<=A
End
InvalidVHDLCode:
process(CLK,RST,SET)begin
if(RST='0')thenFirstresetsignal
A_REG<='0'
elsif(SET='0')thenSecondresetsignalinthisunit
A_REG<='1'
elsif(CLK'eventandCLK='1')then
A_REG<=A
endif
endprocess
Noteinthefollowingdiagramofaninvalidexample,thattheSETandRSTsignalsareboth
consideredtoberesets:
B_1410
Message:Multiplesynchronousresetsinalways/processblock
Thisrulecontrolsthemaximumnumberofsynchronousresetsallowedinaprocess
Description (VHDL)oralways(Verilog)block.Thedefaultis1.Tochangethisparameter,usethe
RuleWizardandchangethenumberinthevaluenodeoftherule.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingareexamplesofVerilogcode,followedbyacircuitdiagramthatillustratesanexample:
InvalidVerilogCode:
moduleb_1410(CLK,RST,SET,A,A_REG)
inputCLK,RST,SET,A
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outputA_REG
regA_REG
always@(posedgeCLK)begin
if(!RST)//Firstresetsignal
A_REG<=1'b0
elseif(!SET)//Secondresetsignalinthisunit
A_REG<=1'b1
else
A_REG<=A
end
endmodule
Noteinthefollowingdiagramofaninvalidexample,thattheSETandRSTsignalsareboth
consideredtoberesets:
B_1411
Message:<%value>asynchronoussetsinthisunitdetected
Thisrulecontrolsthemaximumnumberofasynchronoussetsallowedinaunit.The
Description defaultis1.Tochangethisparameter,usetheRuleWizardandchangethenumber
inthevaluenodeoftherule.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_1412
Message:<%value>synchronoussetsinthisunitdetected
Thisrulecontrolsthemaximumnumberofsynchronoussetsallowedinaunit.The
Description defaultis1.Tochangethisparameter,usetheRuleWizardandchangethenumber
inthevaluenodeoftherule.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_1413
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Message:<%value>asynchronoussetsinalways/processblock
Thisrulecontrolsthemaximumnumberofasynchronoussetsallowedinaprocess
Description (VHDL)oralwaysblock(Verilog).Thedefaultis1.Tochangethisparameter,usethe
RuleWizardandchangethenumberinthevaluenodeoftherule.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_1414
Message:<%value>synchronoussetsinalways/processblock
Thisrulecontrolsthemaximumnumberofsynchronoussetsallowedinaprocess
Description (VHDL)oralwaysblock(Verilog).Thedefaultis1.Tochangethisparameter,usethe
RuleWizardandchangethenumberinthevaluenodeoftherule.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_1415
Message:<%value>asynchronousloadsinthisunitdetected
Thisrulecontrolsthemaximumnumberofasynchronousloadsallowedinaunit.The
Description defaultis1.Tochangethisparameter,usetheRuleWizardandchangethenumber
inthevaluenodeoftherule.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_1416
Message:<%value>asynchronousloadsinthisunitdetected
Thisrulecontrolsthemaximumnumberofsynchronousloadsallowedinaunit.The
Description defaultis1.Tochangethisparameter,usetheRuleWizardandchangethenumber
inthevaluenodeoftherule.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
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Type
Blocklevel
Severity
Warning
B_1417
Message:<%value>asynchronousloadsinalways/processblock
Thisrulecontrolsthemaximumnumberofasynchronousloadsallowedinaprocess
Description (VHDL)oralwaysblock(Verilog).Thedefaultis1.Tochangethisparameter,usethe
RuleWizardandchangethenumberinthevaluenodeoftherule.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_1418
Message:<%value>synchronousloadsinalways/processblock
Thisrulecontrolsthemaximumnumberofsynchronousloadsallowedinaprocess
Description (VHDL)oralwaysblock(Verilog).Thedefaultis1.Tochangethisparameter,usethe
RuleWizardandchangethenumberinthevaluenodeoftherule.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
C_1400
Message:Only1reset/set/loadallowedinthedesign.<%value>have
beendetected
Thisrulecontrolsthemaximumnumberofresets,sets,andloadsinthewhole
design.Thedefaultis1.Tochangethisparameter,usetheRuleWizardandchange
Description
thenumberinthevaluenodeoftherule.Tocheckthisruleontheentiredesign,you
mustspecifyatopdesignunit.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
Example
Thefollowingdiagramsillustratetwoinvalidexamplesofusingmorethanoneresetinadesign.
InvalidExample1:
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Therearetwoasynchronousresetsinthisdesign(RST_1&RST_2):
InvalidExample2:
Therearetworesetsignalinthisdesign(oneasynchronousandonesynchronous):
C_1401
Message:Avoidgatedresets/sets/loadsindesign.
Thisrulelooksforallgatedresets,sets,andloadsinthedesign.Thisruleissimilar
toruleC_1402.Whenbothrulesareactivated,theCheckerappliesonlyruleC_1402
Description
onthedesign.Tocheckthisruleontheentiredesign,youmustspecifyatopdesign
unit.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
Example
Thefollowingdiagramillustratesaninvalidexampleofagatedasynchronousresetinthedesign:
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C_1402
Message:Nogatedreset/set/loadexceptinreset/set/loadgenerator
RSTGEN
Thisrulelooksforallgatedresets,sets,andloadsinthedesignunlessthegated
resets,sets,orloadsoccurinaspecificunitnamedRSTGEN.Tochangethisname,
Description usetheRuleWizardandchangethenameinthevaluenodeoftherule.Seealso
ruleC_1401.Tocheckthisruleontheentiredesign,youmustspecifyatopdesign
unit.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
Example
Followingaretwoexamplediagrams,onevalidandoneinvalid,thatillustratethecircuitsfor
correctandincorrectdesigns.
InvalidExample:
Thereisagatedasynchronousresetinthisdesign,butthegatedresetisnotgeneratedina
modulecalledRSTGEN:
ValidExample:
Thereisagatedasynchronousresetinthisdesign,andthegatedresetisgeneratedinamodule
calledRSTGEN:
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C_1403
Message:Buffersmustnotbeexplicitlyaddedtoreset/set/loadpaths
Description
Checksallreset,set,andloadpathstomakesuretherearenobuffers.Tocheckthis
ruleontheentiredesign,youmustspecifyatopdesignunit.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
Example
Thefollowingillustrationshowsaninvalidexamplewithabufferintheasynchronousresetline.
C_1404
Message:Signalisusedbothassynchronousandasynchronous
reset/set/load
Thisruleensuresthatareset,set,orloadlinedrivesonlyasynchronousreset,set,
Description orloadpinofaregisteroronlyanasynchronouspinofaregister.Tocheckthisrule
ontheentiredesignyoumustspecifyatopdesignunitusingthetopswitch.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
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C_1405
Message:Registerwithfixedvaluereset/set/loadisdetected
Thisruledetectsifthereset,set,orloadofaregisteristiedtoafixedvalue
Description (groundorVCC).Tocheckthisruleontheentiredesignyoumustspecifyatopdesign
unitusingthetopswitch.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
C_1406
Message:Registerwithnoreset/set/loadisdetected
Thisrulesearchesforallflipflopsthathavenoreset,set,orload.Allsequential
Description elementsmusthaveareset,set,orloadfortestabilitypurposes.Tocheckthisrule
ontheentiredesignyoumustspecifyatopdesignunitusingthetopswitch.
Policy
Leda
Ruleset
RESETS
Language
VHDL/Verilog
Type
Chiplevel
Severity
Error
Example
FollowingareexamplesofvalidandinvalidVHDLcodethatillustratethisproblemandhowto
correctit.Thecodesamplesarefollowedbycircuitdiagramsthatalsoillustratetheproblemand
thesolution.
InvalidVHDLCode:
libraryIEEE
useIEEE.std_logic_1164.all
useIEEE.std_logic_arith.all
useIEEE.STD_LOGIC_UNSIGNED.conv_integer
entityc_1406is
port(CLK
RST,DATA_IN
DATA_OUT
end
:instd_logic
:instd_logic
:outstd_logic)
architecturearchofc_1406is
signaltmp:std_logic
begin
process(CLK,RST)begin
if(RST='0')then
DATA_OUT<='0'
elsif(CLK'eventandCLK='1')then
tmp<=DATA_INtmpisaffectedbutnotinitialized
DATA_OUT<=tmp
endif
endprocess
endarchitecture
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ValidVHDLCode:
process(CLK,RST)begin
if(RST='0')then
DATA_OUT<='0'
tmp<='0'tmpinitialization
elsif(CLK'eventandCLK='1')then
tmp<=DATA_IN
DATA_OUT<=tmp
endif
endprocess
InvalidExample:
ValidExample:
RTLSynthesisRuleset
ThefollowingrulesarefromtheRTLsynthesisruleset:
B_2000
Message:Systemtasksarenotallowed
Description
Thisrulechecksthatsystemtasks($display,$printf,etc.)arenotused.Systemtask
arenotsynthesizable.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
Verilog
Type
Blocklevel
Severity
Error
Example
ThefollowingexampleshowsinvalidVerilogcode:
moduleB_2000(clk)
inputclk
always@(posedgeclk)
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begin
$display("HelloWorld")//Systemtaskdetected
end
initial
$printf("helloworld")//Systemtaskdetected
initial$dumpvars()//Systemtaskdetected
endmodule
B_2001
Message:Shiftbyanonconstantvalueisnotallowed
TheruleisviolatedwhentheCheckerdetectsashiftbyanonconstantvalue
(dynamicevaluation)Thisvaluemustbeanexpressionthatcanbeevaluatedat
Description compilationorelaborationtime.Ashiftbyadynamicvalueresultsinahuge
combinatorialarea.Iftheshiftvaluecanbedefinedatthecompilationorelaboration
step,thesynthesistoolwillonlyperformnetassignment.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
Verilog
Type
Blocklevel
Severity
Error
Example
FollowingaresomeexamplesofvalidandinvalidVerilogcode:
InvalidVerilogCode:
moduleB_2001_BAD(DATA_IN,DATA_OUT,A)
input[7:0]DATA_IN
input[3:0]A
output[7:0]DATA_OUT
assignDATA_OUT=(DATA_IN<<A)//Shiftoperatorusingnonconstant
//value
endmodule
ValidVerilogCode:
moduleB_2001_GOOD1(DATA_IN,DATA_OUT)
input[7:0]DATA_IN
output[7:0]DATA_OUT
assignDATA_OUT=(DATA_IN<<3)//Shiftvalueisconstant(literal)
endmodule
ValidVerilogcoding:
moduleB_2001_GOOD2(data_in,data_out)
input[7:0]data_in
output[7:0]data_out
parametern=4
assigndata_out=data_in>>n//Shiftvalueisconstant(parameter)
assigndata_out=data_in<<n//Shiftvalueisconstant(parameter)
endmodule
B_2002
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Message:Disablestatementinalwaysconstructmaynotbesynthesizable
Description
Thisrulechecksthatalwaysconstructsdonotcontaindisablestatements.Disable
statementscannotbesynthesized.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
Verilog
Type
Blocklevel
Severity
Error
Example
FollowingisanexampleofinvalidVerilogcode:
moduleb_2002(clk,flag,a,b,z)
inputclk,flag,a,b
outputz
regz
always@(posedgeclkornegedgeflag)
begin:block1
if(flag)
disableblock1//Disablestatementisinalwaysblock
z<=a&b
end
endmodule
B_2003
Message:Disablestatementintaskmaynotbesynthesizable
Description
Thisrulechecksthattaskbodiesdonotcontaindisablestatements.Disable
statementscannotbesynthesized.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
Verilog
Type
Blocklevel
Severity
Error
Example
ThefollowingisanexampleofaVerilogcode:
moduleb_2003(flag,a,b,z,clk)
inputflag,a,b,clk
outputz
regz
always@(posedgeclk)begin
t1(a,b,flag,z)
end
taskt1
inputa,b,flag
outputz
regz
begin
begin:block1
if(flag)begin
disablet1//Taskdisablestatementintaskbody
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disableblock1//Blockdisablestatementintaskbody
end
z<=a&b
end
end
endtask
endmodule
B_2004
Message:Disablestatementinfunctionmaynotbesynthesizable
Description
Thisrulechecksthatfunctionbodiesdonotcontaindisablestatements.Disable
statementscannotbesynthesized.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
Verilog
Type
Blocklevel
Severity
Error
Example
FollowingisanexampleofinvalidVerilogcode:
moduleb_2004(a,b,flag,flag1)
inputa,b,flag
outputflag1
regflag1
functionadd_func
inputai,b,flag
begin
begin:block1
if(flag)begin
disableblock1//Blockdisablestatementinfunctionbody
end
add_func=a&b
end
end
endfunction
always@(aorborflag)
begin
flag1=add_func(a,b,flag)
end
endmodule
B_2005
Message:Functionsoftyperealarenotsynthesizable
Description
Thisruledetectsallfunctionsusingrealvariables.Realfunctionscannotbe
synthesized.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
Verilog
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Type
Blocklevel
Severity
Error
Example
FollowingisanexampleofinvalidVerilogcode:
moduleB_2005(a,z)
input[2:0]a
output[2:0]z
functionrealreal_func//Realfunctiondeclaration
input[2:0]data_in
begin
real_func=data_in+2.13
end
endfunction
functionintegerint_func//Integerfunctiondeclaration
begin
int_func=4
end
endfunction
assignz=real_func(a)
endmodule
B_2006
Message:Eventdeclarationsarenotallowed
Description Thisruledetectseventdeclarations.Eventdeclarationscannotbesynthesized.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
Verilog
Type
Blocklevel
Severity
Error
Example
FollowingareexamplesofvalidandinvalidVerilogcodethatillustratetheproblemandhowto
correctit:
InvalidVerilogCode:
moduleB_2006_BAD(DATA_IN,DATA_OUT)
inputDATA_IN
outputDATA_OUT
regDATA_OUT
eventclk_event//Eventdeclarationisnotallowed
always@(posedgeclk_event)begin
DATA_OUT<=DATA_IN
end
endmodule
ValidVerilogCode:
moduleB_2006_GOOD(CLK,DATA_IN,DATA_OUT)
inputDATA_IN
inputCLK//PASS
outputDATA_OUT
regDATA_OUT
always@(posedgeCLK)begin//Theclockisanexternalsignal
DATA_OUT<=DATA_IN
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end
endmodule
B_2007
Message:Sameoperandonbothsidesofassignmentdetected
Description
Thisruledetectsselfassignments(forexample,a<=a).Redundantassignments
cangeneratelatches.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVerilogcode:
moduleB_2007(CLK,EN,DATA_IN,DATA_OUT)
inputCLK,EN,DATA_IN
outputDATA_OUT
regDATA_OUT
always@(posedgeCLK)begin
if(EN)
DATA_OUT<=DATA_IN
else
DATA_OUT<=DATA_OUT//Selfassignment
end
endmodule
B_2008
Message:Delaysinsignalassignmentareignoredbysynthesistool
Description
TheCheckerreportsalldelaysinsignalassignments.Delaysinsignalassignments
cannotbesynthesizedandareignoredbysynthesistools.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVHDLcode:
libraryIEEE
useIEEE.std_logic_1164.all
entityb_2008is
port(CLK,RST,A_IN:instd_logic
A_OUT:outstd_logic
)
end
architectureRTLofb_2008is
begin
process(CLK,RST)begin
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if(RST='0')then
A_OUT<='0'
elsif(CLK'eventandCLK='1')then
A_OUT<=A_INafter5nsDelayinsignalassignment
endif
endprocess
end
B_2009
Message:Delaysinconditionalsignalassignmentareignoredbysynthesis
tool
Description
TheCheckerreportsalldelaysinconditionalsignalassignments.Delaysinsignal
assignmentscannotbesynthesizedandareignoredbysynthesistools.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVHDLcode:
libraryIEEE,STD
useIEEE.std_logic_1164.all
useIEEE.std_logic_components.all
useIEEE.std_logic_misc.all
entityb_2009is
port(A_IN,B_IN:instd_logic
DATA_OUT:outstd_logic
)
end
architectureRTLofb_2008is
begin
DATA_OUT<=A_INandB_INafter2nsDelayinconditional
endsignalassignment
B_2010
Message:Nonsynthesizeableoperator===!==encountered
Description
Thisruledetectsallusageofthe"==="and"!=="operatorsinHDLsourcebecause
theycannotbesynthesized.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
Verilog
Type
Blocklevel
Severity
Error
Example
FollowingisanexampleofinvalidVerilogcode:
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moduleB_2010_BAD(A,B,SEL,DATA_OUT)
inputA,B,SEL
outputDATA_OUT
regDATA_OUT
always@(AorBorSEL)begin
if(SEL===1'bX)//"==="operatordetected
DATA_OUT<=A
else
DATA_OUT<=B
end
endmodule
B_2011
Message:Variableisnotalwaysinitializedinprocessbodybeforebeing
read
Thisrulechecksthatallvariablesinaprocessstatementareinitialized.Avariable
Description thatisreadbeforeavalueisassignedtoitcancausesimulationmismatches
betweenpreandpostsynthesis.Thisruleonlyappliestocombinatorialprocesses.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVHDLcodethatexhibitsthisproblem:
B_2011:Variableisnotalwaysinitializedincombinatorialprocess
bodybeforebeingread
libraryIEEE
useIEEE.std_logic_1164.all
useIEEE.std_logic_unsigned.all
useIEEE.std_logic_arith.all
entityB_2011_1isport(EN,EN2:instd_logic
A_IN:instd_logic_vector(3downto0)
A_OUT:outstd_logic_vector(3downto0))
end
architectureRTLofB_2011_1is
begin
process(EN,EN2,A_IN)
variabletmp_1:std_logic_vector(3downto0)
variabletmp_2:integer
begin
tmp_2:=0
if(EN='0')then
A_OUT<=CONV_STD_LOGIC_VECTOR(tmp_2,4)
else
if(EN2='1')then
A_OUT<=tmp_1FAIL:NOTinitialized
else
A_OUT<=A_IN
endif
endif
endprocess
end
B_2031
Message:Bothedgesofthesignalusedinthesensitivitylist
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Description
Ledaflagsthisrulewhenitfindsboththeedgesofasignalisusedinthesensitivity
list.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVerilogcode:
moduletest(inputwirereset,clk,D,outputregQ)
always@(posedgeclkornegedgeclk)//FAIL
begin
if(!reset)
Q<=1'b0
else
Q<=D
end
endmodule
B_2033
Message:Unrecognizedsynthesisdirective
Description LedaflagsthisrulewhenitfindsasynthesisdirectivethatDCdoesnotsupports.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
Verilog/VHDL
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVerilogcode:
moduletest(inputwirereset,clk,D,outputregQ)
always@(posedgeclkorreset)
//synopsyssynth_test//Ruleflagshere
begin
if(!reset)
Q<=1'b0
else
Q<=D
end
endmodule
B_2034
Message:Resetsignalusemodenotsameasitspragmamode
Description
Ledaflagsthisrulewhenitfindstheusemodeofaresetsignalisnotsameasits
pragmamode.
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Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVerilogcode:
moduledff(reset,set,Q,D,clk)
inputreset,set,clk,D
outputQ
regQ
//synopsysasync_set_reset"set,reset"
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
always@(posedgeclk)
if(~reset)//FAIL
Q<=0
elseif(~set)//FAIL
Q<=1
else
Q<=D
endmodule
B_2035
Message:UnsynthesizableIFstatement
Description Ledaflagsthisrulewhenitfindsanunsynthesizableifstatement.
Policy
Leda
Ruleset
RTL_SYNTHESIS
Language
VHDL
Type
Blocklevel
Severity
Warning
DataTypesRuleset
Thefollowingrulesarefromthedatatypesruleset:
B_3000
Message:Assigninga0or1(32bits)toonebitisnotallowed
Description
Thisruledetectsassignmentofa0or1toa1bitvalue.Integervariables0and1
arecodedon32bits.Use1'b0and1'b1forsuchassignments.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
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Severity
Warning
B_3001
Message:Arrayofintegerisnotallowed
Description
Thisruledetectsthedeclarationofarraysofintegers.Thesekindsofarraysarenot
acceptedbysynthesistools.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Error
B_3002
Message:Arrayoftimeisnotallowed
Description
Thisruledetectsthedeclarationofarraysoftime.Arraysoftimearenotacceptedby
synthesistools.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Error
B_3003
Message:Testexpressioninif_statementisexpectedtobeonebitwide
Description Theexpressioninanif_statementisexpectedtobe1bitwide.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Error
B_3004_A
Message:Unrecommendedblockingassignment(convertingintegertoreal)
Thisruledetectsautomaticconversionfromintegertorealinblockingassignment.
Description ImplicittypeconversiondoesnotexistinVHDLandmaycauseproblemswhenusing
atoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
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Language
Verilog
Type
Blocklevel
Severity
Warning
B_3004_B
Message:Unrecommendednonblockingassignment(convertingintegerto
real)
Thisruledetectsautomaticconversionfromintegertorealinanonblocking
Description assignment.ImplicittypeconversiondoesnotexistinVHDLandmaycauseproblems
whenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3004_C
Message:Unrecommendedproceduralcontinuousassignment(converting
integertoreal)
Thisruledetectsautomaticconversionfromintegertorealinaproceduralcontinuous
Description assignment.ImplicittypeconversiondoesnotexistinVHDLandmaycauseproblems
whenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3004_D
Message:Unrecommendedproceduralcontinuousforce(convertinginteger
toreal)
Thisruledetectsautomaticconversionfromintegertorealinaproceduralcontinuous
Description force.ImplicittypeconversiondoesnotexistinVHDLandmaycauseproblemswhen
usingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
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B_3005_A
Message:Unrecommendedblockingassignment(convertingunsignedto
real)
Thisruledetectsautomaticconversionfromunsignedtorealinblocking
Description assignments.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3005_B
Message:Unrecommendednonblockingassignment(convertingunsigned
toreal)
Thisruledetectsautomaticconversionfromunsignedtorealinnonblocking
Description assignments.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3005_C
Message:Unrecommendedproceduralcontinuousassignment(converting
unsignedtoreal)
Thisruledetectsautomaticconversionfromunsignedtorealinaprocedural
Description continuousassignment.ImplicittypeconversiondoesnotexistinVHDLandmay
giveproblemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3005_D
Message:Unrecommendedproceduralcontinuousforce(converting
unsignedtoreal)
Thisruledetectsautomaticconversionfromunsignedtorealinaprocedural
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Description continuousforce.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3006_A
Message:Unrecommendedblockingassignment(convertingrealtointeger)
Thisruledetectsautomaticconversionsfromrealtointegerinblockingassignments.
Description ImplicittypeconversiondoesnotexistinVHDLandmaycauseproblemswhenusing
atoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3006_B
Message:Unrecommendednonblockingassignment(convertingrealto
integer)
Thisruledetectsautomaticconversionsfromrealtointegerinnonblocking
Description assignments.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3006_C
Message:Unrecommendedproceduralcontinuousassignment(converting
realtointeger)
Thisruledetectsautomaticconversionsfromrealtointegerinproceduralcontinuous
Description assignments.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
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Severity
Warning
B_3006_D
Message:Unrecommendedproceduralcontinuousforce(convertingrealto
integer)
Thisruledetectsautomaticconversionsfromrealtointegerinproceduralcontinuous
Description forces.ImplicittypeconversiondoesnotexistinVHDLandmaycauseproblems
whenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3007_A
Message:Unrecommendedblockingassignment(convertingunsignedto
integer)
Thisruledetectsautomaticconversionsfromunsignedtointegerinblocking
Description assignments.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3007_B
Message:Unrecommendednonblockingassignment(convertingunsigned
tointeger)
Thisruledetectsautomaticconversionsfromunsignedtointegerinnonblocking
Description assignments.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3007_C
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Message:Unrecommendedproceduralcontinuousassignment(converting
unsignedtointeger)
Thisruledetectsautomaticconversionsfromunsignedtointegerinprocedural
Description continuousassignments.ImplicittypeconversiondoesnotexistinVHDLandmay
causeproblemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3007_D
Message:Unrecommendedproceduralcontinuousforce(converting
unsignedtointeger)
Thisruledetectsautomaticconversionsfromunsignedtointegerinprocedural
Description continuousforces.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3008_A
Message:Unrecommendedblockingassignment(convertingintegerto
unsigned)
Thisruledetectsautomaticconversionsfromintegertounsignedinblocking
Description assignments.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3008_B
Message:Unrecommendednonblockingassignment(convertingintegerto
unsigned)
Thisruledetectsautomaticconversionsfromintegertounsignedinnonblocking
Description assignments.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
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Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3008_C
Message:Unrecommendedproceduralcontinuousassignment(converting
integertounsigned)
Thisruledetectsautomaticconversionsfromintegertounsignedinprocedural
Description continuousassignments.ImplicittypeconversiondoesnotexistinVHDLandmay
causeproblemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3008_D
Message:Unrecommendedproceduralcontinuousforce(convertinginteger
tounsigned)
Thisruledetectsautomaticconversionsfromintegertounsignedinprocedural
Description continuousforces.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3008_E
Message:Unrecommendedcontinuousassignment(convertingintegerto
unsigned)
Thisruledetectsautomaticconversionsfromintegertounsignedincontinuous
Description assignments.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
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B_3009_A
Message:Unrecommendedblockingassignment(convertingrealto
unsigned)
Thisruledetectsautomaticconversionsfromrealtounsignedinblocking
Description assignments.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3009_B
Message:Unrecommendednonblockingassignment(convertingrealto
unsigned)
Thisruledetectsautomaticconversionsfromrealtounsignedinnonblocking
Description assignments.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3009_C
Message:Unrecommendedproceduralcontinuousassignment(converting
realtounsigned)
Thisruledetectsautomaticconversionsfromrealtounsignedinprocedural
Description continuousassignments.ImplicittypeconversiondoesnotexistinVHDLandmay
causeproblemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3009_D
Message:Unrecommendedproceduralcontinuousforce(convertingrealto
unsigned)
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Thisruledetectsautomaticconversionsfromrealtounsignedinprocedural
Description continuousforces.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3009_E
Message:Unrecommendedcontinuousassignment(convertingrealto
unsigned)
Thisruledetectsautomaticconversionsfromrealtounsignedincontinuous
Description assignments.ImplicittypeconversiondoesnotexistinVHDLandmaycause
problemswhenusingatoolfortranslationfromVerilogtoVHDL.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3010
Message:Loopindexmustbedeclaredasaninteger
Description
Thisruleisviolatedwhenthetypeofaforstatementindexisnotaninteger.This
cancauseproblemswithcodeportability.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Error
ExpressionsRuleset
Thefollowingrulesarefromtheexpressionsruleset:
B_3200
Message:Unequallengthoperandinbit/arithmeticoperatorLHS:
<%size>,RHS:<%size>
Description
Thisruleverifiesthatinabit/arithmeticoperation(+,,*,/,&,|,^,^~,~^)thebit
sizesofthetwooperandsareequal.Thiscancauseproblemswithcodeportability.
Policy
Leda
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Ruleset
EXPRESSIONS
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingareexamplesofvalidandinvalidVerilogcodethatillustratethisproblemandhowto
correctit:
InvalidVerilogCode:
moduleB_3200_BAD(A,B,DATA_OUT)
input[1:0]A
inputB
output[2:0]DATA_OUT
assignDATA_OUT=A+B//Unequallengthoperand,Ais2bitsbutB
//is1bit
endmodule
ValidVerilogCode:
moduleB_3200_GOOD(A,B,DATA_OUT)
input[1:0]A
input[1:0]B
output[2:0]DATA_OUT
assignDATA_OUT=A+B//Equallengthoperand,AandBaresamesize
endmodule
B_3201
Message:UnequallengthoperandincomparisonoperatorLHS:<%size>,
RHS:<%size>
Thisruleverifiesthatinabit/arithmeticcomparison(<,<=,>,>=,===,!==,
Description ==,!=)thebitsizesofthetwooperandsareequal.Thiscancauseproblemswith
codeportability.
Policy
Leda
Ruleset
EXPRESSIONS
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingareexamplesofvalidandinvalidVerilogcodethatillustratethisproblemandhowto
correctit:
InvalidVerilogCode:
moduleB_3201_BAD(A,B,DATA_OUT)
input[1:0]A
inputB
outputDATA_OUT
regDATA_OUT
always@(AorB)begin
if(A<B)//Unequallengthoperand:Ais2bitsandBis1bit
DATA_OUT<=1'b1
else
DATA_OUT<=1'b0
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end
endmodule
ValidVerilogCode
moduleB_3201_GOOD(A,B,DATA_OUT)
input[1:0]A
input[1:0]B
outputDATA_OUT
regDATA_OUT
always@(AorB)begin
if(A<B)//AandBaresamesize
DATA_OUT<=1'b1
else
DATA_OUT<=1'b0
end
endmodule
B_3202
Message:Delayisnotconstantexpression
Thisruleisviolatedwhenthedelayvalueofadelaycontrolisnotconstant(thatis,
itcannotbeevaluatedduringHDLcompilation).Theexpressiontypesthatare
allowedbytherulearetheparameters,anyliteralsandminimum,typical,and
maximumdelayexpressions.Delaycontrolsaredifferentfromgateornetdelays.
Description
Delaycontrolisaproceduraltimingcontrolthatisusedtospecifythetimeduration
betweeninitiallyencounteringthestatementandwhenthestatementactually
executes.Thegateornetdelayspecifiesthepropagationdelayfromgateinputto
gateoutput(gatedelay)orthetimeittakeschangingvalue(netdelay).
Policy
Leda
Ruleset
EXPRESSIONS
Language
Verilog
Type
Blocklevel
Severity
Error
Example
FollowingareexamplesofvalidandinvalidVerilogcodingthatillustratethisproblemandhowto
correctit:
InvalidVerilogCode:
moduleB_3202_1(A,B,C,DELAY)
inputA,B
input[3:0]DELAY
outputC
assign#DELAYC=A&B//Nonconstantdelayvalue
endmodule
ValidVerilogCode:
moduleB_3202_2(A,B,C)
inputA,B
outputC
assign#1C=A&B//Constantdelayvalue(literal)
endmodule
ValidVerilogcoding:
moduleB_3202_3(A,B,C)
parameterDELAY=1
inputA,B
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outputC
assign#DELAYC=A&B//Constantdelayvalue(parameter)
endmodule
B_3203
Message:Theexpressioninforloopmustnotbeconstant
TheCheckerverifiesthatinaforstatement,theconditionexpressionisadynamic
evaluationexpression(thatis,anexpressionthatcanonlybeevaluatedin
Description
simulation).Iftheexpressionisconstant,theforstatementmayloopindefinitely
(forexample:for(j=30j=j2),j=0isneverreached).
Policy
Leda
Ruleset
EXPRESSIONS
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingisaVerilogcodeexample,withtheforloopsthatcontaincomparisonsorconstants
notedwithcomments:
moduleB_3203(a,z)
input[3:0]a
output[3:0]z
reg[3:0]comb
integerj
parameterp1=12
parameterp2=1.5
always@(a)begin
for(j=30j=j1)//Endloopvalueisconstant(0)
comb[j]=a[j]
end
always@(a)begin
for(j=3j<10j=j+1)//Endloopvalueisacomparison
comb[j]=a[j]
end
always@(a)begin
for(j=3j<=10j=j+1)//Endloopvalueisacomparison
comb[j]=a[j]
end
always@(a)begin
for(j=34*p1p2j=j+1)//Endloopvalueisconstant
comb[j]=a[j]
end
assignz=comb
endmodule
B_3204
Message:?inbasednumberconstantisnotallowed
Description
Thisruleforbidstheuseof?inalogicstringliteral.DesignCompileridentifies?
assignmentsasunconnected.
Policy
Leda
Ruleset
EXPRESSIONS
Language
Verilog
Type
Blocklevel
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Severity
Warning
Example
FollowingisanexampleofinvalidVerilogcode:
moduleB_3204(A,B,SEL,DATA_OUT)
inputA,B
input[3:0]SEL
outputDATA_OUT
reg[3:0]DATA_OUT
always@(AorBorSEL)begin
if(SEL==4'b1???)//Undefinedvalueforcomparison
DATA_OUT<=A
else
DATA_OUT<=B
end
endmodule
B_3206
Message:Xinbasednumberconstant
Description TheCheckerreportsXinenumeratedliterals.
Policy
Leda
Ruleset
EXPRESSIONS
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVHDLcode:
libraryIEEE
useIEEE.std_logic_1164.all
entityb_3206is
port(CLK,RST,SEL,A_IN:instd_logic
A_OUT:outstd_logic)
end
architectureRTLofb_3206is
begin
process(CLK,RST)begin
if(RST='X')thenInvalidcomparisonto'X'value
A_OUT<='0'
elsif(CLK'eventandCLK='1')then
if(SEL='1')then
A_OUT<=A_IN
else
A_OUT<='X'Invalidassignmentto'X'value
endif
endif
endprocess
end
B_3207
Message:Zinbasednumberconstant
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Description TheCheckerreportsZinenumeratedliterals.
Policy
Leda
Ruleset
EXPRESSIONS
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVHDLcode:
libraryIEEE
useIEEE.std_logic_1164.all
entityb_3207is
port(CLK,RST,SEL,A_IN:instd_logic
A_OUT:outstd_logic)
end
architectureRTLofb_3207is
begin
process(CLK,RST)begin
if(RST='Z')thenInvalidcomparisonto'Z'value
A_OUT<='0'
elsif(CLK'eventandCLK='1')then
if(SEL='1')then
A_OUT<=A_IN
else
A_OUT<='Z'Invalidassignmentto'Z'value
endif
endif
endprocess
end
B_3208
Message:UnequallengthLHSandRHSinassignmentLHS:<%size>,RHS:
<%size>
Description None.
Policy
Leda
Ruleset
EXPRESSIONS
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3209
Message:Unequallengthportandconnexioninmoduleinstantiation
Formal:<%size>,Actual:<%size>
Description None.
Policy
Leda
Ruleset
EXPRESSIONS
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Language
Verilog
Type
Blocklevel
Severity
Warning
B_3210
Message:UnequallengthargumentsinfunctioncallortaskenableFormal:
<%size>,Actual:<%size>
Description None.
Policy
Leda
Ruleset
EXPRESSIONS
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3211
Message:Unequallengthbetweencaseexpressionandcaseitemcondition
incase,casexorcasezExpression:<%size>,Item:<%size>
Description None.
Policy
Leda
Ruleset
EXPRESSIONS
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3212
Message:Signedandunsignedoperandsshouldnotbeusedinsame
operation
Ifamixtureofsignedandunsignedoperandsareused,theresultisunsignedand
Description maygiveunexpectedresults.TheLRMindicatesforallexpressionwhetherit'ssigned
orunsigned,andthisinformationisusedbytheattribute.
Policy
Leda
Ruleset
EXPRESSIONS
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
moduleB_3212(s_a,s_b2,s_b3,us_b)
inputsigned[9:0]s_a,s_b2
inputsigned[9:0]s_b3
inputunsigned[9:0]us_b
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regsigned[10:0]s_x
wiresigned[10:0]s_x2
//Testsforsigned/unsignedarithmeticoperations
assigns_x2=s_as_b3*f(us_b)//pass
assigns_x2=s_as_b2*s_a//pass
assigns_x2=f(us_b)+$unsigned(b)//Fail
assigns_x2=g(us_b)+$unsigned(b)//pass
assigns_x2=$signed(a)+$unsigned(b)//Fail
assigns_x2=$unsigned(a)+$unsigned(b)//pass
assigns_x2=s_a+us_b//Fail
always@(s_aorus_bors_b2)begin
s_x<=s_aus_b*s_b2//Fail
s_x<=s_as_b2*us_b//Fail
s_x<=s_as_b3*s_a//pass
s_x<=s_as_b3*f(us_b)//pass
s_x<=s_as_b3*g(us_b)//Fail
end
endmodule
functionsignedf
inputunsigned[9:0]c
return1
endfunction
functionunsignedg
inputunsigned[9:0]c
return$unsigned(1)
endfunction
StatementsRuleset
Thefollowingrulesarefromthestatementsruleset:
B_3400
Message:Emptyblockfound:Nostatementsinblock
Description
TheCheckerdetectsemptyblocksinallunits.Emptyblocksareoptimizedoutduring
synthesistheyperformnofunction,occupydiskspace,andcauseconfusion.
Policy
Leda
Ruleset
STATEMENTS
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3401
Message:Blockingdelaynotallowedinnonblockingassignment
Description
Thisrulefiresifthereisadelayinanonblockingassignment.Blockingdelaysin
nonblockingassignmentsarenotsynthesizable.
Policy
Leda
Ruleset
STATEMENTS
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Language
Verilog
Type
Blocklevel
Severity
Warning
Example
RuleB_3401firesifthereisadelayinanonblockingassignment.TheLRMdefinesthenon
blockingassignmentas:
nonblockingassignment::=[delay_or_event_control]expression.
Ifyouconsiderthefollowingtwostatements:
#10ff_out<=data_in//Thisnonblockingassignmenthasnodelay,
//B_3401willnotfire.
#10ff_out<=#5data_in//Thisnonblockingassignmenthasadelay5,
//B_3401willfire
The#10delayisthedelayoftheprocedural_timing_control_statement,whichisdefinedinthe
LRMas:
procedural_timing_control_statement::=delay_or_event_controlstatement
Inthisexample,afterthedelay_or_event_controlis#10,thestatementisff_out<=comb,which
itselfhasnodelay.
Inthefollowingexample,ProVerilogfiresforff_in<=#10data_in
always@(posedgeclk)
begin:Data_input
ff_in<=#10data_in//FAIL(B_3401fires,thenonblocking
end//assignmentdelayis10
//processData_input
assigncomb=ff_in
always@(posedgeclk)
begin:Data_output
#10ff_out<=comb//B_3401doesnotfirethiscase
end//processData_output
B_3402
Message:Taskusesaglobalvariable
Description
Ifavariabledeclaredoutsidethetaskisusedinataskdeclaration,theChecker
reportsawarning.Writingtovariablesdeclaredoutsidethetaskbodyisnotallowed.
Policy
Leda
Ruleset
STATEMENTS
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVerilogcodethatusesaglobalvariabledeclaredoutsidethe
task:
moduleG_3402_1(a,b,z)
inputa
inputb
outputz
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regcomb
always@(aorb)
begin
and_op(a,b)
end
taskand_op//FAIL
inputa
inputb
begin
comb=a&b//Failsbecauseglobalvariablecombisused
end
endtask
assignz=comb
taskis_ok//PASS
inputa
inputb
outputlocal_var
reglocal_var
begin
local_var=a&b//B_3402doesnotfireinthiscasebecauseno
//globalvariablesareusedinsidethetask
end
endtask
endmodule
B_3403
Message:Casestatementshouldhaveadefaultcase
ThisruleverifiesthatacasestatementhasadefaultcaseforVerilogoran"others"
Description clauseforVHDL.Ifnot,theCheckerreportsawarning.Ifthecaseisnotfully
specifiedandthereisnodefaultstatement(inVerilog),alatchisinferred.
Policy
Leda
Ruleset
STATEMENTS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_3404
Message:Casexstatementshouldhaveadefaultcase
Thisruleverifiesthatacasexstatementhasadefaultcase.Ifnot,theChecker
Description reportsawarning.Ifthecaseisnotfullyspecifiedandthereisnodefault
statement,alatchisinferred.
Policy
Leda
Ruleset
STATEMENTS
Language
Verilog
Type
Blocklevel
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Severity
Warning
B_3405
Message:Casezstatementshouldhaveadefaultcase
Thisruleverifiesthatacasezstatementhasadefaultcase.Ifnot,theChecker
Description reportsawarning.Ifthecaseisnotfullyspecifiedandthereisnodefault
statement,alatchisinferred.
Policy
Leda
Ruleset
STATEMENTS
Language
Verilog
Type
Blocklevel
Severity
Warning
B_3407
Message:Nonullstatementsinprocessstatement
Usingnullstatementsisnotatoolissuebutmoreofamethodologyissue(thisisan
exampleofwhatisusuallycalledabadcodingpractice).Nullstatementsareoften
Description
usedwhendesignfunctionalityisnotfullydescribedorwhenallconditionsofacase
arenotcorrectlydefined.Thiscancreatebugsinthedesign.
Policy
Leda
Ruleset
STATEMENTS
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVHDLcode:
libraryIEEE
useIEEE.std_logic_1164.all
entityb_3407is
port(CLK,RST,A_IN:instd_logic
A_OUT:outstd_logic)
end
architectureRTLofb_3407is
begin
process(CLK)begin
if(CLK'eventandCLK='1')then
A_OUT<=A_IN
else
NULLFAIL:Don'tuseNULLstatement
endif
endprocess
end
B_3408
Message:Caseconditionexpressionshouldnotbeconstant
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Thisruleverifiesthatnocasestatementconditionsareconstants.Condition
Description expressionsshouldnotbeevaluatedduringcompilation.Aconstantexpression
violatesthepurposeofacasestatement.
Policy
Leda
Ruleset
STATEMENTS
Language
VHDL
Type
Blocklevel
Severity
Error
Example
ThefollowingisainvalidVHDLcodeexamplebecauseitusesaconstantinacasecondition
expression:
entityB_3408_OKis
port(A_IN,SEL:instd_logic
A_OUT:outstd_logic)
end
architectureRTL_BADofB_3408is
constantTMP:std_logic:='1'
constantFS_COND:std_logic:='1'
begin
process(SEL,A_IN)begin
case(FS_COND)isFAIL:Caseconditionexpression
whenTMP=>A_OUT<=A_INshouldNOTbeconstant
whenothers=>A_OUT<='X'
endcase
endprocess
end
PassingCondition:
architectureRTL_GOODofB_3408is
begin
process(SEL,A_IN)begin
case(SEL)isPASS
when'1'=>A_OUT<=A_IN
whenothers=>A_OUT<='0'
endcase
endprocess
end
B_3409
Message:Whileconditionexpressionisconstant
Thisrulesverifiesthatnowhilestatementconditionsareconstant.Condition
Description expressionshouldnotbeevaluatedduringcompilation.Ifaconstantisused,the
whilewillnevercomeoutoftheloop.
Policy
Leda
Ruleset
STATEMENTS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
Example
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ThefollowingareinvalidVHDLandVerilogcodingexamplesbecausetheyuseconstantsforwhile
conditions:
InvalidVHDLCode:
architectureRTLofB_3409_1is
signalclk:std_logic
signalcount:std_logic_vector(3downto0)
signalqout:std_logic_vector(3downto0)
constantTMP:std_logic:='1'
begin
process(clk)
begin
while(TMP='1')loopFAIL:Don'tuseconstant
if(clk'eventandclk='1')thenforwhilecondition
count<=count+'1'
qout<=qout+count
endif
endloop
endprocess
end
InvalidVerilogCode:
moduleG_3409_1(
a,
z
)
input[3:0]a
output[3:0]z
reg[3:0]comb
regtest
integerj
integerk
always@(a)
begin
j=0
while(k==2)//PASS
begin
comb[j]=a[j]
j=j+1
end
end
always@(a)
begin
j=0
while(3)//FAIL
begin
comb[j]=a[j]
j=j+1
end
end
endmodule
B_3410
Message:Xincaseexpression
Description
ThisruleverifiesthatnocaseexpressionscontainanX.Therewillbesimulation
mismatchesifdifferentsimulatorsareused.
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Policy
Leda
Ruleset
STATEMENTS
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
ThefollowingisanexampleofinvalidVHDLcodebecauseitusesanXinacaseexpression:
libraryIEEE
useIEEE.std_logic_1164.all
entityb_3410is
port(SEL
A_OUT
end
:instd_logic
:outstd_logic)
architectureRTLofb_3410is
begin
process(SEL)begin
case(SEL)is
when'1'=>A_OUT<='1'
when'X'=>A_OUT<='0'FAIL:Don'tuseXinchoiceof
casestatement
whenothers=>A_OUT<='Z'
endcase
endprocess
end
B_3411
Message:Assignmenttoasupply0typenet
Description
Allassignmentstoasupply0netarereportedaserrors.Asupply0netisconnected
togroundassignmentstosupplytypenetscancauseproblemswithlayouttools.
Policy
Leda
Ruleset
STATEMENTS
Language
Verilog
Type
Blocklevel
Severity
Error
B_3412
Message:Assignmenttoasupply1typenet
Description
Allassignmentstoasupply1netarereportedaserrors.Asupply1netisconnected
topowerassignmentstosupplytypenetscancauseproblemswithlayouttools.
Policy
Leda
Ruleset
STATEMENTS
Language
Verilog
Type
Blocklevel
Severity
Error
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B_3413
Message:Taskcallinacombinationalblock
Thisruleverifiesthatacombinatorialblockdoesnotcallatask.Ifso,theChecker
reportsanerror.Ataskcanonlybecalledfromwithinanalwaysstatement.Nested
Description
alwaysstatementsarenotallowedinVerilog.Therefore,sequentiallogiccannotbe
modeledusingatask.Ataskcaneasilyberemodeledasafunction.
Policy
Leda
Ruleset
STATEMENTS
Language
Verilog
Type
Blocklevel
Severity
Note
B_3414
Message:Taskcallinasequentialblock
Thisrulefiresifataskisusedinasequentialblock.Ataskcanonlybecalledfrom
withinanalwaysstatement.NestedalwaysstatementsarenotallowedinVerilog.
Description
Therefore,sequentiallogiccannotbemodeledusingatask.Ataskcaneasilybe
remodeledasafunction.
Policy
Leda
Ruleset
STATEMENTS
Language
Verilog
Type
Blocklevel
Severity
Note
B_3415
Message:Theremustbeatleastonedriverforallelementsofasignal
Description
Thisrulechecksthatasignalisatleastdrivenbyasignaloraport.Uncontrollable
signalscauseproblemsduringtestinsertionanXispropagatedduringsimulation.
Policy
Leda
Ruleset
STATEMENTS
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVHDLcode:
entityB_3415_1is
port(SEL,A_IN,B_IN:instd_logic
DATA_OUT:outstd_logic)
end
architectureRTLofB_3415_1is
signaltmp:std_logicFAIL:Uncontrollablesignal
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begin
process(SEL)begin
if(SEL='1')then
DATA_OUT<=tmp
else
DATA_OUT<='0'
endif
endprocess
end
B_3416
Message:Usingnonblockingassignmentsincombinationalalwaysmay
generateincorrectlogic
Useblockingassignmentsinalwaysblocksthatarewrittentogenerate
Description combinationallogic.Thispreventssimulationmismatchesbetweenpreandpost
synthesisnetlists.
Policy
Leda
Ruleset
STATEMENTS
Language
Verilog
Type
Blocklevel
Severity
Error
B_3417
Message:Usenonblockingassignmentsinsequentialblock
Usenonblockingassignmentsinalwaysblocksthatarewrittentogenerate
Description sequentiallogic.Thispreventssimulationmismatchesbetweenpreandpost
synthesisnetlists.Thisruleisflaggedforunintentionallatchesalso.
Policy
Leda
Ruleset
STATEMENTS
Language
Verilog
Type
Blocklevel
Severity
Error
B_3418
Message:Redundantsignalinsensitivitylist
Redundantorunneededsignalsinsensitivitylistscancreatewarningsinsynthesis,
Description slowdownsimulation,andpossiblycreatemismatchesbetweensimulationand
synthesismodels.Allredundantsignalsmustberemovedfromthesensitivitylist.
Policy
Leda
Ruleset
STATEMENTS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Error
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B_3419
Message:Missingsignalinsensitivitylist
Description None.
Policy
Leda
Ruleset
STATEMENTS
Language
VHDL/Verilog
Type
Blocklevel
Severity
Error
B_3420
Message:While/foreverloophasnobreakcontrol
Description
ThisruleisflaggedwhenLedafindsawhile/foreverloopwithnobreakcontrol
statement.
Policy
Leda
Ruleset
DATA_TYPES
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVerilogcode:
moduletest(inputwirereset,clk,D,outputreg[4:0]count)
parameterP=5
integerI
always
begin
I=0
forever
//FAIL:Nobreak
begin
count<=count+I
end
while(I<5)
//FAIL:Nobreak
begin
count<=count+I
i++
end
end
endmodule
B_3421
Message:Functionorsubprogramsetsaglobalsignal/variable
Description
ThisruleisflaggedwhenLedafindsafunctionorsubprogramsetsaglobal
signal/variable.
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Policy
Leda
Ruleset
DATA_TYPES
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVHDLcode:
FAILglobalvariable"counter"isbeingsetinsidefunction/procedure
libraryIEEE
useIEEE.std_logic_1164.all
useIEEE.std_logic_unsigned.all
useIEEE.Numeric_STD.all
entityshared_varis
end
architecturearchofshared_varis
subtypeshort_rangeisintegerrange0to1
sharedvariablecounter:short_range:=0FAIL
procedureTempProc(A:std_logic)is
begin
counter:=counter+1FAILsharedvar.setinsideaproc
end
impurefunctionTempFunc(A:std_logic)returnstd_logicisFAIL1
variableWRITE1:std_logic
begin
counter:=counter+1FAILsharedvar.setinsideaproc
infunction
returnWRITE1
endTempFunc
begin
endarch
B_3422
Message:Functionorsubprogramusesaglobalsignal/variable
Description
ThisruleisflaggedwhenLedafindsafunctionorsubprogramusesaglobal
signal/variable.
Policy
Leda
Ruleset
DATA_TYPES
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVHDLcode:
FAILglobalvariable"counter"isbeingreadinsidefunction/procedure
libraryIEEE
useIEEE.std_logic_1164.all
useIEEE.std_logic_unsigned.all
useIEEE.Numeric_STD.all
entityshared_varis
end
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architecturearchofshared_varis
subtypeshort_rangeisintegerrange0to1
sharedvariablecounter:short_range:=0
procedureTempProc(A:std_logic)is
begin
counter:=counter+1FAILsharedvar.isusedinsideaproc.
end
impurefunctionTempFunc(A:std_logic)returnstd_logicis
variableWRITE1:std_logic
begin
counter:=counter+1FAILsharedvar.isusedinsideafunc.
returnWRITE1
endTempFunc
begin
endarch
B_3423
Message:Donotconnectbussestoinstancesinreverseorder
Description
ThisruleisflaggedwhenLedafindsabussignalconnectedtoaninstanceinreverse
order.
Policy
Leda
Ruleset
DATA_TYPES
Language
VHDL
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofinvalidVHDLcode:
//Inthetestcase,boththeportsofcomp1areconnectedtothebusesin
reversebitorder
libraryIEEE
useIEEE.std_logic_1164.all
useIEEE.std_logic_unsigned.all
useIEEE.Numeric_STD.all
entityreverse_bitis
end
architecturearchofreverse_bitis
componentcomp1port(a:instd_logic_vector(3downto0)
b:outstd_logic_vector(0to4)
)
endcomponent
signalc:std_logic_vector(0to3)
signald:std_logic_vector(4downto0)
begin
c1:comp1portmap(a=>c,FAIL:reversebitorder
b=>dFAIL:reversebitorder
)
endarch
B_3426
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Message:Avoidusingmultipleifandcaseinaprocessstatementthatinfer
aflipflop.
Description
Ledaflagsthiserrormessagewhenitdetectsmultiple"if"and"case"statementsin
thedescriptionofclockevent.
Policy
Leda
Ruleset
STATEMENTS
Language
VHDL
Type
Blocklevel
Severity
Error
Examples
Thefollowingareexamplesofvalidandinvalidcode:
Example1:Failexample
libraryieee
useieee.std_logic_1164.all
useieee.std_logic_unsigned.all
entitytestis
port(
RSTN:INstd_logic
CLK:INstd_logic
)
endtest
architectureaoftestis
signalM_IN,D_IN,IN_ENB,IN_TMP:std_logic
signalsig_reg:std_logic_vector(3downto1)
constantDE_LAY:integer:=3
begin
DELAY_SIGNAL:process(RSTN,CLK)
begin
if(RSTN='0')then
sig_reg<=(others=>'0')
elsif(CLK'eventandCLK='1')then
multipleifstatements
if(IN_ENB='0')then1if_statement
sig_reg<=sig_reg(DE_LAY1downto1)&M_IN
else
sig_reg<=sig_reg(DE_LAY1downto1)&D_IN
endif
if(IN_ENB='1')then2if_statement
sig_reg(3)<=IN_TMP
else
sig_reg(3)<=sig_reg(3)
endif
endif
endprocess
enda
Configuration:
rule_deselectall
rule_selectruleB_3426
Violations:
19:if(RSTN='0')then
^^
test.vhd:19:STATEM>[ERROR]B_3426:Avoidusingmultipleifandcasein
aprocessstatementthatinferaflipflop
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Example2:Failexample
libraryieee
useieee.std_logic_1164.all
useieee.std_logic_unsigned.all
entitytestis
port(
RSTN:INstd_logic
CLK:INstd_logic
)
endtest
architectureaoftestis
signalM_IN,D_IN,IN_ENB,IN_TMP:std_logic
signalsig_reg:std_logic_vector(3downto1)
constantDE_LAY:integer:=3
begin
DELAY_SIGNAL:process(RSTN,CLK)
begin
if(RSTN='0')then
multipleifstatements
if(M_IN='0')then1if_statement
sig_reg<=(others=>'0')
endif
if(D_IN='0')then2if_statement
sig_reg<=(others=>'1')
endif
elsif(CLK'eventandCLK='1')then
if(IN_ENB='0')then
sig_reg<=sig_reg(DE_LAY1downto1)&M_IN
else
sig_reg<=sig_reg(DE_LAY1downto1)&D_IN
endif
endif
endprocess
enda
Configuration:
rule_deselectall
rule_selectruleB_3426
Violations:
19:if(RSTN='0')then
^^
test1.vhd:19:STATEM>[ERROR]B_3426:Avoidusingmultipleifandcase
inaprocessstatementthatinferaflipflop
Example3:Failexample
libraryIEEE
useIEEE.std_logic_1164.all
useIEEE.std_logic_arith.all
useIEEE.std_logic_unsigned.all
entitytestis
port(
System
RSTN:instd_logicasynchronousresetsignal(lowactive)
CLK:instd_logicclockINPUT
M_IN:instd_logicenablesignal
D_IN:instd_logicenablesignal
IN_ENB:instd_logicenable
IN_TMP:instd_logictempOUTPUT
OUT_ALL:outstd_logic_vector(3downto1)enablesignal
OUT_3:outstd_logicenablesignal)
endtest
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architectureRTLoftestis
constantDE_LAY:positive:=3DFF
signalsig_reg:std_logic_vector(DE_LAYdownto1)
begin
DELAY_SIGNAL:process(RSTN,CLK)
begin
if(RSTN='0')then
sig_reg<=(others=>'0')
elsif(CLK'eventandCLK='1')then
multiplecasestatements
caseIN_ENBis1case_statement
when'0'=>sig_reg<=sig_reg(DE_LAY1downto1)&M_IN
when'1'=>sig_reg<=sig_reg(DE_LAY1downto1)&D_IN
whenothers=>sig_reg<="XXX"
endcase
caseIN_ENBis2case_statement
when'1'=>sig_reg(3)<=IN_TMP
when'0'=>sig_reg(3)<=sig_reg(3)
whenothers=>sig_reg(3)<='X'
endcase
endif
endprocess
OUTPUT
OUT_ALL<=sig_reg
OUT_3<=sig_reg(DE_LAY)
endRTL
Configuration:
rule_deselectall
rule_selectruleB_3426
Violations:
37:if(RSTN='0')then
^^
test2.vhd:37:STATEM>[ERROR]B_3426:Avoidusingmultipleifandcase
inaprocessstatementthatinferaflipflop
Example4:Failexample
test
libraryIEEE
useIEEE.std_logic_1164.all
useIEEE.std_logic_arith.all
useIEEE.std_logic_unsigned.all
entitytestis
port(System
RSTN:instd_logicasynchronousresetsignal(lowactive)
CLK:instd_logicclockINPUT
M_IN:instd_logicenablesignal
D_IN:instd_logicenablesignal
IN_ENB:instd_logicenable
IN_TMP:instd_logictempOUTPUT
OUT_ALL:outstd_logic_vector(3downto1)enablesignal
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OUT_3:outstd_logicenablesignal)
endtest
architectureRTLoftestis
constantDE_LAY:positive:=3
DFF
signalsig_reg:std_logic_vector(DE_LAYdownto1)
begin
DELAY_SIGNAL:process(RSTN,CLK)
begin
if(RSTN='0')then
sig_reg<=(others=>'0')
elsif(CLK'eventandCLK='1')thenFALSE
multipleifandcasestatement
if(IN_ENB='0')then1ifstatment
sig_reg<=sig_reg(DE_LAY1downto1)&M_IN
else
sig_reg<=sig_reg(DE_LAY1downto1)&D_IN
endif
caseIN_ENBis1case_statement
when'1'=>sig_reg(3)<=IN_TMP
when'0'=>sig_reg(3)<=sig_reg(3)
whenothers=>sig_reg(3)<='X'
endcase
endif
endprocess
OUTPUT
OUT_ALL<=sig_reg
OUT_3<=sig_reg(DE_LAY)
endRTL
Configuration:
rule_deselectall
rule_selectruleB_3426
Violations:
37:if(RSTN='0')then
^^
test3.vhd:37:STATEM>[ERROR]B_3426:Avoidusingmultipleifandcase
inaprocessstatementthatinferaflipflop
Example5:Passexample
test
libraryIEEE
useIEEE.std_logic_1164.all
useIEEE.std_logic_arith.all
useIEEE.std_logic_unsigned.all
entitytestis
port(
System
RSTN:instd_logicasynchronousresetsignal(lowactive)
CLK:instd_logicclockINPUT
M_IN:instd_logicenablesignal
D_IN:instd_logicenablesignal
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IN_ENB:instd_logicenable
IN_TMP:instd_logictempOUTPUT
OUT_ALL:outstd_logic_vector(3downto1)enablesignal
OUT_3:outstd_logicenablesignal)
endtest
architectureRTLoftestis
constantDE_LAY:positive:=3
DFF
signalsig_reg:std_logic_vector(DE_LAYdownto1)
begin
DELAY_SIGNAL:process(RSTN,CLK)
begin
if(RSTN='0')then
sig_reg<=(others=>'0')
elseTRUE
noclockdescription,notfire
if(IN_ENB='0')then
sig_reg<=sig_reg(DE_LAY1downto1)&M_IN
else
sig_reg<=sig_reg(DE_LAY1downto1)&D_IN
endif
caseIN_ENBis
when'1'=>sig_reg(3)<=IN_TMP
when'0'=>sig_reg(3)<=sig_reg(3)
whenothers=>sig_reg(3)<='X'
endcase
endif
endprocess
OUTPUT
OUT_ALL<=sig_reg
OUT_3<=sig_reg(DE_LAY)
endRTL
FiniteStateMachineRuleset
Thefollowingrulesarefromthefinitestatemachinesruleset:
B_3600
Message:Codestatemachinesdescriptionwithoneblock
Codestatemachines(andothersequentiallogic)withonesequentialblockor
Description process.Improvereadabilitybygeneratingcomplexintermediatevariablesoutsideof
thesequentialblock.
Policy
Leda
Ruleset
STATE_MACHINES
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
ForinformationonhowLedainfersfinitestatemachines,see"FiniteStateMachineRecognition".
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B_3601
Message:Codestatemachinesdescriptionwithtwoblocks
Description
SeparatethestatemachineHDLdescriptionintotwoblocks,oneforthe
combinationallogicandoneforthesequentiallogic(seefollowingexamples).
Policy
Leda
Ruleset
STATE_MACHINES
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
ForinformationonhowLedainfersfinitestatemachines,see"FiniteStateMachineRecognition".
Example
ThefollowingexamplesillustratehowtocodevalidfinitestatemachinesinVHDLandVerilog.
ValidVHDLFSMCodingExample:
libraryIEEE,STD
useIEEE.std_logic_1164.all
useIEEE.std_logic_components.all
useIEEE.std_logic_misc.all
entityfsmis
port(
x:instd_logic
rst:instd_logic
clock:instd_logic
z
:outstd_logic)
endfsm
architecturertloffsmis
typestateis(STATE_0,STATE_1,STATE_2,STATE_3)
signalcurrent_state,next_state:state
begin
combinationalprocesscalculatesnextstate
COMBO_PROC:process(x,current_state)
begin
case(current_state)is
whenSTATE_0=>
z<='0'
ifx='0'then
next_state<=STATE_0
else
next_state<=STATE_1
endif
whenSTATE_1=>
z<='0'
ifx='0'then
next_state<=STATE_1
else
next_state<=STATE_2
endif
whenSTATE_2=>
z<='0'
ifx='0'then
next_state<=STATE_2
else
next_state<=STATE_3
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endif
whenSTATE_3=>
ifx='0'then
z<='0'
next_state<=STATE_3
else
z<='1'
next_state<=STATE_0
endif
whenothers=>
next_state<=STATE_0
endcase
endprocessCOMBO_PROC
synchronousprocessupdatescurrentstate
SYNCH_PROC:process(rst,clock)
begin
if(rst='1')then
current_state<=STATE_0
elsif(clock'eventandclock='1')then
current_state<=next_state
endif
endprocessSYNCH_PROC
endrtl
ValidVerilogFSMCodingExample:
modulefsm(clock,rst,x,z)
inputclock,rst,x
outputz
reg[1:0]current_state
reg[1:0]next_state
regz
parameter[1:0]
STATE_0=0,
STATE_1=1,
STATE_2=2,
STATE_3=3
//combinationalprocesscalculatesnextstate
always@(current_stateorx)
case(current_state)//synopsysparallel_casefull_case
STATE_0:begin
if(x)begin
next_state<=STATE_1
z<=1'b0
endelsebegin
next_state<=STATE_0
z<=1'b0
end
end
STATE_1:begin
if(x)
begin
next_state<=STATE_2
z<=1'b0
end
else
begin
next_state<=STATE_1
z<=1'b0
end
end
STATE_2:begin
if(x)
begin
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next_state<=STATE_3
z<=1'b0
end
else
begin
next_state<=STATE_2
z<=1'b0
end
end
STATE_3:begin
if(x)
begin
next_state<=STATE_0
z<=1'b1
end
else
begin
next_state<=STATE_3
z<=1'b0
end
end
default:begin
next_state<=STATE_0
z<=1'b0
end
endcase
always@(posedgeclockornegedgerst_na)
begin
if(!rst_na)
current_state<=STATE_0
else
current_state<=next_state
end
endmodule
B_3602
Message:Moorestyledescriptionofstatemachinesisrecommended
Usually,Moorestylestatemachinesarerecommended.InaMoorestylestate
machine,foragivenstateoutputvaluesaredefinedanddonotdependonany
inputs.Thisavoidscombinatorialpathsbetweeninputsandoutputsthatmaycreate
Description
timingissueswhenintegratingthestatemachineinthewholedesign.Thedrawback
ofMoorestylestatemachinesisthatthenumberofstatesincreases.Selectthisrule
orruleB_3603dependingonyourcompany'srecommendedcodingstyle.
Policy
Leda
Ruleset
STATE_MACHINES
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
ForinformationonhowLedainfersfinitestatemachines,see"FiniteStateMachineRecognition".
InthefollowingexampleofaMoorestylestatemachine,thezoutputisclearlydefinedtoafixed
valueanddoesnotdependonanysignal.
Example
modulefsm(clock,rst,z)
inputclock
inputrst
outputz
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reg[1:0]current_state
reg[1:0]next_state
regz
parameter[1:0]STATE_0=0,STATE_1=1,STATE_2=2,STATE_3=3
always@(current_state)
case(current_state)
STATE_0:begin
next_state=STATE_1
z=1'b0
end
STATE_1:begin
next_state=STATE_2
z=1'b0
end
STATE_2:begin
next_state=STATE_3
z=1'b1
end
STATE_3:begin
next_state=STATE_0
z=1'b1
end
default:begin
next_state=STATE_0
z=1'b0
end
endcase
always@(posedgeclockornegedgerst)
begin
if(rst==1'b0)current_state<=STATE_0
elsecurrent_state<=next_state
end
endmodule
B_3603
Message:Mealystyledescriptionofstatemachinesisrecommended
InaMealystylestatemachine,theoutputsdependnotonlyonthecurrentstate,
butalsoontheinputs.Thereisariskoftimingissueswiththiscodingstyle,butthe
Description
numberofstatesdecreasescomparedtoMoorestylestatemachines.Selectthisrule
orruleB_3602dependingonyourcompany'srecommendedcodingstyle.
Policy
Leda
Ruleset
STATE_MACHINES
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
ForinformationonhowLedainfersfinitestatemachines,see"FiniteStateMachineRecognition".
InthefollowingexampleofaMealystylestatemachine,intheSTATE_0state,dependingonthe
valueofmy_input,zwillcanbe0or1andthenext_statewillbedifferent.
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Example
modulefsm(clock,rst,z,my_input)
inputclock
inputrst
inputmy_input
outputz
reg[1:0]current_state
reg[1:0]next_state
regz
parameter[1:0]STATE_0=0,STATE_1=1,STATE_2=2
always@(current_stateormy_input)
case(current_state)
STATE_0:begin
if(my_input==1'b0)begin
next_state=STATE_1
z=1'b0
end
elsebegin
next_state=STATE_0
z=1'b1
end
end
STATE_1:begin
next_state=STATE_2
z=1'b0
end
STATE_2:begin
next_state=STATE_0
z=1'b1
end
default:begin
next_state=STATE_0
z=1'b0
end
endcase
always@(posedgeclockornegedgerst)
begin
if(rst==1'b0)current_state<=STATE_0
elsecurrent_state<=next_state
end
endmodule
B_3604
Message:Assignadefaultstatetothestatemachines
Assignadefaultstateforthestatemachine.Thisisusefultoimplementgraceful
entryintotheidlestateifnootherstateisinitiated.ForVHDL,assignastatefor
Description
the"others"conditionandforVerilog,assigna"default"stateasshowninthe
followingexamples.
Policy
Leda
Ruleset
STATE_MACHINES
Language
VHDL/Verilog
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Type
Blocklevel
Severity
Warning
ForinformationonhowLedainfersfinitestatemachines,see"FiniteStateMachineRecognition".
Example
ThefollowingexamplesillustratehowtocodevalidfinitestatemachinesinVHDLandVerilog.
ValidVHDLFSMCodingExample:
libraryIEEE,STD
useIEEE.std_logic_1164.all
useIEEE.std_logic_components.all
useIEEE.std_logic_misc.all
entityfsmis
port(
x:instd_logic
rst:instd_logic
clock:instd_logic
z
:outstd_logic)
endfsm
architecturertloffsmis
typestateis(STATE_0,STATE_1,STATE_2,STATE_3)
signalcurrent_state,next_state:state
begin
combinationalprocesscalculatesnextstate
COMBO_PROC:process(x,current_state)
begin
case(current_state)is
whenSTATE_0=>
z<='0'
ifx='0'then
next_state<=STATE_0
else
next_state<=STATE_1
endif
whenSTATE_1=>
z<='0'
ifx='0'then
next_state<=STATE_1
else
next_state<=STATE_2
endif
whenSTATE_2=>
z<='0'
ifx='0'then
next_state<=STATE_2
else
next_state<=STATE_3
endif
whenSTATE_3=>
ifx='0'then
z<='0'
next_state<=STATE_3
else
z<='1'
next_state<=STATE_0
endif
whenothers=>
next_state<=STATE_0
endcase
endprocessCOMBO_PROC
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synchronousprocessupdatescurrentstate
SYNCH_PROC:process(rst,clock)
begin
if(rst='1')then
current_state<=STATE_0
elsif(clock'eventandclock='1')then
current_state<=next_state
endif
endprocessSYNCH_PROC
endrtl
ValidVerilogFSMCodingExample:
modulefsm(clock,rst,x,z)
inputclock,rst,x
outputz
reg[1:0]current_state
reg[1:0]next_state
regz
parameter[1:0]
STATE_0=0,
STATE_1=1,
STATE_2=2,
STATE_3=3
//combinationalprocesscalculatesnextstate
always@(current_stateorx)
case(current_state)//synopsysparallel_casefull_case
STATE_0:begin
if(x)begin
next_state<=STATE_1
z<=1'b0
endelsebegin
next_state<=STATE_0
z<=1'b0
end
end
STATE_1:begin
if(x)
begin
next_state<=STATE_2
z<=1'b0
end
else
begin
next_state<=STATE_1
z<=1'b0
end
end
STATE_2:begin
if(x)
begin
next_state<=STATE_3
z<=1'b0
end
else
begin
next_state<=STATE_2
z<=1'b0
end
end
STATE_3:begin
if(x)
begin
next_state<=STATE_0
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z<=1'b1
end
else
begin
next_state<=STATE_3
z<=1'b0
end
end
default:begin
next_state<=STATE_0
z<=1'b0
end
endcase
always@(posedgeclockornegedgerst_na)
begin
if(!rst_na)
current_state<=STATE_0
else
current_state<=next_state
end
endmodule
B_3605_A
Message:Useparameterdeclarationstodefinethestatevectorofastate
machine
Description None.
Policy
Leda
Ruleset
STATE_MACHINES
Language
Verilog
Type
Blocklevel
Severity
Warning
ForinformationonhowLedainfersfinitestatemachines,see"FiniteStateMachineRecognition".
Example
ThefollowingexampleillustrateshowtocodevalidfinitestatemachinesinVerilog:
modulefsm(clock,rst,x,z)
inputclock,rst,x
outputz
reg[1:0]current_state
reg[1:0]next_state
regz
parameter[1:0]
STATE_0=0,
STATE_1=1,
STATE_2=2,
STATE_3=3
//combinationalprocesscalculatesnextstate
always@(current_stateorx)
case(current_state)//synopsysparallel_casefull_case
STATE_0:begin
if(x)begin
next_state<=STATE_1
z<=1'b0
endelsebegin
next_state<=STATE_0
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z<=1'b0
end
end
STATE_1:begin
if(x)
begin
next_state<=STATE_2
z<=1'b0
end
else
begin
next_state<=STATE_1
z<=1'b0
end
end
STATE_2:begin
if(x)
begin
next_state<=STATE_3
z<=1'b0
end
else
begin
next_state<=STATE_2
z<=1'b0
end
end
STATE_3:begin
if(x)
begin
next_state<=STATE_0
z<=1'b1
end
else
begin
next_state<=STATE_3
z<=1'b0
end
end
default:begin
next_state<=STATE_0
z<=1'b0
end
endcase
always@(posedgeclockornegedgerst_na)
begin
if(!rst_na)
current_state<=STATE_0
else
current_state<=next_state
end
endmodule
B_3605_B
Message:Useanenumeratedtypetodefinethestatevectorofastate
machine
Description None.
Policy
Leda
Ruleset
STATE_MACHINES
Language
VHDL
Type
Blocklevel
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Severity
Warning
ForinformationonhowLedainfersfinitestatemachines,see"FiniteStateMachineRecognition".
Example
ThefollowingexampleillustrateshowtocodevalidfinitestatemachinesinVHDL:
libraryIEEE,STD
useIEEE.std_logic_1164.all
useIEEE.std_logic_components.all
useIEEE.std_logic_misc.all
entityfsmis
port(
x:instd_logic
rst:instd_logic
clock:instd_logic
z
:outstd_logic)
endfsm
architecturertloffsmis
typestateis(STATE_0,STATE_1,STATE_2,STATE_3)
signalcurrent_state,next_state:state
begin
combinationalprocesscalculatesnextstate
COMBO_PROC:process(x,current_state)
begin
case(current_state)is
whenSTATE_0=>
z<='0'
ifx='0'then
next_state<=STATE_0
else
next_state<=STATE_1
endif
whenSTATE_1=>
z<='0'
ifx='0'then
next_state<=STATE_1
else
next_state<=STATE_2
endif
whenSTATE_2=>
z<='0'
ifx='0'then
next_state<=STATE_2
else
next_state<=STATE_3
endif
whenSTATE_3=>
ifx='0'then
z<='0'
next_state<=STATE_3
else
z<='1'
next_state<=STATE_0
endif
whenothers=>
next_state<=STATE_0
endcase
endprocessCOMBO_PROC
synchronousprocessupdatescurrentstate
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SYNCH_PROC:process(rst,clock)
begin
if(rst='1')then
current_state<=STATE_0
elsif(clock'eventandclock='1')then
current_state<=next_state
endif
endprocessSYNCH_PROC
endrtl
B_3606
Message:Namingconventionforstatevariables:nameshouldendin_cs
Useadistinctivesuffixforstatevariablenames.Therecommendednameforthe
currentstateisname_cs.Youcanuseregularexpressionsormacroscanbeusedto
Description setthenamingconventions.Tospecifyanamingconvention,usetheRule
ConfigurationWizardandsupplyaregularexpressioninthevaluenodeoftherule.
Touseamacro,supplythenameofthemacrointhevaluenode.
Policy
Leda
Ruleset
STATE_MACHINES
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
ForinformationonhowLedainfersfinitestatemachines,see"FiniteStateMachineRecognition".
B_3607
Message:Thenumberofstatesinastatemachineshouldbeapowerof2
Description None.
Policy
Leda
Ruleset
STATE_MACHINES
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
ForinformationonhowLedainfersfinitestatemachines,see"FiniteStateMachineRecognition".
B_3608
Message:Thenumberofstatesinastatemachineshouldbelessthan40
Thisrulecontrolsthemaximumnumberofstatesinastatemachine.Thedefaultis
Description 40.Tochangethisparameter,usetheRuleConfigurationWizardandsupplythe
numberinthevaluenodeoftherule.
Policy
Leda
Ruleset
STATE_MACHINES
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
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ForinformationonhowLedainfersfinitestatemachines,see"FiniteStateMachineRecognition".
B_3609
Message:Instatemachine,keepFSMlogicandnonFSMlogicapart
Description Keepfinitestatemachine(FSM)logicandnonFSMlogicinseparatemodules.
Policy
Leda
Ruleset
STATE_MACHINES
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
ForinformationonhowLedainfersfinitestatemachines,see"FiniteStateMachineRecognition".
B_3610
Message:Unsynthesizablemodellingstyleforasequentialmachine,clock
andresetcannotbeinferred
Description
Ledaflagsthisrulewhenitfindsanunsynthesizablemodellingstyleofasequential
machine.Clockorresetforsuchsequentialmachinemaynotbeinferred.
Policy
Leda
Ruleset
STATE_MACHINES
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofvalidVerilogcode:
moduleB_3610_good(inputclk,reset,in1,outputregdout)
always@(posedgeclkornegedgereset)//PASS
if(!reset)
dout=0
else
dout=1
always@(posedgeclkorreset)//PASS
if(!reset)
dout=0
else
dout=1
always@(posedgeclkornegedgereset)//PASS
if(clk==1)
dout=0
else
dout=in1
endmodule
FollowingisanexampleofinvalidVerilogcode:
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moduleB_3610_good(inputclk,reset,in1,outputregdout)
always@(posedgeclkornegedgereset)//FAIL
if(!reset||clk==1)
dout=in1
else
dout=1
always@(posedgeclkornegedgereset)//FAIL
dout=in1
endmodule
B_3611
Message:Unsynthesizableimplicitstatemachine:statescanonlybe
updatedonsameclockphase
Ledaflagsthisruleforstatemachinedescriptionswherethestateisupdatedon
differentclockedges.Suchdescriptionsmaynotbesynthesizablebysomesynthesis
tools.Forexample,ifyouintendedtoimplementanimplicitstatemachine,andyou
Description
needtoswitchonmorethanoneclockedge,thenconsiderbreakingthestate
machineintomultiplestatemachines,eachofwhichcanindependentlymeetthis
requirement.
Policy
Leda
Ruleset
STATE_MACHINES
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofvalidVerilogcode:
//FAILmorethanoneedgeofaclockormorethanoneclockused
//insideanalwaysstatement
modulembadImplicitSM2(inputclk,clk1,a,c,outputout1,out2)
always
begin
@(posedgeclk)out1<=c
@(negedgeclk1)out2<=a
end
always
begin
@(posedgeclk)out1<=c
@(posedgeclk1)out2<=a
end
always
begin
@(posedgeclk)out1<=c
@(negedgeclk)out2<=a
end
always
begin
@(posedgeclk)out1<=c
@(negedgeclk)out1<=a
end
always
begin
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@(posedgeclk)out1<=c
@(negedgeclk1)out1<=a
end
always
begin
@(posedgeclk)out1<=c
@(clk1)out1<=a
end
always@(posedgeclkornegedgeclk1)
begin
out1<=c
end
always@(posedgeclkornegedgeclk)
begin
out1<=c
end
always@(posedgeclkorclk1)
begin
out1<=c
end
endmodule
B_3612
Message:Unsynthesizableimplicitstatemachine:eventcontrolexpression
maynothavemorethanoneedge
Ledaflagsthisrulewhenitfindsimplicitstatemachinedescriptionswhereevent
Description controlexpressionsusemultipleedges.Suchdescriptionsmaynotbesynthesizable
bysomesynthesistools.
Policy
Leda
Ruleset
STATE_MACHINES
Language
Verilog
Type
Blocklevel
Severity
Warning
Example
FollowingisanexampleofvalidVerilogcode:
moduleB_3612_good(inputa,in1,outputregout1,out2)
always
begin
if(a)
@(negedgea)out2<=in1
end
endmodule
FollowingisanexampleofinvalidVerilogcode:
moduleB_3612_bad(inputa,in1,outputregout1,out2)
always
begin
if(a)
@(posedgeaornegedgea)out1<=in1
//FAILmultipleedgesofa
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@(posedgeaorin1)out1<=in1
//FAILmultipleedges(aandin1)
@(a)out2<=in1
//FAILbothedgesofa
end
endmodule
HDLLayoutRuleset
ThefollowingrulesarefromtheHDLlayoutruleset:
B_4000
Message:Aprocessshouldbeprecededbyacommentdescribingits
function
Description
Ifaprocessisnotcommented(lineprecedingtheprocessstatement),thenthisrule
isviolated.Codeshouldbecommentedforreadabilityandreuse.
Policy
Leda
Ruleset
HDL_LAYOUT
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4001
Message:Processblocksshouldhavealabel
Ifaprocessdoesnothaveanylabel,thenthisruleisviolated.Labelshelpwitheasy
Description identificationofthebeginningandendofaprocess.Labelsalsohelpidentify
unwantedhardwareinferencesduringsynthesis.
Policy
Leda
Ruleset
HDL_LAYOUT
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4002
Message:Commentsarerequiredonprecedinglineoffunctionorprocedure
declaration
Description
Ifafunctiondefinitionisnotcommented(justbefore),thentheCheckerreportsa
warning.Commentshelppeopleunderstandthepurposeofthefunction.
Policy
Leda
Ruleset
HDL_LAYOUT
Language
VHDL
Type
Blocklevel
Severity
Warning
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HDLNamingRuleset
ThefollowingrulesarefromtheHDLnamingruleset:
B_4200
Message:Namingconventionsforentityname:Entitynameshouldendin
_ENT
Thisruleforcesnamingconventionsonentitynames.Regularexpressionsormacros
canbeusedtosettheconventions.Tospecifyanamingconvention,usetheRule
Description ConfigurationWizardandsupplyaregularexpressioninthevaluenodeoftherule.
Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleiscase
sensitive.Namingconventionsenhancereadability.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4201
Message:Namingconventionsforentityfilename:Filenameshouldbe
<entity>.vhd
Thisruleforcesnamingconventionsonentityfilenames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
Description
casesensitive.Itisrecommendedthatseparatedesignfilesbemaintainedfordesign
units(separateentity,architecturepairs,packagebody,packagedeclarationetc.).
Keepingthefilenamethesameasthedesignunitnamemakesiteasytolocate
designunitswithinthefilestoragesystem.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4202
Message:Namingconventionsforarchitecturename:Nameshouldendin
_ARC
Thisruleforcesnamingconventionsonarchitecturenames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
Description RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
casesensitive.Namingconventionsenhancereadability.
Policy
Leda
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Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4203
Message:Namingconventionsformodulename:Nameshouldendin_MOD
Thisruleforcesnamingconventionsonmodulenames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
Description RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Naming
conventionsenhancereadability.
Policy
Leda
Ruleset
HDL_NAMING
Language
Verilog
Type
Blocklevel
Severity
Warning
B_4204
Message:Namingconventionsforarchitecturefilename:Filenameshould
be<architecture>.vhd
Thisruleforcesnamingconventionsonarchitecturefilenames.Regularexpressions
ormacroscanbeusedtosettheconventions.Tospecifyanamingconvention,use
theRuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeof
therule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisrule
Description
iscasesensitive.Itisrecommendedthatseparatedesignfilesbemaintainedfor
designunits(separateentity,architecturepairs,packagebody,packagedeclaration,
etc.).Keepingthefilenamethesameasthedesignunitnamemakesiteasyto
locatedesignunitswithinthefilestoragesystem.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4205
Message:Namingconventionsformodulefilename:Filenameshouldbe
<module>.v
Thisruleforcesnamingconventionsonmodulefilenames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
Description RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Itsiseasier
tomanagefilesiffilenamesarekeptthesameasthemodulenames.
Policy
Leda
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Ruleset
HDL_NAMING
Language
Verilog
Type
Blocklevel
Severity
Warning
B_4206
Message:Namingconventionsforpackagename:Nameshouldendin
_PACK
Thisruleforcesnamingconventionsonpackagenames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
Description RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
casesensitive.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4207
Message:Namingconventionsforpackagedeclarationfilename:Filename
shouldbe<package>.vhd
Thisruleforcesnamingconventionsonpackagefilenames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
Description
casesensitive.Itisrecommendedthatseparatedesignfilesbemaintainedfordesign
units(separateentity,architecturepairs,packagebody,packagedeclaration,etc.).
Keepingthefilenamesthesameasthedesignunitnamesmakesiteasytolocate
designunitswithinthefilestoragesystem.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4208
Message:Namingconventionsforpackagebodyfilename:Filenameshould
be<package>_body.vhd
Thisruleforcesnamingconventionsonpackagebodyfilenames.Regularexpressions
ormacroscanbeusedtosettheconventions.Tospecifyanamingconvention,use
Description theRuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeof
therule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisrule
iscasesensitive.
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Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4209
Message:Namingconventionsforconfigurationname:Nameshouldendin
_CONF
Thisruleforcesnamingconventionsonconfigurationnames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
Description RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
casesensitive.Namingconventionsenhancereadability.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4210
Message:Namingconventionsforconfigurationdeclarationfilename:File
nameshouldbe<configuration>.vhd
Thisruleforcesnamingconventionsonconfigurationfilenames.Regularexpressions
ormacroscanbeusedtosettheconventions.Tospecifyanamingconvention,use
Description theRuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeof
therule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisrule
iscasesensitive.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4211
Message:Namingconventionsforsignalname:NameshouldbeginwithS
Thisruleforcesnamingconventionsonsignalnames.Regularexpressionsormacros
canbeusedtosettheconventions.Tospecifyanamingconvention,usetheRule
ConfigurationWizardandsupplyaregularexpressioninthevaluenodeoftherule.
Description
Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleiscase
sensitive(checkisperformedatdeclarationonly).Rationale:preventconfusionand
enhancereadability.
Policy
Leda
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Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4212
Message:Namingconventionsforvariablename:NameshouldbeginwithV
Thisruleforcesnamingconventionsonvariablenames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
Description
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
casesensitive(checkisperformedatdeclarationonly).Namingconventionsenhance
readability.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4213
Message:Namingconventionsforconstantname:Nameshouldbeginwith
C
Thisruleforcesnamingconventionsonconstantnames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
Description
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
casesensitive(checkisperformedatdeclarationonly).Namingconventionsenhance
readability.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4214
Message:Namingconventionsforcomponentname:Nameshouldbegin
withCOMP
Thisruleforcesnamingconventionsoncomponentnames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
Description
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
casesensitive(checkisperformedatdeclarationonly).Namingconventionsenhance
readability.
Policy
Leda
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Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4215
Message:Namingconventionsfortypename:NameshouldbeginwithT
Thisruleforcesnamingconventionsontypenames.Regularexpressionsormacros
canbeusedtosettheconventions.Tospecifyanamingconvention,usetheRule
ConfigurationWizardandsupplyaregularexpressioninthevaluenodeoftherule.
Description
Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleiscase
sensitive(checkisperformedatdeclarationonly).Namingconventionsenhance
readability.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4216
Message:Namingconventionsforsubtypename:Nameshouldbeginwith
ST
Thisruleforcesnamingconventionsonsubtypenames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
Description
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
casesensitive(checkisperformedatdeclarationonly).Namingconventionsenhance
readability.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4217
Message:Namingconventionsforfunctionname:NameshouldbeginwithF
Thisruleforcesnamingconventionsonfunctionnames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
Description
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
casesensitive(checkisperformedatdeclarationonly).Namingconventionsenhance
readability.
Policy
Leda
Ruleset
HDL_NAMING
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Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_4218
Message:Namingconventionsforprocedurename:Nameshouldbeginwith
P
Thisruleforcesnamingconventionsonprocedurenames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
Description
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
casesensitive(checkisperformedatdeclarationonly).Namingconventionsenhance
readability.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4219
Message:Namingconventionsforcomponentinstantiationlabel:Name
shouldbeginwithU_
Thisruleforcesnamingconventionsoncomponentinstantiationlabels.Regular
expressionsormacroscanbeusedtosettheconventions.Tospecifyanaming
convention,usetheRuleConfigurationWizardandsupplyaregularexpressioninthe
Description
valuenodeoftherule.Touseamacro,supplythenameofthemacrointhevalue
node.Thisruleiscasesensitive(checkisperformedatinstantiationonly).Naming
conventionsenhancereadability.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4220
Message:Namingconventionsforblockstatementlabel:Nameshouldend
in_BLOCK
Thisruleforcesnamingconventionsonblocklabels,ifdefined.Regularexpressions
ormacroscanbeusedtosettheconventions.Tospecifyanamingconvention,use
theRuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeof
Description
therule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisrule
iscasesensitive(checkisperformedatdefinitiononly).Thisnamingconvention
makesiteasytoidentifyblockstatementsandenhancesreadability.
Policy
Leda
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Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4221
Message:Namingconventionsforgeneratestatementlabel:Nameshould
endin_GEN
Thisruleforcesnamingconventionsongeneratestatementlabels.Regular
expressionsormacroscanbeusedtosettheconventions.Tospecifyanaming
convention,usetheRuleConfigurationWizardandsupplyaregularexpressioninthe
Description
valuenodeoftherule.Tousemacro,supplythenameofthemacrointhevalue
node.Thisruleiscasesensitive(checkisperformedatdefinitiononly).Naming
conventionsenhancereadabilityandmakethecodeeasiertodebug.
Policy
Leda
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4222
Message:Namingconventionsforalwayslabel:Nameshouldendin_ALW
Thisruleforcesnamingconventionsonalwayslabels,ifdefined.Regularexpressions
ormacroscanbeusedtosettheconventions.Tospecifyanamingconvention,use
theRuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeof
Description
therule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisrule
iscasesensitive(checkisperformedatdefinitiononly).Labelsonalwaysblocks
makeiteasytospotunwantedhardwareinferencingduringsynthesis.
Policy
Leda
Ruleset
HDL_NAMING
Language
Verilog
Type
Blocklevel
Severity
Warning
B_4223
Message:Namingconventionsforprocessstatementlabel:Nameshould
endin_PROC
Thisruleforcesnamingconventionsonprocessstatementlabels,ifdefined.Regular
expressionsormacroscanbeusedtosettheconventions.Tospecifyanaming
convention,usetheRuleConfigurationWizardandsupplyaregularexpressioninthe
Description
valuenodeoftherule.Touseamacro,supplythenameofthemacrointhevalue
node.Thisruleiscasesensitive(checkisperformedatdefinitiononly).Process
labelsmakeiteasytoidentifyunwantedhardwareinferencingduringsynthesis.
Policy
Leda
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1LedaGeneralCodingRules
Ruleset
HDL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4224
Message:Namingconventionsforprimitivename:Nameshouldbeginwith
P_
Thisruleforcesnamingconventionsonprimitivenames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
Description RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Naming
conventionshelpmaintaincodeconsistencyandenhancereadability.
Policy
Leda
Ruleset
HDL_NAMING
Language
Verilog
Type
Blocklevel
Severity
Warning
B_4225
Message:Namingconventionsforregistername:Nameshouldendin_r
Thisruleforcesnamingconventionsonregisternames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
Description RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Naming
conventionshelpmaintaincodeconsistencyandenhancereadability.
Policy
Leda
Ruleset
HDL_NAMING
Language
Verilog
Type
Blocklevel
Severity
Warning
B_4226
Message:Namingconventionsfornetname:Nameshouldbeginwithw
Thisruleforcesnamingconventionsonnetnames.Regularexpressionsormacros
canbeusedtosettheconventions.Tospecifyanamingconvention,usetheRule
Description ConfigurationWizardandsupplyaregularexpressioninthevaluenodeoftherule.
Touseamacro,supplythenameofthemacrointhevaluenode.Naming
conventionsenhancereadability.
Policy
Leda
Ruleset
HDL_NAMING
Language
Verilog
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Type
Blocklevel
Severity
Warning
B_4227
Message:Namingconventionsforinputportname:Nameshouldendin_in
Thisruleforcesnamingconventionsoninputportnames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
Description RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Naming
conventionsenhancereadability.
Policy
Leda
Ruleset
HDL_NAMING
Language
Verilog
Type
Blocklevel
Severity
Warning
B_4228
Message:Namingconventionsforoutputportname:Nameshouldendin
_out
Thisruleforcesnamingconventionsonoutputportnames.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
Description RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Naming
conventionsenhancereadability.
Policy
Leda
Ruleset
HDL_NAMING
Language
Verilog
Type
Blocklevel
Severity
Warning
B_4229
Message:Namingconventionsforinoutportname:Nameshouldendin
_inout
Thisruleforcesnamingconventionsonbidirectionalportnames.Regularexpressions
ormacroscanbeusedtosettheconventions.Tospecifyanamingconvention,use
Description theRuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeof
therule.Touseamacro,supplythenameofthemacrointhevaluenode.Naming
conventionsenhancereadability.
Policy
Leda
Ruleset
HDL_NAMING
Language
Verilog
Type
Blocklevel
Severity
Warning
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1LedaGeneralCodingRules
B_4230
Message:Namingconventionsfortaskname:NameshouldbeginwithT_
Thisruleforcesnamingconventionsontasknames.Regularexpressionsormacros
canbeusedtosettheconventions.Tospecifyanamingconvention,usetheRule
Description ConfigurationWizardandsupplyaregularexpressioninthevaluenodeoftherule.
Touseamacro,supplythenameofthemacrointhevaluenode.Naming
conventionsenhancereadability.
Policy
Leda
Ruleset
HDL_NAMING
Language
Verilog
Type
Blocklevel
Severity
Warning
B_4231
Message:Namingconventionsforinitiallabel:Nameshouldendin_INIT
Thisruleforcesnamingconventionsoninitiallabels,ifdefined.Regularexpressions
ormacroscanbeusedtosettheconventions.Tospecifyanamingconvention,use
theRuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeof
Description
therule.Touseamacro,supplythenameofthemacrointhevaluenode.Naming
conventionsenhancereadabilityandmakeiteasytoidentifynonsynthesizable
blocksofcode.
Policy
Leda
Ruleset
HDL_NAMING
Language
Verilog
Type
Blocklevel
Severity
Warning
RTLNamingRuleset
ThefollowingrulesarefromtheRTLnamingruleset:
B_4400
Message:Namingconventionsforlatchinput:Nameshouldendin_d
Thisruleforcesnamingconventionsonlatchinputs.Regularexpressionsormacros
canbeusedtosettheconventions.Tospecifyanamingconvention,usetheRule
ConfigurationWizardandsupplyaregularexpressioninthevaluenodeoftherule.
Description
Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleiscase
sensitive.Namingconventionsenhancereadabilityandmakeiteasytoidentifylatch
signalsinRTL.
Policy
Leda
Ruleset
RTL_NAMING
Language
VHDL
Type
Blocklevel
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Severity
Warning
B_4401
Message:Namingconventionsforlatch:Nameshouldend
in_q
Thisruleforcesnamingconventionsonlatchoutputs.Regularexpressionsormacros
canbeusedtosettheconventions.Tospecifyanamingconvention,usetheRule
ConfigurationWizardandsupplyaregularexpressioninthevaluenodeoftherule.
Description
Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleiscase
sensitive.Namingconventionsenhancereadabilityandmakeiteasytoidentifylatch
signalsinRTL.
Policy
Leda
Ruleset
RTL_NAMING
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_4402
Message:Namingconventionsforregisterinput:Nameshouldendin_d
Thisruleforcesnamingconventionsonflipflopinputs.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
Description
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
casesensitive.Namingconventionsenhancereadabilityandmakeiteasytoidentify
flipflopsinRTL.
Policy
Leda
Ruleset
RTL_NAMING
Language
VHDL
Type
Blocklevel
Severity
Warning
B_4403
Message:Namingconventionsforflipflopoutput:Nameshouldendin_r
Thisruleforcesnamingconventionsonflipflopoutputs.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
Description
rule.Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleis
casesensitive.Namingconventionsenhancereadabilityandmakeiteasytoidentify
flipflopsinRTL.
Policy
Leda
Ruleset
RTL_NAMING
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
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1LedaGeneralCodingRules
B_4404
Message:Namingconventionsforclock:Nameshouldbeginwithclk
Thisruleforcesnamingconventionsonclocksignals.Regularexpressionsormacros
canbeusedtosettheconventions.Tospecifyanamingconvention,usetheRule
ConfigurationWizardandsupplyaregularexpressioninthevaluenodeoftherule.
Description
Touseamacro,supplythenameofthemacrointhevaluenode.Thisruleiscase
sensitive.Namingconventionsenhancereadabilityandmakeiteasytoidentify
clocksandapplyconstraintsduringsynthesis.
Policy
Leda
Ruleset
RTL_NAMING
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_4405
Message:Namingconventionsforasynchronousresetname:Nameshould
beginwithrst
Thisruleforcesnamingconventionsonasynchronousresetsignals.Regular
expressionsormacroscanbeusedtosettheconventions.Tospecifyanaming
convention,usetheRuleConfigurationWizardandsupplyaregularexpressioninthe
Description
valuenodeoftherule.Touseamacro,supplythenameofthemacrointhevalue
node.Thisruleiscasesensitive.Namingconventionsenhancereadabilityandmake
iteasytoidentifyresetsandapplyconstraintsduringsynthesis.
Policy
Leda
Ruleset
RTL_NAMING
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
B_4406
Message:Namingconventionsforsynchronousresetname:Nameshould
beginwithrst
Thisruleforcesnamingconventionsonsynchronousresetsignals.Regular
expressionsormacroscanbeusedtosettheconventions.Tospecifyanaming
convention,usetheRuleConfigurationWizardandsupplyaregularexpressioninthe
Description
valuenodeoftherule.Touseamacro,supplythenameofthemacrointhevalue
node.Thisruleiscasesensitive.Namingconventionsenhancereadabilityandmake
iteasytoidentifyresetsandapplyconstraintsduringsynthesis.
Policy
Leda
Ruleset
RTL_NAMING
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
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B_4407
Message:Namingconventionsfortristatename:Nameshouldendin_z
Thisruleforcesnamingconventionsontristatesignals.Regularexpressionsor
macroscanbeusedtosettheconventions.Tospecifyanamingconvention,usethe
RuleConfigurationWizardandsupplyaregularexpressioninthevaluenodeofthe
Description
rule.Tousemacro,supplythenameofthemacrointhevaluenode.Thisruleis
casesensitive(checkisperformedatdeclaration.).Namingconventionsenhance
readability.
Policy
Leda
Ruleset
RTL_NAMING
Language
VHDL/Verilog
Type
Blocklevel
Severity
Warning
SystemVerilogRuleset
ThefollowingrulesarefromtheSystemVerilogruleset:
B_5000
Message:Nononblockingassignmentsinalways_comb
Description None.
Policy
Leda
Ruleset
SYSTEMVERILOG
Language
Verilog
Type
Blocklevel
Severity
Error
B_5001
Message:Nononblockingassignmentsinalways_latch
Description None.
Policy
Leda
Ruleset
SYSTEMVERILOG
Language
Verilog
Type
Blocklevel
Severity
Error
B_5005
Message:Nolatchesorflipflopsinalways_comb
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1LedaGeneralCodingRules
Description Thealways_combconstructisdesignedtomodelthebehaviorofcombinationallogic.
So,inferringaflipfloporlatchusingalways_combispoorcodingstyle.
Policy
Leda
Ruleset
SYSTEMVERILOG
Language
Verilog
Type
Blocklevel
Severity
Error
B_5006
Message:Noflipflopsinalways_latch
Description
Thealways_latchconstructisdesignedforlatchinferenceonly.Forflipflopsuse
always_ff.
Policy
Leda
Ruleset
SYSTEMVERILOG
Language
Verilog
Type
Blocklevel
Severity
Error
B_5007
Message:Noeventcontrolsordelaysinalways_comb
Description
Thealways_combconstructisdesignistomodelthebehaviorofcombinationallogic.
Usingeventcontrolsmayresultinsequentiallogic(latch,flipflop).
Policy
Leda
Ruleset
SYSTEMVERILOG
Language
Verilog
Type
Blocklevel
Severity
Error
B_5008
Message:Noeventcontrolsordelaysinalways_latch
Description None.
Policy
Leda
Ruleset
SYSTEMVERILOG
Language
Verilog
Type
Blocklevel
Severity
Error
B_5009
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1LedaGeneralCodingRules
Message:Onlyoneeventcontrolinalways_ff
Description Toinferaflipflop,oneeventisrequired.
Policy
Leda
Ruleset
SYSTEMVERILOG
Language
Verilog
Type
Blocklevel
Severity
Error
B_5010
Message:Theremustbeatleastonelatchinalways_latch
Description
Thisruledetectsusageofanalways_latchblockwhichcontainscodethatwillnot
resultinevenonelatch.
Policy
Leda
Ruleset
SYSTEMVERILOG
Language
Verilog
Type
Blocklevel
Severity
Error
B_5011
Message:Theremustbeatleastoneffinalways_ff
Description None.
Policy
Leda
Ruleset
SYSTEMVERILOG
Language
Verilog
Type
Blocklevel
Severity
Error
B_5028
Message:Inputmodeadefaultmodefortask/functionargumentdirection
Description
ForSystemVerilogfunctionsandtasks,iftheargumentdirectioniscodedexplicitly,it
willbeassignedinputmodebydefault.Thisruledetectssuchscenarios.
Policy
Leda
Ruleset
SYSTEMVERILOG
Language
Verilog
Type
Blocklevel
Severity
Error
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1LedaGeneralCodingRules
B_5035
Message:SystemVerilogreservedusedasidentifier
ThisruleflagsifanySystemVerilogreservedwordsareusedasidentifiers.The
reservedwordsare:"^always_comb$","^always_ff$","^always_latch$",
"^wait_order$","^alias$","^assert_strobe$","^assert$","^before$","^bind$",
"^bit$","^break$","^byte$","^chandle$","^clocking$","^class$","^constraint$",
"^context$","^continue$","^cover$","^dist$","^do$","^endclocking$",
"^endclass$","^endinterface$","^endprogram$","^endproperty$","^enum$",
"^endsequence$","^export$","^extends$","^extern$","^first_match$","^final$",
Description
"^forkjoin$","^iff$","^import$","^int$","^inside$","^interface$","^intersect$",
"^join_any$","^join_none$","^local$","^logic$","^longint$","^modport$",
"^new$","^null$","^packed$","^priority$","^program$","^property$",
"^protected$","^pure$","^rand$","^randc$","^ref$","^sequence$","^shortint$",
"^shortreal$","^solve$","^static$","^string$","^struct$","^super$","^this$",
"^timeunit$","^timeprecision$","^type$","^throughout$","^typedef$","^union$",
"^unique$","^var$","^virtual$","^void$","^with$","^within$"
Policy
Leda
Ruleset
SYSTEMVERILOG
Language
Verilog
Type
Blocklevel
Severity
Warning
B_5036
Message:V2Kreservedusedasidentifier
ThisruleflagsifanyV2Kreservedwordsareusedasidentifiers.Thereservedwords
are:"^pulsestyle_ondetect$","^pulsestyle_onevent$","^automatic$","^cell$",
Description "^config$","^design$","^endconfig$","^endgenerate$",^genvar$","^generate$",
"^instance$","^liblist$","^localparam$","^noshowcancelled$","^showcancelled$",
"^use$"
Policy
Leda
Ruleset
SYSTEMVERILOG
Language
Verilog
Type
Blocklevel
Severity
Warning
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