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Lab Assignment Lab Assignment 1

The document outlines two lab assignments for a student named Naresh Kumar with roll number 2014-CE-180. The first assignment asks the student to design a half adder through a schematic and Verilog module, and verify the results with a given truth table. The second assignment repeats this, designing a full adder instead of a half adder. Both assignments include the relevant theory on half adders and full adders, truth tables, and require the student to provide schematic diagrams, Verilog code, and test waveforms.

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Naresh Langhani
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37 views

Lab Assignment Lab Assignment 1

The document outlines two lab assignments for a student named Naresh Kumar with roll number 2014-CE-180. The first assignment asks the student to design a half adder through a schematic and Verilog module, and verify the results with a given truth table. The second assignment repeats this, designing a full adder instead of a half adder. Both assignments include the relevant theory on half adders and full adders, truth tables, and require the student to provide schematic diagrams, Verilog code, and test waveforms.

Uploaded by

Naresh Langhani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Name: Naresh Kumar

Roll no: 2014-CE-180

LAB ASSIGNMENT
Lab Assignment 1:
Design a Half Adder through schematic and verilog module. Also verify the results from truth table
given below.

THEORY
HALF ADDER
In electronics, an adder is a digital circuit that performs addition of numbers. In many computers and other
kind of processors, adders are used not only in the arithmetic logic units, but also in other parts of the
processor where they are used to calculate addresses, table indices and etc.

sum

Carry

Truth Table

Schematic Diagram:

Circuit Diagram

Name: Naresh Kumar

Verilog Module Code:

Verilog Test Fixture

Waveform:

Roll no: 2014-CE-180

Name: Naresh Kumar

Roll no: 2014-CE-180

Lab Assignment 2:
Design a Full Adder through schematic and verilog module. Also verify the results from truth table
given below.

THEORY
FULL ADDER
A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds
three one-bit numbers, often written as A, B and Cin. A and B are the operands and Cin is a bit carried in.
The circuit produces a two bit output, S and Cout. The final sum is 2XCout+S.

Cin

sum

Carry

Verilog Module Code:

Truth Table
Circuit Diagram

Schematic Diagram:

Name: Naresh Kumar

Verilog Test Fixture

Roll no: 2014-CE-180

Name: Naresh Kumar

Waveform:

Roll no: 2014-CE-180

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