ADuCM350-Amperometric, Voltametric, and Impedometric

16-Bit Precision, Low Power Meter On A
Chip with Cortex-M3 and Connectivity

Data Sheet ADuCM350
FEATURES Integrated full-speed USB 2.0 controller and PHY
Analog performance Multilayer advanced microcontroller bus architecture
160 kSPS, 16-bit, precision analog-to-digital converter (ADC) (AMBA) bus matrix
4 dedicated voltage measurement channels Central direct memory access (DMA) controller
8 current measurement channels Real-time clock (RTC)
Impedance measurement engine General-purpose, wake-up, and watchdog timers
High precision voltage reference Communication
Supply noise rejection filtering Input/output
Ultralow leakage configurable switch matrix I2S and beeper interface
12-bit digital-to-analog converter (DAC) LCD display controller (parallel and serial)
Precision instrumentation amplifier control loop LCD segment controller
6-channel CapTouch controller SPI, I2C, and UART peripheral interfaces
Temperature sensor Programmable GPIOs
Analog hardware accelerators Power
Autonomous analog front-end (AFE) controller Coin cell battery compatible
Independent sequencer for AFE functions 2.5 V to 3.6 V active measurement range
Direct digital synthesizer (DDS)/arbitrary waveform Power management unit (PMU)
generator Power-on reset (POR) and power supply monitor (PSM)
Receive filters Packages and temperature range
Complex impedance measurement (DFT) engine Operating temperature range: −40°C to +85°C
Processing Package: 120-lead, 8 mm × 8 mm CSP_BGA
16 MHz ARM Cortex-M3 processor APPLICATIONS
384 kB of embedded flash memory
Point-of-care diagnostics
32 kB system SRAM
Body-worn devices for monitoring vital signs
16 kB Flash configured EEPROM
Amperometric, voltametric, and impedometric measurements
FUNCTIONAL BLOCK DIAGRAM

PLL SW/JTAG
LF XTAL 1 × 256kB
1 × 128kB
ARM
HF XTAL CORTEX-M3 FLASH
HF OSC
16kB
NVIC TRACE EEPROM
LF OSC
DMA SRAM0
AFE SIGNAL (16kB)
● 16-BIT PRECISION ADC GENERATION AMBA
● PRECISION REFERENCE AFE BUS
● SWITCH MATRIX CONTROLLER MATRIX
DFT SRAM1 POR
● 12-BIT DAC (16kB)
● IN-AMP CONTROL LOOP
● TIA USB PHY USB PSM
RECEIVE
FILTERS PDI
LP LDO
CapTouch
SPIH HP LDO
UART SPI0 SPI1 I 2C TMR0 TMR1 PMU BEEP
ABP‐0 AHB ‐APB ABP‐1

BRIDGE
12073-001
I2S LCD GPIO CRC TMR2 WDT RTC MISC
Figure 1.
Rev. A Document Feedback

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ADuCM350 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 25
Applications ....................................................................................... 1 Analog Front End ........................................................................... 30
Functional Block Diagram .............................................................. 1 Excitation Stage .......................................................................... 30
Revision History ............................................................................... 2 Measurement Stage .................................................................... 32
General Description ......................................................................... 3 AFE Control ................................................................................ 33
Specifications..................................................................................... 4 CapTouch Features ..................................................................... 33
Analog Front-End Specifications ............................................... 4 MicroSubSystem ............................................................................. 34
Switch Matrix Specifications ....................................................... 5 Memories ..................................................................................... 34
Transimpedance Amplifier Specifications ................................ 6 Debug Capability ........................................................................ 34
ADC Specifications ...................................................................... 6 Programmable GPIOs ............................................................... 34
Temperature Sensor Specifications ............................................ 6 Timers .......................................................................................... 34
CapTouch....................................................................................... 6 USB ............................................................................................... 34
DFT-Based Impedance Measurements ..................................... 7 Power Management and Clocking ........................................... 35
Digital Platform ............................................................................ 7 Display Options .......................................................................... 35
System Clocks/Timers ............................................................... 10 Audio Options ............................................................................ 36
Power Management Specifications .......................................... 12 Development Support .................................................................... 37
Trickle Charger ........................................................................... 12 Documentation........................................................................... 37
Timing Characteristics .............................................................. 13 Hardware ..................................................................................... 37
Absolute Maximum Ratings.......................................................... 19 Software ....................................................................................... 37
Thermal Resistance .................................................................... 19 Packaging and Ordering Information ......................................... 38
ESD Caution ................................................................................ 19 Outline Dimensions ................................................................... 38
Pin Configuration and Function Descriptions ........................... 20 Ordering Guide .......................................................................... 38
REVISION HISTORY
5/14—Revision A: Initial Version
Rev. A | Page 2 of 40
Data Sheet ADuCM350
GENERAL DESCRIPTION
The ADuCM350 is a complete, coin cell powered, high support portable meters with display, USB communication, and
precision, meter-on-chip for portable device applications for active sensors. The ADuCM350 is available in a 120-lead, 8 mm
applications such as point-of-care diagnostics and body-worn × 8 mm CSP_BGA and operates from −40°C to +85°C.
devices for monitoring vital signs. The ADuCM350 is designed To support extremely low dynamic and hibernate power
for high precision amperometric, voltametric, and impedometric management, the ADuCM350 provides a collection of power
measurement capabilities. modes and features, such as dynamic and software controlled
The ADuCM350 analog front end (AFE) features a 16-bit, clock gating and power gating.
precision, 160 kSPS analog-to-digital converter (ADC); 0.17% The AFE is connected to the ARM Cortex-M3 via an advanced
precision voltage reference; 12-bit, no missing codes digital-to- high performance bus (AHB) slave interface on the advanced
analog converter (DAC); and a reconfigurable ultralow leakage microcontroller bus architecture (AMBA) matrix, as well as
switch matrix. The ADuCM350 also includes an ARM® Cortex- direct memory access (DMA) and interrupt connections.
M3-based processor, memory, and all I/O connectivity to
ADuCM350 Data Sheet
SPECIFICATIONS
All characterization is at VCCM = 2.5 V to 3.6 V, specifications below 2.5 V are for functionality only, all minimum and maximum
specifications are specified for a temperature range of −40°C to +85°C, unless otherwise noted.
ANALOG FRONT-END SPECIFICATIONS
AFE LDO Specifications
Table 1. AFE LDO Specifications
Parameter Min Typ Max Unit Test Conditions/Comments
VOLTAGE
Output Voltage 1.71 1.8 1.89 V Measured with a load capacitance (CLOAD) = 0.47 µF; measured with 1 mA
load current on AVDD_RX/TX; all AFE blocks powered down
Dropout 150 200 mV 10 mA load applied; no AFE blocks enabled
REGULATION
Line 1080 µV/V 10 mA load applied
Load 0.65 mV/mA 10 mA load applied
POWER UP
Power-Up Time 500 µs Measured with a CLOAD = 0.47 µF; current limit enabled
High Precision Internal Reference Specifications

Table 2. High Precision Internal Reference Specifications
ADC VREF
Reference Voltage Initial Accuracy1 1.797 1.8 1.803 V For a temperature range of 0°C to 50°C
1.79 1.8 1.803 V For a temperature range of −40°C to +85°C
Output Impedance 570 mΩ LDO and reference enabled; all other AFE
blocks disabled; reference loaded with
50 µA on VREF
Temperature Coefficient2 −52 +90 ppm/°C For a temperature range of −40°C to
+85°C, maximum value from −40°C to
+25°C, and from +25°C to +85°C specified
−45 +48 ppm/°C For a temperature range of 0°C to 50°C,
maximum value from −40°C to +25°C, and
from 25°C to 85°C specified
VREF Thermal Hysteresis 50 ppm
REF_EXCITE Switching Load 1.789 1.793 1.797 V ILOAD = 200 µA; internal ADC measurement
Line Regulation 50 µV/V VCCM1 = 2.5 V, VCCM2 = 3.6 V; reference
loaded with 300 µA
Short-Circuit Current to Ground 10 mA Current limit off
DAC VREF
Reference Voltage 1.77 1.8 1.83 V
VBIAS
VBIAS Voltage 1.095 1.1 1.102 V Measured with a CLOAD = 0.47 µF; no
current load
1
Reference voltage is trimmed unloaded. Measured with CLOAD = 4.7 µF. Measured at 25°C.
2
Guaranteed by design and/or characterization.
Data Sheet ADuCM350
DAC/RCF/PGA Specifications
Table 3. DAC/PGA/RCF Specifications
Parameter1 Min Typ Max Unit Test Conditions/Comments
DAC
Output Range −600 +600 mV As seen by sensor
Resolution 12 Bits
Integral Nonlinearity (INL) ±0.85 LSB Measured at an output of the excitation
loop, using gain = 1 and default DAC clock
(16 MHz ÷ 49 DAC clock speed)
Differential Nonlinearity (DNL) −1 +1 LSB Measured at an output of the excitation
loop, using gain = 1 and default DAC clock
(16 MHz ÷ 49 DAC clock speed)
Full-Scale Error
Positive ±0.2 % FSR PGA (gain = 1), measured at an output of
the excitation loop, DAC code = 0xE00
±1 % FSR PGA (gain = 0.025), measured at an output
of the excitation loop, DAC code = 0xE00
Negative ±0.2 % FSR PGA (gain = 1), measured at an output of
the excitation loop, DAC code = 0x200
±1 % FSR PGA (gain = 0.025), measured at an output
of the excitation loop, DAC code = 0x200
Offset Error, Midscale ±1 mV PGA (gain = 1 or gain = 0.025), measured
at an output of the excitation loop across
RCAL
Clocking Frequency 280.7 320 380.95 kHz
PROGRAMMABLE GAIN AMPLIFIER (PGA)
Gain from PGA in State 0 1 Covered by DAC full-scale error measured
on an output of the excitation loop
Gain from PGA in State 1 0.025 Covered by DAC full-scale error measured
on an output of the excitation loop
RECONSTRUCTION FILTER (RCF)
3 dB Corner Frequency 50 kHz
1
There may be some system offsets and gain errors that can be calibrated at the system level to improve dc accuracy. Hence, the voltage swing at the output
of the DAC is ±800 mV to guarantee ±600 mV swing on the sensor.
SWITCH MATRIX SPECIFICATIONS

Table 4. Switch Matrix Specifications
RON1
Current Carrying Switches
Dx, DR1, Tx, and TR2 40 50 Ω
IVS 40 75 Ω
Noncurrent Carrying Switches
Px, Nx, and NR2 600 900 Ω
PR1 600 950 Ω
NL 260 350 Ω
PL 210 260 Ω
DC OFF LEAKAGE2
T and N Switches 370 pA Sum value of four T switches and four N
switches
P Switches 340 pA Sum value of four P switches
D Switches 350 pA Sum value of four D switches
ADuCM350 Data Sheet
DC ON LEAKAGE2
T, N, and P Switches 530 pA Sum value for 25 switches, including NL
D Switches 340 pA Sum value for eight switches
1
RON characterized with a voltage sweep from 0 V to VCCM. Production tested at 1.8 V.
2
See Figure 38 as a reference. The AFE x pin is driven to 0.2 V.
TRANSIMPEDANCE AMPLIFIER SPECIFICATIONS

Table 5. Transimpedance Amplifier Specifications
TRANSIMPEDANCE AMPLIFIER
Maximum Current Sink/Source ±5 mA Ensure an RTIA selection to generate ±750 mV swing for optimal
linearity performance
Short-Circuit Protection Functionality 10 mA
ADC SPECIFICATIONS
Table 6. ADC Specifications1
ADC
Input Range 0.35 1.85 V Internal reference
No Missing Codes 16 Bits
DNL ±0.9 LSB
INL ±0.7 LSB @ 160 kSPS with respect to an optimal
voltage range of ±750 mV, from 0°C to
50°C
±1 LSB @ 160 kSPS with respect to an optimal
voltage range of ±750 mV, from −40°C to
+85°C
Sample Rate After Decimation 160 kSPS
3 dB Bandwidth 54 kHz
1
RTIA = 7.5 kΩ, CTIA = 220 pF; ±100 μA current measurement.
TEMPERATURE SENSOR SPECIFICATIONS

Table 7. Temperature Sensor Specifications
TEMPERATURE SENSOR
Accuracy ±1 °C 0°C to 50°C, trimmed at 25°C
±2 °C −40°C to +85°C, trimmed at +25°C
CapTouch
Table 8. CapTouch Specifications
CapTouch™ CHARACTERISTICS
Core Resolution 14 Bits
Core SNR 60 dB 1 kHz test tone, input range of ADC = 1.8 V
CAPT_x ±10 nA GPIO leakage test
Update Rate 7.5 1E6 µs Programmable, dependent on configuration
Update Rate per Sensor 7.5 µs No filtering enabled, clock = 16 MHz
CAPT_x Input Range ±8 pF ∆CIN is register programmable from 0.5 pF to
9.3 pF
CAPT_x Offset (CapDAC) Range 75 pF
Data Sheet ADuCM350
CapDAC Resolution 0.1 pF
Output Noise
Peak-to-Peak 8 Codes
RMS 1.3 Codes
DFT-BASED IMPEDANCE MEASUREMENTS

Table 9. DFT-Based Impedance Measurements1
IMPEDANCE
Accuracy2
Magnitude 0.33 % Standard deviation as a percent of Z
Phase 0.17 Degrees Standard deviation of Z
Precision3
Magnitude 0.17 % Standard deviation as a percent of Z
Phase 0.08 Degrees Standard deviation of Z
1
For a Z of 181 Ω (0.02% tolerant resistor). Excitation frequency = 20 kHz, sine amplitude = 9 mVRMS, RCAL = 1 kΩ, RTIA = 7.5 kΩ, CTIA = 220 pF. Measurements at 25°C. Single
DFT measurement.
2
Device-to-device repeatability for 1000 devices.
3
Single device, repeatable measurements.
DIGITAL PLATFORM
Digital LDO
Table 10. Digital LDO Specifications
OUTPUT VOLTAGE 1.71 1.8 1.89 V Measured with a CLOAD = 0.47 µF,
measured with a 10 mA load current on
DVDD
DROPOUT 150 200 mV 10 mA load applied, no AFE blocks
enabled
REGULATION
Line 1.4 mV/V 10 mA load current on DVDD
Load 0.41 mV/mA 0 mA to 10 mA load current
POWER-UP TIME 42 µs Time taken from LDO enable to when LDO
voltage is within specification, CLOAD =
0.47 µF, regulator unloaded
Low Power LDO

Table 11. Low Power LDO Specifications
OUTPUT VOLTAGE 1.71 1.8 1.89 V
REGULATION
Line 0.45 mV/V VCCM = 2.0 V to 3.6 V
Load 28.5 mV/mA 0 µA to 100 µA load
ADuCM350 Data Sheet
Flash/General-Purpose Flash
Table 12. Flash/General-Purpose Flash Specifications
FLASH/GP FLASH
Endurance1 20,000 Cycles
Erase Time 20 ms @ 1.8 V
Program Time 20 µs @ 1.8 V
Data Retention2 100 Years Below room temperature
1
Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
2
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
Digital Inputs/Outputs: Specified

Specified pin supply range from 2.5 V to 3.6 V.
Table 13. Digital Inputs and Outputs1 Specifications

PIN SUPPLY 2.5 3 3.6 V
Impedance
Pull-Down 20 kΩ ISINK < 10 µA
Pull-Up 15 kΩ ISOURCE < 10 µA
Internal Pull-Up/Pull-Down Enabled Leakage2 200 µA
Digital I/O Leakage Current .01 1 µA
Input Capacitance 10 pF
Input Voltage
Low (VINL) 0.3 × pin supply V
High (VINH) 0.7 × pin supply V
Output Voltage
Low (VOL) 0.4 V ISINK = 1.0 mA
VOL High Drive 0.4 V ISINK = 1.6 mA
High (VOH) 3 Pin supply − 0.4 V ISOURCE = 1.0 mA
VOH High Drive 2.4 V ISOURCE = 1.6 mA
1
Includes GPIO, debug, SPI, I2C, PDI, LCD, I2S, and beeper.
2
See Table 35 for details regarding bumps/pins that have pull-up resistors.
I C does not drive out a high voltage; it uses external pull-up resistors.
3 2
Digital Inputs/Outputs: Functional

Functional pin supply range from 1.65 V to 2.5 V.
Table 14. Digital Inputs/Outputs: Functional Specifications

PIN SUPPLY 1.65 2.5 V
Input Voltage
Low (VINL) 0.3 × pin supply V
High (VINH) 0.7 × pin supply V
Output Voltage
Low (VOL) 0.45 V ISINK = 1.0 mA
High (VOH) 1
Pin supply − 0.5 V ISOURCE = 1.0 mA
1 2
I C does not drive out a high voltage; it uses external pull-up resistors.
Data Sheet ADuCM350
Universal Serial Bus Regulator Specifications
Table 15. Universal Serial Bus Regulator Specifications
SERIAL BUS REGULATOR
Input Voltage Range 3.6 5.25 V
Regulated Output Voltage 3.2 3.4 V
Dropout 440 mV 40 mA continuous current
Regulation
Line 0.0043 %/V 4.5 V to 5.5 V
Load 0.0093 %/mA @ 5 V, 220 nF ceramic decoupling capacitor
Power-Up Time 37 µs
Universal Serial Bus DC Specifications

Table 16. Universal Serial Bus DC Specifications
RECEIVER
Single-Ended Input Voltage (Driven)
High 2.0 V
Low 0.8 V
Differential Receiver Input
Common Mode 0.8 2.5 V
Sensitivity 0.2 V V(USB DP) − V(USB DM)
TRANSMITTER
Output Voltage
Low (VOL) 0 0.3 V Pull-up resistor asserted on the USB pin,
USB DP, RPU to AVDD
High (VOH) 2.8 3.6 V Pull-down resistor asserted on USB DP and
USB DM (15 kΩ to GND)
Driver Output Impedance 28 44 Ω RDRIVER + RSERIES
Term Series Resistor 40 Ω
Pull-Up Resistor (D+ High) 1.425 1.5 3.095 kΩ Termination voltage = USB regulator
voltage
Pull-Up Resistor (D+ Low) 0.9 1.575 kΩ Termination voltage = USB regulator
voltage
Pull-Down Resistors 14.25 15 24.8 kΩ
Universal Serial Bus AC Specifications

Meeting USB 2.0 compliance electrical tests.
Table 17. Universal Serial Bus AC Specifications

FULL SPEED DRIVER TIMING CLOAD = 50 pF
Signaling Rate 11.988 12 MHz
Output Time
Rise 4 20 ns VOH − VOL (10% to 90%), CLOAD = 50 pF
Fall 4 20 ns VOH − VOL (10% to 90%), CLOAD = 50 pF
Rise and Fall Matching 90 111.1 % Exclude transition from idle
Output Voltage Crossover 1.3 2.0 V Exclude transition from idle
FULL SPEED JITTER CLOAD = 50 pF
Driver Jitter Generated −2 +2 ns Next transitions
−1 +1 ns Paired transitions
Load Capacitance 50 pF Testing slew rate
ADuCM350 Data Sheet
LCD, Charge Pump
Table 18. LCD, Charge Pump Specifications
CAPACITANCE
Reservoir Capacitance Between 0.47 1 µF
VLCDVDD and VLCD_GND
Flying Capacitance 2.2 4.7 nF Between VLCD FLY1 and VLCD FLY2
VLCD
Switching Voltage
VLCD FLY1 −0.7 VLCD + 0.2 V Top of flying capacitor
VLCD FLY2 0 VCCM V Bottom of flying capacitor
VLCD Charge Pump Switching 32 kHz
Frequency
Minimum VLCD with Respect to 2.1 V When <2.1 V after 62.5 ms elapses indicates
VCCM_ANA and VCCM_DIG fault condition
VLCDVDD
VLCDVDD Voltage Range 2.4 3.65 V 5-bit programmable in steps of 40 mV
VLCDVDD Pin Leakage 3 nA To VCCM
0.2 nA To GND
VLCDVDD Start-Up Time 5 ms VLCDVDD = 0 V to 3.6 V, reservoir = 1 µF,
flying capacitor = 2.2 nF (minimum) and
4.7 nF (maximum)
VLCDVDD Line Regulation 0.32 %
V_LCD_xx VOLTAGE RANGE
V_LCD_13 Voltage Range VLCD ÷ 3 − 10 VLCD ÷ 3 + 10 mV
V_LCD_23 Voltage Range 2/3 VLCD − 13 2/3 VLCD + 13 mV
COMx PINS
DC Voltage Across Segment and 50 mV
COMx Pins
PIN OUTPUT IMPEDANCE
Segment 2000 Ω
Common 130 Ω
SYSTEM CLOCKS/TIMERS
The following tables document the system clock specifications in the ADuCM350.
Platform External Crystal Oscillator
Table 19. Platform External Crystal Oscillator Specifications
LOW FREQUENCY
CEXT1 = CEXT2 12 15 18 pF External capacitor, C1 = C2 (symmetrical
load)
Frequency 32,768 Hz
HIGH FREQUENCY
CEXT1 = CEXT2 10 12 15 pF External capacitor
Frequency 8 or 16 MHz
Data Sheet ADuCM350
On-Chip RC Oscillators
Table 20. On-Chip RC Oscillators Specifications
HIGH FREQUENCY RC OSCILLATOR
Frequency 16 MHz
Accuracy −5 +5 %
Start-Up Time 35 µs
LOW FREQUENCY RC OSCILLATOR
Frequency 32,768 Hz
Accuracy −20 +20 %
Start-Up Time 980 µs
PLLs
Table 21. PLL Specifications
SYSTEM PLL
Input Frequency 8 16 MHz
Output Frequency 16 32 MHz
Frequency Error 2500 ppm
RMS Jitter 92 ps @ 32 MHz, external XTAL
USB PLL
Input Frequency 8 16 MHz
Output Frequency 16 60 MHz 16 MHz input
Frequency Error 2500 ppm
Period Jitter 68 ps @ 60 MHz, external XTAL
Watchdog, Wake-Up, and General-Purpose Timers

Table 22. Watchdog, Wake-Up, and General-Purpose Timers Specifications
WATCHDOG TIMERS
Timeout Period
Shortest 0.03 ms 32,768 Hz clock, prescaler = 1
Longest 8191 sec 32,768 Hz clock, prescaler = 4096
WAKE-UP TIMERS
Timeout Period
Shortest 62.5 ns 16 MHz clock, prescaler = 1
Longest 136 Years 32,768 Hz clock, prescaler = 32,768
GENERAL-PURPOSE TIMER × 3
Timeout Period
Shortest 62.5 ns 16 MHz clock, prescaler = 1
Longest 65,535 sec 32,768 Hz clock, prescaler = 32,768
Timer Output PWM Frequency 1 16 MHz
1
Guaranteed by design.
ADuCM350 Data Sheet
POWER MANAGEMENT SPECIFICATIONS
The following tables cover the specifications for the power management section of the ADuCM350.
Power Supplies
Table 23. Power Supplies Specifications
SUPPLIES
VCCM_ANA/VCCM_DIG 2 3.6 V VCCM_x pins connected to the CR2032 battery, main supply for ADuCM350
VCCM_ANA/VCCM_DIG 2.5 3.6 V Battery operating range
VBACK 1.62 3.6 V Super capacitor pin, back-up mode supply
VBUS 4.75 5 5.25 V USB 5 V supply
VDD_IO 1.8 3.6 V Supply for some digital I/O pads; see Table 35, I/O supply column for details
VLCDVDD 1.8 3.6 V Supply for LCD I/O
Power Supply Monitoring

Table 24. Power Supply Monitoring Specifications
VCCM PSM
Voltage Detection Range 1.7 3.2 V 100 mV step size
Hysteresis ±10 ±100 mV
Trip Point Detection Accuracy Hysteresis + 70 mV
VRTC PSM
Hysteresis ±25 ±100 mV
VBACK PSM
Hysteresis ±100 mV
1
For details regarding these parameters, see the UG-587 hardware reference manual.
TRICKLE CHARGER
Table 25. Trickle Charger Specifications
CURRENT
Charge Current 0.48 mA Limits load on button cell at power-up
Reverse Current 1 μA
VOLTAGE
Forward Voltage 40 120 mV Where forward current reduces to zero
Data Sheet ADuCM350
TIMING CHARACTERISTICS
LCD Segment/Common Timing Specifications
Table 26. LCD Segment/Common Timing Specifications1, 2
Static Mux 4× Mux
FRAMESEL[3] FRAMESEL[2] FRAMESEL[1] FRAMESEL[0] fLCD (Hz) Frame Rate (Hz) fLCD (Hz) Frame Rate (Hz)
0 0 0 0 256 128 1024 128
0 0 0 1 204.8 102.4 819.2 102.4
0 0 1 0 170.7 85.3 682.7 85.3
0 0 1 1 146.3 73.1 585.1 73.1
0 1 0 0 128 64 512 64
0 1 0 1 113.8 56.9 455.1 56.9
0 1 1 0 102.4 51.2 409.6 51.2
0 1 1 1 93.1 46.5 372.4 46.5
1 0 0 0 85.3 42.7 341.3 42.7
1 0 0 1 78.8 39.4 315.1 39.4
1 0 1 0 73.1 36.6 292.6 36.6
1 0 1 1 68.3 34.1 273.1 34.1
1 1 0 0 64 32 256 32
1 1 0 1 60.2 30.1 240.9 30.1
1 1 1 0 56.9 28.4 227.6 28.4
1 1 1 1 53.9 26.9 215.6 26.9
1
fLCD = fBCLK/(FRAMESEL + 4). See the UG-587 hardware reference manual for details
2
FRAMESEL[3], FRAMESEL[2], FRAMESEL[1], and FRAMESEL[0] indicate the bit numbers in the LCD_COM register.
I2C Timing
Capacitive load for each of the I2C bus lines (CB) = 400 pF maximum as per I2C bus specifications; I2C timing is guaranteed by design and
not production tested.
Table 27. I2C Timing in Fast Mode (400 kHz)

Parameter Description Min Max Unit
tL Clock low pulse width 1300 ns
tH Clock high pulse width 600 ns
tSHD Start condition hold time 600 ns
tDSU Data setup time 100 ns
tDHD1 Data hold time 0 ns
tRSU Setup time for repeated start 600 ns
tPSU Stop condition setup time 600 ns
tBUF Bus-free time between a stop condition and a start condition 1.3 μs
tR Rise time for both clock and data 20 + 0.1 Cb 300 ns
tF Fall time for both clock and data 20 + 0.1 Cb 300 ns
tSUP Pulse width of spike suppressed 0 50 ns
1
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VINH (minimum) of the SCL signal) to bridge the undefined region
of the falling edge of SCL.
Table 28. I2C Timing in Standard Mode (100 kHz)

tL Clock low pulse width 4.7 μs
tH Clock high pulse width 4.0 ns
tSHD Start condition hold time 4.7 μs
tDSU Data setup time 250 ns
tDHD1 Data hold time 0 μs
tRSU Setup time for repeated start 4.0 μs
ADuCM350 Data Sheet
tPSU Stop condition setup time 4.0 μs
tBUF Bus-free time between a stop condition and a start condition 4.7 μs
tR Rise time for both clock and data 1 μs
tF Fall time for both clock and data 300 ns
1
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VINH (minimum) of the SCL signal) to bridge the undefined region
of the falling edge of SCL.
tBUF tSUP
tR
SDA (I/O)
MSB LSB ACK MSB
tDSU tF
tDSU
tDHD tDHD
tPSU
tSHD tR
tH tRSU
SCL (I) 1 8 9 1
2 TO 7
P S
tL tSUP S(R)
12073-002
tF
STOP START REPEATED
CONDITION CONDITION START
Figure 2. I2C-Compatible Interface Timing
Data Sheet ADuCM350
I2S Timing Specifications
I2S timing is guaranteed by design and not production tested; timing specifications are given for a standard I2S data rate of 2.5 MHz; the
I2S bus is designed to operate up to 25 MHz.
Table 29. I2S Timing: Master Transmitter

Parameter Symbol Min Typ Max Unit Test Conditions/Comments1
I2S MASTER TRANSMITTER TIMING
SCLK Period T 360 400 440 ns
Minimum Clock Period TTR 360 ns TTR is the minimum allowed clock
period for the transmitter, T > TTR
Clock High Period tHC 160 ns Minimum > 0.35 × T = 140 ns
Clock Low Period tLC 160 ns Minimum > 0.35 × T = 140 ns
Delay tDTR 300 ns Minimum < 0.80 × T = 320 ns
Data Hold Time tHTR 100 ns Minimum > 0 ns
Clock Rise Time tRC 60 ns Minimum > 0.15 × TTR = 54 ns (slave
mode only)
1
T refers to the typical value listed for the SCLK period; therefore, T = 400 ns in this case.
Table 30. I2S Timing: Slave Receiver

Parameter Symbol Min Typ Max Unit Test Conditions/Comments1
I2S SLAVE RECEIVER TIMING
SCLK Period T 360 400 440 ns TTR = 360 ns
Clock High Period tHC 110 ns Minimum < 0.35 × T = 126 ns
Clock Low Period tLC 160 ns Minimum < 0.35 × T = 126 ns
Data Setup Time tSR 300 ns Minimum < 0.20 × T = 72 ns
Data Hold Time tHTR 100 ns Minimum < 0 ns
1
T refers to the typical value listed for the SCLK period; therefore, T = 400 ns in this case.
tRC*
tLC ≥ 0.35T tHC ≥ 0.35T
VH = 2.0V
SCLK tHTR ≥ 0 VL = 0.8V
tDTR ≤ 0.8T
SD/WS
*tRC IS ONLY RELEVANT FOR TRANSMITTERS IN SLAVE MODE.

12073-003
NOTES
1. SD = SERIAL DATA, WS = WORD SELECT, WS = 0: CHANNEL 1 (LEFT), WS = 1: CHANNEL 2 (RIGHT).
Figure 3. I2S-Compatible Interface Transmitter Timing
ADuCM350 Data Sheet
tLC ≥ 0.35T tHC ≥ 0.35T
VH = 2.0V
SCLK
VL =0.8V
tSR ≥ 0.2T tHTR ≥ 0

SD
AND
WS
12073-004
NOTES
1. SD = SERIAL DATA, WS = WORD SELECT, WS = 0: CHANNEL 1 (LEFT), WS = 1: CHANNEL 2 (RIGHT).
Figure 4. I2S-Compatible Interface Receiver Timing

SPI Timing
SPIH can be used for high data rate peripherals.
Table 31. SPI Master Mode Timing1

Parameter Description Min Typ Max Unit
tSL SCLK low pulse width2 (SPIXDIV[5:0] + 1) × tUCLK ns
tSH SCLK high pulse width2 (SPIXDIV[5:0] + 1) × tUCLK ns
tDAV Data output valid after SCLK edge 0 35.5 ns
tDOSU Data output setup before SCLK edge2 (SPIDIV + 1) × tUCLK ns
tDSU Data input setup time before SCLK edge 58.7 ns
tDHD Data input hold time after SCLK edge 16 ns
tDF Data output fall time 12 35.5 ns
tDR Data output rise time 12 35.5 ns
tSR SCLK rise time 12 35.5 ns
tSF SCLK fall time 12 35.5 ns
1
Guaranteed by design.
2
tUCLK = 62.5 ns. It corresponds to the maximum internal clock frequency before clock dividers.
CS
1/2 SCLK 3/4 SCLK
CYCLE CYCLE
tCS tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSR tSF
SCLK
(POLARITY = 1)
tDAV
tDF tDR
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
tDSU
12073-005
tDHD
Figure 5. SPI Master Mode Timing (Phase Mode = 1)
Data Sheet ADuCM350
1 SCLK CYCLE 1 SCLK CYCLE

CS
tCS tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSR tSF
SCLK
(POLARITY = 1)
tDAV
tDOSU
tDF tDR
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
12073-006
tDSU
tDHD
Figure 6. SPI Master Mode Timing (Phase Mode = 0)
Table 32. SPI Slave Mode Timing

Parameter Description Min Typ Max Unit
tCS CS to SCLK edge 38 ns
tSL SCLK low pulse width1 (SPIXDIV[5:0] + 1) × tUCLK ns
tSH SCLK high pulse width1 62.5 (SPIDIV[5:0] + 1) × tUCLK ns
tDAV Data output valid after SCLK edge 49.1 ns
tDSU Data input setup time before SCLK edge 20.2 ns
tDHD Data input hold time after SCLK edge 10.1 ns
tDF Data output fall time 12 35.5 ns
tDR Data output rise time 12 35.5 ns
tSR SCLK rise time 12 35.5 ns
tSF SCLK fall time 12 35.5 ns
tDOCS Data output valid after CS edge 25 ns
tSFS CS high after SCLK edge 0 ns
1
tUCLK = 62.5 ns. It corresponds to the maximum internal clock frequency before clock dividers.
CS
tCS tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSR tSF
SCLK
(POLARITY = 1)
tDAV
tDF tDR
MISO MSB BIT 6 TO BIT 1 LSB
MOSI MSB IN BIT 6 TO BIT 1 LSB IN
tDSU
12073-007
tDHD
Figure 7. SPI Slave Mode Timing (Phase Mode = 1)
ADuCM350 Data Sheet
CS
tCS tSFS
SCLK
(POLARITY = 0)
tSH tSL
tSR tSF
SCLK
(POLARITY = 1)
tDAV
tDOCS
tDF tDR
MISO MSB BIT 6 TO BIT 1 LSB
MOSI MSB IN BIT 6 TO BIT 1 LSB IN
12073-008
tDSU
tDHD
Figure 8. SPI Slave Mode Timing (Phase Mode = 0)
Data Sheet ADuCM350
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum
Table 33. Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
Parameter Rating
or any other conditions above those indicated in the operational
Supplies
section of this specification is not implied. Operation beyond
VCCM_ANA, VCCM_DIG, VLCDVDD, −0.3 V to +3.6 V
VDD_IO, VBACK to AGND_x/DGNDx the maximum operating conditions for extended periods may
Decoupling affect product reliability.
DVDD, AVDD_RX/TX, VBIAS, VREF, VUSB −0.3 V to +2.0 V
Digital Input/Output
THERMAL RESISTANCE
P0.x, P1.x, P2.x, P3.x, P4.x, BOOT, RESETX −0.3 V to +3.6 V
TRACEx −0.3 V to +3.6 V θJA is specified for the worst-case conditions, that is, a device
Switch Matrix (RCAL 1, RCAL 2, AFE x) −0.3 V to +3.6 V soldered in a circuit board for surface-mount packages; assumes
TIA (TIA_I, TIA_O) −0.3 V to +3.6 V use of a JEDEC 4-layer board.
Analog Inputs (AN_x) −0.3 V to +3.6 V
Table 34. Thermal Resistance
REF_EXCITE −0.3 V to +1.98 V
Package Type θJA Unit
VLCD FLY1, VLCD FLY2 −0.3 V to +3.6 V
CSP_BGA 35 °C/W
V_LCD_13, V_LCD_23 −0.3 V to +3.6 V
VBUS to DGND −0.3 V to +5.25 V
USB DM, USB DP to DGND −0.3 V to +3.6 V ESD CAUTION
HF_XTALx, LF_XTALx −0.3 V to +1.98 V
Analog Ground to Digital Ground
AGND CTOUCH, AGND_RX/TX, AGND_REF −0.3 V to +0.3 V
to DGND, DGND1, DGND2, DGND USB
ADuCM350 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P2.1/ P2.3/ P2.5/S2/ P1.0/S3/ P1.2/S5/ P1.4/S7/ P1.6/S9/ P1.8/S11/ P1.10/ P1.12/ P1.14/
A DNC COM1/ COM3/ ECLOCK- P2.10/S23 P2.9/S22 P2.15/S28
D0/SCL D2/DIN D4 D6 D8 S13/D10 S15/D12 S17/D14
RESX DCX WRX
P2.0/ P2.2/ P2.4/S1/ P1.1/S4/ P1.3/S6/ P1.5/S8/ P1.7/S10/ P1.9/S12/ P1.11/ P1.13/ P1.15/
B V_LCD_23 COM2/ P2.11/S24 P2.12/S25 P2.8/S21
COM0 RWX-RDX D1/DOUT D3 D5 D7 D9 S14/D11 S16/D13 S18/D15
CSX
C HF_XTAL2 V_LCD_13 P2.7/S20/

P3.10/S31 TOUTA
D HF_XTAL1 VLCDVDD P2.13/S26 P2.6/

S19/TE
E VUSB VLCD FLY1 P3.11/S32 P2.14/S27
F USB DM VLCD FLY2 DGND DGND2/ P3.8/S29 P3.9/S30 P3.3/ P3.0/ P3.2/
USB LCD_GND SPI0_CS SPI0_SCLK SPI0_MOSI
P3.4/ P3.6/UTX/
I2CSCL/ P3.1/
G USB DP VBUS DGND1 SPI0_MISO TOUTB/
SPI1_SCLK SPI1_MOSI
TMS- TCK- P3.5/

H SWDIO/ SWCLK/ VCCM_ I2CSD/ DGND VDD_IO
P0.8 P0.9 DIG SPI1_MISO
P3.7/URX/
TDO-SWO/ TDI/P0.7/ P3.14/ TOUTC/ P0.4/ P0.1/
J P0.6/UTX LRCLK CAPT_E CAPT_B
URX SPI1_CS
P3.12/ P3.13/ P0.3/ P0.0/

AGND_RX/
K DVDD P0.11 BEEP/ BEEPX/ RESETX AGND_REF CAPT_D CAPT_A
AGND_TX
BMCLK SDATA
P4.0/ P4.1/ P0.5/ P0.2/

L I2CSCL I2CSD CAPT_F CAPT_C
P0.15/
M VBACK SPIH_CS TRACE0 TRACECLK
N LF_XTAL2 BOOT TRACE2 TRACE1
P0.13/ P0.14/ VCCM_ AGND TRACE3

P LF_XTAL1 SPIH_MISO SPIH_MOSI RCAL 1 AFE 2 AFE 4 AFE 6 AFE 8 VBIAS TIA_I AN_A AN_B CTOUCH
ANA
12073-009
P4.2/ P0.10/ P0.12/ AVDD_RX/ REF_
R TOUTB TOUTC SPIH_SCLK AVDD_TX
RCAL 2 AFE 1 AFE 3 AFE 5 AFE 7 VREF TIA_O AN_C AN_D TRST
EXCITE
Figure 9. Bump Location (Top View Looking Through Device, Bumps Not to Scale)
Table 35. Pin Function Descriptions

GPIO
Pin No. Mnemonic I/O1 I/O Supply2 Pull-Up/Down2 Description
Power and Ground
P4 VCCM_ANA S VCCM_ANA N/A Battery Connection and Analog Circuit Power.
Connect VCCM_ANA to the CR2032 battery.
VCCM_ANA powers the analog circuits. This
pin is connected to VCCM_DIG internally.
H6 VCCM_DIG S VCCM_DIG N/A Battery Connection and Digital Circuit Power.
Connect VCCM_DIG to the CR2032 battery.
VCCM_DIG powers the digital circuits. This pin
is connected to VCCM_ANA internally.
G2 VBUS S VBUS N/A 5 V USB Supply Voltage.
M1 VBACK S VBACK N/A RTC Supply. Connect VBACK to the super
capacitor.
H15 VDD_IO S VDD_IO N/A VDD_IO Supply.
E1 VUSB A VUSB N/A Regulated USB 3.6 V Supply.
R10 VREF A N/A N/A 1.8 V Reference Voltage Decoupling Capacitor
Pin.
P10 VBIAS A N/A N/A 1.1 V Bias Voltage Decoupling Capacitor Pin.
Data Sheet ADuCM350
GPIO
K1 DVDD A N/A N/A 1.8 V Digital Regulator Decoupling Capacitor Pin.
R4 AVDD_RX/AVDD_TX A AVDD TX/RX N/A 1.8 V Analog Regulator Decoupling Capacitor
Pin for Receiver (Rx)/Transmitter (Tx) Circuits.
K9 AGND_RX/AGND_TX G N/A N/A Rx/Tx Analog Ground.
K10 AGND_REF G N/A N/A Reference Ground.
H14 DGND G N/A N/A Digital Ground.
G6 DGND1 G N/A N/A Digital Ground.
F7 DGND2/LCD_GND G N/A N/A Digital Ground/Ground for LCD.
F6 DGND USB G N/A N/A USB Ground. Connect DGND USB to the
digital ground plane.
AFE Pins
P12 AN_A A VCCM_ANA N/A ADC Mux Input.
P13 AN_B A VCCM_ANA N/A ADC Mux Input.
R13 AN_C A VCCM_ANA N/A ADC Mux Input.
R14 AN_D A VCCM_ANA N/A ADC Mux Input.
P5 RCAL 1 A VCCM_ANA N/A Terminal A of Calibration Resistor. Connect
RCAL 1 to the switch matrix.
R5 RCAL 2 A VCCM_ANA N/A Terminal B of Calibration Resistor. Connect
RCAL 2 to the switch matrix.
R6 AFE 1 A VCCM_ANA N/A Uncommitted AFE Pin 1.
P6 AFE 2 A VCCM_ANA N/A Uncommitted AFE Pin 2.
P11 TIA_I A VCCM_ANA N/A Transimpedance Amplifier Input. Connect the
IV resistor to this pin.
R11 TIA_O A VCCM_ANA N/A Transimpedance Amplifier Output. Connect
the IV resistor to this pin.
R12 REF_EXCITE A VCCM_ANA N/A Gated Precision Reference Voltage.
Debug Interface
J1 TDO-SWO/P0.6/UTX I/O VCCM_DIG Pull-up JTAG Serial Data Output or Serial Wire Trace
Output/GPIO/UART_TX. This is a
multifunction pin.
J2 TDI/P0.7/URX I/O VCCM_DIG Pull-up JTAG Serial Data Input/GPIO/UART_RX. This is
a multifunction pin.
H1 TMS-SWDIO/P0.8 I/O VCCM_DIG Pull-up JTAG Test Mode Select or Serial Wire
Data/GPIO. This is a multifunction pin.
H2 TCK-SWCLK/P0.9 I/O VCCM_DIG Pull-down JTAG Test Clock or Serial Wire Clock/GPIO. This
is a multifunction pin.
R15 TRST I VCCM N/A Trace Reset.
M15 TRACECLK O VCCM N/A Trace Clock.
M14 TRACE0 O VCCM N/A Trace Data 0.
N15 TRACE1 O VCCM N/A Trace Data 1.
N14 TRACE2 O VCCM N/A Trace Data 2.
P15 TRACE3 O VCCM N/A Trace Data 3.
ADuCM350 Data Sheet
GPIO
SPI H
R3 P0.12/SPIH_SCLK I/O VCCM_DIG Pull-up GPIO/Serial Port H Clock. This is a dual
function pin.
P2 P0.13/SPIH_MISO I/O VCCM_DIG Pull-up GPIO/Serial Port H MISO. This is a dual
function pin.
P3 P0.14/SPIH_MOSI I/O VCCM_DIG Pull-up GPIO/Serial Port H MOSI. This is a dual
function pin.
M2 P0.15/SPIH_CS I/O VCCM_DIG Pull-up GPIO/Serial Port H Chip Select (Active Low).
This is a dual function pin.
Other Serial Ports
F14 P3.0/SPI0_SCLK I/O VDD_IO Pull-up GPIO/SPI 0 SCLK. This is a dual function pin.
G14 P3.1/SPI0_MISO I/O VDD_IO Pull-up GPIO/SPI 0 MISO. This is a dual function pin.
F15 P3.2/SPI0_MOSI I/O VDD_IO Pull-up GPIO/SPI 0 MOSI. This is a dual function pin.
F10 P3.3/SPI0_CS I/O VDD_IO Pull-up GPIO/SPI 0 Chip Select (Active Low). This is a
dual function pin.
G10 P3.4/I2CSCL/SPI1_SCLK I/O VDD_IO Pull-up GPIO (External Interrupt 7)/I2C Clock/SPI 1
SCLK. This is a multifunction pin.
H10 P3.5/I2CSD/SPI1_MISO I/O VDD_IO Pull-up GPIO/I2C Data/SPI 1 MISO. This is a
multifunction pin.
G15 P3.6/UTX/TOUTB/SPI1_MOSI I/O VDD_IO Pull-up GPIO/UART Tx/Timer B Output/SPI 1 MOSI.
This is a multifunction pin.
J10 P3.7/URX/TOUTC/SPI1_CS I/O VDD_IO Pull-up GPIO/UART Rx/Timer C Output/SPI 1 Chip
Select (Active Low). This is a multifunction pin.
USB
F1 USB DM I/O VCCM_DIG N/A USB Data −.
G1 USB DP I/O VCCM_DIG N/A USB Data +.
CapTouch Interface
K15 P0.0/CAPT_A A VCCM_DIG Pull-up GPIO (External Interrupt 1)/CapTouch A. This is
a dual function pin.
J15 P0.1/CAPT_B A VCCM_DIG Pull-up GPIO (External Interrupt 2)/CapTouch B. This is
L15 P0.2/CAPT_C A VCCM_DIG Pull-up GPIO (External Interrupt 3)/CapTouch C. This is
K14 P0.3/CAPT_D A VCCM_DIG Pull-up GPIO (External Interrupt 4)/CapTouch D. This
is a dual function pin.
J14 P0.4/CAPT_E A VCCM_DIG Pull-up GPIO (External Interrupt 5)/CapTouch E. This is
L14 P0.5/CAPT_F A VCCM_DIG Pull-up GPIO (External Interrupt 6)/CapTouch F. This is
P14 AGND CTOUCH G N/A N/A Capacitance to Digital Converter AC Shield.
System Clocks
P1 LF_XTAL1 A RTC_VBACK N/A 32 kHz XTAL Pin.
N1 LF_XTAL2 A RTC_VBACK N/A 32 kHz XTAL Pin.
D1 HF_XTAL1 A DVDD N/A 16 MHz XTAL Pin.
C1 HF_XTAL2 A DVDD N/A 16 MHz XTAL Pin.
Display
E2 VLCD FLY1 A VLCD VDD N/A LCD Flying Capacitor Top Plate.
F2 VLCD FLY2 A VLCD VDD N/A LCD Flying Capacitor Bottom Plate.
D2 VLCDVDD S N/A N/A Full-Scale LCD Voltage Output or VLCD Supply.
C2 V_LCD_13 A VLCD VDD N/A One-Third (1/3) LCD Voltage. Leave this pin as
no connect.
B1 V_LCD_23 A VLCD VDD N/A Two-Thirds (2/3) LCD Voltage. Leave this pin
as no connect.
Data Sheet ADuCM350
GPIO
B2 P2.0/COM0 I/O VLCD VDD Pull-up GPIO/Common Output 0 for LCD Back Plane
(COM 0). This is a dual function pin.
A2 P2.1/COM1/RESX I/O VLCD VDD Pull-up GPIO/COM 1/Parallel Display Interface (PDI)
Reset. This is a multifunction pin.
B3 P2.2/COM2/CSX I/O VLCD VDD Pull-up GPIO/COM 2/PDI Chip Select. This is a
multifunction pin.
A3 P2.3/COM3/DCX I/O VLCD VDD Pull-up GPIO/COM 3/PDI Data Select. This is a
multifunction pin.
B4 P2.4/S1/RWX-RDX I/O VLCD VDD Pull-up GPIO/Segment Driver 1 (SEG 1)/PDI R/WX or
RDX. This is a multifunction pin.
A4 P2.5/S2/ECLOCK-WRX I/O VLCD VDD Pull-up GPIO/SEG 2/PDI E Clock Output (Motorola Bus
Mode) or PD Write Select (Intel® Bus Mode).
A5 P1.0/S3/D0/SCL I/O VLCD VDD Pull-down GPIO/SEG 3/PDI D0/PDI Serial Port Clock. This
is a multifunction pin.
B5 P1.1/S4/D1/DOUT I/O VLCD VDD Pull-down GPIO/SEG 4/PDI D1/PDI Serial Port Data
Output. This is a multifunction pin.
A6 P1.2/S5/D2/DIN I/O VLCD VDD Pull-down GPIO/SEG 5/PDI D2/PDI Serial Port Data Input.
B6 P1.3/S6/D3 I/O VLCD VDD Pull-down GPIO/SEG 6/PDI D3. This is a multifunction pin.
A7 P1.4/S7/D4 I/O VLCD VDD Pull-down GPIO/SEG 7/PDI D4. This is a multifunction pin.
B7 P1.5/S8/D5 I/O VLCD VDD Pull-down GPIO/SEG 8/PDI D5. This is a multifunction pin.
B8 P1.7/S10/D7 I/O VLCD VDD Pull-down GPIO/SEG 10/PDI D7/System Clock Output.
B9 P1.9/S12/D9 I/O VLCD VDD Pull-down GPIO/SEG 12/ PDI D9. This is a multifunction pin.
A10 P1.10/S13/D10 I/O VLCD VDD Pull-down GPIO/SEG 13/PDI D10. This is a multifunction
pin.
B10 P1.11/S14/D11 I/O VLCD VDD Pull-down GPIO/SEG 14/PDI D11. This is a multifunction
pin.
pin.
pin.
pin.
pin.
D15 P2.6/S19/TE I/O VLCD VDD Pull-down GPIO/SEG 19/TE. This is a multifunction pin.
C15 P2.7/S20/TOUTA I/O VLCD VDD Pull-down GPIO/SEG 20/Timer A Output. This is a multi-
function pin.
B15 P2.8/S21 I/O VLCD VDD Pull-down GPIO/SEG 21. This is a dual function pin.
A14 P2.9/S22 I/O VLCD VDD Pull-down GPIO/SEG 22. This is a dual function pin.
A13 P2.10/S23 I/O VLCD VDD Pull-down GPIO/SEG 23. This is a dual function pin.
B13 P2.11/S24 I/O VLCD VDD Pull-down GPIO/SEG 24. This is a dual function pin.
B14 P2.12/S25 I/O VLCD VDD Pull-up GPIO/SEG 25. This is a dual function pin.
D14 P2.13/S26 I/O VLCD VDD Pull-up GPIO/SEG 26. This is a dual function pin.
E15 P2.14/S27 I/O VLCD VDD Pull-up GPIO/SEG 27. This is a dual function pin.
A15 P2.15/S28 I/O VLCD VDD Pull-up GPIO/SEG 28. This is a dual function pin.
F8 P3.8/S29 I/O VLCD VDD Pull-up GPIO/SEG 29. This is a dual function pin.
F9 P3.9/S30 I/O VLCD VDD Pull-up GPIO/SEG 30. This is a dual function pin.
C14 P3.10/S31 I/O VLCD VDD Pull-up GPIO/SEG 31. This is a dual function pin.
E14 P3.11/S32 I/O VLCD VDD Pull-up GPIO/SEG 32. This is a dual function pin.
ADuCM350 Data Sheet
GPIO
Miscellaneous Digital Input/Output
K8 RESETX I VCCM_DIG Pull-up Reset Pin (Active Low).
L1 P4.0/I2CSCL I/O VCCM_DIG Pull-up GPIO (External Interrupt 0)/I2C Clock. This is a
dual function pin.
L2 P4.1/I2CSD I/O VCCM_DIG Pull-up GPIO/I2C Data. This is a dual function pin.
R1 P4.2/TOUTB I/O VCCM_DIG Pull-up GPIO/Timer B Output. This is a dual function
pin.
R2 P0.10/TOUTC I/O VCCM_DIG Pull-up GPIO (External Interrupt 8)/Timer C Output.
This is a dual function pin.
K2 P0.11 I/O VCCM_DIG Pull-up GPIO (External Clock Input Pin).
N2 BOOT I VCCM_DIG Pull-down The device enters serial download mode if
this pin is held high during, and for a short
time after, a reset. It executes user code after
any reset event or if the pin is low.
A1 DNC N/A N/A Do Not Connect. Leave this pin floating.
Audio
K6 P3.12/BEEP/BMCLK I/O VCCM_DIG Pull-down GPIO/Beeper Output Positive/I2S Bit Clock.
K7 P3.13/BEEPX/SDATA I/O VCCM_DIG Pull-down GPIO/Beeper Output Negative/I2S Serial Data
Output. This is a multifunction pin.
J6 P3.14/LRCLK I/O VCCM_DIG Pull-down GPIO/I2S Frame Clock. This is a dual function pin.
1
S is supply, A is analog input, I is digital input, O is digital output, I/O is digital input/output, and G is ground.
2
N/A means not applicable.
Data Sheet ADuCM350
TYPICAL PERFORMANCE CHARACTERISTICS

1.8010 1.8010
1.8009
1.8005
10mA LOAD 1.8008
VCCM = 3.6V
1.8007
ALDO VOLTAGE (V)
VREF VOLTAGE (V)

1.8000
1.8006
VCCM = 2.5V
1.7995 1.8005
1.8004
1.7990
1.8003
1.8002
1.7985
1.8001
1.7980 1.8000
12073-010
12073-013
2.50 2.75 3.00 3.25 3.50 –0.0003 –0.0002 –0.0001 0
VCCM (V) LOAD CURRENT (A)
Figure 10. ALDO Line Regulation Figure 13. VREF Load Regulation
1.810 1.804
1.802
REF_EXCITE VOLTAGE (V)

1.805
ALDO VOLTAGE (V)
1.800
1.800 1.798
1.796
1.795
1.794
1.790 1.792
12073-014
12073-011
–0.010 –0.008 –0.006 –0.004 –0.002 0 –0.0003 –0.0002 –0.0001 0

ALDO CURRENT (A) REF_EXCITE LOAD CURRENT (A)
Figure 11. ALDO Load Regulation Figure 14. REF_EXCITE Load Regulation
1.80100 1.10004
1.80095
1.10002
1.80090
300µA LOAD ON VREF
1.80085 1.10000
1.80080
VBIAS (V)
VREF (V)
1.09998
1.80075
1.09996
1.80070
1.80065 1.09994
1.80060
1.09992
1.80055
1.80050 1.09990
12073-012
12073-015
2.5 2.7 2.9 3.1 3.3 3.5 2.5 2.7 2.9 3.1 3.3 3.5
VCCM (V) VCCM (V)
Figure 12. VREF Line Regulation Figure 15. VBIAS Line Regulation
ADuCM350 Data Sheet
1.0 1.0
50°C VCCM = 3.0 V
25°C
0.8 0.8 0°C
0.6 0.6
0.4 0.4
TIA_O DNL (LSB)

TIA_O INL (LSB)
0.2 0.2
0 0
–0.2 –0.2
–0.4 –0.4
–0.6 VCCM –0.6
–0.8 VCCM = 3.6V –0.8

VCCM = 3.0V
VCCM = 2.4V
–1.0 –1.0
12073-019
12073-016
10200 15200 20200 25200 30200 35200 40200 45200 50200 10000 15000 20000 25000 30000 35000 40000 45000 50000
CODE CODE
Figure 16. ADC TIA_O INL (16-Bit) vs. Code (±150 μA) Figure 19. ADC TIA_O DNL (16-Bit) vs. Code (Temperature)
1.0 1.0
VCCM VCCM
0.8 VCCM = 3.6V 0.8 VCCM = 3.6V
VCCM = 3.0V VCCM = 3.0V
0.6 VCCM = 2.4V 0.6 VCCM = 2.4V
0.4 0.4
TIA_O DNL (LSB)
AN _A INL (LSB)
0.2 0.2
0 0
–0.2 –0.2
–0.4 –0.4
–0.6 –0.6
–0.8 –0.8
–1.0 –1.0
12073-020
12073-017
10200 15200 20200 25200 30200 35200 40200 45200 50200 17500 22500 27500 32500 37500 42500
CODE CODE
Figure 17. ADC ADC TIA_O DNL (16-Bit) vs. Code Figure 20. ADC AN_A INL (16-Bit) vs. Code
1.0 1.0
50°C VCCM = 3.0 V VCCM
25°C 0.8
0.8 0°C VCCM = 3.6V
VCCM = 3.0V
0.6 0.6 VCCM = 2.4V
0.4 0.4
AN _A DNL ( LSB )
TIA_O INL (LSB)
0.2 0.2
0 0
–0.2 –0.2
–0.4 –0.4
–0.6 –0.6
–0.8 –0.8
–1.0 –1.0
12073-021
12073-018
10000 15000 20000 25000 30000 35000 40000 45000 50000 17500 22500 27500 32500 37500 42500
CODE CODE
Figure 18. ADC ADC TIA_O INL (16-Bit) vs. Code (Temperature) Figure 21. ADC AN_A DNL (16-Bit) vs. Code
Data Sheet ADuCM350
1.0 1.0
50°C VCCM = 3.0V 2.5V MEASURED ACROSS RCAL
25°C 3.0V ATTEN OFF
0.8 0.8 3.6V
0°C COMP OFF
DAC CODE 0x200 TO 0xE00
0.6 0.6
0.4 0.4
AN _A INL (LSB)
DAC INL (LSB)

0.2 0.2
0 0
–0.2 –0.2
–0.4 –0.4
–0.6 –0.6
–0.8 –0.8
12073-025
–1.0 –1.0
12073-022
17510 22510 27510 32510 37510 42510 47510 0 500 1000 1500 2000 2500 3000 3500 4000
CODE CODE
Figure 22. ADC AN_A INL (16-Bit) vs. Code (Temperature) Figure 25. DAC INL (12-Bit) vs. Code
1.0 1.0
50°C VCCM = 3.0V 2.5V MEASURED ACROSS RCAL
0.8 25°C 0.8 3.0V ATTEN OFF
0°C 3.6V COMP OFF
DAC CODE 0x200 TO 0xE00
0.6 0.6
0.4 0.4
AN _A DNL (LSB)
DAC DNL (LSB)

0.2 0.2
0 0
–0.2 –0.2
–0.4 –0.4
–0.6 –0.6
–0.8 –0.8
–1.0 –1.0
12073-023
12073-026
17510 22510 27510 32510 37510 42510 47510 0 500 1000 1500 2000 2500 3000 3500 4000
CODE CODE
Figure 23. ADC AN_A DNL (16-Bit) vs. Code (Temperature) Figure 26. DAC DNL (12-Bit) vs. Code
100
DAC CODE = 0x800 (MIDSCALE)
0 VCCM = 3.3V
MEASURED AT RCAL
–3
10
AMPLITUDE (dB)
–6
(µV/√Hz)
1 DAC_ATTEN_EN = 0
–9
–12
0.1 DAC_ATTEN_EN = 1
–15
3.6V
3.0V
2.4V 0.01
–18
12073-027
12073-024
1k 10k 100k 1 10 100 1k 10k 100k
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 24. Receive Channel Antialias Filter Roll-Off Figure 27. Noise Spectral Density
ADuCM350 Data Sheet
1.6 500
Z = 127Ω + 56nF 1000 MEASUREMENTS
SINE AMPLITUDE = 9mV rms ON 1 ADuCM350 DEVICE
450 DAC_ATTEN_EN = 1
1.4 0x400 TO 0xC00 RTIA = 7.5kΩ
400
VOLTAGE AT RCAL (V)
350
NUMBER OF UNITS
1.2
300
1.0 250
200
0.8 0xC00 TO 0x400
150
100
0.6
50
0.4 0
12073-032
12073-028
–15 –10 –5 0 5 10 15 20 25 30 181.5 182.2 183.0 183.7 184.4 185.2
TIME (µs) IMPEDANCE MAGNITUDE (Ω)
Figure 28. Settling Time of the DAC at RCAL Figure 31. Impedance Measurement Magnitude Precision
90 500
Z = 127Ω + 56nF 1000 ADuCM350 1000 MEASUREMENTS Z = 127Ω + 56nF
SINE AMPLITUDE = 9mV rms DEVICES MEASURED ON 1 ADuCM350 DEVICE SINE AMPLITUDE = 9mV rms
80 DAC_ATTEN_EN = 1 450 DAC_ATTEN_EN = 1
RTIA = 7.5kΩ RTIA = 7.5kΩ
400
70
350
MUMBER OF UNITS
NUMBER OF UNITS
60
300
50
250
40
200
30
150
20
100
10 50
0 0
12073-029
12073-031
190.94 191.04 191.13 191.23 191.32 191.42 40.08 40.28 40.48 40.68 40.88 41.08
IMPEDANCE MAGNITUDE (Ω) IMPEDANCE PHASE (°)
Figure 29. Impedance Measurement Magnitude Accuracy Figure 32. Impedance Measurement Phase Precision
100 18000
1000 ADuCM350 Z = 127Ω + 56nF
DEVICES MEASURED 4.662pF_G1
SINE AMPLITUDE = 9mV rms
90 6.993pF_G1
DAC_ATTEN_EN = 1 16000
RTIA = 7.5kΩ 9.324pF_G1
80 2.331pF_G2
14000 4.662pF_G2
70 6.993pF_G2
NUMBER OF UNITS
12000 9.324pF_G2
60 2.331pF_G4
CDC CODES
10000 4.662pF_G4
50 6.993pF_G4
9.324pF_G4
8000
40
6000
30
4000 CAPDAC COMPENSATED

20 AT 50pF
AUTOZERO = 2µs
10 2000 HOLD TIME = 2µs
PH13 = 2µs
PH23 = 4µs
0 0
12073-030
12073-033
–48.66 –48.63 –48.59 –48.55 –48.52 –48.48 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

IMPEDANCE PHASE (°) INPUT CAPACITANCE (pF)
Figure 30. Impedance Measurement Phase Accuracy Figure 33. CapTouch Linearity
Data Sheet ADuCM350
20 3.5
1kHz TONE
0
3.0
GPIO P1.1 HIGH DRIVE
–20
–40 2.5
GPIO P1.1 LOW DRIVE
AMPLITUDE (dB)
–60
2.0
VOH (V)
–80
1.5
–100
–120 1.0
–140
0.5
–160
–180 0
12073-036
12073-034
0 10 20 30 40 50 60 70 80 –0.016 –0.014 –0.012 –0.010 –0.008 –0.006 –0.004 –0.002 0 0.002
FREQUENCY (kHz) IOH (A)
Figure 34. CapTouch SNR Figure 36. GPIO VOH vs. IOH
0.7
0.6
0.5
0.4
VOL (V)
GPIO P1.1 LOW DRIVE

0.3
0.2
GPIO P1.1 HIGH DRIVE

0.1
0
12073-035
0 0.001 0.002 0.003 0.004 0.005 0.006 0.007

IOL (A)
Figure 35. GPIO VOL vs. IOL
ADuCM350 Data Sheet
ANALOG FRONT END

SWITCH
MATRIX
RCAL 1 DAC CODE
VREFDAC (ARBITRARY)
EXCITATION ATTEN LP RCF
RCAL RCAL 2 AMPLIFIER 1 OR 40 50kHz
12-BIT GAIN AND SINE
AFE 8 D DAC OFFSET GENERATION
CAL
AFE 7
TRAPEZOID
CONFIGURATION
AFE 6 326.53kSPS GENERATION

P
X
EXAMPLE
AFE 5
RZ
AFE 4 N ADC
Y MUX DFT RE
AFE 3 HANN N = 2048
TEMP GAIN VREFADC WINDOW IM
SENS AAF (12.8ms)
DIFFERENTIAL
1 OR 1.5
AFE 2 VBIAS 55kHz
INPUTS
16-BIT GAIN AND 50Hz/60Hz
AFE 1 T ADC OFFSET REJECTION
CAL SINC2HF 178 SINC2LF
TIA_I TIA_O
160kSPS
SINGLED ENDED
RTIA AN_A 900SPS

AN_B
INPUTS
AN_C 900SPS
AN_D
12073-037
VCCM
DVDD
AVDD
Figure 37. AFE System Block Diagram
For full details on the ADuCM350, refer to the UG-587 A large range of impedances can be measured, depending on
hardware reference manual. the application. Users can optimize the calibration resistor
The ADuCM350 is a high accuracy, configurable, AFE with a (RCAL), ac amplitude of the excitation waveform, and the
low power, peripheral rich, microcontroller subsystem. current-to-voltage (IV) resistor to tailor fit the system to the
application demands. Impedances can be measured from 80 Hz
EXCITATION STAGE to ~75 kHz.
The excitation/transmit stage consists of a 12-bit DAC with an The switch matrix offers the user full configurability with 34
excitation buffer and an instrumentation amplifier in a feedback user selectable switches. The current carrying switches on both
path to the DAC, which forces an accurate voltage across the excitation buffer output and the transimpedance input are opti-
impedance to be measured, thereby removing parasitics from mally sized for current loads. The switch matrix allows the device
the measurement system. to measure and store offset and gain results. The ADuCM350
All measurements are referenced to a precision external resistor, can self calibrate Rx offset and gain, Tx offset and gain, and
which is used in the internal calibration loop to ensure no dc switch leakage. This off loads the requirement for an extensive
bias across an unknown impedance. factory calibration routine and removes temperature and aging
induced errors from measurements.
Data Sheet ADuCM350
D2
D3
D4
EXCITATION
D5 AMPLIFIER
D6 EXCITATION
D
D7
D8
DR1
RCAL 1 PL
RCAL 2
PR1
P2
P3
P4
P5
P
P6
P7
P8
N1
N2
N3
N4
N
N5
N6
N7
NR2
NL
T1
T2 VBIAS TIA
T3
T4
T
T5 6 IVS
T6 TIA_I TIA_O
T7 RTIA
TR2
AFE 1
AFE 2
AFE 3
AFE 4
AFE 5
AFE 6
AFE 7
12073-038
AFE 8
Figure 38. Switch Matrix
ADuCM350 Data Sheet
MEASUREMENT STAGE The DFT engine performs a 2048-point single frequency
discrete Fourier transform. It takes the 16-bit ADC output and
The AFE consists of a multiplexed input, 160 kSPS, 16-bit ADC converts it to complex impedance with real and imaginary
with four dedicated voltage measurement channels and up to components. As the ADC samples at 160 kSPS, this allows for a
eight multiplexed current measurement channels using the on- 79.5 Hz signal energy bandwidth, which gives excellent
chip transimpedance amplifier. The multiplexed channels are rejection of interferers.
filtered and differentially buffered prior to data conversion.
100
The ADC data can be interrogated using three methods.
• By raw data at 160 kSPS. 50
• At the output of a 50 Hz/60 Hz filter at 900 SPS.

0
MAGNITUDE (dB)
• Through a discrete Fourier transform (DFT) engine.
The power line filter is optimized for fast settling, just 36.6 ms –50
settling. Data at 900 SPS can be further decimated by the user
without requiring additional filtering. –100
0
MAGNITUDE (dB)
NOTCHES ARCHITECTED AT 50Hz

–20 AND 60Hz TO REJECT POWER LINE –150
INTERFERENCE
–40
12073-041
–60 –200
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
–80 FREQUENCY (Hz)
–100 Figure 40. Frequency Response, 2048-Point DFT at 20 kHz
0 100 200 300 400 500 600 700 800 900
FREQUENCY (Hz)
0
MAGNITUDE (dB)
–20
–40
–60
–80
12073-040
–100
0 500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
Figure 39. Power Line Rejection Modeling
TEMPERATURE
SENSOR
VBIAS
+
+
– AN_A + VREF = 1.8V
TIA_I TIA_O AN_B –
ANTIALIAS
FILTERING
RTIA AN_C –
+ –
AN_D ADC
AVDD/2 – + –
–
CTIA DVDD/2 +
VCCM +
VBIAS
PRECISION VREF
12073-039
REFERENCE
Figure 41. Rx Stage
Data Sheet ADuCM350
AFE CONTROL
AFE
DATA
FIFO
(TO M3)
WAVEFORM
GENERATOR
DFT
ANALOG 50Hz/60Hz MMR ARM

CORTEX-M3
SYSTEM BUS
BLOCKS FILTER
DSP
ACCELERATORS
INTERRUPT
GENERATION
SEQUENCER COMMAND
12073-042
FIFO
Figure 42. AFE Control
The AFE can be controlled by the ARM Cortex-M3 via MMRs. The sensor input configuration is very flexible and uses several
All blocks within the AFE are fully controllable and observable techniques to ensure that there are no false touches (that is, no
using the MMR registers. Access the MMRs through an AHB registering touches caused by a changing environment) on the
bus or indirectly through a programmable sequencer. There are external sensors. To minimize noise pickup from the system,
two dedicated DMA channels to remove burden from the ARM the ADuCM350 CapTouch core includes several algorithms,
Cortex-M3 to manage data and control FIFOs. such as median and averaging filtering measurements, as well
The sequencer handles low level AFE operations and allows the as configurable excitation frequency and duty cycle. The
AFE to perform its functions independently. It performs cycle subsystem includes a self timer and touch-and-release routines
accurate precision AFE measurements asynchronously of the to optimize the power consumption and reduce the computing
core. workload in the ARM Cortex-M3.
CAPACITIVE
The sequencer allows the user to create parameterized wave- TOUCH
forms using the waveform generator block. The waveforms can

be trapezoids or sinusoids. Arbitrary waveforms are possible BU_ONOFF
using the AFE sequencer and DMA transfers. BU_LEFT
BU_RIGHT
SINE BU_UP
GENERATION BU_DOWN
BU_ENTER
TRAPEZOID DAC AGND_TX

GENERATION PCB
12073-044
CapTouch
12073-043
DAC CODE
(DC) Figure 44. CapTouch External Interface
Figure 43. Waveform Generation
CAPTOUCH FEATURES
The ADuCM350 incorporates a capacitive touch subsystem that
interfaces with up to six capacitive touch channels in self
capacitance mode and incorporates high performance
capacitance sensing circuitry without external components.
ADuCM350 Data Sheet
MICROSUBSYSTEM
MEMORIES In power saving mode, GPIO pins retain state; they tristate on
The memory offerings for the ADuCM350 are as follows: reset to prevent any bus irritation. GPIOs of note are as follows:
• 384 kB flash. • 32 pins multiplexed with LCD segment common pins
• 16 kB of flash configured for EEPROM emulation. • Six pins multiplexed with CapTouch
• 2 kB user information. • Nine pins on a dedicated VDDIO for ease of interfacing to
• 32 kB SRAM. peripherals
• 2 kB dedicated SRAM for USB endpoint. TIMERS
Flash General-Purpose Timers
The ADuCM350 includes 384 kB of embedded flash memory, ADuCM350 has three identical general-purpose timers, each
accessed using the flash controller. The flash controller is con- with a 16-bit count-up/count-down counter. The count-
nected to the bus matrix as a slave device for core and DMA up/count-down counter can be clocked from one of four user
access, as well as the 32-bit AHB for MMR access. selectable clock sources. Any selected clock source can be scaled
The flash controller supports 384 kB of user space and 2 kB of down using a prescaler of 16, 256, or 32,768.
information space. Read and write to flash are executed via Watch Dog Timer (WDT)
AHB only. The 384 kB flash memory comprises one 256 kB The watchdog timer is a 16-bit count-down timer with a program-
flash array and one 128 kB flash array. The 256 kB flash mable prescaler. The prescaler source is selectable and can be
memory array and 128 kB flash array are controlled by two scaled by a factor of 1, 16, 256, or 4096. The watchdog timer is
separate flash controllers with separate register controls. clocked either by the 32 kHz crystal oscillator (LFXTAL) or by
With respect to flash integrity, the device supports the 32 kHz on-chip oscillator (LFOSC).The watchdog timer
• Automatic signature check of information space at reset (WDT) is used to recover from an illegal software state. After
the WUT is enabled by user code, it requires periodic servicing
• User signature for application code
to prevent it from forcing a reset or interrupt of the processor. A
• Parity checking on a per access basis
WDT timeout can generate a reset or an interrupt.
• 20,000 cycle endurance with 20 ms erase and 20 μs program
• 100-year data retention at room temperature Wake-Up Timer
General-Purpose Flash The wake-up timer (WUT) consists of a 32-bit counter clocked
from the 32 kHz external crystal (LFXTAL), 32 kHz internal
The device contains 16 kB of embedded flash memory for oscillator (LFOSC), or peripheral clock (PCLK). The selected
general purpose, such as EEPROM emulation. clock source can be scaled
SRAM
USB
There is 32 kB of SRAM on chip of which 16 kB is retained
The USB port on the ADuCM350 is a USB 2.0 full speed com-
during hibernate mode and an optional 16 kB can be retained
pliant port. The module consists of the USB controller, USB
during hibernate for reduced leakage current.
PHY, USB RAM, and a 2-channel DMA. An integrated regulator
DEBUG CAPABILITY powered by VBUS supplies the USB PHY. A dedicated PLL with
The ADuCM350 supports two types of debug host interface: 60 MHz clock capability is available for clock generation.
4-wire JTAG debug (JTAG) interface and a serial 2-wire debug The USB supports bulk, isochronous, interrupt, and control modes.
(SWD) interface. It has seven hardware endpoint and a dedicated 2-channel DMA. It
The ADuCM350 incorporates the complete embedded trace of supports suspend and wakeup.
the ARM Cortex-M3 features to maximize code analysis, system The controller hardware is supplemented by a complete set of
profiling, and debugging capabilities. USB device class drivers to provide complete USB functionality
PROGRAMMABLE GPIOS using a defined Micrium stack. The USB stack has a requirement
for an RTOS to be on the system. Analog Devices, Inc., has
The ADuCM350 has 66 GPIO pins, most of which have
developed its system using the Micrium μC/OS-II.
multiple, configurable functions defined by user code. They can
be configured as an input/output and have programmable pull-
up or pull-down resistors. All I/O pins are functional over the
full supply range (VBAT = 1.8 V to 3.6 V).
Data Sheet ADuCM350
POWER MANAGEMENT AND CLOCKING internal oscillator, HFOSC is a 16 MHz internal oscillator, and
Power Modes LFXTAL is a 32 kHz external crystal oscillator, and HFXTAL is
a 16 MHz external crystal oscillator.
The PMU provides control of the ADuCM350 power modes
and allows the ARM Cortex-M3 to control the clocks and The ADuCM350 supports either 8 MHz or 16 MHz resonant
power gating to reduce the dynamic power and hibernate circuits. The HF RC oscillator has an accuracy of ±5%. A low
power. jitter clock source is used for accurate AFE measurements.
There are four power modes available; each mode provides an The USB has a frequency accuracy requirement of ±200 ppm.
additional low power benefit with a corresponding reduction in The USB control logic must be clocked at >30 MHz. A
functionality. USBPHYCLK for clocking the USB PHY is also available and
must use a 60 MHz clock.
• Active mode—all peripherals can be enabled. Active power is
managed by optimized clock management. The low frequency clocking is optimized for ultralow power
• Core sleep—the core is clock gated but the remainder of the applications. The RTC requires that the 32.768 kHz XTAL be
system is active. No instructions can be executed in this activated to run for 12 hours off a fully charged 0.08 F super
mode, but DMA transfers can continue between peripherals capacitor.
and memory. Real Time Clock
• System sleep—in system sleep, most peripherals are clock The RTC contains a low power crystal oscillation circuit that
gated and are no longer user programmable; the interrupt operates in conjunction with a 32,768 Hz external crystal. It
controller remains active and the NVIC processes wake-up achieves 25 ppm performance in keeping time at 25°C when
events for a limited number of sources. used with a 10 ppm crystal class load capacitors.
• Hibernate mode—some limited state retention, limited
Features of the RTC include
number of wake-up interrupts, and the RTC is active.
• A 32-bit count register of the time in seconds from a known
The device also has a backup mode that supplies minimum
reference point.
power to the RTC and associated circuitry from a super
• A prescaler that divides down the 32,768 Hz crystal input to
capacitor. The RTC can run for >12 hours with an 80 mF
1 Hz to advance the seconds count.
capacitor.
• RTC alarm and interrupt flags.
Power Management • Digital trim capability to allow a positive or negative
The ADuCM350 has an integrated power management system adjustment to the RTC count at fixed intervals.
to optimize performance and extend battery life of the device.
DISPLAY OPTIONS
See the UG-587 hardware reference manual for additional
details. LCD Segment Display Driver and Controller
The power management system consists of The ADuCM350 contains an on-chip LCD controller capable of
directly driving an LCD panel. For LCD functionality, 36 pins
• Integrated analog and digital LDOs regulated to 1.8 V. are available on the device.
• Hibernate mode from 2.0 V to 3.6 V.
The LCD controller supports driving up to 128 segments, as
• High performance AFE measurement from 2.5 V to 3.6 V.
well as selectable multiplex option. The static option consists of
• Integrated power switches for low standby current in one backplane × 32 frontplanes and the 4× mux option consists
hibernate mode. of four backplanes × 32 frontplanes. The LCD controller also
• Integrated smart diode trickle charger for a super capacitor supports LCD waveform voltages that are generated using
for use in backup mode. internal charge pump circuitry and support levels from 2.4 V up
• Dedicated VDDIO voltage via nine GPIO pins for peripheral to 3.6 V LCDs, programmable frame rates, interrupt generation
interoperability. at the frame boundary (for updating LCD data), and the LCD
• Dedicated regulator for USB transceiver and bus supplied frame clock (generated by using the on-board 32 kHz crystal).
from the VUSB pin.
LCD Display Controller Options
• Dedicated supervisory circuits for fail safe operation,
including power supply monitors of DVDD during flash The LCD controller also has the ability to drive external LCD
read/writes, PSM of VCCM to monitor supply during AFE display modules. It has 25 pins for the display interface, which
measurements, and PSM on the LFXTAL block to monitor support data transfers of up to 16 bits.
the clock source for RTC. Display controller supports Type A, Type B, and Type C of the
Clocking MIPI DBI Specification Version 2.0. Specifically, both Fixed-E
mode and Clocked-E mode options of the Type A interface are
Two on-chip oscillators and driver circuitry for two external
supported, as well as all bus width options (8-/9-/16-bit data) for
crystals are available on the ADuCM350: LFOSC is a 32 kHz
ADuCM350 Data Sheet
Type A and Type B, and 9-bit (Option 1) and 8-bit (Option 3) A timer allows for programmable tone durations from 4 ms to
serial interfaces for Type C. 1.02 sec in 4 ms increments. Single-tone (pulse) and multitone
By using the display controller, the depth on various interfaces (sequence) modes provide versatile playback options.
is as follows: In sequence mode, the beeper can be programmed to play any
number of tone pairs from 1 to 254 (2 to 508 tones) or be
• 8-bit interface is 8, 12, or 16 bits per pixel (not 18 or 24).
programmed to play forever (until stopped by the user).
• 9-bit interface is 18 bits per pixel (not 8, 12, 16, or 24).
Interrupts are available to indicate the start or end of any beep,
• 16-bit interface is 8, 12, or 16 bits per pixel (not 18 or 24).
the end of a sequence, or that the sequence is nearing
AUDIO OPTIONS completion.
The ADuCM350 has an integrated audio driver for beeper and I2S
an integrated I2S port. The device supports I2S. The purpose of the I2S port is to
Beeper provide audio data to an amplifier, which drives a small
speaker. The I2S features available on the ADuCM350 include
The beeper driver module in the ADuCM350 generates a
the following:
differential square wave of programmable frequency. It drives
an external piezoelectric sound component whose two • Data samples of up to 24 bits.
terminals connect to the differential square wave output. • Frame clocks from 8 kHz to 192 kHz.
The beeper driver consists of a module that can deliver • Master/slave mode.
frequencies from 8 kHz to ~0.25 kHz. It operates on a fixed • 8-deep Tx FIFOs.
independent 32 kHz (32,768 Hz) clock source that is unaffected • DMA mode with address autoincrement.
by changes in system clocks. • Interrupt mode.
• Downsampling transfers.
Data Sheet ADuCM350
DEVELOPMENT SUPPORT
DOCUMENTATION development kit (SDK) for the ADuCM350 uses the IAR
The ADuCM350 hardware reference manual details the Embedded Workbench for ARM as its development
functionality of each block on the ADuCM350. It includes environment.
power management, clocking, memories, peripherals, and the The SDK consists of full working AFE examples of power-up
AFE. sequences, calibration sequences, and measurement routines.
These AFE example routines are documented in the UG-587
HARDWARE
hardware reference manual with supporting timing diagrams.
The EVAL-ADuCM350EBZ evaluation kit is available to
The SDK also includes operating system (OS) aware drivers and
prototype a user’s sensor configuration with the ADuCM350. A
example code for all the peripherals on the device, including
selection of daughter cards are available to interrogate peripheral
SPI, I2C, CapTouch, PDI, and so forth.
performance, including CapTouch, PDI, LCD segment, beeper,
and I2S. Also available in the support package is the ADuCM350 AFE
development GUI that operates from the National Instruments
SOFTWARE
LabVIEW® environment. This GUI allows the user to rapidly
The EVAL-ADuCM350EBZ includes a complete development prototype different sensors with the ADuCM350 AFE to evaluate
and debug environment for the ADuCM350. The software its high precision performance.
ADuCM350 Data Sheet
PACKAGING AND ORDERING INFORMATION

OUTLINE DIMENSIONS
8.10
8.00 SQ A1 BALL
A1 BALL 7.90 CORNER
14 12 10 8 6 4 2
CORNER 15 13 11 9 7 5 3 1
A
B
C
D
E
7.00 F
BSC SQ G
H
J
0.50 K
L
M
N
P
R
TOP VIEW 0.50 REF BOTTOM VIEW
DETAIL A
*1.35
1.23 1.08
1.14 DETAIL A 1.01
0.94
0.22 NOM
0.17 MIN
0.35 COPLANARITY
SEATING
PLANE 0.30 0.08
0.25
BALL DIAMETER
04-02-2013-A
*COMPLIANT TO JEDEC STANDARDS MO-275-CCCE-1 WITH
EXCEPTION TO PACKAGE HEIGHT.
Figure 45. 120-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-120-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADuCM350BBCZ −40°C to +85°C 120-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-120-3
ADuCM350BBCZ-RL −40°C to +85°C 120-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-120-3
1
Z = RoHS Compliant Part.
Data Sheet ADuCM350
NOTES
ADuCM350 Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners. www.analog.com/ADuCM350
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16-Bit Precision, Low Power Meter On A

Chip with Cortex-M3 and Connectivity

FUNCTIONAL BLOCK DIAGRAM

UART SPI0 SPI1 I 2C TMR0 TMR1 PMU BEEP

ABP‐0 AHB ‐APB ABP‐1

I2S LCD GPIO CRC TMR2 WDT RTC MISC

Rev. A Document Feedback

High Precision Internal Reference Specifications

SWITCH MATRIX SPECIFICATIONS

TRANSIMPEDANCE AMPLIFIER SPECIFICATIONS

TEMPERATURE SENSOR SPECIFICATIONS

DFT-BASED IMPEDANCE MEASUREMENTS

Low Power LDO

Digital Inputs/Outputs: Specified

Table 13. Digital Inputs and Outputs1 Specifications

Digital Inputs/Outputs: Functional

Table 14. Digital Inputs/Outputs: Functional Specifications

Universal Serial Bus DC Specifications

Universal Serial Bus AC Specifications

Table 17. Universal Serial Bus AC Specifications

Watchdog, Wake-Up, and General-Purpose Timers

Power Supply Monitoring

Table 27. I2C Timing in Fast Mode (400 kHz)

Table 28. I2C Timing in Standard Mode (100 kHz)

Table 29. I2S Timing: Master Transmitter

Table 30. I2S Timing: Slave Receiver

*tRC IS ONLY RELEVANT FOR TRANSMITTERS IN SLAVE MODE.

Figure 3. I2S-Compatible Interface Transmitter Timing

tLC ≥ 0.35T tHC ≥ 0.35T

tSR ≥ 0.2T tHTR ≥ 0

Figure 4. I2S-Compatible Interface Receiver Timing

Table 31. SPI Master Mode Timing1

MOSI MSB BIT 6 TO BIT 1 LSB

MISO MSB IN BIT 6 TO BIT 1 LSB IN

1 SCLK CYCLE 1 SCLK CYCLE

MOSI MSB BIT 6 TO BIT 1 LSB

MISO MSB IN BIT 6 TO BIT 1 LSB IN

Figure 6. SPI Master Mode Timing (Phase Mode = 0)

Table 32. SPI Slave Mode Timing

MISO MSB BIT 6 TO BIT 1 LSB

MOSI MSB IN BIT 6 TO BIT 1 LSB IN

Figure 7. SPI Slave Mode Timing (Phase Mode = 1)

MISO MSB BIT 6 TO BIT 1 LSB

MOSI MSB IN BIT 6 TO BIT 1 LSB IN

Figure 8. SPI Slave Mode Timing (Phase Mode = 0)

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

C HF_XTAL2 V_LCD_13 P2.7/S20/

D HF_XTAL1 VLCDVDD P2.13/S26 P2.6/

E VUSB VLCD FLY1 P3.11/S32 P2.14/S27

TMS- TCK- P3.5/

P3.12/ P3.13/ P0.3/ P0.0/

P4.0/ P4.1/ P0.5/ P0.2/

N LF_XTAL2 BOOT TRACE2 TRACE1

P0.13/ P0.14/ VCCM_ AGND TRACE3

Table 35. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

VREF VOLTAGE (V)

REF_EXCITE VOLTAGE (V)

–0.010 –0.008 –0.006 –0.004 –0.002 0 –0.0003 –0.0002 –0.0001 0