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Eitf35: Introduction To Questasim: Steffen Malkowsky Steffen - Malkowsky@Eit - Lth.Se

The document introduces QuestaSim, a simulation tool for verifying RTL designs. It discusses the typical ASIC/FPGA design flow involving RTL, gate-level, and post-layout simulations of increasing accuracy but lower speed. It then provides an overview of QuestaSim's key features, including its Tcl shell, library management, project creation, compilation, simulation, waveform viewing, and error/warning reporting capabilities.

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Eswaran Samy
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119 views11 pages

Eitf35: Introduction To Questasim: Steffen Malkowsky Steffen - Malkowsky@Eit - Lth.Se

The document introduces QuestaSim, a simulation tool for verifying RTL designs. It discusses the typical ASIC/FPGA design flow involving RTL, gate-level, and post-layout simulations of increasing accuracy but lower speed. It then provides an overview of QuestaSim's key features, including its Tcl shell, library management, project creation, compilation, simulation, waveform viewing, and error/warning reporting capabilities.

Uploaded by

Eswaran Samy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EITF35:

Introduction to QuestaSim

Steffen Malkowsky
[email protected]

Lund University / EITF35/ Steffen Malkowsky 2013

Typical (ASIC/FPGA) Design Flow


RTL simulation: Proves
functionality without timing
information.
GL simulation: Verifies netlist
with timing information (slow)
PL simulation: Verification
with parasitics (even slower)

Lund University / EITF35/ Steffen Malkowsky 2013

Questasim overview

Shell (tcl) to write and


execute commands from
the prompt

Libraries that contain


compiled components

Lund University / EITF35/ Steffen Malkowsky 2013

Create new project


Project name

Library used for simulation

Lund University / EITF35/ Steffen Malkowsky 2013

Add VHDL files

Select files required for simulation

Lund University / EITF35/ Steffen Malkowsky 2013

Compiling the project


Compile Compile Order

Auto Generate
A green check shows for each
file if the compilation was
successful

Lund University / EITF35/ Steffen Malkowsky 2013

Simulation
Right-click on your design
(testbench) and select simulate

Signals on top level

Lund University / EITF35/ Steffen Malkowsky 2013

Adding signals to waveform

Hierarchical design tree

Set run time, start


simulation run or restart
simulation after recompilation

Mark signals to be shown in waveform and click


Add to Wave Selected Signals

Lund University / EITF35/ Steffen Malkowsky 2013

Waveform viewer

Different options for zooming

Lund University / EITF35/ Steffen Malkowsky 2013

Different options to jump with


the cursor to falling or rising
edges

Waveform viewer (cont.)


To change representation style of a
bus, right-click on the signal, then
Radix

The signal is now shown in an unsigned


representation instead of binary
Lund University / EITF35/ Steffen Malkowsky 2013

Errors/warnings in the designs


Warning for the design/file

Error in the design/file

A window stating the errors/warnings pops-up

Double-click on the message in the


transcript window to get the error/warning
messages

Lund University / EITF35/ Steffen Malkowsky 2013

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