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    Chapter 6 Digital Circuit 6-6: Department of Mechanical Engineering

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    Goitom Teclai
    1) TTL and CMOS ICs use different output circuit configurations - TTL uses a totem pole configuration while CMOS uses both P-channel and N-channel MOSFETs. 2) N-MOS and CMOS logic gates like inverters, AND, and OR gates are constructed using enhancement mode MOSFETs. 3) When interfacing TTL and CMOS, it is important to ensure voltage levels are compatible since TTL sinks/sources current at output while CMOS input draws nearly no current.

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    Chapter 6 Digital Circuit 6-6: Department of Mechanical Engineering

    Uploaded by

    Goitom Teclai
    29 views33 pages
    1) TTL and CMOS ICs use different output circuit configurations - TTL uses a totem pole configuration while CMOS uses both P-channel and N-channel MOSFETs. 2) N-MOS and CMOS logic gates like inverters, AND, and OR gates are constructed using enhancement mode MOSFETs. 3) When interfacing TTL and CMOS, it is important to ensure voltage levels are compatible since TTL sinks/sources current at output while CMOS input draws nearly no current.

    Original Description:

    Introduction to integrated Circuits.

    Original Title

    Integrated Circuits Chapter6-6

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    1) TTL and CMOS ICs use different output circuit configurations - TTL uses a totem pole configuration while CMOS uses both P-channel and N-channel MOSFETs. 2) N-MOS and CMOS logic gates like inverters, AND, and OR gates are constructed using enhancement mode MOSFETs. 3) When interfacing TTL and CMOS, it is important to ensure voltage levels are compatible since TTL sinks/sources current at output while CMOS input draws nearly no current.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    29 views33 pages

    Chapter 6 Digital Circuit 6-6: Department of Mechanical Engineering

    Uploaded by

    Goitom Teclai
    1) TTL and CMOS ICs use different output circuit configurations - TTL uses a totem pole configuration while CMOS uses both P-channel and N-channel MOSFETs. 2) N-MOS and CMOS logic gates like inverters, AND, and OR gates are constructed using enhancement mode MOSFETs. 3) When interfacing TTL and CMOS, it is important to ensure voltage levels are compatible since TTL sinks/sources current at output while CMOS input draws nearly no current.

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    © All Rights Reserved
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    of 33

    ME2082

    Chapter 6 Digital Circuit 6-6

    Department of Mechanical Engineering

    TTL and CMOS ICs


    ,

    TTL and CMOS output circuit


    totem pole configuration

    When the upper transistor is


    forward biased and the bottom
    When input is high, the ptransistor is off, the output is
    type transistor (top) is off,
    high. The resistor, transistor,
    n-type is on. So the
    and diode drop the actual
    output is pulled low. The
    output voltage to a value
    device sinks current
    typically about 3.4 V. When the
    lower transistor is forward
    When input is low, the nbiased and the top transistor is
    type transistor (bottom) is
    off, the output is low.
    off, p-type is on. So the
    The TTL device sources current
    output is pulled high. The
    when there is a high output and
    device sources current.
    sinks current when the output is
    low.
    TTL device dissipates power continuously
    regardless of whether the output is high or low. Department of Mechanical Engineering

    The MOSFET and MOSFET switching states

    There are presently two general types of MOSFETs: depletion and enhancement.
    MOS digital ICs use enhancement MOSFETs exclusively
    The direction of the arrow indicates either P- or N-channel. The symbols show a broken
    line between the source and drain to indicate that there is normally no conducting
    channel between these electrodes.
    Symbol also shows a separation between the gate and the other terminals to indicate the
    very high resistance (typically around 1012 ) between the gate and channel.
    Department of Mechanical Engineering

    The MOSFET and MOSFET switching states

    Department of Mechanical Engineering

    N-MOS Inverter

    Department of Mechanical Engineering

    N-MOS NAND Gate

    Department of Mechanical Engineering

    N-MOS NOR Gate

    Department of Mechanical Engineering

    CMOS Logic
    The complementary MOS (CMOS) logic family uses both P- and N- channel
    MOSFETs in the same circuit to realize several advantages over the P-MOS and NMOS families. The CMOS is faster and consumes even less power than the other MOS
    families.

    Department of Mechanical Engineering

    CMOS Logic

    Department of Mechanical Engineering

    CMOS Logic

    Department of Mechanical Engineering

    TTL and CMOS ICs


    Logic low (L) or (0)

    Undefined

    Logic high (H) or (1)

    Department of Mechanical Engineering

    TTL and CMOS ICs

    When interfacing digital devices, in addition to


    understanding the voltage levels, it is also important to know
    the input and output current characteristics of the devices.
    Important characteristics are the amount of current a device
    can source (produce) when the output is high and the amount
    of current the device can sink (draw) when the output
    voltage is low.
    IOL low-level output current for sinking capability
    when the output voltage is low
    IOH high-level output current for sourcing capability
    when the output voltage is high
    Department of Mechanical Engineering

    Advantages of CMOS devices


    o

    When an output is unloaded or connected to other CMOS devices,


    CMOS requires power only when an output switches its logic state.
    Therefore, CMOS is useful in battery-operated applications where
    power is limited
    The wide power supply range of CMOS (3-18 V) provides more
    design flexibility and allows use of less tightly regulated power
    supplies.

    Disadvantages of CMOS:
    o

    CMOS is sensitive to static discharge ; the devices are easily


    damaged
    CMOS requires negligible input current, but its output current is also
    small compared to TTL. This limits the ability of CMOS to drive
    large TTL fan-out or other high current devices.
    Department of Mechanical Engineering

    Manufacturer IC data sheet

    Labeling in TTL: AAxxyzz,


    o AA is the manufacturer's prefix (SN for TI and others; DM for
    o
    o

    National Semiconductor);
    xx distinuishes between military (xx = 54) and industrial (xx = 74) quality;
    y distinguishes between different internal designs
    no letter: standard TTL;
    L: low-power dissipation;
    H: high-power dissipation;
    S: Schottky type; Schottky devices have faster switching speeds and
    require less power.
    AS: advanced Schottky,
    LS: low-power Schottky;
    ALS: advanced low-power Schottky); and
    zz is the device number in the data book.
    Department of Mechanical Engineering

    Manufacturer IC data sheet

    Labeling in TTL: AAxxyzz,


    o AA is the manufacturer's prefix (SN for TI and others; DM for
    o
    o

    National Semiconductor);
    xx distinuishes between military (xx = 54) and industrial (xx = 74) quality;
    y distinguishes between different internal designs
    no letter: standard TTL;
    L: low-power dissipation;
    H: high-power dissipation;
    S: Schottky type; Schottky devices have faster switching speeds and
    require less power.
    AS: advanced Schottky,
    LS: low-power Schottky;
    ALS: advanced low-power Schottky); and
    zz is the device number in the data book.
    Department of Mechanical Engineering

    Manufacturer IC data sheet

    CMOS devices are available in the 40XXB series and


    the 74CXX series.
    74CXX series is pin compatible with the TTL 74XX
    series. There are also different varieties of the 74CXX
    family that provide different speed and power
    characteristics.
    o 74HCXX (high-speed CMOS),
    o 74ACXX (advanced CMOS), and
    o 74HCTXX and 74ACTXX (high-speed CMOS with
    TTL threshold).

    Department of Mechanical Engineering

    NAND gate internal design and


    QUAD NAND gate IC pin-out

    Department of Mechanical Engineering

    NAND gate internal design and


    its operation

    D2 and D3: E-B junction

    D4: C-B junction

    Department of Mechanical Engineering

    NAND gate internal design and


    its operation
    D1 is needed to
    keep Q3 off in this
    situation

    Department of Mechanical Engineering

    NAND gate internal design and


    its operation

    V=0.7 V at
    point Y

    Low B input acts as a


    sink to ground to this
    current

    Department of Mechanical Engineering

    TTL NOR gate internal design

    Department of Mechanical Engineering

    Current sinking action


    Q4 is the
    current-sinking
    transistor or the
    pull-down
    transistor

    Department of Mechanical Engineering

    Current sourcing action


    Q3 is the currentsourcing transistor
    Or the pull-up transistor

    Department of Mechanical Engineering

    Digital IC output configurations


    totem pole configuration

    Open-collector output

    When the output transistor is


    saturated, Vout is low
    When it is in cutoff, Vout is high
    Department of Mechanical Engineering

    Digital IC output configurations


    Caution! Totem pole outputs should not be tied together

    Department of Mechanical Engineering

    Digital IC output configurations

    Open-collector output

    Devices with open-collector (OC) outputs can


    have their outputs connected together safely
    Department of Mechanical Engineering

    Digital IC output configurations


    Open collector buffer/drivers:
    A buffer, or a driver or a buffer/driver is designed to have a greater
    output current and/or voltage capability than ordinary logic circuit.
    Buffer/driver ICs are available with totem pole outputs and with opencollector outputs

    Department of Mechanical Engineering

    Digital IC output configurations

    Department of Mechanical Engineering

    Digital IC output configurations


    Tristate TTL inverter

    Tristate TTL allows three possible


    output states: HIGH, LOW and
    high impedance (Hi-Z)

    Department of Mechanical Engineering

    Digital IC output configurations

    The Enabled State With E = 1 the circuit operates as a


    normal inverter because the HIGH voltage at E has no
    effect on Ql or D2. In this enabled condition, the output is
    simply the inverse of logic input A.
    The Disabled State (Hi-Z): When E = O the circuit goes
    into its Hi-Z state regardless of the state of logic input A.
    The LOW at E forward-biases the emitter-base junction of
    Ql and shunts the Rl Current away from Q2 so that Q2
    turns off, which turns Q4 off. The LOW at E also forwardbiases diode D2 to shun current away from the base of Q3,
    so that Q3 also turns off.
    Department of Mechanical Engineering

    Interfacing TTL and CMOS devices

    The output of a TTL device sinks current when it is low and sources current when it
    is high. The TTL low sink current (IoJ is the limiting factor when interfacing to multiple TTL inputs. A TTL output can drive up to 10 standard TTL inputs or up to 40
    Low-power Schottky (LS) TTL inputs.
    TTL outputs are easy to interface to CMOS due to the insulating gate input, which
    draws no steady state current. It is necessary only to ensure voltages match when
    connecting TTL outputs to CMOS inputs.

    Department of Mechanical Engineering

    Interfacing TTL and CMOS devices

    When using ICs of one logic family exclusively, you need not be
    concerned with voltage levels and current drives as long as the fan-out is less than
    10 for TTL (CMOS can be higher).
    CMOS is better for general use because it draws no current unless switching, and
    the output swings nearly from ground to the positive supply value. However, at
    high frequency, CMOS can dissipate nearly the power required by an equivalent
    TTL circuit.
    Department of Mechanical Engineering

    TTL Loading and fan-out

    Department of Mechanical Engineering

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