Dspic33fj32mc202 204

dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
2007-2011 Microchip Technology Inc.
DS70283J
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device

applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2007-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-370-8
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70283J-page 2
dsPIC33FJ16MC304
High-Performance, 16-bit Digital Signal Controllers
Operating Range:
Interrupt Controller:
Up to 40 MIPS operation (@ 3.0-3.6V):

- Industrial temperature range (-40C to +85C)
- Extended temperature range (-40C to +125C)
Up to 20 MIPS operation (@ 3.0-3.6V)
- High temperature range (-40C to +150C)
High-Performance DSC CPU:
Digital I/O:
Modified Harvard architecture

C compiler optimized instruction set
16-bit wide data path
24-bit wide instructions
Linear program memory addressing up to 4M
instruction words
Linear data memory addressing up to 64 Kbytes
83 base instructions: mostly 1 word/1 cycle
Two 40-bit accumulators with rounding and
saturation options
Flexible and powerful addressing modes:
- Indirect
- Modulo
- Bit-reversed
Software stack
16 x 16 fractional/integer multiply operations
32/16 and 16/16 divide operations
Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
Up to 16-bit shifts for up to 40-bit data
Timers/Capture/Compare/PWM:
Timer/Counters, up to three 16-bit timers
- Can pair up to make one 32-bit timer
- One timer runs as Real-Time Clock with
external 32.768 kHz oscillator
- Programmable prescaler
Input Capture (up to four channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
Output Compare (up to two channels):
- Single or Dual 16-Bit Compare mode
- 16-bit Glitchless PWM mode
5-cycle latency
Up to 26 available interrupt sources
Up to three external interrupts
Seven programmable priority levels
Four processor exceptions
Peripheral pin Select functionality

Up to 35 programmable digital I/O pins
Wake-up/Interrupt-on-Change for up to 31 pins
Output pins can drive from 3.0V to 3.6V
Up to 5.5V output with open drain configuration on
5V tolerant pins with external pull-up
4 mA sink on all I/O pins
On-Chip Flash and SRAM:

Flash program memory (up to 32 Kbytes)
Data SRAM (2 Kbytes)
Boot and General Security for program Flash
System Management:
Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low jitter PLL
Power-up Timer
Oscillator Start-up Timer/Stabilizer
Watchdog Timer with its own RC oscillator
Fail-Safe Clock Monitor
Reset by multiple sources
Power Management:
On-chip 2.5V voltage regulator
Switch between clock sources in real time
Idle, Sleep and Doze modes with fast wake-up
DS70283J-page 3
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

Motor Control Peripherals:
CMOS Flash Technology:
6-channel 16-bit Motor Control PWM:

- Three duty cycle generators
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- One Fault input
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
2-channel 16-bit Motor Control PWM:
- One duty cycle generator
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- One Fault input
- Trigger for ADC conversions
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
Quadrature Encoder Interface module:
- Phase A, Phase B and index pulse input
- 16-bit up/down position counter
- Count direction status
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/underflow
Low-power, high-speed Flash technology

Fully static design
3.3V (10%) operating voltage
Industrial and Extended temperature
Low power consumption
Communication Modules:
4-wire SPI:
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
I2C:
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
UART:
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
Packaging:
28-pin SPDIP/SOIC/SSOP/QFN-S
44-pin QFN/TQFP
Note:
See Table 1 for the exact peripheral

features per device.
Analog-to-Digital Converters (ADCs):

10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:
- Two and four simultaneous samples (10-bit ADC)
- Up to nine input channels with auto-scanning
- Conversion start can be manual or
synchronized with one of four trigger sources
- Conversion possible in Sleep mode
- 2 LSb max integral nonlinearity
- 1 LSb max differential nonlinearity
DS70283J-page 4

dsPIC33FJ16MC304 Product Families
The device names, pin counts, memory sizes and
peripheral availability of each device are listed below.
The following pages show their pinout diagrams.
Device
Pins
RAM (Kbyte)
Remappable Pins
16-bit Timer
Input Capture
Output Compare
Standard PWM
Motor Control PWM
Quadrature Encoder
Interface
UART
External Interrupts(3)
SPI
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CONTROLLER FAMILIES

Program Flash Memory (Kbyte)
TABLE 1:
dsPIC33FJ32MC202
28
32
16
3(1)
6ch(2)
2ch(2)
1ADC,
6 ch
21 SPDIP
SOIC
SSOP
QFN-S
dsPIC33FJ32MC204
44
32
26
3(1)
6ch(2)
2ch(2)
1ADC,
9 ch
35
QFN
TQFP
dsPIC33FJ16MC304
44
16
26
3(1)
6ch(2)
2ch(2)
1ADC,
9 ch
35
QFN
TQFP
Note 1:
2:
3:
Packages
I/O Pins
I2C
10-Bit/12-Bit ADC
Remappable Peripherals
Only two out of three timers are remappable.

Only PWM fault inputs are remappable.
Only two out of three interrupts are remappable.
DS70283J-page 5

Pin Diagrams
28-PIN SPDIP, SOIC, SSOP
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
dsPIC33FJ32MC202
MCLR
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1
AN4/RP2(1)/CN6/RB2
AN5/RP3(1)/CN7/RB3
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
SOSCI/RP4(1)/CN1/RB4
SOSCO/T1CK/CN0/RA4
VDD
PGED3/ASDA1/RP5(1)/CN27/RB5
28
27
26
25
24
AVDD
AVSS
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RP14(1)/CN12/RB14
PGEC2/TMS/PWM1L3/RP11(1)/CN15/RB11
PGED2/TDI/PWM1H3/RP10(1)/CN16/RB10
VCAP
VSS
TDO/PWM2L1/SDA1/RP9(1)/CN21/RB9
TCK/PWM2H1/SCL1/RP8(1)/CN22/RB8
INT0/RP7/CN23/RB7
PGEC3/ASCL1/RP6(1)/CN24/RB6
23
22
21
20
19
18
17
16
15
28-Pin QFN-S(2)
AVDD
AVSS
AN1/VREF-/CN3/RA1
AN0/VREF+/CN2/RA0
MCLR
28 27 26 25 24 23 22
PGED1/EMUD1/AN2/C2IN-/RP0(1)/CN4/RB0
PGEC1/EMUC1/AN3/C2IN+/RP1(1)/CN5/RB1
21
20
19
PGEC2/EMUC2/TMS/PWM1L3/RP11(1)/CN15/RB11
AN4/RP2(1)/CN6/RB2
AN5/RP3(1)/CN7/RB3
VSS
dsPIC33FJ32MC202 18
17
VCAP
16
15
VSS
TDO/PWM2L1/SDA1/RP9(1)/CN21/RB9
TCK/PWM2H1/SCL1/RP8(1)/CN22/RB8
SOSCI/RP4/CN1/RB4
PGEC3/EMUC3/ASCL1/RP6(1)/CN24/RB6
INT0/RP7(1)/CN23/RB7
9 10 11 12 13 14
PGED3/EMUD3/ASDA1/RP5(1)/CN27/RB5
SOSCO/T1CK/CN0/RA4
VDD
5
OSC1/CLKI/CN30/RA2 6
OSC2/CLKO/CN29/RA3 7
PGED2/EMUD2/TDI/PWM1H3/RP10(1)/CN16/RB10
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to
be connected to VSS externally.
DS70283J-page 6

Pin Diagrams (Continued)
44-Pin QFN(2)
TMS/RA10
TCK/RA7
AVSS
MCLR
AVDD
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
22 21 20 19 18 17 16 15 14 13 12
AN4/RP2(1)/CN6/RB2
AN5/RP3(1)/CN7/RB3
AN6/RP16(1)/CN8/RC0
(1)
AN7/RP17 /CN9/RC1
11
24
10
25
PGEC2/EMUC2/PWM1L3/RP11(1)/CN15/RB11
26
PGED2/EMUD2/PWM1H3/RP10(1)/CN16/RB10
VCAP
23
AN8/RP18(1)/CN10/RC2
27
VDD
28
VSS
VSS
29
RP25/CN19/RC9
OSC1/CLKI/CN30/RA2
30
RP24/CN20/RC8
OSC2/CLKO/CN29/RA3
31
PWM2L1/RP23(1)/CN17/RC7
TDO/RA8
32
PWM2H1/RP22(1)/CN18/RC6
33
SDA1/RP9(1)/CN21/RB9
dsPIC33FJ32MC204
dsPIC33FJ16MC304
SCL1/RP8(1)/CN22/RB8
INT0/RP7/CN23/RB7
VDD
VSS
RP21(1)/CN26/RC5
RP20(1)/CN25/RC4
RP19(1)/CN28/RC3
TDI/RA9
SOSCO/T1CK/CN0/RA4
34 35 36 37 38 39 40 41 42 43 44
peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to
be connected to VSS externally.
DS70283J-page 7

Pin Diagrams (Continued)
44-Pin TQFP
AN1/VREF-/CN3/RA1
AN0/VREF+/CN2/RA0
MCLR
AVDD
AVSS
TCK/RA7
TMS/RA10
12
13
14
15
16
17
18
19
20
21
22
dsPIC33FJ32MC204
dsPIC33FJ16MC304
11
10
9
8
7
6
5
4
3
2
1
PGEC2/EMUC2/PWM1L3/RP11(1)/CN15/RB11
PGED2/EMUD2/PWM1H3/RP10(1)/CN16/RB10
VCAP
VSS
RP25(1)/CN19/RC9
RP24(1)/CN20/RC8
PWM2L1/RP23(1)/CN17/RC7
PWM2H1/RP22(1)/CN18/RC6
SDA1/RP9(1)/CN21/RB9
34
35
36
37
38
39
40
41
42
43
44
23
24
25
26
27
28
29
30
31
32
33
SOSCO/T1CK/CN0/RA4
TDI/RA9
RP19/(1)CN28/RC3
RP20(1)/CN25/RC4
RP21(1)/CN26/RC5
VSS
VDD
INT0/RP7(1)/CN23/RB7
SCL1/RP8(1)/CN22/RB8
AN4/RP2(1)/CN6/RB2
AN5/RP3(1)/CN7/RB3
AN6/RP16(1)/CN8/RC0
AN7/RP17(1)/CN9/RC1
AN8/RP18(1)/CN10/RC2
VDD
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
TDO/RA8
peripherals.
DS70283J-page 8

Table of Contents
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Product Families.................................................................................................. 5
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 17
3.0 CPU............................................................................................................................................................................................ 21
4.0 Memory Organization ................................................................................................................................................................. 33
5.0 Flash Program Memory.............................................................................................................................................................. 59
6.0 Resets ....................................................................................................................................................................................... 65
7.0 Interrupt Controller ..................................................................................................................................................................... 73
8.0 Oscillator Configuration ............................................................................................................................................................ 105
9.0 Power-Saving Features............................................................................................................................................................ 115
10.0 I/O Ports ................................................................................................................................................................................... 121
11.0 Timer1 ...................................................................................................................................................................................... 147
12.0 Timer2/3 feature ...................................................................................................................................................................... 149
13.0 Input Capture............................................................................................................................................................................ 155
14.0 Output Compare....................................................................................................................................................................... 157
15.0 Motor Control PWM Module ..................................................................................................................................................... 161
16.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 175
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 181
18.0 Inter-Integrated Circuit (I2C).............................................................................................................................................. 187
19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 195
20.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 201
21.0 Special Features ...................................................................................................................................................................... 213
22.0 Instruction Set Summary .......................................................................................................................................................... 221
23.0 Development Support............................................................................................................................................................... 229
24.0 Electrical Characteristics .......................................................................................................................................................... 233
25.0 High Temperature Electrical Characteristics ............................................................................................................................ 281
26.0 Packaging Information.............................................................................................................................................................. 291
Appendix A: Revision History............................................................................................................................................................. 305
Index ................................................................................................................................................................................................. 317
The Microchip Web Site ..................................................................................................................................................................... 321
Customer Change Notification Service .............................................................................................................................................. 321
Customer Support .............................................................................................................................................................................. 321
Reader Response .............................................................................................................................................................................. 322
Product Identification System ............................................................................................................................................................ 323
DS70283J-page 9

TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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DS70283J-page 10

1.0
DEVICE OVERVIEW
Note 1: This data sheet summarizes the features

of the dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 devices. It is not
intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the
dsPIC33F/PIC24H Family Reference
Manual. Please see the Microchip web
site (www.microchip.com) for the latest
Manual sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 Memory Organization in
this data sheet for device-specific register
and bit information.
This document contains device-specific information for
the following Digital Signal Controller (DSC) devices:
dsPIC33FJ32MC202
dsPIC33FJ32MC204
dsPIC33FJ16MC304
The dsPIC33F devices contain extensive Digital Signal
Processor (DSP) functionality with a high performance
16-bit microcontroller (MCU) architecture.
Figure 1-1 shows a general block diagram of the core
and
peripheral
modules
in
the
family of devices. Table 1-1 lists the functions of the
various pins shown in the pinout diagrams.
DS70283J-page 11

FIGURE 1-1:
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 BLOCK DIAGRAM
PSV and Table

Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
PORTA
16
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
23
PORTB
16
23
16
16
PORTC
Address Generator Units
Address Latch
Program Memory
Remappable
Pins
EA MUX
Data Latch
ROM Latch
24
Instruction Reg
Control Signals
to Various Blocks
Timing
Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
VCAP
Divide Support
16 x 16
W Register Array
16
Oscillator
Start-up Timer
Power-on
Reset
16-bit ALU
Watchdog
Timer
16
Brown-out
Reset
MCLR
UART1
IC1,2,7,8
Note:
16
DSP Engine
Power-up
Timer
VDD, VSS
Timers
1-3
Literal Data
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
16
16
SPI1
ADC1
OC/
PWM1-2
PWM
2 Ch
CNx
I2C1
QEI
PWM
6 Ch
Not all pins or features are implemented on all device pinout configurations. See Pin Diagrams for the specific pins
and features present on each device.
DS70283J-page 12

TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS

Pin
Type
Buffer
Type
PPS
Description
AN0-AN8
Analog
No
Analog input channels.
CLKI
CLKO
I
O
ST/CMOS
No
No
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1
ST/CMOS
No
OSC2
I/O
No
Oscillator crystal input. ST buffer when configured in RC mode; CMOS

otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
SOSCI
SOSCO
I
O
ST/CMOS
No
No
32.768 kHz low-power oscillator crystal input; CMOS otherwise.

32.768 kHz low-power oscillator crystal output.
CN0-CN30
ST
No
Change notification inputs.

Can be software programmed for internal weak pull-ups on all inputs.
IC1-IC2
IC7-IC8
I
I
ST
ST
Yes
Yes
Capture inputs 1/2.

Capture inputs 7/8.
OCFA
OC1-OC2
I
O
ST
Yes
Yes
Compare Fault A input (for Compare Channels 1 and 2).

Compare outputs 1 through 2.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No
Yes
Yes
External interrupt 0.
RA0-RA4
RA7-RA10
I/O
ST
No
No
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
No
PORTB is a bidirectional I/O port.
RC0-RC9
I/O
ST
No
PORTC is a bidirectional I/O port.
T1CK
T2CK
T3CK
I
I
I
ST
ST
ST
No
Yes
Yes
Timer1 external clock input.

U1CTS
U1RTS
U1RX
U1TX
I
O
I
O
ST
ST
Yes
Yes
Yes
Yes
UART1 clear to send.

UART1 ready to send.
UART1 receive.
UART1 transmit.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI1.

SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C1.

Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
No
No
No
No
JTAG Test mode select pin.

JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
Legend: CMOS = CMOS compatible input or output;

ST = Schmitt Trigger input with CMOS levels;
PPS = Peripheral Pin Select
Analog = Analog input;

O = Output;
P = Power
I = Input
DS70283J-page 13

TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin
Type
Buffer
Type
PPS
INDX
QEA
I
I
ST
ST
Yes
Yes
QEB
ST
Yes
UPDN
CMOS
Yes
Quadrature Encoder Index Pulse input.

Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
FLTA1
PWM1L1
PWM1H1
PWM1L2
PWM1H2
PWM1L3
PWM1H3
FLTA2
PWM2L1
PWM2H1
I
O
O
O
O
O
O
I
O
O
ST
ST
Yes
No
No
No
No
No
No
Yes
No
No
PWM1 Fault A input.

PWM1 Low output 1.
PWM1 High output 1.
PWM1 Low output 2.
PWM1 High output 2.
PWM1 Low output 3.
PWM1 High output 3.
PWM2 Fault A input.
PWM2 Low output 1.
PWM2 High output 1.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for programming/debugging communication channel 1.

Clock input pin for programming/debugging communication channel 1.
MCLR
I/P
ST
No
Master Clear (Reset) input. This pin is an active-low Reset to the device.
Pin Name
Description
AVDD
No
Positive supply for analog modules. This pin must be connected at all times.
AVSS
No
Ground reference for analog modules.
VDD
No
Positive supply for peripheral logic and I/O pins.
VCAP
No
CPU logic filter capacitor connection.
VSS
No
Ground reference for logic and I/O pins.
VREF+
Analog
No
Analog voltage reference (high) input.
VREF-
Analog
No
Analog voltage reference (low) input.
Legend: CMOS = CMOS compatible input or output;

ST = Schmitt Trigger input with CMOS levels;
PPS = Peripheral Pin Select
DS70283J-page 14
Analog = Analog input;

O = Output;
P = Power
I = Input

1.1
Referenced Sources
This device data sheet is based on the following

individual chapters of the dsPIC33F/PIC24H Family
Reference Manual. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of
the dsPIC33FJ32MC204 product page of
the
Microchip
web
site
(www.microchip.com) or select a family
reference manual section from the
following list.
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
Section 1. Introduction (DS70197)

Section 2. CPU (DS70204)
Section 3. Data Memory (DS70202)
Section 4. Program Memory (DS70202)
Section 5. Flash Programming (DS70191)
Section 7. Oscillator (DS70186)
Section 8. Reset (DS70192)
Section 9. Watchdog Timer and Power-Saving Modes (DS70196)
Section 10. I/O Ports (DS70193)
Section 11. Timers (DS70205)
Section 12. Input Capture (DS70198)
Section 13. Output Compare (DS70209)
Section 14. Motor Control PWM (DS70187)
Section 15. Quadrature Encoder Interface (QEI) (DS70208)
Section 16. Analog-to-Digital Converter (ADC) (DS70183)
Section 17. UART (DS70188)
Section 18. Serial Peripheral Interface (SPI) (DS70206)
Section 19. Inter-Integrated Circuit (I2C) (DS70195)
Section 23. CodeGuard Security (DS70199)
Section 25. Device Configuration (DS70194)
Section 32. Interrupts (Part III) (DS70214)
DS70283J-page 15

NOTES:
DS70283J-page 16

2.0
GUIDELINES FOR GETTING

STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS

dsPIC33FJ16MC304 family of devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
Manual, which is available from the
Microchip web site (www.microchip.com).
2.1
Basic Connection Requirements
Getting started with the dsPIC33FJ32MC202/204 and

dsPIC33FJ16MC304 family of 16-bit Digital Signal
Controllers (DSCs) requires attention to a minimal set
of device pin connections before proceeding with
development. The following is a list of pin names, which
must always be connected:
All VDD and VSS pins
(see Section 2.2 Decoupling Capacitors)
All AVDD and AVSS pins (even if the ADC module is
not used)
(see Section 2.2 Decoupling Capacitors)
VCAP
(see Section 2.3 CPU Logic Filter Capacitor
Connection (VCAP))
MCLR pin
(see Section 2.4 Master Clear (MCLR) Pin)
PGECx/PGEDx pins used for In-Circuit Serial
Programming (ICSP) and debugging purposes
(see Section 2.5 ICSP Pins)
OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 External Oscillator Pins)
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
Value and type of capacitor: Recommendation
of 0.1 F (100 nF), 10-20V. This capacitor should
be a low-ESR and have a resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 F in parallel with 0.001 F.
Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
Additionally, the following pins may be required:

VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be

connected independent of the ADC
voltage reference source.
DS70283J-page 17

FIGURE 2-1:
VDD
RECOMMENDED
MINIMUM CONNECTION
0.1 F
Ceramic
R
R1
MCLR
C
dsPIC33F
VSS
10
2.2.1
VDD
0.1 F
Ceramic
VSS
VDD
AVSS
VDD
AVDD
0.1 F
Ceramic
VSS
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device

functions:
Device Reset
Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
VSS
VCAP
VDD
10 F
2.4
0.1 F
Ceramic
0.1 F
Ceramic
TANK CAPACITORS
For example, as shown in Figure 2-2, it is

recommended that capacitor C is isolated from the
MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device, and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 F to 47 F.
2.3
CPU Logic Filter Capacitor

Connection (VCAP)
A low-ESR (<5 Ohms) capacitor is required on the

VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD, and must have a capacitor between
4.7 F and 10 F, 16V connected to ground. The type
can be ceramic or tantalum. Refer to Section 24.0
Electrical
Characteristics
for
additional
information.
EXAMPLE OF MCLR PIN

CONNECTIONS
VDD
R
R1
MCLR
JP
dsPIC33F
Note 1:
R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2:
R1 470W will limit any current flowing into

MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
The placement of this capacitor should be close to the

VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 21.2
On-Chip Voltage Regulator for details.
DS70283J-page 18

2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit

Serial Programming (ICSP) and debugging purposes.
It is recommended to keep the trace length between
the ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is
recommended, with the value in the range of a few tens
of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
Ensure that the Communication Channel Select (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB ICD 2, MPLAB ICD 3 or MPLAB REAL ICE
in-circuit emulator.
For more information on MPLAB ICD 2, MPLAB ICD 3
or MPLAB REAL ICE in-circuit emulator connection
requirements, refer to the following documents that are
available on the Microchip web site.
MPLAB ICD 2 In-Circuit Debugger Users

Guide DS51331
Using MPLAB ICD 2 (poster) DS51265
MPLAB ICD 2 Design Advisory DS51566
Using MPLAB ICD 3 (poster) DS51765
MPLAB ICD 3 Design Advisory DS51764
MPLAB REAL ICE In-Circuit Emulator Users
Guide DS51616
Using MPLAB REAL ICE In-Circuit Emulator
(poster) DS51749
2.6
External Oscillator Pins
Many DSCs have options for at least two oscillators: a

high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 Oscillator
Configuration for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
13
Guard Ring
14
15
Guard Trace
Secondary
Oscillator
16
17
18
19
20
DS70283J-page 19

2.7
Oscillator Value Conditions on

Device Start-up
If the PLL of the target device is enabled and

configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 8 MHz for start-up with PLL enabled. This means
that if the external oscillator frequency is outside this
range, the application must start-up in FRC mode first.
The default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8
Configuration of Analog and

Digital Pins During ICSP
Operations
If MPLAB ICD 2, MPLAB ICD 3 or MPLAB REAL ICE

in-circuit emulator is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as
digital pins, by setting all bits in the AD1PCFGL register.
The bits in the registers that correspond to the A/D pins
that are initialized by MPLAB ICD 2, MPLAB ICD 3 or
MPLAB REAL ICE in-circuit emulator, must not be
cleared by the user application firmware; otherwise,
communication errors will result between the debugger
and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 2, MPLAB ICD 3 or MPLAB REAL
ICE in-circuit emulator is used as a programmer, the
user application firmware must correctly configure the
AD1PCFGL register. Automatic initialization of this
register is only done during debugger operation.
Failure to correctly configure the register(s) will result in
all A/D pins being recognized as analog input pins,
resulting in the port value being read as a logic 0,
which may affect user application functionality.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and

driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor between VSS
and the unused pins.
DS70283J-page 20

3.0
CPU

information in this data sheet, refer to
Section 2. CPU (DS70204) of the
The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
CPU module has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set, including
significant support for DSP. The CPU has a 24-bit
instruction word with a variable length opcode field. The
Program Counter (PC) is 23 bits wide and addresses up
to 4M x 24 bits of user program memory space. The
actual amount of program memory implemented varies
by device. A single-cycle instruction prefetch mechanism
is used to help maintain throughput and provides
predictable execution. All instructions execute in a single
cycle, with the exception of instructions that change the
program flow, the double-word move (MOV.D) instruction
and the table instructions. Overhead-free program loop
constructs are supported using the DO and REPEAT
instructions, both of which are interruptible at any point.
devices have sixteen, 16-bit working registers in the
programmers model. Each of the working registers can
serve as a data, address or address offset register. The
16th working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
There are two classes of instruction in the
devices: MCU and DSP. These two instruction classes
are seamlessly integrated into a single CPU. The
instruction set includes many addressing modes and is
designed for optimum C compiler efficiency. For most
instructions, the dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 is capable of executing a data (or
program data) memory read, a working register (data)
read, a data memory write and a program (instruction)
memory read per instruction cycle. As a result, three
parameter instructions can be supported, allowing
A + B = C operations to be executed in a single cycle.
3.1
Data Addressing Overview
The data space can be addressed as 32K words or

64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page register (PSVPAG). The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
3.2
DSP Engine Overview
The DSP engine features a high-speed 17-bit by 17-bit

multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal
real-time performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain working
registers to each address space.
A block diagram of the CPU is shown in Figure 3-1, and

the
programmers
model
for
the
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 is
shown in Figure 3-2.
DS70283J-page 21

3.3
Special MCU Features

supports 16/16 and 32/16 divide operations, both
fractional and integer. All divide instructions are iterative
operations. They must be executed within a REPEAT loop,
resulting in a total execution time of 19 instruction cycles.
The divide operation can be interrupted during any of
those 19 cycles without loss of data.

features a 17-bit by 17-bit single-cycle multiplier that is
shared by both the MCU ALU and DSP engine. The
multiplier can perform signed, unsigned and mixed-sign
multiplication. Using a 17-bit by 17-bit multiplier for 16-bit
by 16-bit multiplication not only allows you to perform
mixed-sign multiplication, it also achieves accurate results
for special operations, such as (-1.0) x (-1.0).
FIGURE 3-1:
A 40-bit barrel shifter is used to perform up to a 16-bit

left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU CORE BLOCK DIAGRAM
PSV and Table

Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
8
16
16
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
23
23
PCU PCH PCL

Program Counter
Loop
Stack
Control
Control
Logic
Logic
16
23
16
16
16
16
Address Generator Units
Address Latch
16
Program Memory
EA MUX
Data Latch
ROM Latch
24
24
Instruction
Decode and
Control
Instruction Reg
16
Literal Data
16
Control Signals
to Various Blocks
16
DSP Engine
Divide Support
16
16 x 16
W Register Array
16
16
16-bit ALU
16
To Peripheral Modules
DS70283J-page 22

FIGURE 3-2:
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PROGRAMMERS MODEL

D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
AD39
AD15
AD31
AD0
ACCA
DSP
Accumulators
ACCB
PC22
PC0
Program Counter
0
0
7
TBLPAG
Data Table Page Address
0
PSVPAG
Program Space Visibility Page Address

15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
DC
IPL2 IPL1 IPL0 RA
OV
STATUS Register
SRL
DS70283J-page 23

3.4
CPU Control Registers
REGISTER 3-1:
R-0
OA
SR: CPU STATUS REGISTER

R-0
R/C-0
R/C-0
R-0
R/C-0
R -0
R/W-0
OB
SA(1)
SB(1)
OAB
SAB
DA
DC
bit 15
bit 8
R/W-0(3)
R/W-0(3)
R/W-0(3)
IPL<2:0>(2)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RA
OV
bit 7
bit 0
Legend:
C = Clear only bit
R = Readable bit
U = Unimplemented bit, read as 0
S = Set only bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
OA: Accumulator A Overflow Status bit

1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14
OB: Accumulator B Overflow Status bit

1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13
SA: Accumulator A Saturation Sticky Status bit(1)

1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12
SB: Accumulator B Saturation Sticky Status bit(1)

1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11
OAB: OA || OB Combined Accumulator Overflow Status bit

1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10
SAB: SA || SB Combined Accumulator Sticky Status bit

1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
Note:
This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.
bit 9
DA: DO Loop Active bit

1 = DO loop in progress
0 = DO loop not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit

1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1:
2:
3:
This bit can be read or cleared (not set).

The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
DS70283J-page 24

REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
bit 4
RA: REPEAT Loop Active bit

1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3
N: MCU ALU Negative bit

1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1
Z: MCU ALU Zero bit

1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: MCU ALU Carry/Borrow bit

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
3:
This bit can be read or cleared (not set).

IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
DS70283J-page 25

REGISTER 3-2:
U-0
bit 15
U-0
R/W-0
SATB
Legend:
R = Readable bit
0 = Bit is cleared
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
U-0
R/W-0
US
R/W-0
EDT(1)
R-0
R-0
DL<2:0>
R-0
bit 8
R/W-0
SATA
bit 7
bit 15-13
bit 12
CORCON: CORE CONTROL REGISTER
R/W-1
SATDW
R/W-0
ACCSAT
C = Clear only bit

W = Writable bit
x = Bit is unknown
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
-n = Value at POR
1 = Bit is set
Unimplemented: Read as 0
US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
EDT: Early DO Loop Termination Control bit(1)
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops active
001 = 1 DO loop active

000 = 0 DO loops active
SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
This bit will always read as 0.
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
DS70283J-page 26

3.5
Arithmetic Logic Unit (ALU)

ALU is 16 bits wide and is capable of addition, subtraction,
bit shifts and logic operations. Unless otherwise
mentioned, arithmetic operations are 2s complement in
nature. Depending on the operation, the ALU can affect
the values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the SR
register. The C and DC Status bits operate as Borrow and
Digit Borrow bits, respectively, for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the 16-bit MCU and DSC Programmers Reference Manual (DS70157) for information on the SR
bits affected by each instruction.
CPU incorporates hardware support for both
multiplication and division. This includes a dedicated
hardware multiplier and support hardware for
16-bit-divisor division.
3.5.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the

DSP engine, the ALU supports unsigned, signed or
mixed-sign operation in several MCU multiplication
modes:
16-bit x 16-bit signed

16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
3.5.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operations with the
following data sizes:
1.
2.
3.
4.
32-bit signed/16-bit signed divide

32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
3.6
DSP Engine
The DSP engine consists of a high-speed 17-bit x

17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
is a single-cycle instruction flow architecture; therefore,
concurrent operation of the DSP engine with MCU
instruction flow is not possible. However, some MCU ALU
and DSP engine resources can be used concurrently by
the same instruction (e.g., ED, EDAC).
The DSP engine can also perform inherent accumulator-to-accumulator operations that require no additional
data. These instructions are ADD, SUB and NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
Fractional or integer DSP multiply (IF)

Signed or unsigned DSP multiply (US)
Conventional or convergent rounding (RND)
Automatic saturation on/off for ACCA (SATA)
Automatic saturation on/off for ACCB (SATB)
Automatic saturation on/off for writes to data
memory (SATDW)
Accumulator Saturation mode selection (ACCSAT)
A block diagram of the DSP engine is shown in
Figure 3-3.
TABLE 3-1:
Instruction
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY
MPY.N
MSC
DSP INSTRUCTIONS
SUMMARY
Algebraic
Operation
ACC Write
Back
A=0
Yes
No
No
Yes
No
Yes
No
No
No
Yes
A = (x - y)2
A = A + (x y)2
A = A + (x * y)
A = A + x2
No change in A
A=x y
A = x2
A=xy
A=Axy
The quotient for all divide instructions ends up in W0

and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
DS70283J-page 27

FIGURE 3-3:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-bit Accumulator A
40-bit Accumulator B
Carry/Borrow Out
Saturate
Carry/Borrow In
Adder
Negate
40
40
40
16
X Data Bus
Barrel
Shifter
40
Y Data Bus
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
DS70283J-page 28

3.6.1
MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or

unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed 2s complement value, where the Most
Significant bit (MSb) is defined as a sign bit. The range
of an N-bit 2s complement integer is -2N-1 to 2N-1 - 1.
For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including 0.
For a 32-bit integer, the data range is
-2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
When the multiplier is configured for fractional multiplication, the data is represented as a 2s complement
fraction, where the MSb is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX
format). The range of an N-bit 2s complement fraction
with this implied radix point is -1.0 to (1 - 21-N). For a
16-bit fraction, the Q15 data range is -1.0 (0x8000) to
0.999969482 (0x7FFF) including 0 and has a precision
of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply operation generates a 1.31 product that has a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed,
unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2
DATA ACCUMULATORS AND

ADDER/SUBTRACTER
The data accumulator consists of a 40-bit

adder/subtracter with automatic sign extension logic. It
can select one of two accumulators (A or B) as its
pre-accumulation source and post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
3.6.2.1
Adder/Subtracter, Overflow and

Saturation
The adder/subtracter is a 40-bit adder with an optional

zero input into one side, and either true or complement
data into the other input.
In the case of addition, the Carry/Borrow input is
active-high and the other input is true data (not
complemented).
In the case of subtraction, the Carry/Borrow input
is active-low and the other input is complemented.
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS register:
Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described
previously
and
the
SAT<A:B>
(CORCON<7:6>) and ACCSAT (CORCON<4>) mode
control bits to determine when and to what value to
saturate.
Six STATUS register bits support saturation and
overflow:
OA: ACCA overflowed into guard bits
OB: ACCB overflowed into guard bits
SA: ACCA saturated (bit 31 overflow and
saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB: ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB: Logical OR of OA and OB
SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the
corresponding Overflow Trap Flag Enable bits (OVATE,
OVBTE) in the INTCON1 register are set (refer to
Section 7.0 Interrupt Controller). This allows the
user application to take immediate action, for example,
to correct system gain.
DS70283J-page 29

The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit
saturation) and will be saturated (if saturation is
enabled). When saturation is not enabled, SA and SB
default to bit 39 overflow and thus indicate that a
catastrophic overflow has occurred. If the COVTE bit in
the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is
disabled.
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). Programmers can check one bit in
the STATUS register to determine if either accumulator
has overflowed, or one bit to determine if either
accumulator has saturated. This is useful for complex
number arithmetic, which typically uses both
accumulators.
The device supports three Saturation and Overflow
modes:
Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31 value
(0x8000000000) into the target accumulator. The
SA or SB bit is set and remains set until cleared by
the user application. This condition is referred to as
super saturation and provides protection against
erroneous data or unexpected algorithm problems
(such as gain calculations).
Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are never
set.
Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user application. No saturation
operation is performed, and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
3.6.3
ACCUMULATOR WRITE BACK
The MAC class of instructions (with the exception of

MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
DS70283J-page 30
into data space memory. The write is performed across

the X bus into combined X and Y address space. The
following addressing modes are supported:
W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
[W13] + = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target
accumulator are written into the address pointed
to by W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
3.6.3.1
Round Logic
The round logic is a combinational block that performs

a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15
data value that is passed to the data space write
saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word (lsw) is simply discarded.
Conventional rounding zero-extends bit 15 of the
accumulator and adds it to the ACCxH word (bits 16
through 31 of the accumulator).
If the ACCxL word (bits 0 through 15 of the
accumulator) is between 0x8000 and 0xFFFF
(0x8000 included), ACCxH is incremented.
If ACCxL is between 0x0000 and 0x7FFF, ACCxH
is left unchanged.
A consequence of this algorithm is that over a
succession of random rounding operations, the value
tends to be biased slightly positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the Least
Significant bit (bit 16 of the accumulator) of ACCxH is
examined:
If it is 1, ACCxH is incremented.
If it is 0, ACCxH is not modified.
Assuming that bit 16 is effectively random in nature,
this scheme removes any rounding bias that may
accumulate.
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the X bus, subject to data saturation (see
Section 3.6.3.2 Data Space Write Saturation). For
the MAC class of instructions, the accumulator
write-back operation functions in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.

3.6.3.2
Data Space Write Saturation
3.6.4
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data

space can also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These inputs
are combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.
The barrel shifter can perform up to 16-bit arithmetic or

logic right shifts, or up to 16-bit left shifts in a single
cycle. The source can be either of the two DSP accumulators or the X bus (to support multi-bit shifts of
register or memory data).
If the SATDW bit in the CORCON register is set, data

(after rounding or truncation) is tested for overflow and
adjusted accordingly:
The barrel shifter is 40 bits wide, thereby obtaining a

40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and
31 for right shifts, and between bit positions 0 and 16
for left shifts.
For input data greater than 0x007FFF, data written to memory is forced to the maximum positive
1.15 value, 0x7FFF.
For input data less than 0xFF8000, data written to
memory is forced to the maximum negative 1.15
value, 0x8000.
The shifter requires a signed binary value to determine

both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of 0
does not modify the operand.
The Most Significant bit of the source (bit 39) is used to

determine the sign of the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
DS70283J-page 31

NOTES:
DS70283J-page 32

MEMORY ORGANIZATION
Note:
This data sheet summarizes the features

Section
4.
Program
Memory
(DS70202) of the dsPIC33F/PIC24H
Family Reference Manual, which is available from the Microchip web site
(www.microchip.com).

architecture features separate program and data memory
spaces and buses. This architecture also allows the direct
access of program memory from the data space during
code execution.
FIGURE 4-1:
Program Address Space
The program address memory space of the

devices is 4M instructions. The space is addressable
by a 24-bit value derived either from the 23-bit Program
Counter (PC) during program execution, or from table
operation or data space remapping as described in
Section 4.6 Interfacing Program and Data Memory
Spaces.
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory maps for the dsPIC33FJ32MC202/204
and dsPIC33FJ16MC304 devices are shown in
Figure 4-1.
PROGRAM MEMORY MAPS FOR dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

DEVICES
dsPIC33FJ32MC202/204
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Memory Space
4.1
User Program
Flash Memory
(11264 instructions)
dsPIC33FJ16MC304
GOTO Instruction
Reset Address
Reserved
Alternate Vector Table
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x0057FE
0x005800
Unimplemented
(Read 0s)
User Memory Space
4.0
User Program
Flash Memory
(5632 instructions)
0xF7FFFE
0xF80000
0xF80017
0xF80018
0xFEFFFE
0xFF0000
0xFFFFFE
Configuration Memory Space
Configuration Memory Space
Reserved
Reserved
0x002BFE
0x002C00
0x7FFFFE
0x800000
Reserved
DEVID (2)
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
Unimplemented
(Read 0s)
0x7FFFFE
0x800000
Device Configuration
Registers
0x000000
0x000002
0x000004
Device Configuration
Registers
0xF7FFFE
0xF80000
0xF80017
0xF80018
Reserved
DEVID (2)
0xFEFFFE
0xFF0000
0xFFFFFE
DS70283J-page 33

4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
All dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

devices reserve the addresses between 0x00000 and
0x000200 for hard-coded program execution vectors.
A hardware Reset vector is provided to redirect code
execution from the default value of the PC on device
Reset to the actual start of code. A GOTO instruction is
programmed by the user application at 0x000000, with
the actual address for the start of code at 0x000002.
The program memory space is organized in

word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 4-2).

devices also have two interrupt vector tables, located
from 0x000004 to 0x0000FF and 0x000100 to
0x0001FF. These vector tables allow each of the
device interrupt sources to be handled by separate
Interrupt Service Routines (ISRs). A more detailed
discussion of the interrupt vector tables is provided in
Section 7.1 Interrupt Vector Table.
Program memory addresses are always word-aligned

on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
FIGURE 4-2:
msw
Address
PROGRAM MEMORY ORGANIZATION
16
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
Phantom Byte
(read as 0)
DS70283J-page 34
least significant word
most significant word

23
0x000001
0x000003
0x000005
0x000007
INTERRUPT AND TRAP VECTORS
Instruction Width

4.2
Data Address Space

CPU has a separate 16-bit-wide data memory space. The
data space is accessed using separate Address
Generation Units (AGUs) for read and write operations.
The data memory maps is shown in Figure 4-3.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 4.6.3 Reading Data from
Program Memory Using Program Space Visibility).
devices implement up to 2 Kbytes of data memory.
Should an EA point to a location outside of this area, an
all-zero word or byte will be returned.
4.2.1
DATA SPACE WIDTH
All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the error occurred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user application to examine
the machine state prior to execution of the address
Fault.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
A sign-extend instruction (SE) is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a zero-extend (ZE) instruction on the
appropriate address.
The data memory space is organized in byte

addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.3
4.2.2
SFRs are distributed among the modules that they

control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as 0.
DATA MEMORY ORGANIZATION

AND ALIGNMENT
To maintain backward compatibility with PIC MCU

devices and improve data space memory usage
efficiency,
the
and
dsPIC33FJ16MC304 instruction set supports both
word and byte operations. As a consequence of byte
accessibility, all effective address calculations are
internally scaled to step through word-aligned memory.
For example, the core recognizes that Post-Modified
Register Indirect Addressing mode [Ws++] will result in
a value of Ws + 1 for byte operations and Ws + 2 for
word operations.
Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000

to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
core and peripheral modules for controlling the
operation of the device.
Note:
4.2.4
The actual set of peripheral features and

interrupts varies by the device. Refer to
the corresponding device tables and
pinout diagrams for device-specific
information.
NEAR DATA SPACE
The 8 Kbyte area between 0x0000 and 0x1FFF is

referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an address pointer.
DS70283J-page 35

FIGURE 4-3:
DATA MEMORY MAP FOR dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

DEVICES WITH 2 KB RAM
MSB
Address
MSb
2 Kbyte
SFR Space
2 Kbyte
SRAM Space
LSb
0x0000
0x0001
SFR Space
0x07FF
0x0801
0x0BFF
0x0001
0x07FE
0x0800
X Data RAM (X)
Y Data RAM (Y)
0x0BFE
0x0C00
0x0FFF
0x1001
0x0FFE
0x1000
0x1FFF
0x2001
0x1FFE
0x8001
0x8000
8 Kbyte
Near Data
Space
0x2000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS70283J-page 36
LSB
Address
16 bits
0xFFFE

4.2.5
X AND Y DATA SPACES
The core has two data spaces, X and Y. These data

spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide
two concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
DS70283J-page 37
SFR Name
CPU CORE REGISTERS MAP

SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
WREG0
0000
Working Register 0
0000
WREG1
0002
Working Register 1
0000
WREG2
0004
Working Register 2
0000
WREG3
0006
Working Register 3
0000
WREG4
0008
Working Register 4
0000
WREG5
000A
Working Register 5
0000
WREG6
000C
Working Register 6
0000
WREG7
000E
Working Register 7
0000
WREG8
0010
Working Register 8
0000
WREG9
0012
Working Register 9
0000
WREG10
0014
Working Register 10
0000
WREG11
0016
Working Register 11
0000
WREG12
0018
Working Register 12
0000
WREG13
001A
Working Register 13
0000
WREG14
001C
Working Register 14
0000
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit Register
xxxx
ACCAL
0022
Accumulator A Low Word Register
0000
ACCAH
0024
Accumulator A High Word Register
0000
ACCAU
0026
Accumulator A Upper Word Register
0000
ACCBL
0028
Accumulator B Low Word Register
0000
ACCBH
002A
Accumulator B High Word Register
0000
ACCBU
002C
Accumulator B Upper Word Register
0000
PCL
002E
Program Counter Low Word Register
PCH
0030
Program Counter High Byte Register
0000
TBLPAG
0032
Table Page Address Pointer Register
0000
PSVPAG
0034
Program Memory Visibility Page Address Pointer Register
0000
RCOUNT
0036
Repeat Loop Counter Register
xxxx
DCOUNT
0038
DCOUNT<15:0>
xxxx
0000
DOSTARTL
003A
DOSTARTH
003C
DOENDL
003E
DOENDH
0040
SR
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL2
IPL1
IPL0
RA
OV
CORCON
0044
US
EDT
SATA
SATB
SATDW
ACCSAT
IPL3
PSV
RND
IF
MODCON
0046
XMODEN
YMODEN
Legend:
DOSTARTL<15:1>
BWM<3:0>
x = unknown value on Reset, = unimplemented, read as 0. Reset values are shown in hexadecimal.
xxxx
xxxx
00xx
DOENDL<15:1>
DL<2:0>
0
DOSTARTH<5:0>
DOENDH
YWM<3:0>
00xx
XWM<3:0>
0000
0020
0000
DS70283J-page 38
TABLE 4-1:
CPU CORE REGISTERS MAP (CONTINUED)

SFR
Addr
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
XMODSRT
0048
XS<15:1>
xxxx
XMODEND
004A
XE<15:1>
xxxx
YMODSRT
004C
YS<15:1>
xxxx
YMODEND
004E
YE<15:1>
xxxx
XBREV
0050
BREN
DISICNT
0052
Legend:
xxxx
Disable Interrupts Counter Register
xxxx
TABLE 4-2:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32MC202
SFR
Name
SFR
Addr
Bit 15
CNEN1
0060
CNEN2
0062
CNPU1
0068
CNPU2
006A
Legend:
XB<14:0>
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
CN15IE
CN14IE
CN13IE
CN30IE
CN29IE
CN12IE
CN11IE
CN7IE
CN27IE
CN24IE
CN23IE
CN7PUE
CN6PUE
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE
CN30PUE CN29PUE
CN27PUE
Bit 8
Bit 7
Bit 6
Bit 0
All
Resets
CN1IE
CN0IE
0000
CN16IE
0000
CN2PUE
CN1PUE
CN0PUE
0000
CN16PUE
0000
Bit 2
Bit 1
Bit 0
All
Resets
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN22IE
CN21IE
CN5PUE
CN4PUE
CN3PUE
CN24PUE CN23PUE CN22PUE CN21PUE
TABLE 4-3:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32MC204 and dsPIC33FJ16MC304
SFR
Name
SFR
Addr
Bit 15
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
0062
CN30IE
CN29IE
CN28IE
CN27IE
CN26IE
CN25IE
CN24IE
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CN17IE
CN16IE
0000
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
0000
CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
0000
CNEN2
CNPU1
0068
CNPU2
006A
Legend:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
DS70283J-page 39
TABLE 4-1:
SFR
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP

Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
MATHERR ADDRERR STKERR
Bit 0
All
Resets
0000
INTCON1
0080
NSTDIS OVAERR OVBERR COVAERR COVBERR
OVATE
OVBTE
COVTE
OSCFAIL
INTCON2
0082
ALTIVT
DISI
INT2EP
INT1EP
INT0EP
0000
IFS0
0084
AD1IF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
T1IF
OC1IF
IC1IF
INT0IF
0000
SFTACERR DIV0ERR
Bit 4
IFS1
0086
INT2IF
IC8IF
IC7IF
INT1IF
CNIF
MI2C1IF
SI2C1IF
0000
IFS3
008A
FLTA1IF
QEIIF
PWM1IF
0000
IFS4
008C
FLTA2IF PWM2IF
U1EIF
0000
IEC0
0094
AD1IE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
T1IE
OC1IE
IC1IE
INT0IE
IEC1
0096
INT2IE
IC8IE
IC7IE
INT1IE
CNIE
IEC3
009A
FLTA1IE
QEIIE
PWM1IE
0000
IEC4
009C
FLTA2IE PWM2IE
U1EIE
0000
IPC0
00A4
T1IP<2:0>
OC1IP<2:0>
IC1IP<2:0>
IPC1
00A6
T2IP<2:0>
OC2IP<2:0>
IC2IP<2:0>
4440
IPC2
00A8
IPC3
00AA
IPC4
00AC
IPC5
00AE
IPC7
00B2
IPC14
00C0
IPC15
00C2
IPC16
00C4
IPC18
00C8
INTTREG
00E0
Legend:
U1RXIP<2:0>
4444
SPI1EIP<2:0>
T3IP<2:0>
4444
AD1IP<2:0>
U1TXIP<2:0>
0044
CNIP<2:0>
MI2C1IP<2:0>
SI2C1IP<2:0>
4044
IC8IP<2:0>
INT1IP<2:0>
FLTA1IP<2:0>
SPI1IP<2:0>
INT0IP<2:0>
0000
0000
MI2C1IE SI2C1IE
IC7IP<2:0>
QEIIP<2:0>
INT2IP<2:0>
PWM1IP<2:0>
0040
0440
4000
U1EIP<2:0>
0040
PWM2IP<2:0>
0440
ILR<3:0>
FLTA2IP<2:0>
4404
VECNUM<6:0>
0000
DS70283J-page 40
TABLE 4-4:
SFR
Name
TIMER REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
Timer2 Register
0000
TMR3HLD
0108
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
TMR3
010A
Timer3 Register
0000
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
TSIDL
TGATE
TCKPS<1:0>
T32
TCS
0000
T3CON
0112
TON
TSIDL
TGATE
TCKPS<1:0>
TCS
0000
Legend:
TSIDL
FFFF
TGATE
SFR
Addr
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0146
IC7BUF
0158
IC7CON
015A
IC8BUF
015C
IC8CON
015E
TSYNC
TCS
0000
FFFF
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
ICSIDL
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
Bit 0
Input 1 Capture Register
xxxx
ICTMR
0000
ICSIDL
xxxx
ICTMR
0000
ICSIDL
xxxx
ICTMR
0000
ICSIDL
All
Resets
xxxx
ICTMR
0000
TABLE 4-7:
OUTPUT COMPARE REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DS70283J-page 41
OC1RS
0180
Output Compare 1 Secondary Register
OC1R
0182
Output Compare 1 Register
OC1CON
0184
OC2RS
0186
Output Compare 2 Secondary Register
OC2R
0188
Output Compare 2 Register
OC2CON
018A
Legend:
TCKPS<1:0>
INPUT CAPTURE REGISTER MAP
SFR Name
SFR Name
TABLE 4-6:
Legend:
TON
0000
OCSIDL
OCSIDL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
xxxx
xxxx
OCFLT
OCTSEL
OCM<2:0>
0000
xxxx
xxxx
OCFLT
OCTSEL
OCM<2:0>
0000
TABLE 4-5:
SFR Name
Addr.
6-OUTPUT PWM1 REGISTER MAP

Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
PTSIDL
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
PTOPS<3:0>
Bit 3
Bit 2
PTCKPS<1:0>
Bit 1
Bit 0
PTMOD<1:0>
Reset State
P1TCON
01C0
PTEN
P1TMR
01C2
PTDIR
PWM Timer Count Value Register
0000 0000 0000 0000
P1TPER
01C4
PWM Time Base Period Register
0000 0000 0000 0000
P1SECMP
01C6 SEVTDIR
PWM Special Event Compare Register
PWM1CON1 01C8
PWM1CON2 01CA
P1DTCON1
01CC
DTBPS<1:0>
P1DTCON2
01CE
P1FLTACON 01D0
P1OVDCON 01D4
PMOD3
PMOD2
PMOD1
SEVOPS<3:0>
DTB<5:0>
0000 0000 0000 0000
PEN3H
PEN2H
PEN1H
PEN3L
PEN2L
PEN1L
0000 0000 1111 1111
IUE
OSYNC
UDIS
0000 0000 0000 0000
DTAPS<1:0>
0000 0000 0000 0000
DTA<5:0>
0000 0000 0000 0000
DTS3A
DTS3I
DTS2A
DTS2I
DTS1A
DTS1I
0000 0000 0000 0000
FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L
FLTAM
FAEN3
FAEN2
FAEN1
0000 0000 0000 0000
POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L
POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 1111 1111 0000 0000
P1DC1
01D6
PWM Duty Cycle #1 Register
0000 0000 0000 0000
P1DC2
01D8
0000 0000 0000 0000
P1DC3
01DA
0000 0000 0000 0000
Legend:
u = uninitialized bit, = unimplemented, read as 0
TABLE 4-9:
SFR Name
2-OUTPUT PWM2 REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
05C0
PTEN
PTSIDL
P2TMR
05C2
PTDIR
PWM Timer Count Value Register
0000 0000 0000 0000
P2TPER
05C4
PWM Time Base Period Register
0000 0000 0000 0000
P2SECMP
05C6
SEVTDIR
P2TCON
Bit 6
Bit 5
Bit 4
PTOPS<3:0>
Bit 3
Bit 2
PTCKPS<1:0>
Bit 1
Bit 0
PTMOD<1:0>
PWM Special Event Compare Register
PWM2CON1 05C8
PWM2CON2 05CA
P2DTCON1
05CC
DTBPS<1:0>
P2DTCON2
05CE
P2FLTACON
05D0
P2OVDCON
05D4
P2DC1
05D6
Legend:
Bit 7
PMOD1
SEVOPS<3:0>
DTB<5:0>
0000 0000 0000 0000
PEN1H
PEN1L
0000 0000 1111 1111
IUE
OSYNC
UDIS
0000 0000 0000 0000
DTS1A
DTS1I
0000 0000 0000 0000
FAEN1
0000 0000 0000 0000
DTAPS<1:0>
Reset State
0000 0000 0000 0000
DTA<5:0>
FAOV1H FAOV1L
FLTAM
POVD1H POVD1L
0000 0000 0000 0000
POUT1H POUT1L 1111 1111 0000 0000

0000 0000 0000 0000
DS70283J-page 42
TABLE 4-8:
SFR
Name
QEI1 REGISTER MAP

Bit
10
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
QEI1CON
01E0
CNTERR
QEISIDL
INDEX
UPDN
DFLT1CON
01E2
POS1CNT
01E4
Position Counter<15:0>
0000 0000 0000 0000
MAX1CNT
01E6
Maximum Count<15:0>
1111 1111 1111 1111
Legend:
Bit 9
Bit 8
QEIM<2:0>
IMV<1:0>
CEID
Bit 7
Bit 6
Bit 5
SWPAB
PCDOUT
QEOUT
Bit 4
TQGATE
Bit 3
TQCKPS<1:0>
QECK<2:0>
Bit 2
Bit 1
Bit 0
Reset State
POSRES TQCS UPDN_SRC
0000 0000 0000 0000

0000 0000 0000 0000
TABLE 4-11:
I2C1 REGISTER MAP

All
Resets
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C1RCV
0200
Receive Register
0000
I2C1TRN
0202
Transmit Register
00FF
I2C1BRG
0204
I2C1CON
0206
I2CEN
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C1STAT
0208
ACKSTAT
TRSTAT
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
R_W
RBF
TBF
0000
I2C1ADD
020A
Address Register
0000
I2C1MSK
020C
Address Mask Register
0000
SFR Name
Legend:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
0000
TABLE 4-12:
SFR Name
Bit 7
SFR
Addr
UART1 REGISTER MAP

Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
WAKE
LPBACK
Bit 5
Bit 4
Bit 3
ABAUD
URXINV
BRGH
ADDEN
RIDLE
PERR
Bit 2
Bit 1
All
Resets
STSEL
0000
URXDA
0110
U1MODE
0220
UARTEN
USIDL
IREN
RTSMD
UEN1
UEN0
U1STA
0222
UTXISEL1
UTXINV
UTXISEL0
UTXBRK
UTXEN
UTXBF
TRMT
U1TXREG
0224
UART Transmit Register
xxxx
U1RXREG
0226
UART Receive Register
0000
U1BRG
0228
Legend:
TABLE 4-13:
SFR
Name
URXISEL<1:0>
PDSEL<1:0>
Bit 0
FERR
OERR
Baud Rate Generator Prescaler
0000
SPI1 REGISTER MAP
DS70283J-page 43
SFR
Addr
Bit 15
Bit 14
Bit 13
SPI1STAT
0240
SPIEN
SPISIDL
SPI1CON1
0242
DISSCK
DISSDO
MODE16
SMP
SPI1CON2
0244
FRMEN
SPIFSD
FRMPOL
SPI1BUF
0248
Legend:
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
CKE
SSEN
SPIROV
CKP
MSTEN
SPI1 Transmit and Receive Buffer Register
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
SPITBF
SPIRBF
0000
SPRE<2:0>
PPRE<1:0>
FRMDLY
0000
0000
0000
TABLE 4-10:
ADC1 REGISTER MAP FOR dsPIC33FJ32MC202

Bit 15
Addr
ADC1BUF0
0300
ADC Data Buffer 0
xxxx
ADC1BUF1
0302
ADC Data Buffer 1
xxxx
ADC1BUF2
0304
ADC Data Buffer 2
xxxx
ADC1BUF3
0306
ADC Data Buffer 3
xxxx
ADC1BUF4
0308
ADC Data Buffer 4
xxxx
ADC1BUF5
030A
ADC Data Buffer 5
xxxx
ADC1BUF6
030C
ADC Data Buffer 6
xxxx
ADC1BUF7
030E
ADC Data Buffer 7
xxxx
ADC1BUF8
0310
ADC Data Buffer 8
xxxx
ADC1BUF9
0312
ADC Data Buffer 9
xxxx
ADC1BUFA
0314
ADC Data Buffer 10
xxxx
ADC1BUFB
0316
ADC Data Buffer 11
xxxx
ADC1BUFC
0318
ADC Data Buffer 12
xxxx
ADC1BUFD
031A
ADC Data Buffer 13
xxxx
ADC1BUFE
031C
ADC Data Buffer 14
xxxx
ADC1BUFF
031E
ADC Data Buffer 15
AD1CON1
0320
AD1CON2
0322
AD1CON3
0324
AD1CHS123
AD1CHS0
ADON
Bit 14
Bit 13
ADSIDL
VCFG<2:0>
Bit 12
Bit 11
Bit 10
Bit 9
AD12B
FORM<1:0>
CSCNA
CHPS<1:0>
ADRC
0326
0328
CH0NB
AD1PCFGL
032C
AD1CSSL
0330
Legend:
Bit 8
Bit 7
Bit 6
Bit 5
Bit 2
SIMSAM
ASAM
SMPI<3:0>
SAMC<4:0>
Bit 3
Bit 1
Bit 0
xxxx
SSRC<2:0>
BUFS
Bit 4
All
Reset
s
File Name
SAMP
DONE
BUFM
ALTS
ADCS<7:0>
CH123NB<1:0>
CH123SB
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
0000
0000
0000
CH0NA
CH0SB<4:0>
0000
CH123NA<1:0>
CH123SA
CH0SA<4:0>
0000
0000
DS70283J-page 44
TABLE 4-14:
ADC1 REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304
Addr
ADC1BUF0
0300
ADC Data Buffer 0
xxxx
ADC1BUF1
0302
ADC Data Buffer 1
xxxx
ADC1BUF2
0304
ADC Data Buffer 2
xxxx
ADC1BUF3
0306
ADC Data Buffer 3
xxxx
ADC1BUF4
0308
ADC Data Buffer 4
xxxx
ADC1BUF5
030A
ADC Data Buffer 5
xxxx
ADC1BUF6
030C
ADC Data Buffer 6
xxxx
ADC1BUF7
030E
ADC Data Buffer 7
xxxx
ADC1BUF8
0310
ADC Data Buffer 8
xxxx
ADC1BUF9
0312
ADC Data Buffer 9
xxxx
ADC1BUFA
0314
ADC Data Buffer 10
xxxx
ADC1BUFB
0316
ADC Data Buffer 11
xxxx
ADC1BUFC
0318
ADC Data Buffer 12
xxxx
ADC1BUFD
031A
ADC Data Buffer 13
xxxx
ADC1BUFE
031C
ADC Data Buffer 14
xxxx
ADC1BUFF
031E
ADC Data Buffer 15
AD1CON1
0320
AD1CON2
0322
AD1CON3
0324
ADRC
AD1CHS123
0326
AD1CHS0
0328
CH0NB
AD1PCFGL
032C
0330
AD1CSSL
Legend:
Bit 15
ADON
Bit 14
Bit 13
ADSIDL
VCFG<2:0>
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
AD12B
FORM<1:0>
CSCNA
CHPS<1:0>
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
xxxx
SSRC<2:0>
BUFS
Bit 4
All
Resets
File Name
SIMSAM
ASAM
SMPI<3:0>
SAMC<4:0>
SAMP
DONE
0000
BUFM
ALTS
0000
CH123SA
0000
ADCS<7:0>
CH123NB<1:0>
CH123SB
CH0NA
PCFG8
PCFG7
PCFG6
CSS8
CSS7
CSS6
CH0SB<4:0>
0000
CH123NA<1:0>
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
0000
CH0SA<4:0>
0000
DS70283J-page 45
TABLE 4-15:
File
Name
Addr
PERIPHERAL PIN SELECT INPUT REGISTER MAP

Bit 15 Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
All
Resets
1F00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
INT2R<4:0>
001F
RPINR0
0680
RPINR1
0682
RPINR3
0686
T3CKR<4:0>
T2CKR<4:0>
1F1F
RPINR7
068E
IC2R<4:0>
IC1R<4:0>
1F1F
RPINR10
0694
IC7R<4:0>
1F1F
RPINR11
0696
OCFAR<4:0>
001F
RPINR12
0698
FLTA1R<4:0>
001F
RPINR13
069A
FLTA2R<4:0>
001F
RPINR14
069C
QEA1R<4:0>
1F1F
RPINR15
069E
INDX1R<4:0>
001F
RPINR18
06A4
U1CTSR<4:0>
U1RXR<4:0>
1F1F
RPINR20
06A8
SCK1R<4:0>
SDI1R<4:0>
1F1F
RPINR21
06AA
SS1R<4:0>
001F
Legend:
IC8R<4:0>
QEB1R<4:0>
TABLE 4-17:
File
Name
INT1R<4:0>
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC202
Addr
Bit 15
Bit 14
Bit 13
RPOR0
06C0
RPOR1
06C2
RPOR2
06C4
RPOR3
06C6
RPOR4
06C8
RPOR5
Bit 11
Bit 10
Bit 9
Bit 8
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 7
Bit 6
Bit 5
RP1R<4:0>
RP0R<4:0>
0000
RP3R<4:0>
RP2R<4:0>
0000
RP5R<4:0>
RP4R<4:0>
0000
RP7R<4:0>
RP6R<4:0>
0000
RP9R<4:0>
RP8R<4:0>
0000
06CA
RP11R<4:0>
RP10R<4:0>
0000
RPOR6
06CC
RP13R<4:0>
RP12R<4:0>
0000
RPOR7
06CE
RP15R<4:0>
RP14R<4:0>
0000
Legend:
Bit 12
DS70283J-page 46
TABLE 4-16:
File
Name
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304
Addr
Bit 15
Bit 14
Bit 13
RPOR0
06C0
RPOR1
06C2
RPOR2
06C4
RPOR3
06C6
RPOR4
06C8
RPOR5
Bit 7
Bit 6
Bit 5
RP1R<4:0>
RP0R<4:0>
0000
RP3R<4:0>
RP2R<4:0>
0000
RP5R<4:0>
RP4R<4:0>
0000
RP7R<4:0>
RP6R<4:0>
0000
RP9R<4:0>
RP8R<4:0>
0000
06CA
RP11R<4:0>
RP10R<4:0>
0000
RPOR6
06CC
RP13R<4:0>
RP12R<4:0>
0000
RPOR7
06CE
RP15R<4:0>
RP14R<4:0>
0000
RPOR8
06D0
RP17R<4:0>
RP16R<4:0>
0000
RPOR9
06D2
RP19R<4:0>
RP18R<4:0>
0000
RPOR10
06D4
RP21R<4:0>
RP20R<4:0>
0000
RPOR11
06D6
RP23R<4:0>
RP22R<4:0>
0000
RPOR12
06D8
RP25R<4:0>
RP24R<4:0>
0000
Legend:
TABLE 4-19:
File
Name
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
PORTA REGISTER MAP FOR dsPIC33FJ32MC202
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
TRISA
02C0
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
001F
PORTA
02C2
RA4
RA3
RA2
RA1
RA0
xxxx
LATA
02C4
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
ODCA
02C6
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
0000
Legend:
TABLE 4-20:
File
Name
PORTA REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304
DS70283J-page 47
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
TRISA
02C0
TRISA10
TRISA9
TRISA8
TRISA7
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
079F
PORTA
02C2
RA10
RA9
RA8
RA7
RA4
RA3
RA2
RA1
RA0
xxxx
LATA
02C4
LAT10
LAT8
LAT8
LAT7
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
ODCA
02C6
ODCA10
ODCA9
ODCA8
ODCA7
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
0000
Legend:
TABLE 4-18:
File
Name
PORTB REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
TRISB
02C8
TRISB15
TRISB14
TRISB13
TRISB12
TRISB11
TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB6
TRISB5
TRISB1
TRISB0
FFFF
PORTB
02CA
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB6
RB5
RB1
RB0
xxxx
LATB
02CC
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB6
LATB5
LATB1
LATB0
xxxx
ODCB
02CE
ODCB15
ODCB14
ODCB13
ODCB12
ODCB11
ODCB10
ODCB9
ODCB8
ODCB7
ODCB6
ODCB5
ODCB4
ODCB6
ODCB5
ODCB1
ODCB0
0000
Legend:
x = unknown value on Reset, = unimplemented, read as 0. Reset values are shown in hexadecimal for 100-pin devices.
TABLE 4-22:
PORTC REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
TRISC
02D0
TRISC9
TRISC8
TRISC7
TRISC6
TRISC5
TRISC4
TRISC6
TRISC5
TRISC1
TRISC0
03FF
PORTC
02D2
RC9
RC8
RC7
RC6
RC5
RC4
RC6
RC5
RC1
RC0
xxxx
LATC
02D4
LATC9
LATC8
LATC7
LATC6
LATC5
LATC4
LATC6
LATC5
LATC1
LATC0
xxxx
ODCC
02D6
ODCC9
ODCC8
ODCC7
ODCC6
ODCC5
ODCC4
ODCC6
ODCC5
ODCC1
ODCC0
0000
Legend:
TABLE 4-23:
SYSTEM CONTROL REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RCON
0740
TRAPR
IOPUWR
CM
VREGS
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
POR
xxxx(1)
OSCCON
0742
CF
LPOSCEN
OSWEN
0300(2)
COSC<2:0>
DOZE<2:0>
DOZEN
NOSC<2:0>
CLKLOCK IOLOCK
LOCK
FRCDIV<2:0>
PLLPOST<1:0>
CLKDIV
0744
ROI
PLLFBD
0746
OSCTUN
0748
Legend:
Note 1:
2:
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
PLLPRE<4:0>
PLLDIV<8:0>
3040
0030
TUN<5:0>
0000
DS70283J-page 48
TABLE 4-21:
NVM REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
ERASE
Bit 4
Bit 3
NVMCON
0760
WR
WREN
WRERR
NVMKEY
0766
Legend:
Note 1:
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
Bit 2
Bit 1
Bit 0
All
Resets
0000(1)
NVMOP<3:0>
NVMKEY<7:0>
0000
TABLE 4-25:
PMD REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PMD1
0770
T3MD
T2MD
T1MD
QEIMD
PWM1MD
I2C1MD
U1MD
SPI1MD
AD1MD
0000
PMD2
0772
IC8MD
IC7MD
IC2MD
IC1MD
OC2MD
OC1MD
0000
PMD3
0774
PWM2MD
0000
Legend:
Bit 0
All
Resets
DS70283J-page 49
TABLE 4-24:

4.2.6
SOFTWARE STACK
4.2.7
In addition to its use as a working register, the W15

register in the dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 devices is also used as a
software Stack Pointer. The Stack Pointer always
points to the first available free word and grows from
lower to higher addresses. It predecrements for stack
pops and post-increments for stack pushes, as shown
in Figure 4-4. For a PC push during any CALL
instruction, the MSb of the PC is zero-extended before
the push, ensuring that the MSb is always clear.
Note:
A PC push during exception processing

concatenates the SRL register to the MSb
of the PC prior to the push.
The Stack Pointer Limit register (SPLIM) associated

with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to 0
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap will not occur. The stack error trap will occur on a
subsequent push operation. For example, to cause a
stack error trap when the stack grows beyond address
0x1000 in RAM, initialize the SPLIM with the value
0x0FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-4:
Stack Grows Toward

Higher Address
0x0000
15
CALL STACK FRAME

0
PC<15:0>
000000000 PC<22:16>
<Free Word>
W15 (before CALL)

W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
DS70283J-page 50
DATA RAM PROTECTION FEATURE
The dsPIC33F product family supports Data RAM

protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot
Segment Flash code when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code when enabled. See
Table 4-1 for an overview of the BSRAM and SSRAM
SFRs.
4.3
Instruction Addressing Modes
The addressing modes shown in Table 4-26 form the

basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field

(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (that is,
the addressing mode can only be register direct), which
is referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-bit or 10-bit Literal
Note:
Not all instructions support all the

addressing modes given above. Individual instructions can support different
subsets of these addressing modes.

TABLE 4-26:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
File Register Direct
Description
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the Effective Address (EA).
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented

or decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset
4.3.3
The sum of Wn and a literal forms the EA.
MOVE AND ACCUMULATOR

INSTRUCTIONS
Move instructions and the DSP accumulator class of

instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU
instructions, move and accumulator instructions also
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
Note:
For the MOV instructions, the addressing

mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared by both source and
destination (but typically only used by
one).
In summary, the following addressing modes are

supported by move and accumulator instructions:
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
Not all instructions support all the

addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
4.3.4
MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
to as MAC instructions, use a simplified set of addressing
modes to allow the user application to effectively
manipulate the data pointers through register indirect
tables.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The effective addresses generated (before and after
modification) must, therefore, be valid addresses within
X data space for W8 and W9 and Y data space for W10
and W11.
Note:
Register Indirect with Register Offset

Addressing mode is available only for W9
(in X space) and W11 (in Y space).
In summary, the following addressing modes are

supported by the MAC class of instructions:
Register Indirect
Register Indirect Post-Modified by 2
Register Indirect with Register Offset (Indexed)
4.3.5
OTHER INSTRUCTIONS
Besides the addressing modes outlined previously, some

instructions use literal constants of various sizes. For
example, BRA (branch) instructions use 16-bit signed
literals to specify the branch destination directly, whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
DS70283J-page 51

4.4
Modulo Addressing
Note:
Modulo Addressing mode is a method of providing an

automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either data or program
space (since the data pointer mechanism is essentially
the same for both). One circular buffer can be supported
in each of the X (which also provides the pointers into
program space) and Y data spaces. Modulo Addressing
can operate on any W register pointer. However, it is not
advisable to use W14 or W15 for Modulo Addressing
since these two registers are used as the Stack Frame
Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can be
configured to operate in only one direction as there are
certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing
buffers), based upon the direction of the buffer.
The only exception to the usage restrictions is for
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
4.4.1
START AND END ADDRESS
The Modulo Addressing scheme requires that a

starting and ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 4-1).
FIGURE 4-5:
Y space Modulo Addressing EA

calculations assume word-sized data
(LSb of every EA is always clear).
The length of a circular buffer is not directly specified. It

is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
4.4.2
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control

register, MODCON<15:0>, contains enable flags as well
as a W register field to specify the W Address registers.
The XWM and YWM fields select the registers that will
operate with Modulo Addressing:
If XWM = 15, X RAGU and X WAGU Modulo
Addressing is disabled.
If YWM = 15, Y AGU Modulo Addressing is
disabled.
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 4-1). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than 15 and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than
15 and the YMODEN bit is set at MODCON<14>.
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
0x1100
0x1163
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100, W0
W0, XMODSRT
#0x1163, W0
W0, MODEND
#0x8001, W0
W0, MODCON
MOV
#0x0000, W0
;W0 holds buffer fill value
MOV
#0x1110, W1
;point W1 to buffer
DO
AGAIN, #0x31
MOV
W0, [W1++]
AGAIN: INC W0, W0
;set modulo start address

;set modulo end address
;enable W1, X AGU for modulo
;fill the 50 buffer locations

;fill the next location
;increment the fill value
Start Addr = 0x1100

End Addr = 0x1163
Length = 0x0032 words
DS70283J-page 52

4.4.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective

Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
The upper boundary addresses for incrementing
buffers
The lower boundary addresses for decrementing
buffers
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to).
Address changes can, therefore, jump beyond
boundaries and still be adjusted correctly.
Note:
4.5
The modulo corrected effective address is

written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the effective
address. When an address offset (such as
[W7 + W2]) is used, Modulo Address
correction is performed but the contents of
the register remain unchanged.
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify

data re-ordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.5.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
If the length of a bit-reversed buffer is M = 2N bytes,

the last N bits of the data buffer start address must
be zeros.
XB<14:0> is the Bit-Reversed Address modifier, or
pivot point, which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
All bit-reversed EA calculations assume

word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing is executed

only for Register Indirect with Pre-Increment or
Post-Increment Addressing and word-sized data
writes. It will not function for any other addressing
mode or for byte-sized data, and normal addresses are
generated instead. When Bit-Reversed Addressing is
active, the W Address Pointer is always added to the
address modifier (XB), and the offset associated with
the Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
Note:
Modulo Addressing and Bit-Reversed

Addressing should not be enabled
together. If an application attempts to do
so, Bit-Reversed Addressing will assume
priority when active for the X WAGU and X
WAGU, Modulo Addressing will be
disabled. However, Modulo Addressing will
continue to function in the X RAGU.
If Bit-Reversed Addressing has already been enabled

by setting the BREN bit (XBREV<15>), a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
Bit-Reversed Addressing mode is enabled in any of

these situations:
BWM bits (W register selection) in the MODCON
register are any value other than 15 (the stack
cannot be accessed using Bit-Reversed
Addressing)
The BREN bit is set in the XBREV register
The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
DS70283J-page 53

FIGURE 4-6:
BIT-REVERSED ADDRESS EXAMPLE

Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b4
b3 b2
b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
TABLE 4-27:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

Normal Address
A3
A2
A1
A0
Bit-Reversed Address
Decimal
A3
A2
A1
A0
Decimal
12
10
14
10
11
13
12
13
11
14
15
15
DS70283J-page 54

4.6
Interfacing Program and Data

Memory Spaces
4.6.1
The
and
dsPIC33FJ16MC304 architecture uses a 24-bit-wide
program space and a 16-bit-wide data space. The
architecture is also a modified Harvard scheme,
meaning that data can also be present in the program
space. To use this data successfully, it must be
accessed in a way that preserves the alignment of
information in both spaces.
For table operations, the 8-bit Table Page register

(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
Aside
from
normal
execution,
the
architecture provides two methods by which program
space can be accessed during operation:
For remapping operations, the 8-bit Program Space

Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is 1, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
Using table instructions to access individual bytes

or words anywhere in the program space
Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for look-ups
from a large table of static data. The application can
only access the least significant word of the program
word.
TABLE 4-28:
Table 4-28 and Figure 4-7 show how the program EA is

created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, and D<15:0> refers to a data space word.
PROGRAM SPACE ADDRESS CONSTRUCTION

Access
Space
Access Type
Instruction Access
(Code Execution)
User
TBLRD/TBLWT
(Byte/Word Read/Write)
User
Program Space Address

<23>
Program Space Visibility

(Block Remap/Read)
<22:16>
<15>
0xx
xxxx
xxxx
TBLPAG<7:0>
0xxx xxxx
User
<14:1>
PC<22:1>
Configuration
Note 1:
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program

spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
<0>
0
xxxx
xxxx xxx0
Data EA<15:0>
xxxx xxxx xxxx xxxx
TBLPAG<7:0>
Data EA<15:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
PSVPAG<7:0>
xxxx xxxx
Data EA<14:0>(1)
xxx xxxx xxxx xxxx
Data EA<15> is always 1 in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
DS70283J-page 55

FIGURE 4-7:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
23 bits
EA
Table Operations(2)
1/0
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
Program Space Visibility(1)
(Remapping)
EA
PSVPAG
8 bits
15 bits
23 bits
User/Configuration
Space Select
Byte Select
Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as 0 to
maintain word alignment of data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted
in the configuration memory space.
DS70283J-page 56

4.6.2
DATA ACCESS FROM PROGRAM

MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct

method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two
16-bit-wide word address spaces, residing side by side,
each with the same address range. TBLRDL and
TBLWTL access the space that contains the least
significant data word. TBLRDH and TBLWTH access the
space that contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
TBLRDL (Table Read Low):
- In Word mode, this instruction maps the
lower word of the program space
location (P<15:0>) to a data address
(D<15:0>).
FIGURE 4-8:
- In Byte mode, either the upper or lower byte

of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when Byte Select is 1; the lower
byte is selected when it is 0.
TBLRDH (Table Read High):
- In Word mode, this instruction maps the entire
upper word of a program address (P<23:16>)
to a data address. Note that D<15:8>, the
phantom byte, will always be 0.
- In Byte mode, this instruction maps the upper
or lower byte of the program word to D<7:0>
of the data address, in the TBLRDL instruction. The data is always 0 when the upper
phantom byte is selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 Flash
Program Memory.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and
configuration spaces. When TBLPAG<7> = 0, the table
page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space
TBLPAG
02
23
15
0x000000
23
16
00000000
00000000
0x020000
00000000
0x030000
00000000
Phantom Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
0x800000
The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
DS70283J-page 57

4.6.3
READING DATA FROM PROGRAM

MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be

mapped into any 16K word page of the program space.
This option provides transparent access to stored
constant data from the data space without the need to
use special instructions (such as TBLRDL/H).
Program space access through the data space occurs
if the Most Significant bit of the data space EA is 1 and
program space visibility is enabled by setting the PSV
bit in the Core Control register (CORCON<2>). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG
functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. By incrementing the PC by 2 for each
program memory word, the lower 15 bits of data space
addresses directly map to the lower 15 bits in the
corresponding program space addresses.
Data reads to this area add a cycle to the instruction
being executed, since two program memory fetches
are required.
Although each data space address 8000h and higher
maps directly into a corresponding program memory
address (see Figure 4-9), only the lower 16 bits of the
FIGURE 4-9:
24-bit program word are used to contain the data. The

upper 8 bits of any program space location used as
data should be programmed with 1111 1111 or
0000 0000 to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
Note:
PSV access is temporarily disabled during

table reads/writes.
For operations that use PSV and are executed outside

a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, and are executed inside
a REPEAT loop, these instances require two instruction
cycles in addition to the specified execution time of the
instruction:
Execution in the first iteration
Execution in the last iteration
Execution prior to exiting the loop due to an
interrupt
Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction using PSV to access data, to execute in a
single cycle.
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1 and EA<15> = 1:
Program Space
PSVPAG
02
23
15
Data Space
0
0x000000
0x0000
Data EA<14:0>
0x010000
0x018000
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
0x8000
PSV Area
0x800000
DS70283J-page 58
...while the lower 15 bits

of the EA specify an
exact address within
0xFFFF the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.

5.0
FLASH PROGRAM MEMORY
customers to manufacture boards with unprogrammed

devices and then program the digital signal controller
just before shipping the product. This also allows the
most recent firmware or a custom firmware to be programmed.

intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section
5. Flash Programming (DS70191) of
the dsPIC33F/PIC24H Family Reference Manual which is available from the
Microchip web site (www.microchip.com)
RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions. With RTSP, the user
application can write program memory data either in
blocks or rows of 64 instructions (192 bytes) at a time
or a single program memory word, and erase program
memory in blocks or pages of 512 instructions (1536
bytes) at a time.

5.1

devices contain internal Flash program memory for
storing and executing application code. The memory is
readable, writable and erasable during normal operation
over the entire VDD range.
Flash memory can be programmed in two ways:
In-Circuit Serial Programming (ICSP)
programming capability
Run-Time Self-Programming (RTSP)
ICSP allows a dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 device to be serially programmed
while in the end application circuit. This is done with
two lines for programming clock and programming data
(one of the alternate programming pin pairs:
PGECx/PGEDx), and three other lines for power (VDD),
ground (VSS) and Master Clear (MCLR). This allows
FIGURE 5-1:
Table Instructions and Flash

Programming
Regardless of the method used, all programming of

Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits <7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits <15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits <23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
ADDRESSING FOR TABLE REGISTERS

24 bits
Using
Program Counter
Program Counter
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 bits
User/Configuration
Space Select
16 bits
24-bit EA
Byte
Select
DS70283J-page 59

5.2
RTSP Operation

Flash program memory array is organized into rows of 64
instructions or 192 bytes. RTSP allows the user
application to erase a page of memory, which consists of
eight rows (512 instructions) at a time, and to program
one row or one word at a time. Table 24-12 shows typical
erase and programming times. The 8-row erase pages
and single row write rows are edge-aligned from the
beginning of program memory, on boundaries of 1536
bytes and 192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written. A programming cycle is required for
programming each row.
5.3
Programming Operations
A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 24-18, AC Characteristics: Internal RC
Accuracy) and the value of the FRC Oscillator Tuning
register (see Register 8-4). Use the following formula to
calculate the minimum and maximum values for the
Row Write Time, Page Erase Time, and Word Write
Cycle Time parameters (see Table 24-12, DC
Characteristics: Program Memory).
EQUATION 5-1:
For example, if the device is operating at +125 C, the

FRC accuracy will be 5%. If the TUN<5:0> bits (see
Register 8-4) are set to b111111,the minimum row
write time is equal to Equation 5-2.
EQUATION 5-2:
MINIMUM ROW WRITE

TIME
11064 Cycles
T RW = ------------------------------------------------------------------------------------------------ = 1.435ms
7.37 MHz ( 1 + 0.05 ) ( 1 0.00375 )
The maximum row write time is equal to Equation 5-3.
EQUATION 5-3:
MAXIMUM ROW WRITE

TIME
11064 Cycles
T RW = ------------------------------------------------------------------------------------------------ = 1.586ms
7.37 MHz ( 1 0.05 ) ( 1 0.00375 )
Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the
operation is finished.
5.4
Control Registers
Two SFRs are used to read and write the program

Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user application must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 5.3
Programming Operations for further details.
PROGRAMMING TIME
T
--------------------------------------------------------------------------------------------------------------------------7.37 MHz ( FRC Accuracy )% ( FRC Tuning )%
DS70283J-page 60

REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
R/W-0(1)
R/W-0(1)
U-0
U-0
U-0
U-0
U-0
WR
WREN
WRERR
bit 15
bit 8
U-0
R/W-0(1)
U-0
U-0
ERASE
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0(1)
NVMOP<3:0>(2)
bit 7
bit 0
Legend:
SO = Settable Only bit
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
WR: Write Control bit

1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
bit 14
WREN: Write Enable bit

1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
bit 13
WRERR: Write Sequence Error Flag bit

1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7
bit 6
ERASE: Erase/Program Enable bit

1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command
0 = Perform the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4
bit 3-0
NVMOP<3:0>: NVM Operation Select bits(2)

If ERASE = 1:
1111 = Memory bulk erase operation
1101 = Erase General Segment
1100 = Erase Secure Segment
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = Erase a single Configuration register byte
If ERASE = 0:
1111 = No operation
1101 = No operation
1100 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = Memory row program operation
0000 = Program a single Configuration register byte
Note 1:
2:
These bits can only be Reset on a POR.

All other combinations of NVMOP<3:0> are unimplemented.
DS70283J-page 61

REGISTER 5-2:
NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY<7:0>
bit 7
bit 0
Legend:
SO = Settable Only bit
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-8
bit 7-0
NVMKEY<7:0>: Key Register (write-only) bits
DS70283J-page 62
x = Bit is unknown

5.4.1
PROGRAMMING ALGORITHM FOR

FLASH PROGRAM MEMORY
4.
5.
Programmers can program one row of program Flash

memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is:
1.
2.
3.
Read eight rows of program memory

(512 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the block (see Example 5-1):
a) Set the NVMOP bits (NVMCON<3:0>) to
0010 to configure for block erase. Set the
ERASE (NVMCON<6>) and WREN
(NVMCON<14>) bits.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the
duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 5-1:
For protection against accidental operations, the write

initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
application must wait for the programming time until
programming is complete. The two instructions
following the start of the programming sequence
should be NOPs, as shown in Example 5-3.
ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation

MOV
#0x4042, W0
MOV
W0, NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR), W0
MOV
W0, TBLPAG
MOV
#tbloffset(PROG_ADDR), W0
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
6.
Write the first 64 instructions from data RAM into

the program memory buffers (see Example 5-2).
Write the program block to Flash memory:
a) Set the NVMOP bits to 0001 to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash memory.
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
;
; Initialize NVMCON
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PM Page Boundary SFR

Initialize in-page EA[15:0] pointer
Set base address of erase block
Block all interrupts with priority <7
for next 5 instructions
Write the 55 key
Write the AA key
Start the erase sequence
Insert two NOPs after the erase
command is asserted
DS70283J-page 63

EXAMPLE 5-2:
LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations

MOV
#0x4001, W0
;
MOV
W0, NVMCON
; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
#0x0000, W0
;
MOV
W0, TBLPAG
; Initialize PM Page Boundary SFR
MOV
#0x6000, W0
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
#LOW_WORD_0, W2
;
MOV
#HIGH_BYTE_0, W3
;
TBLWTL W2, [W0]
; Write PM low word into program latch
TBLWTH W3, [W0++]
; Write PM high byte into program latch
; 1st_program_word
MOV
#LOW_WORD_1, W2
;
MOV
#HIGH_BYTE_1, W3
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; 2nd_program_word
MOV
#LOW_WORD_2, W2
;
MOV
#HIGH_BYTE_2, W3
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; 63rd_program_word
MOV
#LOW_WORD_31, W2
;
MOV
#HIGH_BYTE_31, W3
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
EXAMPLE 5-3:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
DS70283J-page 64
; Block all interrupts with priority <7

; for next 5 instructions
;
;
;
;
;
;
Write the 55 key

Write the AA key
Start the erase sequence
Insert two NOPs after the
erase command is asserted

6.0
RESETS
A simplified block diagram of the Reset module is

shown in Figure 6-1.

Section 8. Reset (DS70192) of the
The Reset module combines all reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
POR: Power-on Reset

BOR: Brown-out Reset
MCLR: Master Clear Pin Reset
SWR: RESET Instruction
WDTO: Watchdog Timer Reset
CM: Configuration Mismatch Reset
TRAPR: Trap Conflict Reset
IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
FIGURE 6-1:
Any active source of reset will make the SYSRST

signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
Note:
Refer to the specific peripheral section or

Section 3.0 CPU of this manual for
register Reset states.
All types of device Reset sets a corresponding status

bit in the RCON register to indicate the type of Reset
(see Register 6-1).
A POR clears all the bits, except for the POR bit
(RCON<0>), that are set. The user application can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
The status bits in the RCON register

should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
RESET SYSTEM BLOCK DIAGRAM

RESET Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator
SYSRST
VDD
VDD Rise
Detect
POR
Trap Conflict
Illegal Opcode
Uninitialized W Register
Configuration Mismatch
DS70283J-page 65

RCON: RESET CONTROL REGISTER(1)
REGISTER 6-1:
R/W-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
TRAPR
IOPUWR
CM
VREGS
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
EXTR
SWR
SWDTEN(2)
WDTO
SLEEP
IDLE
BOR
POR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or uninitialized W Reset has not occurred
bit 13-10
bit 9
CM: Configuration Mismatch Flag bit

1 = A configuration mismatch Reset has occurred
0 = A configuration mismatch Reset has NOT occurred
bit 8
VREGS: Voltage Regulator Standby During Sleep bit

1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Standby mode during Sleep
bit 7
EXTR: External Reset (MCLR) Pin bit

1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6
SWR: Software Reset (Instruction) Flag bit

1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5
SWDTEN: Software Enable/Disable of WDT bit(2)

1 = WDT is enabled
0 = WDT is disabled
bit 4
WDTO: Watchdog Timer Time-out Flag bit

1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3
SLEEP: Wake-up from Sleep Flag bit

1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2
IDLE: Wake-up from Idle Flag bit

1 = Device was in Idle mode
0 = Device was not in Idle mode
Note 1:
2:
All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is 1 (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
DS70283J-page 66

REGISTER 6-1:
RCON: RESET CONTROL REGISTER(1) (CONTINUED)
bit 1
BOR: Brown-out Reset Flag bit

1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit

1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
Note 1:
2:
All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is 1 (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
DS70283J-page 67

6.1
System Reset
Cold Reset
Warm Reset
A warm Reset is the result of all other reset sources,

including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
bits (COSC<2:0>) in the Oscillator Control register
(OSCCON<14:12>).
A cold Reset is the result of a Power-on Reset (POR)

or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC configuration bits in the FOSC device
configuration register selects the device clock source.
The device is kept in a Reset state until the system

power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is shown in Figure 6-2.

family of devices have two types of Reset:
TABLE 6-1:
OSCILLATOR PARAMETERS
Oscillator
Start-up Delay
Oscillator Start-up
Timer
PLL Lock Time
Total Delay
FRC, FRCDIV16,
FRCDIVN
TOSCD
TOSCD
FRCPLL
TOSCD
TLOCK
TOSCD + TLOCK
XT
TOSCD
TOST
TOSCD + TOST
HS
TOSCD
TOST
TOSCD + TOST
EC
XTPLL
TOSCD
TOST
TLOCK
TOSCD + TOST + TLOCK
HSPLL
TOSCD
TOST
TLOCK
TOSCD + TOST + TLOCK
Oscillator Mode
ECPLL
TLOCK
TLOCK
SOSC
TOSCD
TOST
TOSCD + TOST
TOSCD
TOSCD
LPRC
Note 1:
2:
3:
TOSCD = Oscillator Start-up Delay (1.1 s max for FRC, 70 s max for LPRC). Crystal Oscillator start-up
times vary with crystal characteristics, load capacitance, etc.
TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 s for a
10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.
TLOCK = PLL lock time (1.5 ms nominal), if PLL is enabled.
DS70283J-page 68

FIGURE 6-2:
SYSTEM RESET TIMING

VBOR
Vbor
VPOR
VDD
TPOR
1
POR
TBOR
2
BOR
3
TPWRT
SYSRST
4
Oscillator Clock
TOSCD
TOST
TLOCK
6
TFSCM
FSCM
5
Reset
Device Status
Run
Time
Note 1:
POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active
until VDD crosses the VPOR threshold and the delay TPOR has elapsed.
2:
BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the
VBOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output
becomes stable.
3:
PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized
at the appropriate level for full-speed operation. After the delay TPWRT has elapsed, the SYSRST becomes
inactive, which in turn enables the selected oscillator to start generating clock cycles.
4:
Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
Table 6-1. Refer to Section 8.0 Oscillator Configuration for more information.
5:
When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
6:
The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock
is ready and the delay TFSCM elapsed.
DS70283J-page 69

TABLE 6-2:
OSCILLATOR DELAY
Symbol
Parameter
Value
VPOR
POR threshold
1.8V nominal
TPOR
POR extension time
30 s maximum
VBOR
BOR threshold
2.5V nominal
TBOR
BOR extension time
100 s maximum
TPWRT
Programmable power-up time delay
0-128 ms nominal
TFSCM
Fail-Safe Clock Monitor Delay
900 s maximum
Note:
6.2
When the device exits the Reset

condition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, otherwise the device may not function correctly. The user application must
ensure that the delay between the time
power is first applied, and the time
SYSRST becomes inactive, is long
enough to get all operating parameters
within specification.
Power-on Reset (POR)
A Power-on Reset (POR) circuit ensures the device is

reset from power-on. The POR circuit is active until
VDD crosses the VPOR threshold and the delay TPOR
has elapsed. The delay TPOR ensures the internal
device bias circuits become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
Section 24.0 Electrical Characteristics for details.
The POR status bit (POR) in the Reset Control register
(RCON<0>) is set to indicate the Power-on Reset.
DS70283J-page 70
6.2.1
Brown-out Reset (BOR) and

Power-up timer (PWRT)
The on-chip regulator has a Brown-out Reset (BOR)

circuit that resets the device when the VDD is too low
(VDD < VBOR) for proper device operation. The BOR
circuit keeps the device in Reset until VDD crosses
VBOR threshold and the delay TBOR has elapsed. The
delay TBOR ensures the voltage regulator output
becomes stable.
The BOR status bit (BOR) in the Reset Control register
(RCON<1>) is set to indicate the Brown-out Reset.
The device will not run at full speed after a BOR as the
VDD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (TPWRT) is programmed by
the Power-on Reset Timer Value Select bits
(FPWRT<2:0>) in the POR Configuration register
(FPOR<2:0>), which provides eight settings (from 0 ms
to 128 ms). Refer to Section 21.0 Special Features
for further details.
Figure 6-3 shows the typical brown-out scenarios. The
reset delay (TBOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point

FIGURE 6-3:
BROWN-OUT SITUATIONS
VDD
VBOR
TBOR + TPWRT
SYSRST
VDD
VBOR
TBOR + TPWRT
SYSRST
VDD dips before PWRT expires
VDD
VBOR
TBOR + TPWRT
SYSRST
6.3
External Reset (EXTR)
The external Reset is generated by driving the MCLR

pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse-width will generate a Reset. Refer
to Section 24.0 Electrical Characteristics for
minimum pulse-width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
register (RCON) is set to indicate the MCLR Reset.
6.3.1
EXTERNAL SUPERVISORY CIRCUIT
Many systems have external supervisory circuits that

generate reset signals to Reset multiple devices in the
system. This external Reset signal can be directly
connected to the MCLR pin to Reset the device when
the rest of system is Reset.
6.3.2
INTERNAL SUPERVISORY CIRCUIT
When using the internal power supervisory circuit to

Reset the device, the external reset pin (MCLR) should
be tied directly or resistively to VDD. In this case, the
MCLR pin will not be used to generate a Reset. The
external reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.4
Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the

device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not
re-initialize the clock. The clock source in effect prior to
the RESET instruction will remain. SYSRST is released
at the next instruction cycle, and the reset vector fetch
will commence.
The Software Reset (Instruction) Flag (SWR) bit in the

Reset Control register (RCON<6>) is set to indicate
the software Reset.
6.5
Watchdog Time-out Reset (WDTO)
Whenever a Watchdog time-out occurs, the device will

asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out Flag bit (WDTO) in the
the Watchdog Reset. Refer to Section 21.4
Watchdog Timer (WDT) for more information on
Watchdog Reset.
6.6
Trap Conflict Reset
If a lower-priority hard trap occurs while a

higher-priority trap is being processed, a hard trap
conflict Reset occurs. The hard traps include
exceptions of priority level 13 through level 15,
inclusive. The address error (level 13) and oscillator
error (level 14) traps fall into this category.
The Trap Reset Flag bit (TRAPR) in the Reset Control
register (RCON<15>) is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 Interrupt Controller for
more information on trap conflict Resets.
DS70283J-page 71

6.7
Configuration Mismatch Reset
each program memory section to store the data values.

The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
To maintain the integrity of the peripheral pin select

control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell
disturbances caused by ESD or other external events),
a configuration mismatch Reset occurs.
6.8.2
Any attempts to use the uninitialized W register as an

address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
resets and is considered uninitialized until written to.
The Configuration Mismatch Flag bit (CM) in the

the configuration mismatch Reset. Refer to
Section 10.0 I/O Ports for more information on the
configuration mismatch Reset.
Note:
6.8
6.8.3
The PFC occurs when the Program Counter is

reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
Illegal Condition Device Reset
The VFC occurs when the Program Counter is

reloaded with an Interrupt or Trap vector.
Illegal Opcode Reset

Uninitialized W Register Reset
Security Reset
Refer to Section 21.8 Code Protection and

CodeGuard Security for more information on
Security Reset.
The Illegal Opcode or Uninitialized W Access Reset

Flag bit (IOPUWR) in the Reset Control register
(RCON<14>) is set to indicate the illegal condition
device Reset.
6.9
Using the RCON Status Bits
The user application can read the Reset Control register (RCON) after any device Reset to determine the
cause of the reset.
ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to

execute an illegal opcode value that is fetched from
program memory.
Note:
The illegal opcode Reset function can prevent the

device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
TABLE 6-3:
SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow

Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The configuration mismatch feature and

associated reset flag is not available on all
devices.
An illegal condition device Reset occurs due to the

following sources:
6.8.1
UNINITIALIZED W REGISTER
RESET
The status bits in the RCON register

should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Table 6-3 provides a summary of the reset flag bit

operation.
RESET FLAG BIT OPERATION

Flag Bit
Set by:
Cleared by:
TRAPR (RCON<15>)
Trap conflict event
POR,BOR
IOPWR (RCON<14>)
Illegal opcode or uninitialized

W register access or Security Reset
POR,BOR
CM (RCON<9>)
Configuration Mismatch
POR,BOR
EXTR (RCON<7>)
MCLR Reset
POR
SWR (RCON<6>)
RESET instruction
POR,BOR
WDTO (RCON<4>)
WDT time-out
PWRSAV instruction,
CLRWDT instruction, POR,BOR
SLEEP (RCON<3>)
PWRSAV #SLEEP instruction
POR,BOR
IDLE (RCON<2>)
PWRSAV #IDLE instruction
POR,BOR
BOR (RCON<1>)
POR, BOR
POR (RCON<0>)
POR
Note:
All Reset flag bits can be set or cleared by user software.
DS70283J-page 72

7.0
INTERRUPT CONTROLLER

32. Interrupts (Part III) (DS70214) of
the dsPIC33F/PIC24H Family Reference
The
and
dsPIC33FJ16MC304 interrupt controller reduces the
numerous peripheral interrupt request signals to a
single
interrupt
request
signal
to
the
CPU. It has the following features:
Up to 8 processor exceptions and software traps

7 user-selectable priority levels
Interrupt Vector Table (IVT) with up to 118 vectors
A unique vector for each interrupt or exception
source
Fixed priority within a specified user priority level
Alternate Interrupt Vector Table (AIVT) for debug
support
Fixed interrupt entry and return latencies
7.1
7.1.1
ALTERNATE INTERRUPT VECTOR

TABLE
The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 7-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a means to
switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
7.2
Reset Sequence
A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.
The
and
dsPIC33FJ16MC304 device clears its registers in
response to a Reset, which forces the PC to zero. The
digital signal controller then begins program execution
at location 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
Note:
Any unimplemented or unused vector

locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
The Interrupt Vector Table (IVT) is shown in Figure 7-1.

The IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
8 nonmaskable trap vectors plus up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit-wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with vector 0 will take priority over interrupts at any
other vector address.
devices implement up to 26 unique interrupts and 4
nonmaskable traps. These are summarized in
Table 7-1 and Table 7-2.
DS70283J-page 73
Decreasing Natural Order Priority
FIGURE 7-1:
Note 1:
DS70283J-page 74
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 INTERRUPT VECTOR TABLE

Reset GOTO Instruction
Reset GOTO Address
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
~
~
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
~
~
Interrupt Vector 116
Reserved
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
~
~
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
~
~
Start of Code
0x000000
0x000002
0x000004
0x000014
0x00007C
0x00007E
0x000080
Interrupt Vector Table (IVT)(1)
0x0000FC
0x0000FE
0x000100
0x000102
0x000114
Alternate Interrupt Vector Table (AIVT)(1)

0x00017C
0x00017E
0x000180
0x0001FE
0x000200
See Table 7-1 for the list of implemented interrupt vectors.

TABLE 7-1:
INTERRUPT VECTORS
Vector
Number
Interrupt
Request (IRQ)
Number
IVT Address
AIVT Address
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
0x000014
0x000016
0x000018
0x00001A
0x00001C
0x00001E
0x000020
0x000022
0x000024
0x000026
0x000028
0x00002A
0x00002C
0x00002E
0x000030
0x000032
0x000034
0x000036
0x000038
0x00003A
0x00003C
0x00003E
0x000040
0x000042
0x000044
0x000046
0x000048
0x00004A
0x00004C
0x00004E
0x000050
0x000052
0x000054
0x000056
0x000058
0x00005A
0x00005C
0x00005E
0x000060
0x000062
0x000064
0x000066
0x000068
0x00006A
0x00006C
0x00006E
0x000114
0x000116
0x000118
0x00011A
0x00011C
0x00011E
0x000120
0x000122
0x000124
0x000126
0x000128
0x00012A
0x00012C
0x00012E
0x000130
0x000132
0x000134
0x000136
0x000138
0x00013A
0x00013C
0x00013E
0x000140
0x000142
0x000144
0x000146
0x000148
0x00014A
0x00014C
0x00014E
0x000150
0x000152
0x000154
0x000156
0x000158
0x00015A
0x00015C
0x00015E
0x000160
0x000162
0x000164
0x000166
0x000168
0x00016A
0x00016C
0x00016E
Interrupt Source
INT0 External Interrupt 0
IC1 Input Capture 1
OC1 Output Compare 1
T1 Timer1
Reserved
IC2 Input Capture 2
OC2 Output Compare 2
T2 Timer2
T3 Timer3
SPI1E SPI1 Error
SPI1 SPI1 Transfer Done
U1RX UART1 Receiver
U1TX UART1 Transmitter
ADC1 ADC1
Reserved
Reserved
SI2C1 I2C1 Slave Events
MI2C1 I2C1 Master Events
Reserved
Change Notification Interrupt
Reserved
IC7 Input Capture 7
IC8 Input Capture 8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DS70283J-page 75

TABLE 7-1:
INTERRUPT VECTORS (CONTINUED)
Vector
Number
Interrupt
Request (IRQ)
Number
IVT Address
AIVT Address
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
0x000070
0x000072
0x000074
0x000076
0x000078
0x00007A
0x00007C
0x00007E
0x000080
0x000082
0x000084
0x000086
0x000088
0x00008A
0x00008C
0x00008E
0x000090
0x000170
0x000172
0x000174
0x000176
0x000178
0x00017A
0x00017C
0x00017E
0x000180
0x000182
0x000184
0x000186
0x000188
0x00018A
0x00018C
0x00018E
0x000190
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWM1 PWM1 Period Match
QEI Position Counter Compare
Reserved
Reserved
Reserved
Reserved
71
63
0x000092
0x000192
FLTA1 PWM1 Fault A
72
73
74
75
76
77
78
79
80
81
82
64
65
66
67
68
69
70
71
72
73
74
0x000094
0x000096
0x000098
0x00009A
0x00009C
0x00009E
0x0000A0
0x0000A2
0x0000A4
0x0000A6
0x0000A8
0x000194
0x000196
0x000198
0x00019A
0x00019C
0x00019E
0x0001A0
0x0001A2
0x0001A4
0x0001A6
0x0001A8
Reserved
U1E UART1 Error
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWM2 PWM2 Period Match
83-125
75-117
TABLE 7-2:
Interrupt Source
FLTA2 PWM2 Fault A

0x0000AA-0x0000FE 0x0001AA-0x0001FE Reserved
TRAP VECTORS
Vector Number
IVT Address
AIVT Address
Trap Source
0x000004
0x000104
Reserved
0x000006
0x000106
Oscillator Failure
0x000008
0x000108
Address Error
0x00000A
0x00010A
Stack Error
0x00000C
0x00010C
Math Error
0x00000E
0x00010E
Reserved
0x000010
0x000110
Reserved
0x000012
0x000112
Reserved
DS70283J-page 76

7.3
Interrupt Control and Status

Registers

devices implement a total of 22 registers for the
interrupt controller:
INTCON1
INTCON2
IFSx
IECx
IPCx
INTTREG
7.3.1
INTCON1 AND INTCON2
Global interrupt control functions are controlled from

INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable bit (NSTDIS) as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.2
IFSx
The IFS registers maintain all of the interrupt request

flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
7.3.3
IECx
The IEC registers maintain all of the interrupt enable

bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
7.3.4
IPCx
The IPC registers are used to set the interrupt priority

level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
7.3.5
INTTREG
The INTTREG register contains the associated

interrupt vector number and the new CPU interrupt
priority level, which are latched into vector number
(VECNUM<6:0>) and Interrupt level bit (ILR<3:0>)
fields in the INTTREG register. The new interrupt
priority level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 7-1. For example, the INT0 (External
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP
bits in the first position of IPC0 (IPC0<2:0>).
7.3.6
STATUS/CONTROL REGISTERS
Although they are not specifically part of the interrupt

control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
The CPU STATUS register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU interrupt priority level. The user can
change the current CPU priority level by writing to
the IPL bits.
The CORCON register contains the IPL3 bit
which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
All Interrupt registers are described in Register 7-1
through Register 7-24 in the following pages.
DS70283J-page 77

REGISTER 7-1:
SR: CPU STATUS REGISTER(1)
R-0
R-0
R/C-0
R/C-0
R-0
R/C-0
R -0
R/W-0
OA
OB
SA
SB
OAB
SAB
DA
DC
bit 15
bit 8
R/W-0(3)
R/W-0(3)
R/W-0(3)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL2(2)
IPL1(2)
IPL0(2)
RA
OV
bit 7
bit 0
Legend:
C = Clear only bit
R = Readable bit
S = Set only bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
bit 7-5
Note 1:
2:
3:
For complete register details, see Register 3-1: SR: CPU STATUS Register.
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
REGISTER 7-2:
U-0
bit 15
U-0
R/W-0
SATB
Legend:
R = Readable bit
0 = Bit is cleared
Note 1:
2:
U-0
R/W-0
US
R/W-0
EDT
R-0
R-0
DL<2:0>
R-0
bit 8
R/W-0
SATA
bit 7
bit 3
CORCON: CORE CONTROL REGISTER(1)
R/W-1
SATDW
R/W-0
ACCSAT
C = Clear only bit

W = Writable bit
x = Bit is unknown
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
-n = Value at POR
1 = Bit is set
IPL3: CPU Interrupt Priority Level Status bit 3(2)

1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
For complete register details, see Register 3-2: CORCON: CORE Control Register.
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
DS70283J-page 78

REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NSTDIS
OVAERR
OVBERR
COVAERR
COVBERR
OVATE
OVBTE
COVTE
bit 15
bit 8
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
SFTACERR
DIV0ERR
MATHERR
ADDRERR
STKERR
OSCFAIL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14
OVAERR: Accumulator A Overflow Trap Flag bit

1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
bit 13
OVBERR: Accumulator B Overflow Trap Flag bit

1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
bit 12
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit

1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
bit 11
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit

1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
bit 10
OVATE: Accumulator A Overflow Trap Enable bit

1 = Trap overflow of Accumulator A
0 = Trap disabled
bit 9
OVBTE: Accumulator B Overflow Trap Enable bit

1 = Trap overflow of Accumulator B
0 = Trap disabled
bit 8
COVTE: Catastrophic Overflow Trap Enable bit

1 = Trap on catastrophic overflow of Accumulator A or B enabled
0 = Trap disabled
bit 7
SFTACERR: Shift Accumulator Error Status bit

1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR: Arithmetic Error Status bit

1 = Math error trap was caused by a divide by zero
0 = Math error trap was not caused by a divide by zero
bit 5
bit 4
MATHERR: Arithmetic Error Status bit

1 = Math error trap has occurred
0 = Math error trap has not occurred
bit 3
ADDRERR: Address Error Trap Status bit

1 = Address error trap has occurred
0 = Address error trap has not occurred
x = Bit is unknown
DS70283J-page 79

REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 2
STKERR: Stack Error Trap Status bit

1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1
OSCFAIL: Oscillator Failure Trap Status bit

1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0
DS70283J-page 80

REGISTER 7-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
ALTIVT
DISI
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
ALTIVT: Enable Alternate Interrupt Vector Table bit

1 = Use alternate vector table
0 = Use standard (default) vector table
bit 14
DISI: DISI Instruction Status bit

1 = DISI instruction is active
0 = DISI instruction is not active
bit 13-3
bit 2
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1

bit 0

x = Bit is unknown
DS70283J-page 81

REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AD1IF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
T2IF
OC2IF
IC2IF
T1IF
OC1IF
IC1IF
INT0IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-14
bit 13
AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit

1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12
U1TXIF: UART1 Transmitter Interrupt Flag Status bit

bit 11
U1RXIF: UART1 Receiver Interrupt Flag Status bit

bit 10
SPI1IF: SPI1 Event Interrupt Flag Status bit

bit 9
SPI1EIF: SPI1 Fault Interrupt Flag Status bit

bit 8
T3IF: Timer3 Interrupt Flag Status bit

bit 7

bit 6
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

bit 5
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

bit 4
bit 3

bit 2
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

DS70283J-page 82
x = Bit is unknown

REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 1

bit 0
INT0IF: External Interrupt 0 Flag Status bit

DS70283J-page 83

REGISTER 7-6:
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
INT2IF
bit 15
bit 8
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
IC8IF
IC7IF
INT1IF
CNIF
MI2C1IF
SI2C1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-14
bit 13

bit 12-8
bit 7

bit 6

bit 5
bit 4

bit 3
CNIF: Input Change Notification Interrupt Flag Status bit

bit 2
bit 1
MI2C1IF: I2C1 Master Events Interrupt Flag Status bit

bit 0
SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit

DS70283J-page 84
x = Bit is unknown

REGISTER 7-7:
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
FLTA1IF
QEIIF
PWM1IF
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
FLTA1IF: PWM1 Fault A Interrupt Flag Status bit

bit 14-11
bit 10
QEIIF: QEI Event Interrupt Flag Status bit

bit 9
PWM1IF: PWM1 Interrupt Flag Status bit

bit 8-0
x = Bit is unknown
DS70283J-page 85

REGISTER 7-8:
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
FLTA2IF
PWM2IF
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
U1EIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-11
bit 10
FLTA2IF: PWM2 Fault A Interrupt Flag Status bit

bit 9
PWM2IF: PWM2 Error Interrupt Enable bit

bit 8-2
bit 1
U1EIF: UART1 Interrupt Flag Status bit

bit 0
DS70283J-page 86
x = Bit is unknown

REGISTER 7-9:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AD1IE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
T2IE
OC2IE
IC2IE
T1IE
OC1IE
IC1IE
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-14
bit 13
AD1IE: ADC1 Conversion Complete Interrupt Enable bit

1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12
U1TXIE: UART1 Transmitter Interrupt Enable bit

bit 11
U1RXIE: UART1 Receiver Interrupt Enable bit

bit 10
SPI1IE: SPI1 Event Interrupt Enable bit

bit 9
SPI1EIE: SPI1 Event Interrupt Enable bit

bit 8
T3IE: Timer3 Interrupt Enable bit

bit 7

bit 6
OC2IE: Output Compare Channel 2 Interrupt Enable bit

bit 5
IC2IE: Input Capture Channel 2 Interrupt Enable bit

bit 4
bit 3

bit 2
OC1IE: Output Compare Channel 1 Interrupt Enable bit

x = Bit is unknown
DS70283J-page 87

REGISTER 7-9:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 1

bit 0
INT0IE: External Interrupt 0 Enable bit

DS70283J-page 88

REGISTER 7-10:
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
INT2IE
bit 15
bit 8
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
IC8IE
IC7IE
INT1IE
CNIE
MI2C1IE
SI2C1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-14
bit 13

bit 12-8
bit 7

bit 6

bit 5
bit 4

bit 3
CNIE: Input Change Notification Interrupt Enable bit

bit 2
bit 1
MI2C1IE: I2C1 Master Events Interrupt Enable bit

bit 0
SI2C1IE: I2C1 Slave Events Interrupt Enable bit

x = Bit is unknown
DS70283J-page 89

REGISTER 7-11:
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
FLTA1IE
QEIIE
PWM1IE
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
FLTA1IE: PWM1 Fault A Interrupt Enable bit

bit 14-11
bit 10
QEIIE: QEI Event Interrupt Enable bit

bit 9
PWM1IE: PWM1 Error Interrupt Enable bit

bit 8-0
DS70283J-page 90
x = Bit is unknown

REGISTER 7-12:
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
FLA2IE
PWM2IE
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
U1EIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-11
bit 10
FLA2IE: PWM2 Fault A Interrupt Enable bit

bit 9
PWM2IE: PWM2 Error Interrupt Enable bit

bit 8-2
bit 1
U1EIE: UART1 Error Interrupt Enable bit

bit 0
x = Bit is unknown
DS70283J-page 91

REGISTER 7-13:
U-0
IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0

R/W-1
R/W-0
R/W-0
T1IP<2:0>
U-0
R/W-1
R/W-0
R/W-0
OC1IP<2:0>
bit 15
bit 8
U-0
R/W-1
R/W-0
IC1IP<2:0>
R/W-0
U-0
R/W-1
R/W-0
R/W-0
INT0IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
bit 14-12
T1IP<2:0>: Timer1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1

000 = Interrupt source is disabled
bit 11
bit 10-8
OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits


bit 7
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits


bit 3
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits


DS70283J-page 92
x = Bit is unknown

REGISTER 7-14:
U-0

R/W-1
R/W-0
R/W-0
T2IP<2:0>
U-0
R/W-1
R/W-0
R/W-0
OC2IP<2:0>
bit 15
bit 8
U-0
R/W-1
R/W-0
IC2IP<2:0>
R/W-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
bit 14-12


bit 11
bit 10-8
OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits


bit 7
bit 6-4


bit 3-0
x = Bit is unknown
DS70283J-page 93

REGISTER 7-15:
U-0

R/W-1
R/W-0
R/W-0
U1RXIP<2:0>
U-0
R/W-1
R/W-0
R/W-0
SPI1IP<2:0>
bit 15
bit 8
U-0
R/W-1
R/W-0
SPI1EIP<2:0>
R/W-0
U-0
R/W-1
R/W-0
R/W-0
T3IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
bit 14-12
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits


bit 11
bit 10-8
SPI1IP<2:0>: SPI1 Event Interrupt Priority bits


bit 7
bit 6-4
SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits


bit 3
bit 2-0


DS70283J-page 94
x = Bit is unknown

REGISTER 7-16:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
R/W-1
R/W-0
AD1IP<2:0>
R/W-0
U-0
R/W-1
R/W-0
R/W-0
U1TXIP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-7
bit 6-4
AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits


bit 3
bit 2-0
U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits


x = Bit is unknown
DS70283J-page 95

REGISTER 7-17:
U-0

R/W-1
R/W-0
R/W-0
CNIP<2:0>
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
R/W-1
R/W-0
MI2C1IP<2:0>
R/W-0
U-0
R/W-1
R/W-0
R/W-0
SI2C1IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
bit 14-12
CNIP<2:0>: Change Notification Interrupt Priority bits


bit 11-7
bit 6-4
MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits


bit 3
bit 2-0
SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits


DS70283J-page 96
x = Bit is unknown

REGISTER 7-18:
U-0

R/W-1
R/W-0
R/W-0
IC8IP<2:0>
U-0
R/W-1
R/W-0
R/W-0
IC7IP<2:0>
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
INT1IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
bit 14-12


bit 11
bit 10-8


bit 7-3
bit 2-0


x = Bit is unknown
DS70283J-page 97

REGISTER 7-19:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
R/W-1
R/W-0
INT2IP<2:0>
R/W-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-7
bit 6-4


bit 3-0
DS70283J-page 98
x = Bit is unknown

REGISTER 7-20:
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
QEIIP<2:0>
bit 15
bit 8
U-0
R/W-1
R/W-0
PWM1IP<2:0>
R/W-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-12
bit 10-8
QEIIP<2:0>: QEI Interrupt Priority bits


bit 7
bit 6-4
PWM1IP<2:0>: PWM1 Interrupt Priority bits


bit 3-0
x = Bit is unknown
DS70283J-page 99

REGISTER 7-21:
U-0

R/W-1
R/W-0
R/W-0
FLTA1IP<2:0>
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
bit 14-12
FLTA1IP<2:0>: PWM1 Fault A Interrupt Priority bits


bit 11-0
REGISTER 7-22:
x = Bit is unknown
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
R/W-1
R/W-0
U1EIP<2:0>
R/W-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-7
bit 6-4
U1EIP<2:0>: UART1 Error Interrupt Priority bits


bit 3-0
DS70283J-page 100
x = Bit is unknown

REGISTER 7-23:
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
FLTA2IP<2:0>
bit 15
bit 8
U-0
R/W-1
R/W-0
PWM2IP<2:0>
R/W-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-11
bit 8-10
FLTA2IP<2:0>: PWM2 Fault A Interrupt Priority bits


bit 7
bit 6-4
PWM2IP<2:0>: PWM2 Interrupt Priority bits


bit 3-0
x = Bit is unknown
DS70283J-page 101

REGISTER 7-24:
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
ILR<3:0>
bit 15
bit 8
U-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VECNUM<6:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-12
bit 11-8
ILR<3:0>: New CPU Interrupt Priority Level bits

1111 = CPU Interrupt Priority Level is 15

bit 7
bit 6-0
VECNUM<6:0>: Vector Number of Pending Interrupt bits

0111111 = Interrupt Vector pending is number 135

DS70283J-page 102
x = Bit is unknown

7.4
Interrupt Setup Procedures
7.4.1
INITIALIZATION
To configure an interrupt source at initialization:

1.
2.
Set the NSTDIS bit (INTCON1<15>) if nested

interrupts are not desired.
Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources can be programmed
to the same non-zero value.
Note:
3.
4.
At a device Reset, the IPCx registers are

initialized such that all user interrupt
sources are assigned to priority level 4.
Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx register.
Enable the interrupt source by setting the
interrupt enable control bit associated with the
source in the appropriate IECx register.
7.4.2
7.4.3
TRAP SERVICE ROUTINE
A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.4
INTERRUPT DISABLE
All user interrupts can be disabled using this

procedure:
1.
2.
Push the current SR value onto the software

stack using the PUSH instruction.
Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
To enable user interrupts, the POP instruction can be

used to restore the previous SR value.
Note:
Only user interrupts with a priority level of

7 or lower can be disabled. Trap sources
(level 8-level 15) cannot be disabled.
The DISI instruction provides a convenient way to

disable interrupts of priority levels 1-6 for a fixed period
of time. Level 7 interrupt sources are not disabled by
the DISI instruction.
INTERRUPT SERVICE ROUTINE
The method used to declare an Interrupt Service Routine (ISR) and initialize the IVT with the correct vector
address depends on the programming language (C or
assembler) and the language development tool suite
used to develop the application.
In general, the user application must clear the interrupt
flag in the appropriate IFSx register for the source of
interrupt that the ISR handles. Otherwise, program will
re-enter the ISR immediately after exiting the routine. If
the ISR is coded in assembly language, it must be
terminated using a RETFIE instruction to unstack the
saved PC value, SRL value and old CPU priority level.
DS70283J-page 103

NOTES:
DS70283J-page 104

8.0
OSCILLATOR
CONFIGURATION
The oscillator system for dsPIC33FJ32MC202/204 and

dsPIC33FJ16MC304 devices provides:

7. Oscillator (DS70186) of the
Microchip
web
site
External and internal oscillator options as clock

sources.
An on-chip Phase-Locked Loop (PLL) to scale the
internal operating frequency to the required
system clock frequency.
An internal FRC oscillator that can also be used
with the PLL, thereby allowing full-speed
operation without any external clock generation
hardware.
Clock switching between various clock sources.
Programmable clock postscaler for system power
savings.
A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures.
A Clock Control register (OSCCON).
Nonvolatile Configuration bits for main oscillator
selection.
A simplified diagram of the oscillator system is shown
in Figure 8-1.
FIGURE 8-1:
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 OSCILLATOR SYSTEM DIAGRAM

Primary Oscillator (POSC)
XT, HS, EC
R(2)
S3
PLL
S1
OSC2
(1)
DOZE<2:0>
S2
XTPLL, HSPLL,
ECPLL, FRCPLL
DOZE
OSC1
S1/S3
POSCMD<1:0>
FCY(3)
FRCDIV
FP(3)
FRC
Oscillator
FRCDIVN
S7
2
FOSC
FRCDIV<2:0>
TUN<5:0>
FRCDIV16
16
FRC
LPRC
LPRC
Oscillator
Secondary Oscillator (SOSC)
SOSC
SOSCO
S6
S0
S5
S4
LPOSCEN
SOSCI
Clock Fail
S7
Clock Switch
Reset
NOSC<2:0> FNOSC<2:0>
WDT, PWRT,
FSCM
Timer 1
Note 1: See Figure 8-2 for PLL details.

2: If the Oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M must be connected.
3: The term FP refers to the clock source for all of the peripherals, while FCY refers to the clock source for the CPU.
Throughout this document, FCY and FP are used interchangeably, except in the case of DOZE mode. FP and FCY will
be different when DOZE mode is used with any ratio other than 1:1 which is the default.
DS70283J-page 105

8.1
CPU Clocking System
The
and
dsPIC33FJ16MC304 devices provide seven system
clock options:
Fast RC (FRC) Oscillator

FRC Oscillator with PLL
Primary (XT, HS or EC) Oscillator
Primary Oscillator with PLL
Secondary (LP) Oscillator
Low-Power RC (LPRC) Oscillator
FRC Oscillator with postscaler
8.1.1
8.1.1.1
SYSTEM CLOCK SOURCES

Fast RC
The Fast RC (FRC) internal oscillator runs at a nominal

frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> bits (CLKDIV<10:8>).
8.1.1.2
Primary
The primary oscillator can use one of the following as

its clock source:
XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
HS (High-Speed Crystal): Crystals in the range of
10 MHz to 40 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
EC (External Clock): The external clock signal is
directly applied to the OSC1 pin.
8.1.1.3
Secondary
The secondary (LP) oscillator is designed for low power

and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
8.1.1.4
Low-Power RC
The LPRC (Low-Power RC) internal oscIllator runs at a

nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
8.1.1.5
FRC
The clock signals generated by the FRC and primary

oscillators can be optionally applied to an on-chip
Phase Locked Loop (PLL) to provide a wide range of
output frequencies for device operation. PLL
configuration is described in Section 8.1.3 PLL
Configuration.
The FRC frequency depends on the FRC accuracy
(see Table 24-18) and the value of the FRC Oscillator
Tuning register (see Register 8-4).
DS70283J-page 106
8.1.2
SYSTEM CLOCK SELECTION
The oscillator source used at a device Power-on

Reset event is selected using Configuration bit
settings. The oscillator Configuration bit settings are
located in the Configuration registers in the program
memory. (Refer to Section 21.1 Configuration
Bits for further details.) The Initial Oscillator
Selection
Configuration
bits,
FNOSC<2:0>
(FOSCSEL<2:0>), and the Primary Oscillator Mode
Select
Configuration
bits,
POSCMD<1:0>
(FOSC<1:0>), select the oscillator source that is used
at a Power-on Reset. The FRC primary oscillator is
the default (unprogrammed) selection.
The Configuration bits allow users to choose among 12
different clock modes, shown in Table 8-1.
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected) FOSC is divided by 2 to
generate the device instruction clock (FCY) and the
peripheral clock time base (FP). FCY defines the
operating speed of the device, and speeds up to 40
MHz are supported by the dsPIC33FJ32MC202/204
and dsPIC33FJ16MC304 architecture.
Instruction execution speed or device operating
frequency, FCY, is given by:
EQUATION 8-1:
DEVICE OPERATING
FREQUENCY
OSC
------------F CY = F
2
8.1.3
PLL CONFIGURATION
The primary oscillator and internal FRC oscillator can

optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 8-2.
The output of the primary oscillator or FRC, denoted as
FIN, is divided down by a prescale factor (N1) of 2, 3,
... or 33 before being provided to the PLLs Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale factor N1 is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor M,
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor
N2. This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). N2 can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(FOSC) is in the range of 12.5 MHz to 80 MHz, which
generates device operating speeds of 6.25-40 MIPS.

For a primary oscillator or FRC oscillator, output FIN,
the PLL output FOSC is given by:
EQUATION 8-2:
If PLLDIV<8:0> = 0x1E, then

M = 32. This yields a VCO output of 5 x 32 = 160
MHz, which is within the 100-200 MHz ranged
needed.
If PLLPOST<1:0> = 0, then N2 = 2. This provides
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
FOSC CALCULATION
M
F OSC = F IN ----------------------
N1 N2
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL.
EQUATION 8-3:
If PLLPRE<4:0> = 0, then N1 = 2. This yields a

VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
FIGURE 8-2:
XT WITH PLL MODE

EXAMPLE
1
10000000 32
OSC
------------= --- ------------------------------------- = 40 MIPS
F CY = F
2
2 2
2
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PLL BLOCK DIAGRAM

FVCO
100-200 MHz
Here(1)
0.8-8.0 MHz
Here(1)
Source (Crystal, External Clock
or Internal RC)
PLLPRE
VCO
12.5-80 MHz
Here(1)
FOSC
PLLPOST
PLLDIV
N1
Divide by
2-33
M
Divide by
2-513
N2
Divide by
2, 4, 8
Note 1: This frequency range must be satisfied at all times.
TABLE 8-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source
POSCMD<1:0>
FNOSC<2:0>
See Note
Fast RC Oscillator with Divide-by-N

(FRCDIVN)
Internal
xx
111
1, 2
Fast RC Oscillator with Divide-by-16

(FRCDIV16)
Internal
xx
110
Low-Power RC Oscillator (LPRC)
Internal
xx
101
Secondary
xx
100
Primary Oscillator (HS) with PLL

(HSPLL)
Primary
10
011
Primary Oscillator (XT) with PLL

(XTPLL)
Primary
01
011
Primary Oscillator (EC) with PLL

(ECPLL)
Primary
00
011
Primary Oscillator (HS)
Primary
10
010
Secondary (Timer1) Oscillator (SOSC)
Primary Oscillator (XT)
Primary
01
010
Primary Oscillator (EC)
Primary
00
010
Fast RC Oscillator with PLL (FRCPLL)
Internal
xx
001
Fast RC Oscillator (FRC)
Internal
xx
000
Note 1:
2:
OSC2 pin function is determined by the OSCIOFNC Configuration bit.

This is the default oscillator mode for an unprogrammed (erased) device.
DS70283J-page 107

OSCCON: OSCILLATOR CONTROL REGISTER(1,3)
REGISTER 8-1:
U-0
R-0
R-0
R-0
COSC<2:0>
U-0
R/W-y
R/W-y
R/W-y
NOSC<2:0>(2)
bit 15
bit 8
R/W-0
R/W-0
R-0
U-0
R/C-0
U-0
R/W-0
R/W-0
CLKLOCK
IOLOCK
LOCK
CF
LPOSCEN
OSWEN
bit 7
bit 0
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
COSC<2:0>: Current Oscillator Selection bits (read-only)

111 = Fast RC oscillator (FRC) with Divide-by-n
110 = Fast RC oscillator (FRC) with Divide-by-16
101 = Low-Power RC oscillator (LPRC)
100 = Secondary oscillator (SOSC)
011 = Primary oscillator (XT, HS, EC) with PLL
010 = Primary oscillator (XT, HS, EC)
001 = Fast RC oscillator (FRC) with PLL
000 = Fast RC oscillator (FRC)
bit 11
bit 10-8
NOSC<2:0>: New Oscillator Selection bits(2)

111 = Fast RC oscillator (FRC) with Divide-by-n
110 = Fast RC oscillator (FRC) with Divide-by-16
101 = Low-Power RC oscillator (LPRC)
100 = Secondary oscillator (SOSC)
011 = Primary oscillator (XT, HS, EC) with PLL
010 = Primary oscillator (XT, HS, EC)
001 = Fast RC oscillator (FRC) with PLL
000 = Fast RC oscillator (FRC)
bit 7
CLKLOCK: Clock Lock Enable bit

If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01)
1 = Clock switching is disabled, system clock source is locked
0 = Clock switching is enabled, system clock source can be modified by clock switching
bit 6
IOLOCK: Peripheral Pin Select Lock bit

1 = Peripherial pin select is locked, write to peripheral pin select registers not allowed
0 = Peripherial pin select is not locked, write to peripheral pin select registers allowed
bit 5
LOCK: PLL Lock Status bit (read-only)

1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
bit 4
Note 1:
2:
3:
Writes to this register require an unlock sequence. Refer to Section 7. Oscillator (DS70186) in the
dsPIC33F/PIC24H Family Reference Manual for details.
Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transition clock source between the two PLL modes.
This register is reset only on a Power-on Reset (POR).
DS70283J-page 108

REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER(1,3) (CONTINUED)
bit 3
CF: Clock Fail Detect bit (read/clear by application)

1 = FSCM has detected clock failure
0 = FSCM has not detected clock failure
bit 2
bit 1
LPOSCEN: Secondary (LP) Oscillator Enable bit

1 = Enable secondary oscillator
0 = Disable secondary oscillator
bit 0
OSWEN: Oscillator Switch Enable bit

1 = Request oscillator switch to selection specified by NOSC<2:0> bits
0 = Oscillator switch is complete
Note 1:
2:
3:
Writes to this register require an unlock sequence. Refer to Section 7. Oscillator (DS70186) in the
dsPIC33F/PIC24H Family Reference Manual for details.
Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transition clock source between the two PLL modes.
DS70283J-page 109

REGISTER 8-2:
R/W-0
ROI
bit 15
CLKDIV: CLOCK DIVISOR REGISTER(2)

R/W-0
Legend:
R = Readable bit
-n = Value at POR
bit 14-12
bit 11
bit 10-8
bit 7-6
bit 5
bit 4-0
Note 1:
2:
R/W-1
R/W-0
DOZEN(1)
R/W-0
R/W-0
FRCDIV<2:0>
R/W-0
bit 8
R/W-0
R/W-1
PLLPOST<1:0>
bit 7
bit 15
R/W-1
DOZE<2:0>
U-0
R/W-0
R/W-0
R/W-0
PLLPRE<4:0>
R/W-0
R/W-0
bit 0
y = Value set from Configuration bits on POR

W = Writable bit
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
ROI: Recover on Interrupt bit

1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
DOZE<2:0>: Processor Clock Reduction Select bits
111 = FCY/128
110 = FCY/64
101 = FCY/32
100 = FCY/16
011 = FCY/8 (default)
010 = FCY/4
001 = FCY/2
000 = FCY/1
DOZEN: DOZE Mode Enable bit(1)
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock/peripheral clock ratio forced to 1:1
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divide by 256
000 = FRC divide by 1 (default)
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as N2, PLL postscaler)
11 = Output/8
10 = Reserved
01 = Output/4 (default)
00 = Output/2
PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as N1, PLL prescaler)
00000 = Input/2 (default)
00001 = Input/3
11111 = Input/33
This bit is cleared when the ROI bit is set and an interrupt occurs.
DS70283J-page 110

REGISTER 8-3:
PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
PLLDIV<8>
bit 15
bit 8
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
PLLDIV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-9
bit 8-0
PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as M, PLL multiplier)

000000000 = 2
000000001 = 3
000000010 = 4
000110000 = 50 (default)
111111111 = 513
Note 1:
DS70283J-page 111

REGISTER 8-4:
OSCTUN: FRC OSCILLATOR TUNING REGISTER(2)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN<5:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-6
bit 5-0
TUN<5:0>: FRC Oscillator Tuning bits(1)

011111 = Center frequency + 11.625% (8.23 MHz)

000000 = Center frequency (7.37 MHz nominal)
111111 = Center frequency -0.375% (7.345 MHz)
100001 = Center frequency -11.625% (6.52 MHz)

100000 = Center frequency -12% (6.49 MHz)
Note 1:
2:
x = Bit is unknown
OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither
characterized nor tested.
DS70283J-page 112

8.2
Clock Switching Operation
Applications are free to switch among any of the four

clock sources (Primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 devices have a safeguard lock
built into the switch process.
Note:
Primary Oscillator mode has three different

submodes (XT, HS and EC), which are
determined by the POSCMD<1:0>
Configuration bits. While an application
can switch to and from Primary Oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
2.
If a valid clock switch has been initiated, the

LOCK
(OSCCON<5>)
and
the
CF
(OSCCON<3>) status bits are cleared.
The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM
are enabled) or LP (if LPOSCEN remains set).
3.
4.
5.
6.
8.2.1
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration

bit in the Configuration register must be programmed to
0. (Refer to Section 21.1 Configuration Bits for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (1), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
Note 1: The processor continues to execute code

throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
2: Direct clock switches between any primary oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direction. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
3: Refer to Section 7. Oscillator
(DS70186) in the dsPIC33F/PIC24H
Family Reference Manual for details.
The NOSC control bits (OSCCON<10:8>) do not

control the clock selection when clock switching is
disabled. However, the COSC bits (OSCCON<14:12>)
reflect the clock source selected by the FNOSC
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at 0 at all
times.
8.2.2
Performing
sequence:
1.
2.
3.
4.
5.
OSCILLATOR SWITCHING
SEQUENCE
a
clock switch requires
8.3
this basic
If
desired,
read
the
COSC
bits
(OSCCON<14:12>) to determine the current
oscillator source.
Perform the unlock sequence to allow a write to
the OSCCON register high byte.
Write the appropriate value to the NOSC control
bits (OSCCON<10:8>) for the new oscillator
source.
Perform the unlock sequence to allow a write to
the OSCCON register low byte.
Set the OSWEN bit (OSCCON<0>) to initiate
the oscillator switch.
Once the basic sequence is completed, the system

clock hardware responds automatically as follows:
1.
Fail-Safe Clock Monitor (FSCM)
The Fail-Safe Clock Monitor (FSCM) allows the device

to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. Then the
application program can either attempt to restart the
oscillator or execute a controlled shutdown. The trap
can be treated as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
The clock switching hardware compares the

COSC status bits with the new value of the
NOSC control bits. If they are the same, the
clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
DS70283J-page 113

NOTES:
DS70283J-page 114

9.0
POWER-SAVING FEATURES

intended to be a comprehensive
Section 9. Watchdog Timer and
Power-Saving Modes (DS70196) the
devices provide the ability to manage power consumption
by selectively managing clocking to the CPU and the
peripherals. In general, a lower clock frequency and a
reduction in the number of circuits being clocked
constitutes
lower
consumed
power.
devices can manage power consumption in four different
ways:
Clock frequency
Instruction-based Sleep and Idle modes
Software-controlled Doze mode
Selective peripheral control in software
Combinations of these methods can be used to selectively tailor an applications power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
9.1
Clock Frequency and Clock

Switching

devices allow a wide range of clock frequencies to be
selected under application control. If the system clock
configuration is not locked, users can choose
low-power or high-precision oscillators by simply
changing the NOSC bits (OSCCON<10:8>). The
process of changing a system clock during operation,
as well as limitations to the process, are discussed in
more
detail
in
Section 8.0
Oscillator
Configuration.
EXAMPLE 9-1:
9.2
Instruction-Based Power-Saving
Modes

devices have two special power-saving modes that are
entered through the execution of a special PWRSAV
instruction. Sleep mode stops clock operation and halts
all code execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV
instruction is shown in Example 9-1.
Note:
SLEEP_MODE and IDLE_MODE are constants defined in the assembler include

file for the selected device.
Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
9.2.1
SLEEP MODE
The following occur in Sleep mode:

The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current.
The Fail-Safe Clock Monitor does not operate,
since the system clock source is disabled.
The LPRC clock continues to run in Sleep mode if
the WDT is enabled.
The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
Some device features or peripherals may continue
to operate. This includes items such as the input
change notification on the I/O ports, or peripherals
that use an external clock input.
Any peripheral that requires the system clock
source for its operation is disabled.
The device will wake-up from Sleep mode on any of the
these events:
Any interrupt source that is individually enabled
Any form of device Reset
A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
PWRSAV INSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into SLEEP mode

; Put the device into IDLE mode
DS70283J-page 115

9.2.2
IDLE MODE
The following occur in Idle mode:

The CPU stops executing instructions.
The WDT is automatically cleared.
The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 9.4
Peripheral Module Disable).
If the WDT or FSCM is enabled, the LPRC also
remains active.
The device will wake from Idle mode on any of these
events:
Any interrupt that is individually enabled
Any device Reset
A WDT time-out
Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible
configurations, from 1:1 to 1:128, with 1:1 being the
default setting.
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU idles, waiting for something to invoke an
interrupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
On wake-up from Idle mode, the clock is reapplied to

the CPU and instruction execution will begin (2-4
cycles later), starting with the instruction following the
PWRSAV instruction, or the first instruction in the ISR.
For example, suppose the device is operating at

20 MIPS and the CAN module has been configured for
500 kbps based on this device operating speed. If the
device is placed in Doze mode with a clock frequency
ratio of 1:4, the CAN module continues to communicate
at the required bit rate of 500 kbps, but the CPU now
starts executing instructions at a frequency of 5 MIPS.
9.2.3
9.4
INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a

PWRSAV instruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
9.3
Doze Mode
The preferred strategies for reducing power

consumption are changing clock speed and invoking
one of the power-saving modes. In some
circumstances, this may not be practical. For example,
it may be necessary for an application to maintain
uninterrupted synchronous communication, even while
it is doing nothing else. Reducing system clock speed
can introduce communication errors, while using a
power-saving mode can stop communications
completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
DS70283J-page 116
Peripheral Module Disable
The Peripheral Module Disable registers (PMD)

provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers will have no effect and read
values will be invalid.
A peripheral module is enabled only if both the
associated bit in the PMD register is cleared and the
peripheral is supported by the specific dsPIC DSC
variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
Note:
If a PMD bit is set, the corresponding

module is disabled after a delay of one
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of one instruction
cycle (assuming the module control
registers are already configured to enable
module operation).

REGISTER 9-1:
PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
T3MD
T2MD
T1MD
QEIMD
PWM1MD
bit 15
bit 8
R/W-0
U-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
I2C1MD
U1MD
SPI1MD
AD1MD(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-14
bit 13
T3MD: Timer3 Module Disable bit

1 = Timer3 module is disabled
0 = Timer3 module is enabled
bit 12

bit 11

bit 10
QEIMD: QEI Module Disable bit

1 = QEI module is disabled
0 = QEI module is enabled
bit 9
PWM1MD: PWM1 Module Disable bit

1 = PWM1 module is disabled
0 = PWM1 module is enabled
bit 8
bit 7
I2C1MD: I2C1 Module Disable bit

1 = I2C1 module is disabled
0 = I2C1 module is enabled
bit 6
bit 5
U1MD: UART1 Module Disable bit

1 = UART1 module is disabled
0 = UART1 module is enabled
bit 4
bit 3
SPI1MD: SPI1 Module Disable bit

1 = SPI1 module is disabled
0 = SPI1 module is enabled
bit 2-1
bit 0
AD1MD: ADC1 Module Disable bit(1)

1 = ADC1 module is disabled
0 = ADC1 module is enabled
Note 1:
x = Bit is unknown
PCFGx bits have no effect if the ADC module is disabled by setting this bit. In this case, all port pins
multiplexed with ANx will be in Digital mode.
DS70283J-page 117

REGISTER 9-2:
R/W-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
IC8MD
IC7MD
IC2MD
IC1MD
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
OC2MD
OC1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
IC8MD: Input Capture 8 Module Disable bit

1 = Input Capture 8 module is disabled
0 = Input Capture 8 module is enabled
bit 14

bit 13-10
bit 9

bit 8

bit 7-2
bit 1
OC2MD: Output Compare 2 Module Disable bit

1 = Output Compare 2 module is disabled
0 = Output Compare 2 module is enabled
bit 0
OC1MD: Output Compare 1 Module Disable bit

1 = Output Compare 1 module is disabled
0 = Output Compare 1 module is enabled
DS70283J-page 118
x = Bit is unknown

REGISTER 9-3:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
PWM2MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-5
bit 4
PWM2MD: PWM2 Module Disable bit

1 = PWM2 module is disabled
0 = PWM2 module is enabled
bit 3-0
x = Bit is unknown
DS70283J-page 119

NOTES:
DS70283J-page 120

10.0
I/O PORTS

10. I/O Ports (DS70193) of the
Manual, which is available on Microchip
web site (www.microchip.com).
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared among the peripherals and the
parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
10.1
Parallel I/O (PIO) Ports
Generally a parallel I/O port that shares a pin with a

peripheral is subservient to the peripheral. The
peripherals output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
FIGURE 10-1:
the I/O pin. The logic also prevents loop through, in

which a ports digital output can drive the input of a
peripheral that shares the same pin. Figure 10-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is disabled. If a peripheral is enabled, but the peripheral
is not actively driving a pin, that pin can be driven by a
port.
All port pins have three registers directly associated
with their operation as digital I/O. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a 1, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx) read the latch.
Writes to the latch write the latch. Reads from the port
(PORTx) read the port pins, while writes to the port pins
write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module
Output Multiplexers
Peripheral Input Data

Peripheral Module Enable
I/O
Peripheral Output Enable
Peripheral Output Data
PIO Module
WR TRIS
Output Data
Read TRIS
Data Bus
Output Enable
I/O Pin
CK
TRIS Latch
D
WR LAT +
WR Port
CK
Data Latch
Read LAT
Input Data
Read Port
DS70283J-page 121

10.2
Open-Drain Configuration
In addition to the PORT, LAT and TRIS registers for

data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired 5V
tolerant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
See the Pin Diagrams section for the available pins
and their functionality.
10.3
Configuring Analog Port Pins
The AD1PCFG and TRIS registers control the operation of the analog-to-digital (A/D) port pins. The port
pins that are to function as analog inputs must have
their corresponding TRIS bit set (input). If the TRIS bit
is cleared (output), the digital output level (VOH or VOL)
will be converted.
The AD1PCFGL register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
When the PORT register is read, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input
buffer to consume current that exceeds the device
specifications.
10.4
One instruction cycle is required between a port

direction change or port write operation and a read
operation of the same port. Typically this instruction
would be an NOP. Examples are shown in
Example 10-1 and Example 10-2. This also applies to
PORT bit operations, such as BSET PORTB, # RB0,
which are single cycle read-modify-write. All PORT bit
operations, such as MOV PORTB, W0 or BSET PORTB,
# RBx, read the pin and not the latch.
10.5
MOV
MOV
NOP
btss
Four control registers are associated with the CN module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
push-button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
Pull-ups on change notification pins
should always be disabled when the port
pin is configured as a digital output.
PORT WRITE/READ EXAMPLE
0xFF00, W0
W0, TRISBB
;
;
;
;
PORTB, #13
EXAMPLE 10-2:
Input Change Notification
The input change notification function of the I/O ports

allows
the
and
dsPIC33FJ16MC304 devices to generate interrupt
requests to the processor in response to a
change-of-state on selected input pins. This feature
can detect input change-of-states even in Sleep mode,
when the clocks are disabled. Depending on the device
pin count, up to 31 external signals (CNx pin) can be
selected (enabled) for generating an interrupt request
on a change-of-state.
Note:
EXAMPLE 10-1:
I/O Port Write/Read Timing
Configure PORTB<15:8> as inputs

and PORTB<7:0> as outputs
Delay 1 cycle
Next Instruction
PORT BIT OPERATIONS
Incorrect:
BSET
BSET
PORTB, #RB1
PORTB, #RB6
;Set PORTB<RB1> high

PORTB, #RB1
PORTB, #RB6
LATB, LATB1
LATB, LATB6

Correct:
BSET
NOP
BSET
NOP
Preferred:
BSET
BSET
DS70283J-page 122

10.6
Peripheral Pin Select
Peripheral pin select configuration enables peripheral

set selection and placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, programmers can better tailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
The peripheral pin select configuration feature
operates over a fixed subset of digital I/O pins.
Programmers can independently map the input and/or
output of most digital peripherals to any one of these
I/O pins. Peripheral pin select is performed in software,
and generally does not require the device to be
reprogrammed. Hardware safeguards are included that
prevent accidental or spurious changes to the
peripheral mapping, once it has been established.
10.6.1
AVAILABLE PINS
The peripheral pin select feature is used with a range

of up to 26 pins. The number of available pins depends
on the particular device and its pin count. Pins that
support the peripheral pin select feature include the
designation RPn in their full pin designation, where
RP designates a remappable peripheral and n is the
remappable pin number.
10.6.2
10.6.2.1
Figure 10-2 Illustrates remappable pin selection for

U1RX input.
Note:
The association of a peripheral to a peripheral

selectable pin is handled in two different ways,
depending on whether an input or output is being
mapped.
For input mapping only, the Peripheral Pin

Select (PPS) functionality does not have
priority over the TRISx settings. Therefore, when configuring the RPn pin for
input, the corresponding bit in the TRISx
register must also be configured for input
(i.e., set to 1).
FIGURE 10-2:
CONTROLLING PERIPHERAL PIN

SELECT
Peripheral pin select features are controlled through

two sets of special function registers: one to map
peripheral inputs, and one to map outputs. Because
they are separately controlled, a particular peripherals
input and output (if the peripheral has both) can be
placed on any selectable function pin without
constraint.
Input Mapping
The inputs of the peripheral pin select options are

mapped on the basis of the peripheral. A control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 10-1
through Register 10-13). Each register contains sets of
5-bit fields, with each set associated with one of the
remappable peripherals. Programming a given
peripherals bit field with an appropriate 5-bit value
maps the RPn pin with that value to that peripheral. For
any given device, the valid range of values for any bit
field corresponds to the maximum number of peripheral
pin selections supported by the device.
REMAPPABLE MUX
INPUT FOR U1RX
U1RXR<4:0>
0
RP0
1
RP1
2
U1RX input
to peripheral
RP2
25
RP25
DS70283J-page 123

SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)
TABLE 10-1:
Function Name
Register
Configuration
Bits
INT1
RPINR0
INT1R<4:0>
External Interrupt 2
INT2
RPINR1
INT2R<4:0>
Timer2 External Clock
T2CK
RPINR3
T2CKR<4:0>
Timer3 External Clock
T3CK
RPINR3
T3CKR<4:0>
IC1
RPINR7
IC1R<4:0>
Input Name
External Interrupt 1
Input Capture 1
Input Capture 2
IC2
RPINR7
IC2R<4:0>
Input Capture 7
IC7
RPINR10
IC7R<4:0>
Input Capture 8
IC8
RPINR10
IC8R<4:0>
OCFA
RPINR11
OCFAR<4:0>
PWM1 Fault
FLTA1
RPINR12
FLTA1R<4:0>
PWM2 Fault
FLTA2
RPINR13
FLTA2R<4:0>
QEI1 Phase A
QEA
RPINR14
QEA1R<4:0>
QEI1 Phase B
QEB
RPINR14
QEB1R<4:0>
Output Compare Fault A
QEI1 Index
INDX
RPINR15
INDX1R<4:0>
UART1 Receive
U1RX
RPINR18
U1RXR<4:0>
UART1 Clear To Send
U1CTS
RPINR18
U1CTSR<4:0>
SPI1 Data Input
SDI1
RPINR20
SDI1R<4:0>
SPI1 Clock Input
SCK1
RPINR20
SCK1R<4:0>
SS1
RPINR21
SS1R<4:0>
SPI1 Slave Select Input

Note 1:
Unless otherwise noted, all inputs use the Schmitt input buffers.
DS70283J-page 124

10.6.2.2
Output Mapping
FIGURE 10-3:
In contrast to inputs, the outputs of the peripheral pin

select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains sets
of 5-bit fields, with each set associated with one RPn
pin (see Register 10-14 through Register 10-26). The
value of the bit field corresponds to one of the peripherals, and that peripherals output is mapped to the pin
(see Table 10-2 and Figure 10-3).
The list of peripherals for output mapping also includes
a null value of 00000 because of the mapping technique. This permits any given pin to remain unconnected from the output of any of the pin selectable
peripherals.
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPn
RPnR<4:0>
Default
U1TX Output Enable
3
U1RTS Output Enable 4
Output Enable
OC2 Output Enable

UPDN Output Enable
Default
U1TX Output
U1RTS Output
19
26
0
3
4
RPn
Output Data
OC2 Output
UPDN Output
TABLE 10-2:
19
26
OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
Function
RPnR<4:0>
Output Name
NULL
00000
RPn tied to default port pin
U1TX
00011
RPn tied to UART1 Transmit
U1RTS
00100
RPn tied to UART1 Ready To Send
SDO1
00111
RPn tied to SPI1 Data Output
SCK1OUT
01000
RPn tied to SPI1 Clock Output
SS1OUT
01001
RPn tied to SPI1 Slave Select Output
OC1
10010
RPn tied to Output Compare 1
OC2
10011
RPn tied to Output Compare 2
UPDN
11010
RPn tied to QEI direction (UPDN) status
DS70283J-page 125

10.6.3
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. dsPIC33F devices include three features to
prevent alterations to the peripheral map:
Control register lock sequence
Continuous state monitoring
Configuration bit pin select lock
10.6.3.1
Control Register Lock
Under normal operation, writes to the RPINRx and

RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK bit
(OSCCON<6>). Setting IOLOCK prevents writes to the
control registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1.
2.
3.
Write 0x46 to OSCCON<7:0>.

Write 0x57 to OSCCON<7:0>.
Clear (or set) IOLOCK as a single operation.
Note:
10.6.3.2
Continuous State Monitoring
In addition to being protected from direct writes, the

contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a configuration mismatch Reset will
be triggered.
10.6.3.3
Configuration Bit Pin Select Lock
As an additional level of safety, the device can be

configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
(FOSC<IOL1WAY>) configuration bit blocks the
IOLOCK bit from being cleared after it has been set
once. If IOLOCK remains set, the register unlock
procedure will not execute, and the peripheral pin
select control registers cannot be written to. The only
way to clear the bit and re-enable peripheral remapping
is to perform a device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
peripheral pin select registers.
MPLAB C30 provides built-in C

language functions for unlocking the
OSCCON register:
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
See MPLAB Help for more information.

Unlike the similar sequence with the oscillators LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
DS70283J-page 126

10.7
Peripheral Pin Select Registers
The
and
dsPIC33FJ16MC304 family of devices implement 21
registers for remappable peripheral configuration:
Input Remappable Peripheral Registers (13)
Output Remappable Peripheral Registers (8)
Note:
Input and Output Register values can only

be changed if OSCCON[IOLOCK] = 0.
See Section 10.6.3.1 Control Register
Lock for a specific command sequence.
REGISTER 10-1:
RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT1R<4:0>
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin bits
11111 = Input tied VSS
11001 = Input tied to RP25
.
.
.
bit 7-0
DS70283J-page 127

REGISTER 10-2:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT2R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4-0
INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin bits
.
.
.
DS70283J-page 128

REGISTER 10-3:
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T3CKR<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T2CKR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the corresponding RPn pin bits
.
.
.
bit 7-5
bit 4-0
T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin bits
.
.
.
DS70283J-page 129

REGISTER 10-4:
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IC2R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IC1R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
IC2R<4:0>: Assign Input Capture 2 (IC2) to the corresponding RPn pin bits
.
.
.
bit 7-5
bit 4-0
IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin bits
.
.
.
DS70283J-page 130

REGISTER 10-5:
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IC8R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IC7R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
IC8R<4:0>: Assign Input Capture 8 (IC8) to the corresponding pin RPn pin bits
.
.
.
bit 7-5
bit 4-0
IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding pin RPn pin bits
.
.
.
DS70283J-page 131

REGISTER 10-6:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
OCFAR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4-0
OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin bits
.
.
.
REGISTER 10-7:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTA1R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4-0
FLTA1R<4:0>: Assign PWM1 Fault (FLTA1) to the corresponding RPn pin bits
.
.
.
DS70283J-page 132

REGISTER 10-8:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTA2R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4-0
FLTA2R<4:0>: Assign PWM2 Fault (FLTA2) to the corresponding RPn pin bits
.
.
.
DS70283J-page 133

REGISTER 10-9:
RPINR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
QEB1R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
QEA1R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-13
bit 12-8
QEB1R<4:0>: Assign B (QEB) to the corresponding pin bits

.
.
.
bit 7-5
bit 4-0
QEA1R<4:0>: Assign A(QEA) to the corresponding pin bits

.
.
.
DS70283J-page 134
x = Bit is unknown

REGISTER 10-10: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INDX1R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4-0
INDX1R<4:0>: Assign QEI INDEX (INDX) to the corresponding RPn pin bits
.
.
.
DS70283J-page 135

U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U1CTSR<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U1RXR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
U1CTSR<4:0>: Assign UART1 Clear to Send (U1CTS) to the corresponding RPn pin bits
.
.
.
bit 7-5
bit 4-0
U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin bits
.
.
.
DS70283J-page 136

U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SCK1R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SDI1R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
SCK1R<4:0>: Assign SPI1 Clock Input (SCK1IN) to the corresponding RPn pin bits
.
.
.
bit 7-5
bit 4-0
SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin bits
.
.
.
DS70283J-page 137

U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SS1R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4-0
SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin bits
.
.
.
DS70283J-page 138

REGISTER 10-14: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP1R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP0R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 10-2 for
peripheral function numbers)
bit 7-5
bit 4-0

U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP3R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP2R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-5
bit 4-0
DS70283J-page 139

U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP5R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP4R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-5
bit 4-0

U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP7R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP6R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-5
bit 4-0
DS70283J-page 140

U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP9R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP8R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-5
bit 4-0

U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP11R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP10R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-5
bit 4-0
DS70283J-page 141

U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP13R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP12R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-5
bit 4-0

U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP15R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP14R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-5
bit 4-0
DS70283J-page 142

U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP17R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP16R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-5
bit 4-0

U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP19R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP18R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-5
bit 4-0
DS70283J-page 143

U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP21R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP20R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-5
bit 4-0

U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP23R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP22R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-5
bit 4-0
DS70283J-page 144

U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP25R<4:0>
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP24R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-5
bit 4-0
DS70283J-page 145

NOTES:
DS70283J-page 146

11.0
TIMER1
Timer1 also supports these features:

Timer gate operation
Selectable prescaler settings
Timer operation during CPU Idle and Sleep
modes
Interrupt on 16-bit Period register match or falling
edge of external gate signal

Section 11. Timers (DS70205) of the
Manual, which is available from the Microchip web site (www.microchip.com).
Figure 11-1 presents a block diagram of the 16-bit timer

module.
To configure Timer1 for operation:
1.
2.

3.
4.
The Timer1 module is a 16-bit timer, which can serve

as the time counter for the real-time clock, or operate
as a free-running interval timer/counter. Timer1 can
operate in three modes:
5.
6.
16-bit Timer
16-bit Synchronous Counter
16-bit Asynchronous Counter
FIGURE 11-1:
Set the TON bit (= 1) in the T1CON register.

Select the timer prescaler ratio using the
TCKPS<1:0> bits in the T1CON register.
Set the Clock and Gating modes using the TCS
and TGATE bits in the T1CON register.
Set or clear the TSYNC bit in T1CON to select
synchronous or asynchronous operation.
Load the timer period value into the PR1
register.
If interrupts are required, set the interrupt enable
bit, T1IE. Use the priority bits, T1IP<2:0>, to set
the interrupt priority.
16-BIT TIMER1 MODULE BLOCK DIAGRAM

TCKPS<1:0>
2
TON
SOSCO/
T1CK
1x
SOSCEN
SOSCI
Gate
Sync
01
TCY
00
Prescaler
1, 8, 64, 256
TGATE
TCS
TGATE
CK
Set T1IF
Reset
0
TMR1
1
Comparator
Sync
TSYNC
Equal
PR1
DS70283J-page 147

REGISTER 11-1:
T1CON: TIMER1 CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON
TSIDL
bit 15
bit 8
U-0
R/W-0
TGATE
R/W-0
R/W-0
TCKPS<1:0>
U-0
R/W-0
R/W-0
U-0
TSYNC
TCS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
TON: Timer1 On bit

1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 14
bit 13
TSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-7
bit 6
TGATE: Timer1 Gated Time Accumulation Enable bit

When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
bit 5-4
TCKPS<1:0> Timer1 Input Clock Prescale Select bits

11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
bit 2
TSYNC: Timer1 External Clock Input Synchronization Select bit

When TCS = 1:
1 = Synchronize external clock input
0 = Do not synchronize external clock input
When TCS = 0:
bit 1
TCS: Timer1 Clock Source Select bit

1 = External clock from pin T1CK (on the rising edge)
0 = Internal clock (FCY)
bit 0
DS70283J-page 148
x = Bit is unknown

12.0
TIMER2/3 FEATURE

Section 11. Timers (DS70205) of the
The Timer2/3 feature has three 2-bit timers that can
also be configured as two independent 16-bit timers
with selectable operating modes.
As a 32-bit timer, the Timer2/3 feature permits
operation in three modes:
Two Independent 16-bit timers (e.g., Timer2 and
Timer3) with all 16-bit operating modes (except
Asynchronous Counter mode)
Single 32-bit timer (Timer2/3)
Single 32-bit synchronous counter (Timer2/3)
12.1
To configure the Timer2/3 feature timers for 32-bit

operation:
1.
2.
3.
4.
5.
6.
Timer gate operation

Selectable prescaler settings
Timer operation during Idle and Sleep modes
Interrupt on a 32-bit period register match
Time base for Input Capture and Output Compare
modules (Timer2 and Timer3 only)
ADC1 event trigger (Timer2/3 only)
Individually, all eight of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the event trigger. The
operating modes and enabled features are determined
by setting the appropriate bit(s) in the T2CON, T3CON
registers. T2CON registers are shown in generic form
in Register 12-1. T3CON registers are shown in
Register 12-2.
Set the T32 control bit.

Select the prescaler ratio for Timer2 using the
TCKPS<1:0> bits.
Set the Clock and Gating modes using the
corresponding TCS and TGATE bits.
Load the timer period value. PR3 contains the
most significant word of the value, while PR2
contains the least significant word.
bit, T3IE. Use the priority bits, T3IP<2:0>, to set
the interrupt priority. While Timer2 controls the
timer, the interrupt appears as a Timer3
interrupt.
Set the corresponding TON bit.
The timer value at any point is stored in the register

pair, TMR3:TMR2, which always contains the most significant word of the count, while TMR2 contains the
least significant word.
12.2
16-bit Operation
To configure any of the timers for individual 16-bit

operation:
1.
2.
The Timer2/3 feature also supports:
32-bit Operation
3.
4.
5.
6.
Clear the T32 bit corresponding to that timer.

Select the timer prescaler ratio using the
TCKPS<1:0> bits.
Set the Clock and Gating modes using the TCS
and TGATE bits.
Load the timer period value into the PRx
register.
bit, TxIE. Use the priority bits, TxIP<2:0>, to set
the interrupt priority.
Set the TON bit.
For 32-bit timer/counter operation, Timer2 is the least

significant word (lsw), and Timer3 is the most
significant word (msw) of the 32-bit timers.
Note:
For 32-bit operation, T3CON control bits

are ignored. Only T2CON control bits are
used for setup and control. Timer2 clock
and gate inputs are used for the 32-bit
timer modules, but an interrupt is
generated with the Timer3 interrupt flags.
DS70283J-page 149

TIMER2/3 (32-BIT) BLOCK DIAGRAM(1)
FIGURE 12-1:
T2CK
1x
Gate
Sync
01
TCY
00
TCKPS<1:0>
2
TON
Prescaler
1, 8, 64, 256
TGATE
TCS
TGATE
1
Set T3IF
D
CK
0
PR3
ADC Event Trigger(2)
Equal
PR2
Comparator
MSb
LSb
TMR3
Reset
TMR2
Sync
16
Read TMR2
Write TMR2
16
16
TMR3HLD
16
Data Bus<15:0>
Note 1:
2:
The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective
to the T2CON register.
The ADC event trigger is available only on Timer2/3.
DS70283J-page 150

FIGURE 12-2:
TIMER2 (16-BIT) BLOCK DIAGRAM
TON
T2CK
TCKPS<1:0>
2
1x
Gate
Sync
Prescaler
1, 8, 64, 256
01
00
TGATE
TCS
TCY
1
Set T2IF
0
Reset
CK
TMR2
TGATE
Sync
Comparator
Equal
PR2
DS70283J-page 151

REGISTER 12-1:
T2CON CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON
TSIDL
bit 15
bit 8
U-0
R/W-0
TGATE
R/W-0
R/W-0
TCKPS<1:0>
R/W-0
U-0
R/W-0
U-0
T32
TCS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
TON: Timer2 On bit

When T32 = 1:
1 = Starts 32-bit Timer2/3
0 = Stops 32-bit Timer2/3
When T32 = 0:
bit 14
bit 13
TSIDL: Stop in Idle Mode bit

bit 12-7
bit 6
TGATE: Timer2 Gated Time Accumulation Enable bit

When TCS = 1:
When TCS = 0:
bit 5-4
TCKPS<1:0>: Timer2 Input Clock Prescale Select bits

11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
T32: 32-bit Timer Mode Select bit

1 = Timer2 and Timer3 form a single 32-bit timer
0 = Timer2 and Timer3 act as two 16-bit timers
bit 2
bit 1
TCS: Timer2 Clock Source Select bit

1 = External clock from pin T2CK (on the rising edge)
0 = Internal clock (FCY)
bit 0
DS70283J-page 152
x = Bit is unknown

REGISTER 12-2:
R/W-0
T3CON CONTROL REGISTER

U-0
TON(2)
R/W-0
U-0
U-0
U-0
U-0
U-0
(1)
TSIDL
bit 15
bit 8
U-0
R/W-0
R/W-0
(2)
TGATE
R/W-0
TCKPS<1:0>
(2)
U-0
U-0
R/W-0
(2)
TCS
bit 7
U-0
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
TON: Timer3 On bit(2)

bit 14
bit 13
TSIDL: Stop in Idle Mode bit(1)

1 = Discontinue timer operation when device enters Idle mode
0 = Continue timer operation in Idle mode
bit 12-7
bit 6
TGATE: Timer3 Gated Time Accumulation Enable bit(2)

When TCS = 1:
When TCS = 0:
bit 5-4
TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(2)

11 = 1:256 prescale value
bit 3-2
bit 1
TCS: Timer3 Clock Source Select bit(2)

1 = External clock from T3CK pin
0 = Internal clock (FOSC/2)
bit 0
Note 1:
2:
x = Bit is unknown
When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit
must be cleared to operate the 32-bit timer in Idle mode.
When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), these bits
have no effect.
DS70283J-page 153

NOTES:
DS70283J-page 154

13.0
INPUT CAPTURE
1.

Section 12. Input Capture (DS70198)
of the dsPIC33F/PIC24H Family Reference Manual, which is available from the
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
devices support up to eight input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
FIGURE 13-1:
Simple Capture Event modes:

- Capture timer value on every falling edge of
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
2. Capture timer value on every edge (rising and
falling).
3. Prescaler Capture Event modes:
- Capture timer value on every 4th rising edge
of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select one of two
16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
Other operational features include:
Device wake-up from capture pin during CPU
Sleep and Idle modes
Interrupt on input capture event
4-word FIFO buffer for capture values
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
Use of input capture to provide additional sources
of external interrupts
INPUT CAPTURE BLOCK DIAGRAM

From 16-bit Timers
TMR2 TMR3
16
16
1
Edge Detection Logic
and
Clock Synchronizer
Prescaler
Counter
(1, 4, 16)
FIFO
R/W
Logic
ICTMR
(ICxCON<7>)
ICx Pin
ICM<2:0> (ICxCON<2:0>)
Mode Select
FIFO
ICOV, ICBNE (ICxCON<4:3>)

ICxBUF
ICxI<1:0>
ICxCON
Interrupt
Logic
System Bus
Set Flag ICxIF
(in IFSn Register)
Note: An x in a signal, register or bit name denotes the number of the capture channel.
DS70283J-page 155

13.1
Input Capture Registers
REGISTER 13-1:
ICxCON: INPUT CAPTURE x CONTROL REGISTER
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ICSIDL
bit 15
bit 8
R/W-0
R/W-0
ICTMR
R/W-0
ICI<1:0>
R-0, HC
R-0, HC
ICOV
ICBNE
R/W-0
R/W-0
R/W-0
ICM<2:0>
bit 7
bit 0
Legend:
HC = Cleared in Hardware
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
ICSIDL: Input Capture Module Stop in Idle Control bit

1 = Input capture module will halt in CPU Idle mode
0 = Input capture module will continue to operate in CPU Idle mode
bit 12-8
bit 7
ICTMR: Input Capture Timer Select bits

1 = TMR2 contents are captured on capture event
0 = TMR3 contents are captured on capture event
bit 6-5
ICI<1:0>: Select Number of Captures per Interrupt bits

11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4
ICOV: Input Capture Overflow Status Flag bit (read-only)

1 = Input capture overflow occurred
0 = No input capture overflow occurred
bit 3
ICBNE: Input Capture Buffer Empty Status bit (read-only)

1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0
ICM<2:0>: Input Capture Mode Select bits

111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode
(Rising edge detect only, all other control bits are not applicable.)
110 = Unused (module disabled)
101 = Capture mode, every 16th rising edge
100 = Capture mode, every 4th rising edge
011 = Capture mode, every rising edge
010 = Capture mode, every falling edge
001 = Capture mode, every edge (rising and falling)
(ICI<1:0> bits do not control interrupt generation for this mode.)
000 = Input capture module turned off
DS70283J-page 156

14.0
OUTPUT COMPARE
The Output Compare module can select either Timer2

or Timer3 for its time base. The module compares the
value of the timer with the value of one or two compare
registers depending on the operating mode selected.
The state of the output pin changes when the timer
value matches the compare register value. The Output
Compare module generates either a single output
pulse or a sequence of output pulses, by changing the
state of the output pin on the compare match events.
The Output Compare module can also generate
interrupts on compare match events.

Section 13. Output Compare
Family Reference Manual, which is
available from the Microchip web site
The Output Compare module has multiple operating

modes:

FIGURE 14-1:
Active-Low One-Shot mode

Active-High One-Shot mode
Toggle mode
Delayed One-Shot mode
Continuous Pulse mode
PWM mode without fault protection
PWM mode with fault protection
OUTPUT COMPARE MODULE BLOCK DIAGRAM

Set Flag bit
OCxIF
OCxRS
Output
Logic
OCxR
S Q
R
3
OCM<2:0>
Mode Select
Comparator
0
16
OCTSEL
Output
Enable
OCx
Output
Enable
Logic
OCFA
16
TMR2 TMR3
TMR2
Rollover
TMR3
Rollover
DS70283J-page 157

14.1
Output Compare Modes
application must disable the associated timer when

writing to the output compare control registers to avoid
malfunctions.
Configure the Output Compare modes by setting the

appropriate Output Compare Mode bits (OCM<2:0>) in
the Output Compare Control register (OCxCON<2:0>).
Table 14-1 lists the different bit settings for the Output
Compare modes. Figure 14-2 illustrates the output
compare operation for various modes. The user
TABLE 14-1:
Note:
See Section 13. Output Compare

(DS70209) in the dsPIC33F/PIC24H
Family Reference Manual (DS70209) for
OCxR and OCxRS register restrictions.
OUTPUT COMPARE MODES
OCM<2:0>
Mode
000
Module Disabled
001
Active-Low One-Shot
010
Active-High One-Shot
011
Toggle Mode
OCx Pin Initial State
OCx Interrupt Generation
Controlled by GPIO register

0
1
Current output is maintained
OCx Rising edge

OCx Falling edge
OCx Rising and Falling edge
100
Delayed One-Shot
OCx Falling edge
101
Continuous Pulse mode
OCx Falling edge
110
PWM mode without fault

protection
111
PWM mode with fault protection 0, if OCxR is zero

1, if OCxR is non-zero
FIGURE 14-2:
0, if OCxR is zero
1, if OCxR is non-zero
No interrupt
OCFA Falling edge for OC1 to OC4
OUTPUT COMPARE OPERATION

Output Compare
Mode enabled
Timer is reset on
period match
OCxRS
TMRy
OCxR
Active-Low One-Shot
(OCM = 001)
Active-High One-Shot
(OCM = 010)
Toggle Mode
(OCM = 011)
Delayed One-Shot
(OCM = 100)
Continuous Pulse Mode
(OCM = 101)
PWM Mode
(OCM = 110 or 111)
DS70283J-page 158

REGISTER 14-1:
OCxCON: OUTPUT COMPARE x CONTROL REGISTER
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
OCSIDL
bit 15
bit 8
U-0
U-0
U-0
R-0 HC
R/W-0
OCFLT
OCTSEL
R/W-0
R/W-0
R/W-0
OCM<2:0>
bit 7
bit 0
Legend:
HC = Cleared in Hardware
HS = Set in Hardware
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
OCSIDL: Stop Output Compare in Idle Mode Control bit

1 = Output Compare x will halt in CPU Idle mode
0 = Output Compare x will continue to operate in CPU Idle mode
bit 12-5
bit 4
OCFLT: PWM Fault Condition Status bit

1 = PWM Fault condition has occurred (cleared in hardware only)
0 = No PWM Fault condition has occurred
(This bit is only used when OCM<2:0> = 111.)
bit 3
OCTSEL: Output Compare Timer Select bit

1 = Timer3 is the clock source for Compare x
0 = Timer2 is the clock source for Compare x
bit 2-0
OCM<2:0>: Output Compare Mode Select bits

111 = PWM mode on OCx, Fault pin enabled
110 = PWM mode on OCx, Fault pin disabled
101 = Initialize OCx pin low, generate continuous output pulses on OCx pin
100 = Initialize OCx pin low, generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high, compare event forces OCx pin low
001 = Initialize OCx pin low, compare event forces OCx pin high
000 = Output compare channel is disabled
DS70283J-page 159

NOTES:
DS70283J-page 160

15.0
MOTOR CONTROL PWM

MODULE

Section 14. Motor Control PWM
Family Reference Manual, which is
available from the Microchip web site
device supports up to two dedicated Pulse-Width
Modulation (PWM) modules. The PWM1 module is a
6-channel PWM generator, and the PWM2 module is a
2-channel PWM generator.
The PWM module has the following features:
Up to 16-bit resolution.
On-the-fly PWM frequency changes.
Edge and Center-Aligned Output modes.
Single Pulse Generation mode.
Interrupt support for asymmetrical updates in
Center-Aligned mode.
Output override control for Electrically
Commutative Motor (ECM) operation or BLDC.
Special Event comparator for scheduling other
peripheral events.
Fault pins to optionally drive each of the PWM
output pins to a defined state.
15.1
PWM1: 6-Channel PWM Module
This module simplifies the task of generating multiple

synchronized PWM outputs. The following power and
motion control applications are supported by the PWM
module:
3-Phase AC Induction Motor

Switched Reluctance (SR) Motor
Brushless DC (BLDC) Motor
Uninterruptible Power Supply (UPS)
This module contains three duty cycle generators,

numbered 1 through 3. The module has six PWM
output pins, numbered PWM1H1/PWM1L1 through
PWM1H3/PWM1L3. The six I/O pins are grouped into
high/low numbered pairs, denoted by the suffix H or L,
respectively. For complementary loads, the low PWM
pins are always the complement of the corresponding
high I/O pin.
15.2
PWM2: 2-Channel PWM Module
This module provides an additional pair

complimentary PWM outputs that can be used for:
of
Independent PFC correction in a motor system

Induction cooking
This module contains a duty cycle generator that
provides
two
PWM
outputs,
numbered
PWM2H1/PWM2L1.
Duty cycle updates configurable to be immediate or

synchronized to the PWM time base.
DS70283J-page 161

FIGURE 15-1:
6-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM1)
PWM1CON1
PWM Enable and Mode SFRs
PWM1CON2
P1DTCON1
Dead-Time Control SFRs
P1DTCON2
P1FLTACON
Fault Pin Control SFRs
P1OVDCON
PWM Manual
Control SFR
PWM Generator 3
16-bit Data Bus
P1DC3 Buffer
P1DC3
Comparator
PWM
Generator 2
P1TMR
Channel 3 Dead-Time
Generator and
Override Logic
PWM1H3
Channel 2 Dead-Time
Generator and
Override Logic
PWM1H2
PWM1L3
Output
PWM1L2
Driver
Comparator
PWM
Generator 1
P1TPER
Channel 1 Dead-Time
Generator and
Override Logic
Block
PWM1H1
PWM1L1
P1TPER Buffer
FLTA1
P1TCON
Comparator
SEVTDIR
P1SECMP
Special Event
Postscaler
Special Event Trigger
PTDIR
PWM Time Base
Note:
Details of PWM Generator 1and PWM Generator 2 are not shown for clarity.
DS70283J-page 162

FIGURE 15-2:
2-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM2)
PWM2CON1
PWM Enable and Mode SFRs
PWM2CON2
P2DTCON1
Dead-Time Control SFRs
P2DTCON2
P2FLTACON
Fault Pin Control SFRs
P2OVDCON
PWM Manual
Control SFR
PWM Generator 1
16-bit Data Bus
P2DC1Buffer
P2DC1
Comparator
PWM2H1
Channel 1 Dead-Time
Generator and
Override Logic
PWM2L1
P2TMR
Output
Driver
Comparator
Block
P2TPER
P2TPER Buffer
FLTA2
P2TCON
Comparator
SEVTDIR
P2SECMP
Special Event
Postscaler
Special Event Trigger
PTDIR
PWM Time Base
DS70283J-page 163

REGISTER 15-1:
PxTCON: PWM TIME BASE CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
PTEN
PTSIDL
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTOPS<3:0>
R/W-0
R/W-0
PTCKPS<1:0>
R/W-0
PTMOD<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
PTEN: PWM Time Base Timer Enable bit

1 = PWM time base is on
0 = PWM time base is off
bit 14
bit 13
PTSIDL: PWM Time Base Stop in Idle Mode bit

1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
bit 12-8
bit 7-4
PTOPS<3:0>: PWM Time Base Output Postscale Select bits

1111 = 1:16 postscale

bit 3-2
PTCKPS<1:0>: PWM Time Base Input Clock Prescale Select bits

11 = PWM time base input clock period is 64 TCY (1:64 prescale)
00 = PWM time base input clock period is TCY (1:1 prescale)
bit 1-0
PTMOD<1:0>: PWM Time Base Mode Select bits

11 = PWM time base operates in a Continuous Up/Down Count mode with interrupts for double
PWM updates
10 = PWM time base operates in a Continuous Up/Down Count mode
01 = PWM time base operates in Single Pulse mode
00 = PWM time base operates in a Free-Running mode
DS70283J-page 164

REGISTER 15-2:
R-0
PxTMR: PWM TIMER COUNT VALUE REGISTER

R/W-0
R/W-0
R/W-0
PTDIR
R/W-0
R/W-0
R/W-0
R/W-0
PTMR<14:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTMR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
PTDIR: PWM Time Base Count Direction Status bit (read-only)

1 = PWM time base is counting down
0 = PWM time base is counting up
bit 14-0
PTMR <14:0>: PWM Time Base Register Count Value bits
REGISTER 15-3:
U-0
PxTPER: PWM TIME BASE PERIOD REGISTER

R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTPER<14:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTPER<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
bit 14-0
PTPER<14:0>: PWM Time Base Period Value bits
x = Bit is unknown
DS70283J-page 165

REGISTER 15-4:
R/W-0
PxSECMP: SPECIAL EVENT COMPARE REGISTER

R/W-0
R/W-0
R/W-0
SEVTDIR(1)
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP<14:8>(2)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP<7:0>(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
SEVTDIR: Special Event Trigger Time Base Direction bit(1)

1 = A Special Event Trigger will occur when the PWM time base is counting downward
0 = A Special Event Trigger will occur when the PWM time base is counting upward
bit 14-0
SEVTCMP<14:0>: Special Event Compare Value bits(2)
Note 1:
2:
SEVTDIR is compared with PTDIR (PXTMR<15>) to generate the Special Event Trigger.
PxSECMP<14:0> is compared with PXTMR<14:0> to generate the Special Event Trigger.
DS70283J-page 166

REGISTER 15-5:
PWMxCON1: PWM CONTROL REGISTER 1(2)
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
PMOD3
PMOD2
PMOD1
bit 15
bit 8
U-0
R/W-1
(1)
PEN3H
R/W-1
(1)
PEN2H
R/W-1
(1)
PEN1H
U-0
R/W-1
(1)
PEN3L
R/W-1
(1)
PEN2L
R/W-1
PEN1L(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-11
bit 10-8
PMOD3:PMOD1: PWM I/O Pair Mode bits

1 = PWM I/O pin pair is in the Independent PWM Output mode
0 = PWM I/O pin pair is in the Complementary Output mode
bit 7
bit 6-4
PEN3H:PEN1H: PWMxH I/O Enable bits(1)

1 = PWMxH pin is enabled for PWM output
0 = PWMxH pin disabled, I/O pin becomes general purpose I/O
bit 3
bit 2-0
PEN3L:PEN1L: PWMxL I/O Enable bits(1)

1 = PWMxL pin is enabled for PWM output
0 = PWMxL pin disabled, I/O pin becomes general purpose I/O
Note 1:
2:
x = Bit is unknown
Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in
the FPOR Configuration register.
PWM2 supports only 1 PWM I/O pin pair.
DS70283J-page 167

REGISTER 15-6:
PWMxCON2: PWM CONTROL REGISTER 2
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVOPS<3:0>
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
IUE
OSYNC
UDIS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-12
bit 11-8
SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits


bit 7-3
bit 2
IUE: Immediate Update Enable bit

1 = Updates to the active PxDC registers are immediate
0 = Updates to the active PxDC registers are synchronized to the PWM time base
bit 1
OSYNC: Output Override Synchronization bit

1 = Output overrides via the PxOVDCON register are synchronized to the PWM time base
0 = Output overrides via the PxOVDCON register occur on next TCY boundary
bit 0
UDIS: PWM Update Disable bit

1 = Updates from Duty Cycle and Period Buffer registers are disabled
0 = Updates from Duty Cycle and Period Buffer registers are enabled
DS70283J-page 168

REGISTER 15-7:
R/W-0
PxDTCON1: DEAD-TIME CONTROL REGISTER 1

R/W-0
R/W-0
R/W-0
DTBPS<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
DTB<5:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
DTAPS<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTA<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-14
DTBPS<1:0>: Dead-Time Unit B Prescale Select bits

11 = Clock period for Dead-Time Unit B is 8 TCY
00 = Clock period for Dead-Time Unit B is TCY
bit 13-8
DTB<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit B bits
bit 7-6
DTAPS<1:0>: Dead-Time Unit A Prescale Select bits

11 = Clock period for Dead-Time Unit A is 8 TCY
00 = Clock period for Dead-Time Unit A is TCY
bit 5-0
DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits
x = Bit is unknown
DS70283J-page 169

REGISTER 15-8:
PxDTCON2: DEAD-TIME CONTROL REGISTER 2(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTS3A
DTS3I
DTS2A
DTS2I
DTS1A
DTS1I
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-6
bit 5
DTS3A: Dead-Time Select for PWM3 Signal Going Active bit

1 = Dead time provided from Unit B
0 = Dead time provided from Unit A
bit 4
DTS3I: Dead-Time Select for PWM3 Signal Going Inactive bit

bit 3

bit 2

bit 1

bit 0

Note 1:
x = Bit is unknown
DS70283J-page 170

REGISTER 15-9:
PxFLTACON: FAULT A CONTROL REGISTER(1)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FAOV3H
FAOV3L
FAOV2H
FAOV2L
FAOV1H
FAOV1L
bit 15
bit 8
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
FLTAM
FAEN3
FAEN2
FAEN1
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13-8
FAOVxH<3:1>:FAOVxL<3:1>: Fault Input A PWM Override Value bits

1 = The PWM output pin is driven active on an external Fault input event
0 = The PWM output pin is driven inactive on an external Fault input event
bit 7
FLTAM: Fault A Mode bit

1 = The Fault A input pin functions in the Cycle-by-Cycle mode
0 = The Fault A input pin latches all control pins to the programmed states in PxFLTACON<13:8>
bit 6-3
bit 2
FAEN3: Fault Input A Enable bit

1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input A
0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input A
bit 1

bit 0

Note 1:
DS70283J-page 171

REGISTER 15-10: PxOVDCON: OVERRIDE CONTROL REGISTER(1)
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
POVD3H
POVD3L
POVD2H
POVD2L
POVD1H
POVD1L
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POUT3H
POUT3L
POUT2H
POUT2L
POUT1H
POUT1L
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13-8
POVDxH<3:1>:POVDxL<3:1>: PWM Output Override bits

1 = Output on PWMx I/O pin is controlled by the PWM generator
0 = Output on PWMx I/O pin is controlled by the value in the corresponding POUTxH:POUTxL bit
bit 7-6
bit 5-0
POUTxH<3:1>:POUTxL<3:1>: PWM Manual Output bits

1 = PWMx I/O pin is driven active when the corresponding POVDxH:POVDxL bit is cleared
0 = PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bit is cleared
Note 1:
DS70283J-page 172

REGISTER 15-11: PxDC1: PWM DUTY CYCLE REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDC1<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDC1<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-0
x = Bit is unknown
PDC1<15:0>: PWM Duty Cycle 1 Value bits
REGISTER 15-12: P1DC2: PWM DUTY CYCLE REGISTER 2

R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDC2<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDC2<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-0
x = Bit is unknown
REGISTER 15-13: P1DC3: PWM DUTY CYCLE REGISTER 3

R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDC3<15:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDC3<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-0
x = Bit is unknown
DS70283J-page 173

NOTES:
DS70283J-page 174

16.0
QUADRATURE ENCODER
INTERFACE (QEI) MODULE
This section describes the Quadrature Encoder Interface (QEI) module and associated operational modes.
The QEI module provides the interface to incremental
encoders for obtaining mechanical position data.

Section 15. Quadrature Encoder
Interface (QEI) (DS70208) of the
Microchip website (www.microchip.com).
The operational features of the QEI include:

Three input channels for two phase signals and
index pulse
16-bit up/down position counter
Count direction status
Position Measurement (x2 and x4) mode
Programmable digital noise filters on inputs
Alternate 16-bit Timer/Counter mode
Quadrature Encoder Interface interrupts

FIGURE 16-1:
These operating modes are determined by setting the

appropriate bits, QEIM<2:0> in (QEIxCON<10:8>).
Figure 16-1 depicts the Quadrature Encoder Interface
block diagram.
QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM

TQCKPS<1:0>
Sleep Input
TQCS
TCY
Synchronize
Det
Prescaler
1, 8, 64, 256
1
1
QEIM<2:0>
0
D
TQGATE
CK
QEAx
Programmable
Digital Filter
UPDN_SRC
0
QEIxCON<11>
QEBx
Programmable
Digital Filter
INDXx
Programmable
Digital Filter
PCDOUT
0
1
Quadrature
Encoder
Interface Logic
16-bit Up/Down Counter

(POSCNT)
Reset
Comparator/
Zero Detect
Equal
3
QEIM<2:0>
Mode Select
UPDNx
QEIIF
Event
Flag
Max Count Register

(MAXCNT)
Existing Pin Logic

Up/Down
DS70283J-page 175

16.1
Control and Status Registers
The QEI module has four user-accessible registers,

accessible in either Byte or Word mode:
Control/Status Register (QEICON) Allows
control of the QEI operation and status flags
indicating the module state.
Digital Filter Control Register (DFLTCON)
Allows control of the digital input filter operation.
Position Count Register (POSCNT) Allows
reading and writing of the 16-bit position counter.
Maximum Count Register (MAXCNT) Holds a
value that is compared to the POSCNT counter in
some operations.
Note:
The POSCNT register allows byte

accesses. However, reading the register
in Byte mode can result in partially
updated values in subsequent reads.
Either use Word mode reads/writes, or
ensure that the counter is not counting
during Byte operations.
DS70283J-page 176

REGISTER 16-1:
QEIxCON: QEI CONTROL REGISTER
R/W-0
U-0
R/W-0
R-0
R/W-0
CNTERR
QEISIDL
INDEX
UPDN
R/W-0
R/W-0
R/W-0
QEIM<2:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
SWPAB
PCDOUT
TQGATE
R/W-0
R/W-0
TQCKPS<1:0>
R/W-0
R/W-0
R/W-0
POSRES
TQCS
UPDN_SRC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
CNTERR: Count Error Status Flag bit

1 = Position count error has occurred
0 = No position count error has occurred
bit 14
bit 13
QEISIDL: Stop in Idle Mode bit

bit 12
INDEX: Index Pin State Status bit (Read-Only)

1 = Index pin is High
0 = Index pin is Low
bit 11
UPDN: Position Counter Direction Status bit

1 = Position Counter Direction is positive (+)
0 = Position Counter Direction is negative (-)
(Read-only bit when QEIM<2:0> = 1XX)
(Read/Write bit when QEIM<2:0> = 001)
bit 10-8
QEIM<2:0>: Quadrature Encoder Interface Mode Select bits

111 = Quadrature Encoder Interface enabled (x4 mode) with position counter reset by match
(MAXCNT)
110 = Quadrature Encoder Interface enabled (x4 mode) with Index Pulse reset of position counter
101 = Quadrature Encoder Interface enabled (x2 mode) with position counter reset by match
(MAXCNT)
100 = Quadrature Encoder Interface enabled (x2 mode) with Index Pulse reset of position counter
011 = Unused (Module disabled)
010 = Unused (Module disabled)
001 = Starts 16-bit Timer
000 = Quadrature Encoder Interface/Timer off
bit 7
SWPAB: Phase A and Phase B Input Swap Select bit

1 = Phase A and Phase B inputs swapped
0 = Phase A and Phase B inputs not swapped
bit 6
PCDOUT: Position Counter Direction State Output Enable bit

1 = Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin)
0 = Position Counter Direction Status Output Disabled (Normal I/O pin operation)
bit 5
TQGATE: Timer Gated Time Accumulation Enable bit

1 = Timer gated time accumulation enabled
0 = Timer gated time accumulation disabled
Note:
CNTERR flag only applies when QEIM<2:0> = 110 or 100.
DS70283J-page 177

REGISTER 16-1:
QEIxCON: QEI CONTROL REGISTER (CONTINUED)
bit 4-3
TQCKPS<1:0>: Timer Input Clock Prescale Select bits

(Prescaler utilized for 16-bit Timer mode only)
bit 2
POSRES: Position Counter Reset Enable bit

1 = Index Pulse resets Position Counter
0 = Index Pulse does not reset Position Counter
Note:
Bit applies only when QEIM<2:0> = 100 or 110.
bit 1
TQCS: Timer Clock Source Select bit

1 = External clock from pin QEA (on the rising edge)
0 = Internal clock (TCY)
bit 0
UPDN_SRC: Position Counter Direction Selection Control bit

1 = QEB pin state defines position counter direction
0 = Control/Status bit, UPDN (QEICON<11>), defines timer counter (POSCNT) direction
Note:
DS70283J-page 178
When configured for QEI mode, control bit is a dont care.

REGISTER 16-2:
DFLTxCON: DIGITAL FILTER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
IMV<1:0>
CEID
bit 15
bit 8
R/W-0
R/W-0
U-0
U-0
U-0
U-0
QEOUT
QECK<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-11
bit 10-9
IMV<1:0>: Index Match Value bits These bits allow the user application to specify the state of the
QEA and QEB input pins during an Index pulse when the POSxCNT register is to be reset.
In 4X Quadrature Count Mode:
IMV1 = Required State of Phase B input signal for match on index pulse
IMV0 = Required State of Phase A input signal for match on index pulse
In 2X Quadrature Count Mode:
IMV1 = Selects Phase input signal for Index state match (0 = Phase A, 1 = Phase B)
IMV0 = Required state of the selected Phase input signal for match on index pulse
bit 8
CEID: Count Error Interrupt Disable bit

1 = Interrupts due to count errors are disabled
0 = Interrupts due to count errors are enabled
bit 7
QEOUT: QEA/QEB/INDX Pin Digital Filter Output Enable bit

1 = Digital filter outputs enabled
0 = Digital filter outputs disabled (normal pin operation)
bit 6-4
QECK<2:0>: QEA/QEB/INDX Digital Filter Clock Divide Select Bits

111 = 1:256 Clock Divide
bit 3-0
DS70283J-page 179

NOTES:
DS70283J-page 180

17.0
SERIAL PERIPHERAL
INTERFACE (SPI)

Section
18.
Serial
Peripheral
Interface (SPI) (DS70206) of the
Manual, which is available on the
FIGURE 17-1:
The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with
other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shift registers, display drivers, analog-to-digital converters, etc.
The SPI module is compatible with SPI and SIOP from
Motorola.
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates status conditions.
The serial interface consists of these four pins:
SDIx (serial data input)

SDOx (serial data output)
SCKx (shift clock input or output)
SSx (active-low slave select)
In Master mode operation, SCK is a clock output. In

Slave mode, it is a clock input.
SPI MODULE BLOCK DIAGRAM
SCKx
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
Prescaler
FCY
SSx
Sync
Control
Select
Edge
Control
Clock
SPIxCON1<1:0>
Shift Control
SPIxCON1<4:2>
SDOx
Enable
Master Clock
bit 0
SDIx
SPIxSR
Transfer
Transfer
SPIxRXB
SPIxTXB
SPIxBUF
Read SPIxBUF
Write SPIxBUF
16
Internal Data Bus
DS70283J-page 181

REGISTER 17-1:
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
SPIEN
SPISIDL
bit 15
bit 8
U-0
R/C-0
U-0
U-0
U-0
U-0
R-0
R-0
SPIROV
SPITBF
SPIRBF
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit

1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
bit 14
bit 13
SPISIDL: Stop in Idle Mode bit

bit 12-7
bit 6
SPIROV: Receive Overflow Flag bit

1 = A new byte/word is completely received and discarded. The user software has not read the
previous data in the SPIxBUF register
0 = No overflow has occurred.
bit 5-2
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit

1 = Transmit not yet started, SPIxTXB is full
0 = Transmit started, SPIxTXB is empty
Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit

1 = Receive complete, SPIxRXB is full
0 = Receive is not complete, SPIxRXB is empty
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.
DS70283J-page 182

REGISTER 17-2:
SPIXCON1: SPIx CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DISSCK
DISSDO
MODE16
SMP
CKE(1)
bit 15
bit 8
R/W-0
R/W-0
(2)
CKP
SSEN
R/W-0
R/W-0
MSTEN
R/W-0
R/W-0
R/W-0
(3)
R/W-0
PPRE<1:0>(3)
SPRE<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12
DISSCK: Disable SCKx pin bit (SPI Master modes only)

1 = Internal SPI clock is disabled, pin functions as I/O
0 = Internal SPI clock is enabled
bit 11
DISSDO: Disable SDOx pin bit

1 = SDOx pin is not used by module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10
MODE16: Word/Byte Communication Select bit

1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9
SMP: SPIx Data Input Sample Phase bit

Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
CKE: SPIx Clock Edge Select bit(1)

1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
bit 7
SSEN: Slave Select Enable bit (Slave mode)(2)

1 = SSx pin used for Slave mode
0 = SSx pin not used by module. Pin controlled by port function
bit 6
CKP: Clock Polarity Select bit

1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5
MSTEN: Master Mode Enable bit

1 = Master mode
0 = Slave mode
Note 1:
2:
3:
The CKE bit is not used in the Framed SPI modes. Program this bit to 0 for the Framed SPI modes
(FRMEN = 1).
This bit must be cleared when FRMEN = 1.
Do not set both Primary and Secondary prescalers to a value of 1:1.
DS70283J-page 183

REGISTER 17-2:
SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2
SPRE<2:0>: Secondary Prescale bits (Master mode)(3)

111 = Secondary prescale 1:1
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master mode)(3)

11 = Primary prescale 1:1
Note 1:
2:
3:
The CKE bit is not used in the Framed SPI modes. Program this bit to 0 for the Framed SPI modes
(FRMEN = 1).
This bit must be cleared when FRMEN = 1.
Do not set both Primary and Secondary prescalers to a value of 1:1.
DS70283J-page 184

REGISTER 17-3:
SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
FRMEN
SPIFSD
FRMPOL
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
FRMDLY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
FRMEN: Framed SPIx Support bit

1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0 = Framed SPIx support disabled
bit 14
SPIFSD: Frame Sync Pulse Direction Control bit

1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
bit 13
FRMPOL: Frame Sync Pulse Polarity bit

1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
bit 12-2
bit 1
FRMDLY: Frame Sync Pulse Edge Select bit

1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
bit 0
Unimplemented: This bit must not be set to 1 by the user application
DS70283J-page 185

NOTES:
DS70283J-page 186

18.0
INTER-INTEGRATED
CIRCUIT (I2C)

Section 19. Inter-Integrated Circuit
(DS70195)
of
the
(I2C)
The Inter-Integrated Circuit (I2C) module provides
complete hardware support for both Slave and
Multi-Master modes of the I2C serial communication
standard, with a 16-bit interface.
The I2C module has a 2-pin interface:
The SCLx pin is clock
The SDAx pin is data
The I2C module offers the following key features:
I2C interface supporting both Master and Slave
modes of operation
I2C Slave mode supports 7-bit and 10-bit
addressing
I2C Master mode supports 7-bit and 10-bit
addressing
I2C port allows bidirectional transfers between
master and slaves
Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
I2C supports multi-master operation, detects bus
collision and arbitrates accordingly
18.1
Operating Modes
The hardware fully implements all the master and slave

functions of the I2C Standard and Fast mode
specifications, as well as 7-bit and 10-bit addressing.
The I2C module can operate either as a slave or a
master on an I2C bus.
The following types of I2C operation are supported:
I2C slave operation with 7-bit addressing

I2C slave operation with 10-bit addressing
I2C master operation with 7-bit or 10-bit addressing
For details about the communication sequence in each

of these modes, refer to the dsPIC33F/PIC24H Family
Reference Manual. Please see the Microchip web site
(www.microchip.com) for the latest dsPIC33F/PIC24H
Family Reference Manual sections.
18.2
I2C Registers
I2CxCON and I2CxSTAT are control and status

registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write:
I2CxRSR is the shift register used for shifting
data.
I2CxRCV is the receive buffer and the register to
which data bytes are written, or from which data
bytes are read.
I2CxTRN is the transmit register to which bytes
are written during a transmit operation.
The I2CxADD register holds the slave address.
A status bit, ADD10, indicates 10-bit Address
mode.
The I2CxBRG acts as the Baud Rate Generator
(BRG) reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
DS70283J-page 187

FIGURE 18-1:
I2C BLOCK DIAGRAM (X = 1)

Internal
Data Bus
I2CxRCV
Read
SCLx
Shift
Clock
I2CxRSR
LSb
SDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSb
Read
Shift Clock
Reload
Control
BRG Down Counter
Write
I2CxBRG
Read
TCY/2
DS70283J-page 188

REGISTER 18-1:
I2CxCON: I2Cx CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-1 HC
R/W-0
R/W-0
R/W-0
R/W-0
I2CEN
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0 HC
R/W-0 HC
R/W-0 HC
R/W-0 HC
R/W-0 HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
HS = Set in hardware
HC = Cleared in hardware
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
I2CEN: I2Cx Enable bit

1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module. All I2C pins are controlled by port functions
bit 14
bit 13
I2CSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters an Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)

1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write 0 to initiate stretch and write 1 to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write 1 to release clock). Hardware clear at beginning of slave
transmission.
bit 11
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit

1 = IPMI mode is enabled; all addresses Acknowledged
0 = IPMI mode disabled
bit 10
A10M: 10-bit Slave Address bit

1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9
DISSLW: Disable Slew Rate Control bit

1 = Slew rate control disabled
0 = Slew rate control enabled
bit 8
SMEN: SMBus Input Levels bit

1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)

1 = Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0 = General call address disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
DS70283J-page 189

REGISTER 18-1:
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit

(when operating as I2C master, applicable during master receive)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence
0 = Acknowledge sequence not in progress
bit 3
RCEN: Receive Enable bit (when operating as I2C master)

1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte
0 = Receive sequence not in progress
bit 2
PEN: Stop Condition Enable bit (when operating as I2C master)

1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence
0 = Stop condition not in progress
bit 1
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
master Repeated Start sequence
0 = Repeated Start condition not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)

1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence
0 = Start condition not in progress
DS70283J-page 190

REGISTER 18-2:
I2CxSTAT: I2Cx STATUS REGISTER
R-0 HSC
R-0 HSC
U-0
U-0
U-0
R/C-0 HS
R-0 HSC
R-0 HSC
ACKSTAT
TRSTAT
BCL
GCSTAT
ADD10
bit 15
bit 8
R/C-0 HS
R/C-0 HS
R-0 HSC
R/C-0 HSC
R/C-0 HSC
R-0 HSC
R-0 HSC
R-0 HSC
IWCOL
I2COV
D_A
R_W
RBF
TBF
bit 7
bit 0
Legend:
U = Unimplemented bit, read as 0 C = Clear only bit
R = Readable bit
W = Writable bit
HS = Set in hardware
HSC = Hardware set/cleared
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
ACKSTAT: Acknowledge Status bit

(when operating as I2C master, applicable to master transmit operation)
1 = NACK received from slave
0 = ACK received from slave
Hardware set or clear at end of slave Acknowledge.
bit 14
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13-11
bit 10
BCL: Master Bus Collision Detect bit

1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
bit 9
GCSTAT: General Call Status bit

1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
bit 8
ADD10: 10-bit Address Status bit

1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
bit 7
IWCOL: Write Collision Detect bit

1 = An attempt to write the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
bit 6
I2COV: Receive Overflow Flag bit

1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5
D_A: Data/Address bit (when operating as I2C slave)

1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
DS70283J-page 191

REGISTER 18-2:
I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 3
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 2
R_W: Read/Write Information bit (when operating as I2C slave)

1 = Read indicates data transfer is output from slave
0 = Write indicates data transfer is input to slave
Hardware set or clear after reception of I 2C device address byte.
bit 1
RBF: Receive Buffer Full Status bit

1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit

1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
DS70283J-page 192

REGISTER 18-3:
I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
AMSK9
AMSK8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK7
AMSK6
AMSK5
AMSK4
AMSK3
AMSK2
AMSK1
AMSK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-10
bit 9-0
AMSKx: Mask for Address bit x Select bit

1 = Enable masking for bit x of incoming message address; bit match not required in this position
0 = Disable masking for bit x; bit match required in this position
DS70283J-page 193

NOTES:
DS70283J-page 194

19.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)

Section 17. UART (DS70188) of the
Manual, which is available on the Microchip web site (www.microchip.com).
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 device family. The UART is a
full-duplex
asynchronous
system
that
can
communicate with peripheral devices, such as
personal computers, LIN, and RS-232 and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins and
also includes an IrDA encoder and decoder.
FIGURE 19-1:
The primary features of the UART module are:

Full-Duplex, 8-bit or 9-bit Data Transmission
through the UxTX and UxRX pins
Even, Odd or No Parity Options (for 8-bit data)
One or two stop bits
Hardware flow control option with UxCTS and
UxRTS pins
Fully integrated Baud Rate Generator with 16-bit
prescaler
Baud rates ranging from 10 Mbps to 38 bps at 40
MIPS
4-deep First-In First-Out (FIFO) Transmit Data
buffer
4-deep FIFO Receive Data buffer
Parity, framing and buffer overrun error detection
Support for 9-bit mode with Address Detect
(9th bit = 1)
Transmit and Receive interrupts
A separate interrupt for all UART error conditions
Loopback mode for diagnostic support
Support for sync and break characters
Support for automatic baud rate detection
IrDA encoder and decoder logic
16x baud clock output for IrDA support
A simplified block diagram of the UART module is
shown in Figure 19-1. The UART module consists of
these key hardware elements:
Baud Rate Generator
Asynchronous Transmitter
Asynchronous Receiver
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA
Hardware Flow Control
UxRTS/BCLK
UxCTS
UART Receiver
UxRX
UART Transmitter
UxTX
DS70283J-page 195

REGISTER 19-1:
R/W-0
UxMODE: UARTx MODE REGISTER

U-0
UARTEN(1)
R/W-0
R/W-0
R/W-0
U-0
USIDL
IREN(2)
RTSMD
R/W-0
R/W-0
UEN<1:0>
bit 15
bit 8
R/W-0 HC
R/W-0
R/W-0, HC
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
URXINV
BRGH
R/W-0
R/W-0
PDSEL<1:0>
R/W-0
STSEL
bit 7
bit 0
Legend:
HC = Hardware Clearable
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
UARTEN: UARTx Enable bit(1)

1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption minimal
bit 14
bit 13
USIDL: Stop in Idle Mode bit

bit 12
IREN: IrDA Encoder and Decoder Enable bit(2)

1 = IrDA encoder and decoder enabled
0 = IrDA encoder and decoder disabled
bit 11
RTSMD: Mode Selection for UxRTS Pin bit

1 = UxRTS pin in Simplex mode
0 = UxRTS pin in Flow Control mode
bit 10
bit 9-8
UEN<1:0>: UARTx Pin Enable bits

11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by
port latches
bit 7
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared
in hardware on following rising edge
0 = No wake-up enabled
bit 6
LPBACK: UARTx Loopback Mode Select bit

1 = Enable Loopback mode
0 = Loopback mode is disabled
bit 5
ABAUD: Auto-Baud Enable bit

1 = Enable baud rate measurement on the next character requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0 = Baud rate measurement disabled or completed
bit 4
URXINV: Receive Polarity Inversion bit

1 = UxRX Idle state is 0
0 = UxRX Idle state is 1
Note 1:
2:
Refer to Section 17. UART (DS70188) in the dsPIC33F/PIC24H Family Reference Manual for
information on enabling the UART module for receive or transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0).
DS70283J-page 196

REGISTER 19-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 3
BRGH: High Baud Rate Enable bit

1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits

11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit

1 = Two Stop bits
0 = One Stop bit
Note 1:
2:
information on enabling the UART module for receive or transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0).
DS70283J-page 197

REGISTER 19-2:
R/W-0
UxSTA: UARTx STATUS AND CONTROL REGISTER

R/W-0
UTXISEL1
UTXINV
R/W-0
UTXISEL0
U-0
R/W-0 HC
R/W-0
R-0
R-1
UTXBRK
UTXEN(1)
UTXBF
TRMT
bit 15
bit 8
R/W-0
R/W-0
URXISEL<1:0>
R/W-0
R-1
R-0
R-0
R/C-0
R-0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
HC = Hardware cleared
C = Clear only bit
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15,13
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits

11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the
transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is
at least one character open in the transmit buffer)
bit 14
UTXINV: Transmit Polarity Inversion bit

If IREN = 0:
1 = UxTX Idle state is 0
0 = UxTX Idle state is 1
If IREN = 1:
1 = IrDA encoded UxTX Idle state is 1
0 = IrDA encoded UxTX Idle state is 0
bit 12
bit 11
UTXBRK: Transmit Break bit

1 = Send Sync Break on next transmission Start bit, followed by twelve 0 bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission disabled or completed
bit 10
UTXEN: Transmit Enable bit(1)

1 = Transmit enabled, UxTX pin controlled by UARTx
0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled
by port
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)

1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)

1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bits

11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer. Receive buffer has one or more characters
Note 1:
information on enabling the UART module for transmit operation.
DS70283J-page 198

REGISTER 19-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect
0 = Address Detect mode disabled
bit 4
RIDLE: Receiver Idle bit (read-only)

1 = Receiver is Idle
0 = Receiver is active
bit 3
PERR: Parity Error Status bit (read-only)

1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)

1 = Framing error has been detected for the current character (character at the top of the receive
FIFO)
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit (read/clear only)

1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1 0 transition) will reset
the receiver buffer and the UxRSR to the empty state
bit 0
URXDA: Receive Buffer Data Available bit (read-only)

1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1:
information on enabling the UART module for transmit operation.
DS70283J-page 199

NOTES:
DS70283J-page 200

20.0
10-BIT/12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)

Section
16.
Analog-to-Digital
Converter (ADC) (DS70183) of the
Manual, which is available on the
The 12-bit ADC configuration supports all the above

features, except:
In the 12-bit configuration, conversion speeds of
up to 500 ksps are supported.
There is only 1 sample-and-hold amplifier in the
12-bit configuration, so simultaneous sampling of
multiple channels is not supported.
Depending on the particular device pinout, the ADC
can have up to nine analog input pins, designated AN0
through AN8. In addition, there are two analog input
pins for external voltage reference connections. These
voltage reference inputs can be shared with other
analog input pins.
The actual number of analog input pins and external
voltage reference input configuration will depend on the
specific device. Refer to the device data sheet for
further details.
A block diagram of the ADC is shown in Figure 20-1.
20.2
ADC Initialization

devices have up to nine Analog-to-Digital Converter
(ADC) module input channels.
To configure the ADC module:
The AD12B bit (AD1CON1<10>) allows each of the

ADC modules to be configured as either a 10-bit,
4 sample-and-hold ADC (default configuration), or a
12-bit, 1 sample-and-hold ADC.
2.
Note:
1.
3.
The ADC module must be disabled before

the AD12B bit can be modified.
4.
20.1
Key Features
The 10-bit ADC configuration has the following key

features:
Successive Approximation (SAR) conversion

Conversion speeds of up to 1.1 Msps
Up to 9 analog input pins
External voltage reference input pins
Simultaneous sampling of up to four analog input
pins
Automatic Channel Scan mode
Selectable conversion trigger source
Selectable Buffer Fill modes
Four result alignment options (signed/unsigned,
fractional/integer)
Operation during CPU Sleep and Idle modes
16-word conversion result buffer
5.
6.
7.
8.
Select
port
pins
as
analog
inputs
(AD1PCFGH<15:0> or AD1PCFGL<15:0>).
Select voltage reference source to match
expected
range
on
analog
inputs
(AD1CON2<15:13>).
Select the analog conversion clock to match the
desired data rate with the processor clock
(AD1CON3<7:0>).
Determine how many sample-and-hold channels will be used (AD1CON2<9:8> and
AD1PCFGH<15:0> or AD1PCFGL<15:0>).
Select the appropriate sample/conversion
sequence
(AD1CON1<7:5>
and
AD1CON3<12:8>).
Select the way conversion results are presented
in the buffer (AD1CON1<9:8>).
Turn on the ADC module (AD1CON1<15>).
Configure ADC interrupt (if required):
a) Clear the AD1IF bit.
b) Select the ADC interrupt priority.
DS70283J-page 201

FIGURE 20-1:
ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ16MC304 AND

dsPIC33FJ32MC204 DEVICES
AN0
AN8
S/H0
CHANNEL
SCAN
CH0SA<4:0>
CH0
CH0SB<4:0>
CSCNA
AN1
VREFL
CH0NA CH0NB
AN0
(1)
VREF+(1) AVDD VREF-
AN3
AVSS
S/H1
+
-
CH123SA CH123SB
CH1(2)
AN6
VCFG<2:0>
ADC1BUF0
VREFL
ADC1BUF1
ADC1BUF2
VREFH
VREFL
CH123NA CH123NB
SAR ADC
AN1
AN4
S/H2
CH123SA CH123SB
CH2(2)
ADC1BUFE
ADC1BUFF
AN7
VREFL
CH123NA CH123NB
AN2
AN5
S/H3
+
CH123SA CH123SB
CH3(2)
AN8
VREFL
CH123NA CH123NB
Alternate
Input Selection
Note
1:
2:
VREF+, VREF- inputs can be multiplexed with other analog inputs.

Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
DS70283J-page 202

FIGURE 20-2:
ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32MC202 DEVICE

AN0
AN5
S/H0
CHANNEL
SCAN
CH0SA<4:0>
CH0
CH0SB<4:0>
CSCNA
AN1
VREFL
CH0NA CH0NB
AN0
VREF+(1) AVDD VREF-(1) AVSS
AN3
S/H1
+
-
CH123SA CH123SB
CH1(2)
VCFG<2:0>
ADC1BUF0
VREFL
ADC1BUF1
ADC1BUF2
VREFH
VREFL
CH123NA CH123NB
SAR ADC
AN1
AN4
S/H2
CH123SA CH123SB
CH2
ADC1BUFE
ADC1BUFF
(2)
VREFL
CH123NA CH123NB
AN2
AN5
S/H3
+
CH123SA CH123SB
CH3(2)
VREFL
CH123NA CH123NB
Alternate
Input Selection
Note
1:
2:
VREF+, VREF- inputs can be multiplexed with other analog inputs.

Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
DS70283J-page 203

FIGURE 20-3:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM

AD1CON3<15>
ADC Internal
RC Clock(2)
TAD
AD1CON3<5:0>
TOSC(1)
X2
TCY
ADC Conversion
Clock Multiplier
1, 2, 3, 4, 5,..., 64
Note 1:
2:
Refer to Figure 8-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal
to the clock frequency. TOSC = 1/FOSC.
See the ADC Electrical Characteristics for the exact RC clock value.
DS70283J-page 204

REGISTER 20-1:
AD1CON1: ADC1 CONTROL REGISTER 1
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
ADON
ADSIDL
AD12B
R/W-0
R/W-0
FORM<1:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
SSRC<2:0>
U-0
R/W-0
R/W-0
R/W-0
HC,HS
R/C-0
HC, HS
SIMSAM
ASAM
SAMP
DONE
bit 7
bit 0
Legend:
HC = Cleared by hardware
HS = Set by hardware
C = Clear only bit
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15
ADON: ADC Operating Mode bit

1 = ADC module is operating
0 = ADC is off
bit 14
bit 13
ADSIDL: Stop in Idle Mode bit

bit 12-11
bit 10
AD12B: 10-bit or 12-bit Operation Mode bit

1 = 12-bit, 1-channel ADC operation
0 = 10-bit, 4-channel ADC operation
bit 9-8
FORM<1:0>: Data Output Format bits

For 10-bit operation:
11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>)
10 = Fractional (DOUT = dddd dddd dd00 0000)
01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>)
00 = Integer (DOUT = 0000 00dd dddd dddd)
For 12-bit operation:
11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d<11>)
10 = Fractional (DOUT = dddd dddd dddd 0000)
01 = Signed Integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d<11>)
00 = Integer (DOUT = 0000 dddd dddd dddd)
bit 7-5
SSRC<2:0>: Sample Clock Source Select bits

111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = Reserved
101 = Motor Control PWM2 interval ends sampling and starts conversion
100 = Reserved
011 = Motor Control PWM1 interval ends sampling and starts conversion
010 = GP timer 3 compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing sample bit ends sampling and starts conversion
bit 4
bit 3
SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> = 01 or 1x)
When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as 0
1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or
Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)
0 = Samples multiple channels individually in sequence
DS70283J-page 205

REGISTER 20-1:
AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)
bit 2
ASAM: ADC Sample Auto-Start bit

1 = Sampling begins immediately after last conversion. SAMP bit is auto-set
0 = Sampling begins when SAMP bit is set
bit 1
SAMP: ADC Sample Enable bit

1 = ADC sample-and-hold amplifiers are sampling
0 = ADC sample-and-hold amplifiers are holding
If ASAM = 0, software can write 1 to begin sampling. Automatically set by hardware if ASAM = 1.
If SSRC = 000, software can write 0 to end sampling and start conversion. If SSRC 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0
DONE: ADC Conversion Status bit

1 = ADC conversion cycle is completed
0 = ADC conversion not started or in progress
Automatically set by hardware when ADC conversion is complete. Software can write 0 to clear
DONE status (software not allowed to write 1). Clearing this bit will NOT affect any operation in
progress. Automatically cleared by hardware at start of a new conversion.
DS70283J-page 206

REGISTER 20-2:
R/W-0

R/W-0
R/W-0
VCFG<2:0>
U-0
U-0
R/W-0
CSCNA
R/W-0
R/W-0
CHPS<1:0>
bit 15
bit 8
R-0
U-0
BUFS
R/W-0
R/W-0
R/W-0
R/W-0
SMPI<3:0>
R/W-0
R/W-0
BUFM
ALTS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-13
x = Bit is unknown
VCFG<2:0>: Converter Voltage Reference Configuration bits
000
001
010
011
1xx
ADREF+
ADREF-
AVDD
External VREF+
AVDD
External VREF+
AVDD
AVSS
AVSS
External VREFExternal VREFAVSS
bit 12-11
bit 10
CSCNA: Scan Input Selections for CH0+ during Sample A bit

1 = Scan inputs
0 = Do not scan inputs
bit 9-8
CHPS<1:0>: Select Channels Utilized bits

When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as 0
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
bit 7
BUFS: Buffer Fill Status bit (valid only when BUFM = 1)

1 = ADC is currently filling second half of buffer, user should access data in the first half
0 = ADC is currently filling first half of buffer, user application should access data in the second half
bit 6
bit 5-2
SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits

1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1
BUFM: Buffer Fill Mode Select bit

1 = Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt
0 = Always starts filling buffer from the beginning
bit 0
ALTS: Alternate Input Sample Mode Select bit

1 = Uses channel input selects for Sample A on first sample and Sample B on next sample
0 = Always uses channel input selects for Sample A
DS70283J-page 207

REGISTER 20-3:
R/W-0

U-0
ADRC
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SAMC<4:0>(1)
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS<7:0>(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
ADRC: ADC Conversion Clock Source bit

1 = ADC internal RC clock
0 = Clock derived from system clock
bit 14-13
bit 12-8
SAMC<4:0>: Auto Sample Time bits(1)

11111 = 31 TAD
00001 = 1 TAD
00000 = 0 TAD
bit 7-0
ADCS<7:0>: ADC Conversion Clock Select bits(2)

11111111 = Reserved
01000000 = Reserved
00111111 = TCY (ADCS<7:0> + 1) = 64 TCY = TAD
00000010 = TCY (ADCS<7:0> + 1) = 3 TCY = TAD

00000001 = TCY (ADCS<7:0> + 1) = 2 TCY = TAD
00000000 = TCY (ADCS<7:0> + 1) = 1 TCY = TAD
Note 1:
2:
x = Bit is unknown
This bit only used if AD1CON1<7:5> (SSRC2:0) = 111.

This bit is not used if AD1CON3<15> (ADRC) = 1.
DS70283J-page 208

REGISTER 20-4:
AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
CH123NB<1:0>
R/W-0
CH123SB
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
CH123NA<1:0>
R/W-0
CH123SA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-11
bit 10-9
CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits

dsPIC33FJ32MC202 devices only:
If AD12B = 1:
11 = Reserved
10 = Reserved
01 = Reserved
00 = Reserved
x = Bit is unknown
If AD12B = 0:
11 = Reserved
10 = Reserved
01 = CH1, CH2, CH3 negative input is VREF00 = CH1, CH2, CH3 negative input is VREFdsPIC33FJ32MC204 and dsPIC33FJ16MC304 devices only:
If AD12B = 1:
11 = Reserved
10 = Reserved
01 = Reserved
00 = Reserved
If AD12B = 0:
11 = Reserved
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
01 = CH1, CH2, CH3 negative input is VREF00 = CH1, CH2, CH3 negative input is VREFbit 8
CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit

If AD12B = 1:
1 = Reserved
0 = Reserved
If AD12B = 0:
1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
bit 7-3
DS70283J-page 209

REGISTER 20-4:
bit 2-1
AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER (CONTINUED)
CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits

If AD12B = 1:
11 = Reserved
10 = Reserved
01 = Reserved
00 = Reserved
If AD12B = 0:
11 = Reserved
10 = Reserved
01 = CH1, CH2, CH3 negative input is VREF00 = CH1, CH2, CH3 negative input is VREFdsPIC33FJ32MC204 and dsPIC33FJ16MC304 devices only:
If AD12B = 1:
11 = Reserved
10 = Reserved
01 = Reserved
00 = Reserved
If AD12B = 0:
11 = Reserved
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
01 = CH1, CH2, CH3 negative input is VREF00 = CH1, CH2, CH3 negative input is VREF-
bit 0
CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit

If AD12B = 1:
1 = Reserved
0 = Reserved
If AD12B = 0:
DS70283J-page 210

REGISTER 20-5:
AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER
R/W-0
U-0
U-0
CH0NB
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0SB<4:0>
bit 15
bit 8
R/W-0
U-0
U-0
CH0NA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0SA<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15
CH0NB: Channel 0 Negative Input Select for Sample B bit

1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VREF-
bit 14-13
bit 12-8
CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits

dsPIC33FJ32MC204 and dsPIC33FJ16MC304 devices only:
01000 = Channel 0 positive input is AN8
x = Bit is unknown


00000 = Channel 0 positive input is AN0.
bit 7
CH0NA: Channel 0 Negative Input Select for Sample A bit

1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VREF-
bit 6-5
bit 4-0
CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits

dsPIC33FJ32MC204 and dsPIC33FJ16MC304 devices only:


DS70283J-page 211

,2
REGISTER 20-6:
AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CSS8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 15-9
bit 8-0
CSS<8:0>: ADC Input Scan Selection bits

1 = Select ANx for input scan
0 = Skip ANx for input scan
x = Bit is unknown
Note 1: On devices without 9 analog inputs, all AD1CSSL bits can be selected by the user application. However,
inputs selected for scan without a corresponding input on device converts VREFL.
2: CSSx = ANx, where x = 0 through 8.
REGISTER 20-7:
AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW(1,2,3)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
PCFG8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-9
bit 8-0
PCFG<8:0>: ADC Port Configuration Control bits

1 = Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS
0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1:
2:
3:
On devices without 9 analog inputs, all PCFG bits are R/W by user software. However, the PCFG bits are
ignored on ports without a corresponding input on device.
PCFGx = ANx, where x = 0 through 8.
The PCFGx bits have no effect if the ADC module is disabled by setting ADxMD bit in the PMDx Register.
In this case, all port pins multiplexed with ANx will be in Digital mode.
DS70283J-page 212

21.0
SPECIAL FEATURES
Note:
21.1

devices provide nonvolatile memory implementation
for device configuration bits. Refer to Section 25.
Device
Configuration
(DS70194)
of
the
dsPIC33F/PIC24H Family Reference Manual, for
more information on this implementation.

Manual sections.
The Configuration bits can be programmed (read as

0), or left unprogrammed (read as 1), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.

devices include several features intended to maximize
application flexibility and reliability, and minimize cost
through elimination of external components. These are:
Flexible configuration
Watchdog Timer (WDT)
Code Protection and CodeGuard Security
JTAG Boundary Scan Interface
In-Circuit Serial Programming (ICSP)
In-Circuit emulation
TABLE 21-1:
Address
Configuration Bits
The individual Configuration bit descriptions for the

Configuration registers are shown in Table 21-2.
Note that address 0xF80000 is beyond the user program
memory space. It belongs to the configuration memory
space (0x800000-0xFFFFFF), which can only be
accessed using table reads and table writes.
The Device Configuration register map is shown in
Table 21-1.
DEVICE CONFIGURATION REGISTER MAP

Name
Bit 7
Bit 6
Bit 5
Bit 4
0xF80000 FBS
0xF80002 RESERVED
IESO
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
FCKSM<1:0>
0xF8000A FWDT
FWDTEN WINDIS
0xF8000C FPOR
PWMPIN
0xF8000E FICD
HPOL
Reserved(1)
Bit 3
Bit 2
BSS<2:0>
Bit 0
BWRP
GSS<1:0>
IOL1WAY
Bit 1
GWRP
FNOSC<2:0>
WDTPRE
LPOL
ALTI2C
JTAGEN
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
0xF80010 FUID0
User Unit ID Byte 0
0xF80012 FUID1
User Unit ID Byte 1
0xF80014 FUID2
User Unit ID Byte 2
0xF80016 FUID3
User Unit ID Byte 3
FPWRT<2:0>
ICS<1:0>
Legend: = unimplemented bit, read as 0.

Note 1: These bits are reserved for use by development tools and must be programmed as 1.
DS70283J-page 213

TABLE 21-2:
dsPIC33F CONFIGURATION BITS DESCRIPTION

RTSP
Effect
Bit Field
Register
Description
BWRP
FBS
Immediate Boot Segment Program Flash Write Protection

1 = Boot segment can be written
0 = Boot segment is write-protected
BSS<2:0>
FBS
Immediate dsPIC33FJ32MC202 and dsPIC33FJ32MC204 Devices Only

Boot Segment Program Flash Code Protection Size
X11 = No Boot program Flash segment
Boot space is 768 Instruction Words (except interrupt vectors)
110 = Standard security; boot program Flash segment ends at 0x0007FE
010 = High security; boot program Flash segment ends at 0x0007FE
101 = Standard security; boot program Flash segment, ends at 0x001FFE
001 = High security; boot program Flash segment ends at 0x001FFE
100 = Standard security; boot program Flash segment ends at 0x003FFE
BSS<2:0>
FBS
Immediate dsPIC33FJ16MC304 Device Only

Boot Segment Program Flash Code Protection Size
X11 = No Boot program Flash segment
110 = Standard security; boot program Flash segment ends at 0x0007FE
010 = High security; boot program Flash segment ends at 0x0007FE
101 = Standard security; boot program Flash segment, ends at 0x001FFE
100 = Standard security; boot program Flash segment ends at 0x002BFE
000 = High security; boot program Flash segment ends at 0x002BFE
GSS<1:0>
FGS
Immediate General Segment Code-Protect bit

11 = User program memory is not code-protected
10 = Standard security
0x = High security
GWRP
FGS
Immediate General Segment Write-Protect bit

1 = User program memory is not write-protected
0 = User program memory is write-protected
IESO
FNOSC<2:0>
DS70283J-page 214
FOSCSEL Immediate Two-speed Oscillator Start-up Enable bit

1 = Start-up device with FRC, then automatically switch to the
user-selected oscillator source when ready
0 = Start-up device with user-selected oscillator source
FOSCSEL
If clock
switch is
enabled,
RTSP
effect is
on any
device
Reset;
otherwise,
Immediate
Initial Oscillator Source Selection bits

111 = Internal Fast RC (FRC) oscillator with postscaler
110 = Internal Fast RC (FRC) oscillator with divide-by-16
101 = LPRC oscillator
100 = Secondary (LP) oscillator
011 = Primary (XT, HS, EC) oscillator with PLL
010 = Primary (XT, HS, EC) oscillator
001 = Internal Fast RC (FRC) oscillator with PLL
000 = FRC oscillator

TABLE 21-2:
dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)

RTSP
Effect
Bit Field
Register
FCKSM<1:0>
FOSC
Immediate Clock Switching Mode bits

1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
FOSC
Immediate Peripheral pin select configuration

1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
OSCIOFNC
FOSC
Immediate OSC2 Pin Function bit (except in XT and HS modes)

1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
POSCMD<1:0>
FOSC
Immediate Primary Oscillator Mode Select bits

11 = Primary oscillator disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
FWDTEN
FWDT
Immediate Watchdog Timer Enable bit

1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register will have no effect.)
0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register)
WINDIS
FWDT
Immediate Watchdog Timer Window Enable bit

1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
WDTPRE
FWDT
Immediate Watchdog Timer Prescaler bit

1 = 1:128
0 = 1:32
WDTPOST<3:0>
FWDT
Immediate Watchdog Timer Postscaler bits

1111 = 1:32,768
1110 = 1:16,384
0001 = 1:2
0000 = 1:1
PWMPIN
FPOR
Immediate Motor Control PWM Module Pin Mode bit

1 = PWM module pins controlled by PORT register at device Reset
(tri-stated)
0 = PWM module pins controlled by PWM module at device Reset
(configured as output pins)
Description
DS70283J-page 215

TABLE 21-2:
dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)

RTSP
Effect
Bit Field
Register
HPOL
FPOR
Immediate Motor Control PWM High Side Polarity bit

1 = PWM module high side output pins have active-high output polarity
0 = PWM module high side output pins have active-low output polarity
LPOL
FPOR
Immediate Motor Control PWM Low Side Polarity bit

1 = PWM module low side output pins have active-high output polarity
0 = PWM module low side output pins have active-low output polarity
FPWRT<2:0>
FPOR
Immediate Power-on Reset Timer Value Select bits

111 = PWRT = 128 ms
110 = PWRT = 64 ms
101 = PWRT = 32 ms
100 = PWRT = 16 ms
011 = PWRT = 8 ms
010 = PWRT = 4 ms
001 = PWRT = 2 ms
000 = PWRT = Disabled
ALTI2C
FPOR
Immediate Alternate I2C pins

1 = I2C mapped to SDA1/SCL1 pins
0 = I2C mapped to ASDA1/ASCL1 pins
JTAGEN
FICD
Immediate JTAG Enable bit

1 = JTAG enabled
0 = JTAG disabled
ICS<1:0>
FICD
Immediate ICD Communication Channel Select bits

11 = Communicate on PGEC1 and PGED1
00 = Reserved, do not use
DS70283J-page 216
Description

21.2
On-Chip Voltage Regulator
The
and
dsPIC33FJ16MC304 devices power their core digital
logic at a nominal 2.5V. This can create a conflict for
designs that are required to operate at a higher typical
voltage, such as 3.3V. To simplify system design, all
devices in the dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 family incorporate an on-chip
regulator that allows the device to run its core logic from
VDD.
The regulator provides power to the core from the other
VDD pins. When the regulator is enabled, a low-ESR
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the VCAP pin
(Figure 21-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capacitor is provided in Table 24-13 located in Section 24.1
DC Characteristics.
Note:
It is important for low-ESR capacitors to

be placed as close as possible to the VCAP
pin.
On a POR, it takes approximately 20 s for the on-chip

voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
FIGURE 21-1:
CONNECTIONS FOR THE

ON-CHIP VOLTAGE
REGULATOR(1)
21.3
BOR: Brown-out Reset (BOR)
The Brown-out Reset (BOR) module is based on an

internal voltage reference circuit that monitors the regulated supply voltage VCAP. The main purpose of the
BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines, or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is 1.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
3.3V
dsPIC33F
VDD
VCAP
CEFC
10 F
Note 1:
2:
3:
VSS
These are typical operating voltages. Refer to

Table 24-13 located in Section 24.1 DC
Characteristics for the full operating ranges
of VDD and VCAP.
It is important for low-ESR capacitors to be
placed as close as possible to the VCAP pin.
Typical VCAP pin voltage = 2.5V when VDD
VDDMIN.
DS70283J-page 217

21.4
Watchdog Timer (WDT)
21.4.2
For
and
dsPIC33FJ16MC304 devices, the WDT is driven by the
LPRC oscillator. When the WDT is enabled, the clock
source is also enabled.
21.4.1
PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.

This feeds a prescaler than can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT time-out period (TWDT) of 1 ms in 5-bit mode, or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allow the selection of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
On any device Reset
On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
When the device exits Sleep or Idle mode to
resume normal operation
By a CLRWDT instruction during normal execution
Note:
SLEEP AND IDLE MODES
If the WDT is enabled, it will continue to run during Sleep

or Idle modes. When the WDT time-out occurs, the
device will wake the device and code execution will continue from where the PWRSAV instruction was executed.
The corresponding SLEEP or IDLE bits (RCON<3,2>) will
need to be cleared in software after the device wakes up.
21.4.3
ENABLING WDT
The WDT is enabled or disabled by the FWDTEN

Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to 0. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user application to enable the
WDT for critical code segments and disable the WDT
during non-critical segments for maximum power
savings.
Note:
If the WINDIS bit (FWDT<6>) is cleared,

the CLRWDT instruction should be executed
by the application software only during the
last 1/4 of the WDT period. This CLRWDT
window can be determined by using a timer.
If a CLRWDT instruction is executed before
this window, a WDT Reset occurs.
The WDT flag bit, WDTO (RCON<4>), is not automatically

cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts
when executed.
FIGURE 21-2:
WDT BLOCK DIAGRAM
All Device Resets

Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
Watchdog Timer
Sleep/Idle
WDTPRE
WDTPOST<3:0>
WDT
Wake-up
SWDTEN
FWDTEN
RS
Prescaler
(divide by N1)
LPRC Clock
RS
Postscaler
(divide by N2)
0
WINDIS
WDT
Reset
WDT Window Select
CLRWDT Instruction
DS70283J-page 218

21.5
JTAG Interface
21.7
In-Circuit Debugger

devices implement a JTAG interface, which supports
boundary scan device testing, as well as in-circuit
programming. Detailed information on this interface will
be provided in future revisions of the document.
When MPLAB ICD 2 is selected as a debugger, the

in-circuit debugging functionality is enabled. This
function allows simple debugging functions when used
with MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pin functions.
21.6
Any of the three pairs of debugging clock/data pins can

be used:
In-Circuit Serial Programming

family digital signal controllers can be serially
programmed while in the end application circuit. This is
done with two lines for clock and data and three other
lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the digital signal controller just before
shipping the product. Serial programming also allows
the most recent firmware or a custom firmware to be
programmed. Refer to the dsPIC33F/PIC24H Flash
Programming Specification (DS70152) document for
details about In-Circuit Serial Programming (ICSP).
PGEC1 and PGED1

PGEC2 and PGED2
PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS, and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
Any of the three pairs of programming clock/data pins

can be used:
PGEC1 and PGED1
PGEC2 and PGED2
PGEC3 and PGED3
DS70283J-page 219

21.8
Code Protection and

CodeGuard Security
When coupled with software encryption libraries, CodeGuard Security can be used to securely update Flash
even when multiple IPs reside on the single chip.
The
and
dsPIC33FJ16MC304 devices offer the intermediate
implementation of CodeGuard Security. CodeGuard
Security enables multiple parties to securely share
resources (memory, interrupts and peripherals) on a
single chip. This feature helps protect individual
Intellectual Property in collaborative system designs.
TABLE 21-3:
CODE FLASH SECURITY

SEGMENT SIZES FOR
32 KBYTE DEVICES
CONFIG BITS
BSS<2:0> = x11
GS = 11008 IW
VS = 256 IW
BSS<2:0> = x10
BS = 768 IW
256
GS = 10240 IW
VS = 256 IW
BSS<2:0> = x01
BS = 3840 IW
768
GS = 7168 IW
VS = 256 IW
BSS<2:0> = x00
BS = 7936 IW
1792
GS = 3072 IW
DS70283J-page 220
Secure segment and RAM protection is not

implemented
in
and
dsPIC33FJ16MC304 devices.
Note:
Refer to Section 23. CodeGuard

Security
(DS70199)
in
the
Manual for further information on usage,
configuration
and
operation
of
CodeGuard Security.
TABLE 21-4:
CODE FLASH SECURITY

SEGMENT SIZES FOR
16 KBYTE DEVICES
CONFIG BITS
VS = 256 IW
0K
The code protection features are controlled by the

Configuration registers: FBS and FGS.
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
003FFEh
004000h
0057FEh
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
003FFEh
004000h
VS = 256 IW
BSS<2:0> = x11
0K
002BFEh
VS = 256 IW
BSS<2:0> = x10
GS = 4608 IW
VS = 256 IW
BSS<2:0> = x01
0057FEh
BS = 3840 IW
768
GS = 1536 IW
0057FEh
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
003FFEh
004000h
BS = 768 IW
256
0057FEh
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
003FFEh
004000h
GS = 5376 IW
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
VS = 256 IW
BSS<2:0> = x00
1792
BS = 5376 IW
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
002BFEh
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
002BFEh
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
002BFEh

22.0
Note:
INSTRUCTION SET SUMMARY

Manual sections.
The dsPIC33F instruction set is identical to that of the

dsPIC30F.
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into five basic categories:
Word or byte-oriented operations

Bit-oriented operations
Literal operations
DSP operations
Control operations
Table 22-1 shows the general symbols used in

describing the instructions.
The dsPIC33F instruction set summary in Table 22-2
lists all the instructions, along with the status flags
affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
The first source operand, which is typically a
register Wb without any address modifier
The second source operand, which is typically a
register Ws with or without an address modifier
The destination of the result, which is typically a
register Wd with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
Most bit-oriented instructions (including

rotate/shift instructions) have two operands:
simple
The W register (with or without an address

modifier) or file register (specified by the value of
Ws or f)
The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register Wb)
The literal instructions that involve data movement can
use some of the following operands:
A literal value to be loaded into a W register or file
register (specified by k)
The W register or file register where the literal
value is to be loaded (specified by Wb or f)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
The first source operand, which is a register Wb
without any address modifier
The second source operand, which is a literal
value
The destination of the result (only if not the same
as the first source operand), which is typically a
register Wd with or without an address modifier
The MAC class of DSP instructions can use some of the
following operands:
The accumulator (A or B) to be used (required
operand)
The W registers to be used as the two operands
The X and Y address space prefetch operations
The X and Y address space prefetch destinations
The accumulator write-back destination
The other DSP instructions do not involve any
multiplication and can include:
The accumulator to be used (required)
The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
The amount of shift specified by a W register Wn
or a literal value
The control instructions can use some of the following
operands:
A program memory address
The mode of the table read and table write
instructions
The file register specified by the value f

The destination, which could be either the file
register f or the W0 register, which is denoted as
WREG
DS70283J-page 221

Most instructions are a single word. Certain
double-word instructions are designed to provide all the
required information in these 48 bits. In the second
word, the 8 MSbs are 0s. If this second word is executed as an instruction (by itself), it will execute as a
NOP.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles with the additional instruction cycle(s)
executed as a NOP. Notable exceptions are the BRA
TABLE 22-1:
(unconditional/computed branch), indirect CALL/GOTO,

all table reads and writes and RETURN/RETFIE
instructions, which are single-word instructions but take
two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two
or three cycles if the skip is performed, depending on
whether the instruction being skipped is a single-word or
two-word instruction. Moreover, double-word moves
require two cycles.
Note:
For more details on the instruction set,

refer to the 16-bit MCU and DSC
Programmers
Reference
Manual
(DS70157).
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
#text
Description
Means literal defined by text
(text)
Means content of text
[text]
Means the location addressed by text
{ }
Optional field or operation
<n:m>
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
Acc
One of two accumulators {A, B}
AWB
Accumulator write back destination address register {W13, [W13]+ = 2}
bit4
4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
File register address {0x0000...0x1FFF}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
lit8
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
lit16
lit23
23-bit unsigned literal {0...8388608}; LSb must be 0
None
Field does not require an entry, can be blank
OA, OB, SA, SB
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
Slit6
Wb
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor working register pair (direct addressing)
DS70283J-page 222

TABLE 22-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm*Wm
Multiplicand and Multiplier working register pair for Square instructions

{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn
Multiplicand and Multiplier working register pair for DSP instructions

{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 working registers {W0..W15}
Wnd
One of 16 destination working registers {W0...W15}
Wns
One of 16 source working registers {W0...W15}
WREG
W0 (working register used in file register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X data space prefetch address register for DSP instructions

{[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd
X data space prefetch destination register for DSP instructions {W4...W7}
Wy
Y data space prefetch address register for DSP instructions

{[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd
Y data space prefetch destination register for DSP instructions {W4...W7}
DS70283J-page 223

TABLE 22-2:
Base
Instr
#
1
INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
ADD
ADDC
AND
ASR
Assembly Syntax
# of
# of
Words Cycles
Description
Status Flags
Affected
ADD
Acc
Add Accumulators
ADD
f = f + WREG
OA,OB,SA,SB
C,DC,N,OV,Z
ADD
f,WREG
WREG = f + WREG
C,DC,N,OV,Z
ADD
#lit10,Wn
Wd = lit10 + Wd
C,DC,N,OV,Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
C,DC,N,OV,Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
C,DC,N,OV,Z
OA,OB,SA,SB
ADD
Wso,#Slit4,Acc
16-bit Signed Add to Accumulator
ADDC
f = f + WREG + (C)
C,DC,N,OV,Z
ADDC
f,WREG
WREG = f + WREG + (C)
C,DC,N,OV,Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
C,DC,N,OV,Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
C,DC,N,OV,Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
C,DC,N,OV,Z
AND
f = f .AND. WREG
N,Z
AND
f,WREG
WREG = f .AND. WREG
N,Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
N,Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
N,Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
N,Z
ASR
f = Arithmetic Right Shift f
C,N,OV,Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
C,N,OV,Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
C,N,OV,Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
N,Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
N,Z
f,#bit4
Bit Clear f
None
None
BCLR
BCLR
BCLR
Ws,#bit4
Bit Clear Ws
BRA
BRA
C,Expr
Branch if Carry
1 (2)
None
BRA
GE,Expr
Branch if greater than or equal
1 (2)
None
BRA
GEU,Expr
Branch if unsigned greater than or equal
1 (2)
None
BRA
GT,Expr
Branch if greater than
1 (2)
None
BRA
GTU,Expr
Branch if unsigned greater than
1 (2)
None
BRA
LE,Expr
Branch if less than or equal
1 (2)
None
BRA
LEU,Expr
Branch if unsigned less than or equal
1 (2)
None
BRA
LT,Expr
Branch if less than
1 (2)
None
BRA
LTU,Expr
Branch if unsigned less than
1 (2)
None
BRA
N,Expr
Branch if Negative
1 (2)
None
BRA
NC,Expr
Branch if Not Carry
1 (2)
None
BRA
NN,Expr
Branch if Not Negative
1 (2)
None
BRA
NOV,Expr
Branch if Not Overflow
1 (2)
None
BRA
NZ,Expr
Branch if Not Zero
1 (2)
None
BRA
OA,Expr
Branch if Accumulator A overflow
1 (2)
None
BRA
OB,Expr
Branch if Accumulator B overflow
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1 (2)
None
BSET
BSW
BRA
SA,Expr
Branch if Accumulator A saturated
1 (2)
None
BRA
SB,Expr
Branch if Accumulator B saturated
1 (2)
None
BRA
Expr
Branch Unconditionally
None
BRA
Z,Expr
Branch if Zero
1 (2)
None
BRA
Wn
Computed Branch
None
BSET
f,#bit4
Bit Set f
None
BSET
Ws,#bit4
Bit Set Ws
None
BSW.C
Ws,Wb
Write C bit to Ws<Wb>
None
BSW.Z
Ws,Wb
Write Z bit to Ws<Wb>
None
DS70283J-page 224

TABLE 22-2:
Base
Instr
#
9
10
11
12
13
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
BTG
BTSC
BTSS
BTST
BTSTS
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
BTG
f,#bit4
Bit Toggle f
None
BTG
Ws,#bit4
Bit Toggle Ws
None
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
(2 or 3)
None
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
(2 or 3)
None
BTSS
f,#bit4
Bit Test f, Skip if Set
1
(2 or 3)
None
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
(2 or 3)
None
BTST
f,#bit4
Bit Test f
BTST.C
Ws,#bit4
Bit Test Ws to C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
BTST.C
Ws,Wb
Bit Test Ws<Wb> to C
C
Z
BTST.Z
Ws,Wb
Bit Test Ws<Wb> to Z
BTSTS
f,#bit4
Bit Test then Set f
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
14
CALL
CALL
lit23
Call subroutine
None
CALL
Wn
Call indirect subroutine
None
15
CLR
CLR
f = 0x0000
None
CLR
WREG
WREG = 0x0000
None
CLR
Ws
Ws = 0x0000
None
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
OA,OB,SA,SB
16
CLRWDT
CLRWDT
Clear Watchdog Timer
WDTO,Sleep
17
COM
COM
f=f
N,Z
COM
f,WREG
WREG = f
N,Z
COM
Ws,Wd
Wd = Ws
N,Z
CP
Compare f with WREG
C,DC,N,OV,Z
CP
Wb,#lit5
Compare Wb with lit5
C,DC,N,OV,Z
CP
Wb,Ws
Compare Wb with Ws (Wb Ws)
C,DC,N,OV,Z
CP0
Compare f with 0x0000
C,DC,N,OV,Z
CP0
Ws
Compare Ws with 0x0000
C,DC,N,OV,Z
CPB
Compare f with WREG, with Borrow
C,DC,N,OV,Z
CPB
Wb,#lit5
Compare Wb with lit5, with Borrow
C,DC,N,OV,Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow

(Wb - Ws - C)
C,DC,N,OV,Z
18
19
20
CP
CP0
CPB
21
CPSEQ
CPSEQ
Wb, Wn
Compare Wb with Wn, skip if =
1
(2 or 3)
None
22
CPSGT
CPSGT
Wb, Wn
Compare Wb with Wn, skip if >
1
(2 or 3)
None
23
CPSLT
CPSLT
Wb, Wn
Compare Wb with Wn, skip if <
1
(2 or 3)
None
24
CPSNE
CPSNE
Wb, Wn
Compare Wb with Wn, skip if
1
(2 or 3)
None
25
DAW
DAW
Wn
Wn = decimal adjust Wn
26
DEC
DEC
f=f-1
C,DC,N,OV,Z
DEC
f,WREG
WREG = f - 1
C,DC,N,OV,Z
DEC
Ws,Wd
Wd = Ws - 1
C,DC,N,OV,Z
DEC2
f=f-2
C,DC,N,OV,Z
DEC2
f,WREG
WREG = f - 2
C,DC,N,OV,Z
DEC2
Ws,Wd
Wd = Ws - 2
C,DC,N,OV,Z
DISI
#lit14
Disable Interrupts for k instruction cycles
None
27
28
DEC2
DISI
DS70283J-page 225

TABLE 22-2:
Base
Instr
#
29
Assembly
Mnemonic
DIV
Assembly Syntax
# of
# of
Words Cycles
Description
Status Flags
Affected
DIV.S
Wm,Wn
Signed 16/16-bit Integer Divide
18
N,Z,C,OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
18
N,Z,C,OV
DIV.U
Wm,Wn
Unsigned 16/16-bit Integer Divide
18
N,Z,C,OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
18
N,Z,C,OV
Signed 16/16-bit Fractional Divide
18
N,Z,C,OV
None
30
DIVF
DIVF
31
DO
DO
#lit14,Expr
Do code to PC + Expr, lit14 + 1 times
DO
Wn,Expr
Do code to PC + Expr, (Wn) + 1 times
None
Wm,Wn
32
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance (no accumulate)
OA,OB,OAB,
SA,SB,SAB
33
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
OA,OB,OAB,
SA,SB,SAB
34
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
None
35
FBCL
FBCL
Ws,Wnd
Find Bit Change from Left (MSb) Side
36
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
37
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
38
GOTO
GOTO
Expr
Go to address
None
GOTO
Wn
Go to indirect
None
INC
f=f+1
C,DC,N,OV,Z
INC
f,WREG
WREG = f + 1
C,DC,N,OV,Z
C,DC,N,OV,Z
39
40
41
INC
INC2
IOR
INC
Ws,Wd
Wd = Ws + 1
INC2
f=f+2
C,DC,N,OV,Z
INC2
f,WREG
WREG = f + 2
C,DC,N,OV,Z
C,DC,N,OV,Z
INC2
Ws,Wd
Wd = Ws + 2
IOR
f = f .IOR. WREG
N,Z
IOR
f,WREG
WREG = f .IOR. WREG
N,Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
N,Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
N,Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
N,Z
OA,OB,OAB,
SA,SB,SAB
42
LAC
LAC
Wso,#Slit4,Acc
Load Accumulator
43
LNK
LNK
#lit14
Link Frame Pointer
None
44
LSR
LSR
f = Logical Right Shift f
C,N,OV,Z
LSR
f,WREG
WREG = Logical Right Shift f
C,N,OV,Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
C,N,OV,Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
N,Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
N,Z
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
,
AWB
Multiply and Accumulate
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
OA,OB,OAB,
SA,SB,SAB
MOV
f,Wn
Move f to Wn
None
MOV
Move f to f
N,Z
MOV
f,WREG
Move f to WREG
None
45
46
47
MAC
MOV
MOVSAC
MOV
#lit16,Wn
Move 16-bit literal to Wn
None
MOV.b
#lit8,Wn
Move 8-bit literal to Wn
None
MOV
Wn,f
Move Wn to f
None
MOV
Wso,Wdo
Move Ws to Wd
None
MOV
WREG,f
None
Move WREG to f
MOV.D
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd + 1):W(nd)
None
Prefetch and store accumulator
None
MOVSAC
DS70283J-page 226
Acc,Wx,Wxd,Wy,Wyd,AWB

TABLE 22-2:
Base
Instr
#
48
Assembly
Mnemonic
MPY
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
MPY
Multiply Wm by Wn to Accumulator
OA,OB,OAB,
SA,SB,SAB
MPY
Square Wm to Accumulator
OA,OB,OAB,
SA,SB,SAB
49
MPY.N
MPY.N
-(Multiply Wm by Wn) to Accumulator
None
50
MSC
MSC
,
AWB
Multiply and Subtract from Accumulator
OA,OB,OAB,
SA,SB,SAB
51
MUL
MUL.SS
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
None
MUL.SU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
None
MUL.US
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
None
MUL.UU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(Ws)
None
MUL.SU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
None
MUL.UU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(lit5)
None
MUL
W3:W2 = f * WREG
None
NEG
Acc
Negate Accumulator
OA,OB,OAB,
SA,SB,SAB
52
53
54
NEG
NOP
POP
NEG
f=f+1
C,DC,N,OV,Z
NEG
f,WREG
WREG = f + 1
C,DC,N,OV,Z
NEG
Ws,Wd
Wd = Ws + 1
C,DC,N,OV,Z
NOP
No Operation
None
NOPR
No Operation
None
POP
Pop f from Top-of-Stack (TOS)
None
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to

W(nd):W(nd + 1)
None
Pop Shadow Registers
All
Push f to Top-of-Stack (TOS)
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
None
PUSH.D
Wns
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
None
POP.S
55
PUSH
PUSH
Push Shadow Registers
None
Go into Sleep or Idle mode
WDTO,Sleep
Expr
Relative Call
None
Wn
Computed Call
None
REPEAT
#lit14
Repeat Next Instruction lit14 + 1 times
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 times
None
PUSH.S
56
PWRSAV
PWRSAV
57
RCALL
RCALL
RCALL
58
REPEAT
#lit1
59
RESET
RESET
Software device Reset
None
60
RETFIE
RETFIE
Return from interrupt
3 (2)
None
61
RETLW
RETLW
Return with literal in Wn
3 (2)
None
62
RETURN
RETURN
Return from Subroutine
3 (2)
None
63
RLC
RLC
f = Rotate Left through Carry f
C,N,Z
RLC
f,WREG
WREG = Rotate Left through Carry f
C,N,Z
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
C,N,Z
RLNC
f = Rotate Left (No Carry) f
N,Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
N,Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
N,Z
RRC
f = Rotate Right through Carry f
C,N,Z
RRC
f,WREG
WREG = Rotate Right through Carry f
C,N,Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
C,N,Z
64
65
RLNC
RRC
#lit10,Wn
DS70283J-page 227

TABLE 22-2:
Base
Instr
#
66
67
Assembly
Mnemonic
RRNC
SAC
Assembly Syntax
# of
# of
Words Cycles
Description
Status Flags
Affected
RRNC
f = Rotate Right (No Carry) f
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
N,Z
N,Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
N,Z
SAC
Acc,#Slit4,Wdo
Store Accumulator
None
SAC.R
Acc,#Slit4,Wdo
Store Rounded Accumulator
None
Ws,Wnd
Wnd = sign-extended Ws
C,N,Z
None
68
SE
SE
69
SETM
SETM
f = 0xFFFF
SETM
WREG
WREG = 0xFFFF
None
SETM
Ws
Ws = 0xFFFF
None
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
OA,OB,OAB,
SA,SB,SAB
SL
f = Left Shift f
C,N,OV,Z
SL
f,WREG
WREG = Left Shift f
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
C,N,OV,Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
N,Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
N,Z
SUB
Acc
Subtract Accumulators
OA,OB,OAB,
SA,SB,SAB
SUB
f = f - WREG
C,DC,N,OV,Z
SUB
f,WREG
WREG = f - WREG
C,DC,N,OV,Z
SUB
#lit10,Wn
Wn = Wn - lit10
C,DC,N,OV,Z
SUB
Wb,Ws,Wd
Wd = Wb - Ws
C,DC,N,OV,Z
SUB
Wb,#lit5,Wd
Wd = Wb - lit5
C,DC,N,OV,Z
SUBB
f = f - WREG - (C)
C,DC,N,OV,Z
SUBB
f,WREG
WREG = f - WREG - (C)
C,DC,N,OV,Z
SUBB
#lit10,Wn
Wn = Wn - lit10 - (C)
C,DC,N,OV,Z
70
71
72
73
74
75
76
SFTAC
SL
SUB
SUBB
SUBR
SUBBR
SWAP
SUBB
Wb,Ws,Wd
Wd = Wb - Ws - (C)
C,DC,N,OV,Z
SUBB
Wb,#lit5,Wd
Wd = Wb - lit5 - (C)
C,DC,N,OV,Z
SUBR
f = WREG - f
C,DC,N,OV,Z
SUBR
f,WREG
WREG = WREG - f
C,DC,N,OV,Z
SUBR
Wb,Ws,Wd
Wd = Ws - Wb
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBR
Wb,#lit5,Wd
Wd = lit5 - Wb
SUBBR
f = WREG - f - (C)
C,DC,N,OV,Z
SUBBR
f,WREG
WREG = WREG - f - (C)
C,DC,N,OV,Z
SUBBR
Wb,Ws,Wd
Wd = Ws - Wb - (C)
C,DC,N,OV,Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 - Wb - (C)
C,DC,N,OV,Z
SWAP.b
Wn
Wn = nibble swap Wn
None
SWAP
Wn
Wn = byte swap Wn
None
77
TBLRDH
TBLRDH
Ws,Wd
Read Prog<23:16> to Wd<7:0>
None
78
TBLRDL
TBLRDL
Ws,Wd
Read Prog<15:0> to Wd
None
79
TBLWTH
TBLWTH
Ws,Wd
Write Ws<7:0> to Prog<23:16>
None
80
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog<15:0>
None
81
ULNK
ULNK
Unlink Frame Pointer
None
82
XOR
XOR
f = f .XOR. WREG
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
N,Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
N,Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
N,Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
N,Z
ZE
Ws,Wnd
Wnd = Zero-extend Ws
C,Z,N
83
ZE
DS70283J-page 228

23.0
DEVELOPMENT SUPPORT
The PIC microcontrollers and dsPIC digital signal

controllers are supported with a full range of software
and hardware development tools:
Integrated Development Environment
- MPLAB IDE Software
Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
Simulators
- MPLAB SIM Software Simulator
Emulators
- MPLAB REAL ICE In-Circuit Emulator
In-Circuit Debuggers
- MPLAB ICD 3
- PICkit 3 Debug Express
Device Programmers
- PICkit 2 Programmer
- MPLAB PM3 Device Programmer
Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
23.1
MPLAB Integrated Development

Environment Software
The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows
operating system-based application that contains:
A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
A full-featured editor with color-coded context
A multiple project manager
Customizable data windows with direct edit of
contents
High-level source code debugging
Mouse over variable inspection
Drag and drop variables from source to watch
windows
Extensive on-line help
Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
Edit your source files (either C or assembly)
One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
DS70283J-page 229

23.2
MPLAB C Compilers for Various

Device Families
The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchips PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
23.3
HI-TECH C for Various Device

Families
The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchips PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple
platforms.
23.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
23.5
MPLINK Object Linker/

MPLIB Object Librarian
The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
Efficient linking of single libraries instead of many
smaller files
Enhanced code maintainability by grouping
related modules together
Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
23.6
MPLAB Assembler, Linker and

Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
Support for the entire device instruction set

Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
Integration into MPLAB IDE projects

User-defined macros to streamline
assembly code
Conditional assembly for multi-purpose
source files
Directives that allow complete control over the
assembly process
DS70283J-page 230

23.7
MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
23.8
MPLAB REAL ICE In-Circuit

Emulator System
MPLAB REAL ICE In-Circuit Emulator System is

Microchips next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC Flash MCUs and dsPIC Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineers PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
23.9
MPLAB ICD 3 In-Circuit Debugger

System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
23.10 PICkit 3 In-Circuit Debugger/

Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with users guide, lessons, tutorial, compiler and
MPLAB IDE software.
DS70283J-page 231

23.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
23.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use interface for programming and debugging Microchips Flash
families of microcontrollers. The full featured
Windows programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchips powerful MPLAB Integrated
Development Environment (IDE) the PICkit 2
enables in-circuit debugging on most PIC microcontrollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.
A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM
with users guide, lessons, tutorial, compiler and
MPLAB IDE software.
23.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
DS70283J-page 232
The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM and dsPICDEM demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ security ICs, CAN,
IrDA, PowerSmart battery management, SEEVAL
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

24.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 electrical characteristics.

Additional information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family are listed below. Exposure
to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device
at these or any other conditions above the parameters indicated in the operation listings of this specification is not
implied.
Absolute Maximum Ratings(1)

Ambient temperature under bias.............................................................................................................-40C to +125C
Storage temperature .............................................................................................................................. -65C to +160C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(4) .................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to Vss when VDD 3.0V(4) .................................................... -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(4)..................................................... -0.3V to 3.6V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2) ...........................................................................................................................250 mA
Maximum output current sunk by any I/O pin(3) ........................................................................................................4 mA
Maximum output current sourced by any I/O pin(3) ...................................................................................................4 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2) ...............................................................................................................200 mA
Note 1: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 24-2).
3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx
and PGEDx pins, which are able to sink/source 12 mA.
4: Refer to the Pin Diagrams section for 5V tolerant pins.
DS70283J-page 233

24.1
DC Characteristics
TABLE 24-1:
OPERATING MIPS VS. VOLTAGE

Max MIPS
Characteristic
DC5
TABLE 24-2:
VDD Range
(in Volts)
Temp Range
(in C)
3.0-3.6V
-40C to +85C
40
3.0-3.6V
-40C to +125C
40
dsPIC33FJ16MC304
THERMAL OPERATING CONDITIONS

Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
+125
Operating Ambient Temperature Range
TA
-40
+85
TJ
-40
+140
TA
-40
+125
Industrial Temperature Devices
Extended Temperature Devices
Power Dissipation:
Internal chip power dissipation:
PINT = VDD x (IDD - IOH)
PD
PINT + PI/O
PDMAX
(TJ - TA)/ JA
I/O Pin Power Dissipation:

I/O = ({VDD - VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 24-3:
THERMAL PACKAGING CHARACTERISTICS

Characteristic
Package Thermal Resistance, 44-pin QFN

Package Thermal Resistance, 44-pin TFQP
Package Thermal Resistance, 28-pin SPDIP
Package Thermal Resistance, 28-pin SOIC
Package Thermal Resistance, 28-pin SSOP
Package Thermal Resistance, 28-pin QFN-S
Note 1:
Symbol
JA
JA
JA
JA
JA
JA
Typ
Max
Unit
Notes
32
C/W
45
C/W
45
C/W
50
C/W
71
C/W
35
C/W
Junction to ambient thermal resistance, Theta-JA ( JA) numbers are achieved by package simulations.
DS70283J-page 234

TABLE 24-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
3.0
3.6
Conditions
Operating Voltage
DC10
Supply Voltage
VDD
(2)
Industrial and Extended
DC12
VDR
RAM Data Retention Voltage
1.8
DC16
VPOR
VDD Start Voltage

to ensure internal
Power-on Reset signal
VSS
DC17
SVDD
VDD Rise Rate

to ensure internal
Power-on Reset signal
0.03
Note 1:
2:
V/ms 0-3.0V in 0.1s
Data in Typ column is at 3.3V, 25C unless otherwise stated.

This is the limit to which VDD may be lowered without losing RAM data.
DS70283J-page 235

TABLE 24-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)

DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Operating Current (IDD)(2)

DC20d
20
30
mA
-40C
DC20a
19
22
mA
+25C
DC20b
19
25
mA
+85C
DC20c
19
30
mA
+125C
DC21d
28
40
mA
-40C
DC21a
27
30
mA
+25C
DC21b
27
32
mA
+85C
DC21c
27
36
mA
+125C
DC22d
33
50
mA
-40C
DC22a
33
40
mA
+25C
DC22b
33
40
mA
+85C
DC22c
33
50
mA
+125C
DC23d
44
60
mA
-40C
DC23a
43
50
mA
+25C
DC23b
42
55
mA
+85C
DC23c
41
65
mA
+125C
DC24d
55
75
mA
-40C
DC24a
54
65
mA
+25C
DC24b
52
70
mA
+85C
DC24c
51
80
mA
+125C
Note 1:
2:
3:
3.3V
10 MIPS(3)
3.3V
16 MIPS(3)
3.3V
20 MIPS(3)
3.3V
30 MIPS(3)
3.3V
40 MIPS
Data in Typical column is at 3.3V, 25C unless otherwise stated.

The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS.
MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are
operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits
are all zeroed).
These parameters are characterized, but are not tested in manufacturing.
DS70283J-page 236

TABLE 24-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core OFF Clock ON Base Current(2)

DC40d
20
mA
-40C
DC40a
mA
+25C
DC40b
10
mA
+85C
DC40c
20
mA
+125C
DC41d
10
20
mA
-40C
DC41a
mA
+25C
DC41b
10
mA
+85C
DC41c
20
mA
+125C
DC42d
11
20
mA
-40C
DC42a
10
10
mA
+25C
DC42b
10
12
mA
+85C
DC42c
10
20
mA
+125C
DC43d
14
25
mA
-40C
DC43a
13
14
mA
+25C
DC43b
13
15
mA
+85C
DC43c
13
25
mA
+125C
DC44d
14
25
mA
-40C
DC44a
17
20
mA
+25C
DC44b
17
20
mA
+85C
DC44c
18
30
mA
+125C
Note 1:
2:
3:
3.3V
10 MIPS
3.3V
16 MIPS
3.3V
20 MIPS
3.3V
30 MIPS
3.3V
40 MIPS
Data in Typical column is at 3.3V, 25C unless otherwise stated.

Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module
Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.
DS70283J-page 237

TABLE 24-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Power-Down Current (IPD)(2)

DC60d
55
500
-40C
DC60a
63
300
+25C
DC60b
85
350
+85C
DC60c
146
600
+125C
DC61d
15
-40C
DC61a
+25C
DC61b
+85C
DC61c
+125C
Note 1:
2:
3:
4:
5:
3.3V
Base Power-Down Current(3,4)
3.3V
Watchdog Timer Current: IWDT(3,5)
Data in the Typical column is at 3.3V, 25C unless otherwise stated.

Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled to VSS. WDT, etc., are all switched off, and VREGS (RCON<8>) = 1.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
These currents are measured on the device containing the most memory in this family.
TABLE 24-8:
DC CHARACTERISTICS: DOZE CURRENT (IDOZE)

DC CHARACTERISTICS
Parameter No.
Typical(1,2)
Max
Doze
Ratio
Units
DC73a
41
51
1:2
mA
DC73f
20
28
1:64
mA
DC73g
19
24
1:128
mA
DC70a
40
46
1:2
mA
DC70f
18
20
1:64
mA
DC70g
18
20
1:128
mA
DC71a
40
46
1:2
mA
DC71f
18
25
1:64
mA
DC71g
18
20
1:128
mA
DC72a
39
55
1:2
mA
DC72f
18
30
1:64
mA
DC72g
18
25
1:128
mA
Note 1:
2:
Conditions
-40C
3.3V
40 MIPS
+25C
3.3V
40 MIPS
+85C
3.3V
40 MIPS
+125C
3.3V
40 MIPS
Data in the Typical column is at 3.3V, 25C unless otherwise stated.

Parameters with Doze ratios of 1:2 and 1:64 are characterized, but are not tested in manufacturing.
DS70283J-page 238

TABLE 24-9:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage
DI10
I/O pins
VSS
0.2 VDD
DI15
MCLR
VSS
0.2 VDD
DI16
I/O Pins with OSC1 or SOSCI
VSS
0.2 VDD
DI18
SDAx, SCLx
VSS
0.3 VDD
SMBus disabled
SDAx, SCLx
VSS
0.8 V
SMBus enabled
DI19
VIH
Input High Voltage
DI20
I/O Pins Not 5V Tolerant(4)

I/O Pins 5V Tolerant(4)
0.7 VDD
0.7 VDD
VDD
5.5
V
V
DI28
SDAx, SCLx
0.7 VDD
5.5
SMBus disabled
SDAx, SCLx
2.1
5.5
SMBus enabled
50
250
400
VDD = 3.3V, VPIN = VSS
DI29
ICNPU
CNx Pull-up Current
DI30
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:

The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
See Pin Diagrams for a list of digital-only and analog pins.
VIL source < (VSS 0.3). Characterized but not tested.
Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any positive input injection current from input sources > 5.5V.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical absolute instantaneous sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
DS70283J-page 239

TABLE 24-9:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)

DC CHARACTERISTICS
Param
Symbol
No.
IIL
Characteristic
Min
Typ(1)
Max
Units
Conditions
Input Leakage Current(2,3)
DI50
I/O Pins 5V Tolerant(4)
VSS VPIN VDD,

Pin at high-impedance
DI51
VSS VPIN VDD,

Pin at high-impedance,
-40C TA +85C
DI51a
Shared with external reference pins, -40C TA

+85C
DI51b
3.5
VSS VPIN VDD, Pin at

high-impedance,
-40C TA +125C
DI51c
Analog pins shared with

external reference pins,
-40C TA +125C
DI55
MCLR
VSS VPIN VDD
DI56
OSC1
VSS VPIN VDD,

XT and HS modes
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:

voltages.
tested.
DS70283J-page 240

TABLE 24-9:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)

DC CHARACTERISTICS
Param
Symbol
No.
IICL
Characteristic
DI60c
3:
4:
5:
6:
7:
8:
9:
Units
Conditions
-5(5,8)
mA
All pins except VDD, VSS,

AVDD, AVSS, MCLR, VCAP,
SOSCI, SOSCO, and RB14
+5(6,7,8)
mA
All pins except VDD, VSS,

AVDD, AVSS, MCLR, VCAP,
SOSCI, SOSCO, RB14,
and digital 5V-tolerant
designated pins
-20(9)
+20(9)
mA
Absolute instantaneous
sum of all input injection
currents from all I/O pins
( | IICL + | IICH | ) IICT
Total Input Injection Current

(sum of all I/O and control pins)
Note 1:
2:
Max
Input High Injection Current
DI60b
IICT
Typ(1)
Input Low Injection Current
DI60a
IICH
Min

voltages.
tested.
DS70283J-page 241

TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Param
Symbol
No.
VOL
DO10
DO16
VOH
Characteristic
Min
Typ
Max
Units
Conditions
I/O ports
0.4
IOL = 2 mA, VDD = 3.3V
OSC2/CLKO
0.4
Output Low Voltage
Output High Voltage
DO20
I/O ports
2.40
IOH = -2.3 mA, VDD = 3.3V
DO26
OSC2/CLKO
2.41
IOH = -1.3 mA, VDD = 3.3V
TABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR

DC CHARACTERISTICS
Param
No.
Symbol

Characteristic(1)
Min
Typ
Max
Units
Conditions
2.40
2.55
VDD
BO10
VBOR
Note 1:
Parameters are for design guidance only and are not tested in manufacturing.
DS70283J-page 242
BOR Event on VDD transition

high-to-low

TABLE 24-12: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic(3)
Min
Typ(1)
Max
10,000
Units
Conditions
Program Flash Memory

D130
EP
Cell Endurance
D131
VPR
VDD for Read
VMIN
3.6
VMIN = Minimum operating

voltage
D132B
VPEW
VDD for Self-Timed Write
VMIN
3.6
VMIN = Minimum operating

voltage
D134
TRETD
Characteristic Retention
20
Year Provided no other specifications

are violated, -40 C to +125 C
D135
IDDP
Supply Current during

Programming
10
mA
D136a
TRW
Row Write Time
1.32
1.74
ms
TRW = 11064 FRC cycles,

TA = +85C, See Note 2
D136b
TRW
Row Write Time
1.28
1.79
ms
TRW = 11064 FRC cycles,

D137a
TPE
Page Erase Time
20.1
26.5
ms
TPE = 168517 FRC cycles,

D137b
TPE
Page Erase Time
19.5
27.3
ms
TPE = 168517 FRC cycles,

D138a
TWW
Word Write Cycle Time
42.3
55.9
TWW = 355 FRC cycles,

D138b
TWW
Word Write Cycle Time
41.1
57.6
TWW = 355 FRC cycles,

Note 1:
2:
3:
E/W -40 C to +125 C

Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max).
This parameter depends on the FRC accuracy (see Table 24-18) and the value of the FRC Oscillator Tuning register (see Register 8-4). For complete details on calculating the Minimum and Maximum time see
Section 5.3 Programming Operations.
These parameters are assured by design, but are not characterized or tested in manufacturing.
TABLE 24-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Operating temperature
-40C TA +85C for Industrial
Param
No.
Note 1:
Symbol
CEFC
Characteristics
External Filter Capacitor
Value(1)
Min
Typ
Max
Units
4.7
10
Comments
Capacitor must be low
series resistance
(< 5 ohms)
Typical VCAP voltage = 2.5V when VDD VDDMIN.
DS70283J-page 243

24.2
AC Characteristics and Timing

Parameters
This section defines dsPIC33FJ32MC202/204 and

dsPIC33FJ16MC304 AC characteristics and timing
parameters.
TABLE 24-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS AC

Operating voltage VDD range as described in Table 24-1.
AC CHARACTERISTICS
FIGURE 24-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 for all pins except OSC2
Load Condition 2 for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 24-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param
Symbol
No.
DO50
Characteristic
Min
Typ
Max
Units
Conditions
15
pF
In XT and HS modes when

external clock is used to drive
OSC1
COSC2
OSC2/SOSC2 pin
DO56
CIO
All I/O pins and OSC2
50
pF
EC mode
DO58
CB
SCLx, SDAx
400
pF
In I2C mode
DS70283J-page 244

FIGURE 24-2:
EXTERNAL CLOCK TIMING

Q1
Q2
Q3
Q4
Q1
Q2
OS30
OS30
Q3
Q4
OSC1
OS20
OS31
OS31
OS25
CLKO
OS41
OS40
TABLE 24-16: EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
OS10
Symb
FIN
Min
Typ(1)
Max
Units
External CLKI Frequency(4)

(External clocks allowed only
in EC and ECPLL modes)
DC
40
MHz
EC
Oscillator Crystal Frequency(5)
3.5
10
10
40
33
MHz
MHz
kHz
XT
HS
SOSC
12.5
DC
ns
25
DC
ns
0.375 x TOSC
0.625 x TOSC
ns
EC
Characteristic
OS20
TOSC
TOSC = 1/FOSC(4)
OS25
TCY
Instruction Cycle Time(2,4)

(OSC1)(5)
Conditions
OS30
TosL,
TosH
External Clock in
High or Low Time
OS31
TosR,
TosF
External Clock in (OSC1)(5)

Rise or Fall Time
20
ns
EC
OS40
TckR
CLKO Rise Time(3,5)
5.2
ns
5.2
ns
14
16
18
mA/V
Time(3,5)
OS41
TckF
CLKO Fall
OS42
GM
External Oscillator
Transconductance(6)
Note 1:
2:
3:
4:
5:
6:
VDD = 3.3V
TA = +25C

Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at min.
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
max. cycle time limit is DC (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
These parameters are characterized by similarity, but are tested in manufacturing at FIN = 40 MHz only.
These parameters are characterized by similarity, but are not tested in manufacturing.
Data for this parameter is preliminary. This parameter is characterized, but is not tested in manufacturing.
DS70283J-page 245

TABLE 24-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Param
No.
OS50
FPLLI
OS51
FSYS
OS52
OS53
TLOCK
DCLK
Note 1:
2:
3:
Characteristic
Min
Typ(1)
Max
Units
PLL Voltage Controlled

Oscillator (VCO) Input
Frequency Range(2)
On-Chip VCO System
Frequency(3)
PLL Start-up Time (Lock Time)(3)
CLKO Stability (Jitter)(3)
0.8
MHz
100
200
MHz
0.9
-3
1.5
0.5
3.1
3
mS
%
Symbol
Conditions
ECPLL, XTPLL modes
Measured over 100 ms

period
Data in Typ column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only
and are not tested.
These parameters are characterized by similarity, but are tested in manufacturing at 7.7 MHz input only.
These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases
or communication clocks use this formula:
D CLK
Peripheral Clock Jitter = ----------------------------------------------------------------------F OSC
------------------------------------------------------------
Peripheral Bit Rate Clock
For example: Fosc = 32 MHz, DCLK = 3%, SPI bit rate clock, (i.e., SCK) is 2 MHz.
D CLK
3%
3%
SPI SCK Jitter = ------------------------------ = ---------- = -------- = 0.75%
4
16
32
MHz
--------------------
2 MHz
TABLE 24-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY

AC CHARACTERISTICS
Param
No.
Characteristic

Operating temperature
-40C TA +85C for industrial
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)

F20a
FRC
-2
+2
%
-40C TA +85C
VDD = 3.0-3.6V
VDD = 3.0-3.6V
F20b
FRC
-5
+5
%
-40C TA +125C
Note 1: Frequency calibrated at 25C and 3.3V. TUN bits can be used to compensate for temperature drift.
TABLE 24-19: INTERNAL RC ACCURACY

AC CHARACTERISTICS
Param
No.
Characteristic

Min
Typ
Max
Units
Conditions
LPRC @ 32.768 kHz(1,2)

F21a LPRC
-15
6
+15
%
-40C TA +85C
VDD = 3.0-3.6V
VDD = 3.0-3.6V
F21b LPRC
-40
+40
%
-40C TA +125C
Note 1: Change of LPRC frequency as VDD changes.
2: LPRC impacts the Watchdog Timer Time-out Period (TWDT1). See Section 21.4 Watchdog Timer
(WDT) for more information.
DS70283J-page 246

FIGURE 24-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-20: I/O TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(2)
Min
Typ(1)
Max
Units
Conditions
DO31
TIOR
Port Output Rise Time
10
25
ns
DO32
TIOF
Port Output Fall Time
10
25
ns
DI35
TINP
INTx Pin High or Low Time (input)
25
ns
DI40
TRBP
CNx High or Low Time (input)
TCY
Note 1:
2:

DS70283J-page 247

FIGURE 24-4:
VDD
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING CHARACTERISTICS
SY12
MCLR
SY10
Internal
POR
SY11
PWRT
Time-out
OSC
Time-out
SY30
Internal
Reset
Watchdog
Timer
Reset
SY13
SY20
SY13
I/O Pins
SY35
FSCM
Delay
DS70283J-page 248

TABLE 24-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(2)
Max
Units
Conditions
SY10
TMCL
MCLR Pulse Width (low)(1)
-40C to +85C
SY11
TPWRT
Power-up Timer Period(1)
2
4
8
16
32
64
128
ms
-40C to +85C
User programmable
SY12
TPOR
Power-on Reset Delay(3)
10
30
-40C to +85C
SY13
TIOZ
I/O High-Impedance from

MCLR Low or Watchdog
Timer Reset(1)
0.68
0.72
1.2
SY20
TWDT1
Watchdog Timer Time-out

Period (1)
ms
See Section 21.4 Watchdog

Timer (WDT) and LPRC
parameter F21a (Table 24-21).
SY30
TOST
Oscillator Start-up Time
1024
TOSC
TOSC = OSC1 period
SY35
TFSCM
Fail-Safe Clock Monitor

Delay(1)
500
900
-40C to +85C
Note 1:
2:
3:
These parameters are characterized but not tested in manufacturing.

DS70283J-page 249

FIGURE 24-5:
TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
OS60
Tx20
TMRx
TABLE 24-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)

AC CHARACTERISTICS
Param
No.
TA10
TA11
Symbol
TTXH
TTXL
Characteristic(2)
TxCK High Time
TxCK Low Time
Min
Typ
Max
Units
Conditions
Synchronous,
no prescaler
0.5 TCY + 20
ns
Must also meet

parameter TA15
Synchronous,
with prescaler
10
ns
Asynchronous
10
ns
Synchronous,
no prescaler
0.5 TCY + 20
ns
Synchronous,
with prescaler
10
ns
Asynchronous
TA15
TTXP
TxCK Input Period Synchronous,

no prescaler
Synchronous,
with prescaler
Asynchronous
OS60
Ft1
TA20
TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment
Note 1:
2:
SOSC1/T1CK Oscillator Input

frequency Range (oscillator enabled
by setting bit TCS (T1CON<1>))
10
ns
TCY + 40
ns
Greater of:
20 ns or
(TCY + 40)/N
Must also meet

parameter TA15
N = prescale
value
(1, 8, 64, 256)
20
ns
DC
50
kHz
1.5 TCY
0.5 TCY
Timer1 is a Type A.
DS70283J-page 250

TABLE 24-23: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
TB10
TtxH
TxCK High Synchronous

mode
Time
Greater of:
20 or
(TCY + 20)/N
ns
Must also meet

parameter TB15
N = prescale
value
(1, 8, 64, 256)
TB11
TtxL
TxCK Low Synchronous

Time
mode
Greater of:
20 or
(TCY + 20)/N
ns
Must also meet

parameter TB15
N = prescale
value
(1, 8, 64, 256)
TB15
TtxP
TxCK
Input
Period
Greater of:
40 or
(2 TCY + 40)/N
ns
N = prescale
value
(1, 8, 64, 256)
TB20
TCKEXTMRL Delay from External TxCK 0.75 TCY + 40

Clock Edge to Timer Increment
1.75 TCY + 40
ns
Note 1:
Synchronous
mode
TABLE 24-24: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
TC10
TtxH
TxCK High
Time
Synchronous
TCY + 20
ns
Must also meet

parameter TC15
TC11
TtxL
TxCK Low
Time
Synchronous
TCY + 20
ns
Must also meet

parameter TC15
TC15
TtxP
TxCK Input
Period
Synchronous,
with prescaler
2 TCY + 40
ns
N = prescale
value
(1, 8, 64, 256)
TC20
TCKEXTMRL Delay from External TxCK

Clock Edge to Timer Increment
0.75 TCY + 40
1.75 TCY + 40
ns
Note 1:
DS70283J-page 251

FIGURE 24-6:
TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS
QEB
TQ11
TQ10
TQ15
TQ20
POSCNT
TABLE 24-25: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
TQ10
TtQH
TQCK High Time
Synchronous,
with prescaler
TCY + 20
ns
Must also meet

parameter TQ15
TQ11
TtQL
TQCK Low Time
Synchronous,
with prescaler
TCY + 20
ns
Must also meet

parameter TQ15
TQ15
TtQP
TQCP Input
Period
Synchronous, 2 * TCY + 40
with prescaler
ns
TQ20
TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment
1.5 TCY
Note 1:
0.5 TCY
DS70283J-page 252

FIGURE 24-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

ICx
IC10
IC11
IC15
TABLE 24-26: INPUT CAPTURE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol
IC10
TccL
Characteristic(1)
ICx Input Low Time
Min
No Prescaler
TccH
ICx Input High Time
No Prescaler
Note 1:
TccP
ICx Input Period
Conditions
ns
10
ns
0.5 TCY + 20
ns
10
ns
(TCY + 40)/N
ns
With Prescaler
IC15
Units
0.5 TCY + 20
With Prescaler
IC11
Max
N = prescale
value (1, 4, 16)
FIGURE 24-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
TABLE 24-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)

Min
Typ
Max
Units
Conditions
OC10
TccF
OCx Output Fall Time
ns
See parameter D032
OC11
TccR
OCx Output Rise Time
ns
See parameter D031
Note 1:
DS70283J-page 253

FIGURE 24-9:
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
Active
OCx
Tri-state
TABLE 24-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O

Change
TCY + 20
ns
OC20
TFLT
Fault Input Pulse-Width
TCY + 20
ns
Note 1:
DS70283J-page 254

FIGURE 24-10:
MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS

MP30
FLTA
MP20
PWMx
FIGURE 24-11:
MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS

MP11 MP10
PWMx
TABLE 24-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
MP10
TFPWM
PWM Output Fall Time
ns
See parameter D032
MP11
TRPWM
PWM Output Rise Time
ns
See parameter D031
TFD
Fault Input to PWM

I/O Change
50
ns
TFH
Minimum Pulse-Width
50
ns
MP20
MP30
Note 1:
DS70283J-page 255

FIGURE 24-12:
QEA/QEB INPUT CHARACTERISTICS

TQ36
QEA
(input)
TQ30
TQ31
TQ35
QEB
(input)
TQ41
TQ40
TQ30
TQ31
TQ35
QEB
Internal
TABLE 24-30: QUADRATURE DECODER TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Max
Units
Conditions
6 TCY
ns
TQ30
TQUL
TQ31
TQUH
Quadrature Input High Time
6 TCY
ns
TQ35
TQUIN
Quadrature Input Period
12 TCY
ns
TQ36
TQUP
Quadrature Phase Period
3 TCY
ns
TQ40
TQUFL
Filter Time to Recognize Low,

with Digital Filter
3 * N * TCY
ns
N = 1, 2, 4, 16, 32, 64,

128 and 256 (Note 3)
TQ41
TQUFH
Filter Time to Recognize High,

with Digital Filter
3 * N * TCY
ns
N = 1, 2, 4, 16, 32, 64,

128 and 256 (Note 3)
Note 1:
2:

Data in Typ column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only
and are not tested.
N = Index Channel Digital Filter Clock Divide Select bits. Refer to Section 15. Quadrature Encoder
Interface (QEI) (DS70208) in the dsPIC33F/PIC24H Family Reference Manual. Please see the
Microchip web site for the latest dsPIC33F/PIC24H Family Reference Manual sections.
3:
DS70283J-page 256
Quadrature Input Low Time
Typ(2)

FIGURE 24-13:
QEI MODULE INDEX PULSE TIMING CHARACTERISTICS
QEA
(input)
QEB
(input)
Ungated
Index
TQ50
TQ51
Index Internal
TQ55
Position Counter Reset
TABLE 24-31: QEI INDEX PULSE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol
TQ50
TqIL
TQ51
TQ55
Note 1:
2:
Characteristic(1)
Min
Max
Units
Conditions
Filter Time to Recognize Low,

with Digital Filter
3 * N * TCY
ns
N = 1, 2, 4, 16, 32, 64,

128 and 256 (Note 2)
TqiH
Filter Time to Recognize High,

with Digital Filter
3 * N * TCY
ns
N = 1, 2, 4, 16, 32, 64,

128 and 256 (Note 2)
Tqidxr
Index Pulse Recognized to Position

Counter Reset (ungated index)
3 TCY
ns

Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for
forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but
index pulse recognition occurs on falling edge.
DS70283J-page 257

TABLE 24-32: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
15 Mhz
Table 24-33
9 Mhz
9 Mhz
15 Mhz
11 Mhz
Slave
Transmit/Receive
(Full-Duplex)
CKE
Table 24-34
Table 24-35
15 Mhz
11 Mhz
FIGURE 24-14:
Master
Transmit/Receive
(Full-Duplex)
CKP
SMP
0,1
0,1
0,1
0,1
0,1
Table 24-36
Table 24-37
Table 24-38
Table 24-39
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 0) TIMING

CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
LSb
SP30, SP31
FIGURE 24-15:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING

CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
SDOx
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
DS70283J-page 258

TABLE 24-33: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP10
TscP
Maximum SCK Frequency
15
MHz
SP20
TscF
SCKx Output Fall Time
ns
See parameter DO32

and Note 4
SP21
TscR
SCKx Output Rise Time
ns
See parameter DO31

and Note 4
SP30
TdoF
SDOx Data Output Fall Time
ns
See parameter DO32

and Note 4
SP31
TdoR
SDOx Data Output Rise Time
ns
See parameter DO31

and Note 4
SP35
TscH2doV,
TscL2doV
SDOx Data Output Valid after

SCKx Edge
20
ns
SP36
TdiV2scH,
TdiV2scL
SDOx Data Output Setup to

First SCKx Edge
30
ns
Note 1:
2:
3:
4:

The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS70283J-page 259

FIGURE 24-16:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING

CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
SP40
SDIx
LSb
MSb In
LSb In
Bit 14 - - - -1
SP41
TABLE 24-34: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP10
SP20
TscP
TscF

MHz
ns
SP21
TscR
ns
SP30
TdoF
ns
SP31
TdoR
ns
SP35
TscH2doV, SDOx Data Output Valid after
6
20
ns
TscL2doV SCKx Edge
TdoV2sc, SDOx Data Output Setup to
30
ns
TdoV2scL First SCKx Edge

TdiV2scH, Setup Time of SDIx Data
30
ns
TdiV2scL Input to SCKx Edge

TscH2diL, Hold Time of SDIx Data Input
30
ns
TscL2diL
to SCKx Edge
The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
SP36
SP40
SP41
Note 1:
2:
3:
4:
DS70283J-page 260
See parameter DO32

and Note 4
See parameter DO31
and Note 4
See parameter DO32
and Note 4
See parameter DO31
and Note 4

FIGURE 24-17:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING

CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
SP30, SP31
SDIx
MSb In
LSb
SP30, SP31
LSb In
Bit 14 - - - -1
SP40 SP41
TABLE 24-35: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
-40C to +125C and
see Note 3
See parameter DO32
and Note 4
See parameter DO31
and Note 4
See parameter DO32
and Note 4
See parameter DO31
and Note 4
SP10
TscP
MHz
SP20
TscF
ns
SP21
TscR
ns
SP30
TdoF
ns
SP31
TdoR
ns
SP35
6
20
ns
TscL2doV SCKx Edge
TdoV2scH, SDOx Data Output Setup to
30
ns

TdiV2scH, Setup Time of SDIx Data
30
ns
TdiV2scL Input to SCKx Edge

TscH2diL, Hold Time of SDIx Data Input
30
ns
TscL2diL
to SCKx Edge
The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
SP36
SP40
SP41
Note 1:
2:
3:
4:
DS70283J-page 261

FIGURE 24-18:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING

CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDI
SDIx
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
DS70283J-page 262

TABLE 24-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP70
SP72
TscP
TscF
Maximum SCK Input Frequency

SCKx Input Fall Time
15
MHz
ns
SP73
TscR
SCKx Input Rise Time
ns
SP30
TdoF
ns
SP31
TdoR
ns
SP35
TscH2doV,
TscL2doV
TdoV2scH,
TdoV2scL
TdiV2scH,
TdiV2scL

SCKx Edge
First SCKx Edge
Setup Time of SDIx Data Input
to SCKx Edge
20
ns
See parameter DO32

and Note 4
See parameter DO31
and Note 4
See parameter DO32
and Note 4
See parameter DO31
and Note 4
30
ns
30
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input

to SCKx Edge
30
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
ns
SP51
TssH2doZ
SSx to SDOx Output

High-Impedance(4)
10
50
ns
SP52
TscH2ssH SSx after SCKx Edge

TscL2ssH
1.5 TCY + 40
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
50
ns
SSx Edge
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must
not violate this specification.
SP36
SP40
Note 1:
2:
3:
4:
DS70283J-page 263

FIGURE 24-19:

CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
SP52
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
SDI
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
DS70283J-page 264

REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP70
TscP
11
MHz
SP72
TscF
ns
See parameter DO32

and Note 4
SP73
TscR
ns
See parameter DO31

and Note 4
SP30
TdoF
ns
See parameter DO32

and Note 4
SP31
TdoR
ns
See parameter DO31

and Note 4
SP35

TscL2doV SCKx Edge
20
ns
SP36

30
ns
SP40
TdiV2scH,
TdiV2scL

to SCKx Edge
30
ns
SP41
TscH2diL,
TscL2diL

to SCKx Edge
30
ns
SP50
TssL2scH,
TssL2scL
120
ns
SP51
TssH2doZ
SSx to SDOx Output

High-Impedance(4)
10
50
ns
SP52

TscL2ssH
1.5 TCY + 40
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after

SSx Edge
50
ns
Note 1:
2:
3:
4:

The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not
DS70283J-page 265

FIGURE 24-20:
SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING

CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
DS70283J-page 266

REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP70
TscP
15
MHz
SP72
TscF
ns
See parameter DO32

and Note 4
SP73
TscR
ns
See parameter DO31

and Note 4
SP30
TdoF
ns
See parameter DO32

and Note 4
SP31
TdoR
ns
See parameter DO31

and Note 4
SP35

TscL2doV SCKx Edge
20
ns
SP36

30
ns
SP40
TdiV2scH,
TdiV2scL

to SCKx Edge
30
ns
SP41
TscH2diL,
TscL2diL

to SCKx Edge
30
ns
SP50
TssL2scH,
TssL2scL
120
ns
SP51
TssH2doZ
SSx to SDOx Output

High-Impedance(4)
10
50
ns
SP52

TscL2ssH
1.5 TCY + 40
ns
See Note 4
Note 1:
2:
3:
4:

The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must
not violate this specification.
DS70283J-page 267

FIGURE 24-21:

CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
DS70283J-page 268

REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP70
TscP
11
MHz
SP72
TscF
ns
See parameter DO32

and Note 4
SP73
TscR
ns
See parameter DO31

and Note 4
SP30
TdoF
ns
See parameter DO32

and Note 4
SP31
TdoR
ns
See parameter DO31

and Note 4
SP35

TscL2doV SCKx Edge
20
ns
SP36

30
ns
SP40
TdiV2scH,
TdiV2scL

to SCKx Edge
30
ns
SP41
TscH2diL,
TscL2diL

to SCKx Edge
30
ns
SP50
TssL2scH,
TssL2scL
120
ns
SP51
TssH2doZ
SSx to SDOx Output

High-Impedance(4)
10
50
ns
SP52

TscL2ssH
1.5 TCY + 40
ns
See Note 4
Note 1:
2:
3:
4:

The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not
DS70283J-page 269

FIGURE 24-22:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
FIGURE 24-23:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM25
IM33
SDAx
In
IM40
IM40
IM45
SDAx
Out
DS70283J-page 270

TABLE 24-40: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Param
Symbol
No.
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
IM51
Note 1:
2:
3:
4:
Characteristic(3)
Min(1)
Max
Units
Conditions
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)

THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)

TF:SCL
SDAx and SCLx 100 kHz mode
300
ns
CB is specified to be
Fall Time
from 10 to 400 pF
300
ns
400 kHz mode
20 + 0.1 CB
(2)
100
ns
1 MHz mode
TR:SCL SDAx and SCLx 100 kHz mode
1000
ns
CB is specified to be
Rise Time
from 10 to 400 pF
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
TSU:DAT Data Input
100 kHz mode
250
ns
Setup Time
400 kHz mode
100
ns
40
ns
1 MHz mode(2)
THD:DAT Data Input
100 kHz mode
0
Hold Time
400 kHz mode
0
0.9
s
0.2
s
1 MHz mode(2)
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
s
Only relevant for
Setup Time
Repeated Start
s
condition
(2)
TCY/2 (BRG + 1)
s
1 MHz mode
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
s
After this period the
Hold Time
first clock pulse is
s
generated
s
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
Setup Time
s
s
ns
THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)

CY
/2
(BRG
+
1)
ns
Hold Time
400 kHz mode T
ns
TAA:SCL Output Valid
100 kHz mode
3500
ns
From Clock
400 kHz mode
1000
ns
(2)
400
ns
1 MHz mode
TBF:SDA Bus Free Time 100 kHz mode
4.7
s
Time the bus must be
free before a new
400 kHz mode
1.3
s
transmission can start
0.5
s
1 MHz mode(2)
CB
Bus Capacitive Loading
400
pF
Pulse Gobbler Delay

65
390
ns
See Note 4
TPGD
BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. Inter-Integrated Circuit (I2C)
(DS70195) in the dsPIC33F/PIC24H Family Reference Manual. Please see the Microchip web site for
the latest dsPIC33F/PIC24H Family Reference Manual sections.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
Typical value for this parameter is 130 ns.
DS70283J-page 271

FIGURE 24-24:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 24-25:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS25
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
DS70283J-page 272

TABLE 24-41: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Param. Symbol
IS10
IS11
Characteristic(2)
TLO:SCL Clock Low Time
THI:SCL
Clock High Time
IS20
TF:SCL
SDAx and SCLx

Fall Time
IS21
TR:SCL
SDAx and SCLx

Rise Time
IS25
TSU:DAT Data Input

Setup Time
IS26
THD:DAT Data Input

Hold Time
IS30
TSU:STA Start Condition

Setup Time
IS31
THD:STA Start Condition

Hold Time
IS33
TSU:STO Stop Condition

Setup Time
IS34
THD:ST
O
Stop Condition
Hold Time
IS40
TAA:SCL Output Valid

From Clock
IS45
TBF:SDA Bus Free Time
Min
Max
Units
100 kHz mode
4.7
400 kHz mode
1.3
1 MHz mode(1)
100 kHz mode
0.5
4.0
s
s
400 kHz mode
0.6
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
0.5
20 + 0.1 CB
20 + 0.1 CB
250
100
100
0
0
0
4.7
0.6
0.25
4.0
0.6
0.25
4.7
0.6
0.6
4000
600
250
0
0
0
4.7
300
300
100
1000
300
300
0.9
0.3
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
s
3500
1000
350
Conditions
Device must operate at a
minimum of 1.5 MHz
minimum of 10 MHz

minimum of 1.5 MHz
minimum of 10 MHz
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
Only relevant for Repeated

Start condition
After this period, the first
clock pulse is generated
Time the bus must be free

before a new transmission
can start
400 kHz mode

1.3
s
0.5
s
1 MHz mode(1)
IS50
CB
Bus Capacitive Loading
400
pF
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2: These parameters are characterized by similarity, but are not tested in manufacturing.
DS70283J-page 273

TABLE 24-42: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param Symb
No.
ol
Characteristic
Min.
Typ
Max.
Units
Lesser of
VDD + 0.3
or 3.6
VSS + 0.3
Conditions
Device Supply
AD01
AD02
AVDD
AVSS
Module
VDD Supply(2)
Module VSS Supply(2)
Greater of
VDD 0.3
or 3.0
VSS 0.3
Reference Inputs
AD05
VREFH
Reference Voltage High
AD05a
AD06
VREFL
Reference Voltage Low
AD06a
AVSS + 2.5
AVDD
See Note 1
3.0
3.6
VREFH = AVDD
VREFL = AVSS = 0, see Note 2
AVSS
AVDD 2.5
See Note 1
VREFH = AVDD
VREFL = AVSS = 0, see Note 2
AD07
VREF
Absolute Reference
Voltage(2)
2.5
3.6
VREF = VREFH - VREFL
AD08
IREF
Current Drain
250
550
10
A
A
ADC operating, See Note 1

ADC off, See Note 1
AD08a IAD
Operating Current
7.0
2.7
9.0
3.2
mA
mA
10-bit ADC mode, See Note 2

12-bit ADC mode, See Note 2
AD12
VINH
Input Voltage Range VINH(2)
VINL
VREFH
This voltage reflects Sample

and Hold Channels 0, 1, 2,
and 3 (CH0-CH3), positive
input
AD13
VINL
Input Voltage Range VINL(2)
VREFL
AVSS + 1V
This voltage reflects Sample

and Hold Channels 0, 1, 2,
and 3 (CH0-CH3), negative
input
AD17
RIN
Recommended Impedance
of Analog Voltage Source(3)
200
200
10-bit ADC
12-bit ADC
Analog Input
Note 1:
2:
3:
These parameters are not characterized or tested in manufacturing.

DS70283J-page 274

TABLE 24-43: ADC MODULE SPECIFICATIONS (12-BIT MODE)
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
ADC Accuracy (12-bit Mode) Measurements with external VREF+/VREF-(3)

AD20a
Nr
Resolution(4)
bits
AD21a
INL
Integral Nonlinearity
-2
+2
LSb
VINL = AVSS = VREFL = 0V, AVDD

= VREFH = 3.6V
AD22a
DNL
Differential Nonlinearity
>-1
<1
LSb

= VREFH = 3.6V
AD23a
GERR
Gain Error
3.4
10
LSb

= VREFH = 3.6V
AD24a
EOFF
Offset Error
0.9
LSb

= VREFH = 3.6V
AD25a
Monotonicity
12 data bits
Guaranteed(1)
ADC Accuracy (12-bit Mode) Measurements with internal VREF+/VREF-(3)

AD20a
Nr
Resolution(4)
AD21a
INL
-2
+2
LSb
VINL = AVSS = 0V, AVDD = 3.6V
AD22a
DNL
>-1
<1
LSb
AD23a
GERR
Gain Error
10.5
20
LSb
AD24a
EOFF
Offset Error
3.8
10
LSb
AD25a
Monotonicity
12 data bits
bits

Guaranteed(1)
Dynamic Performance (12-bit Mode)(2)

AD30a
THD
Total Harmonic Distortion
AD31a
SINAD
Signal to Noise and

Distortion
AD32a
SFDR
Spurious Free Dynamic

Range
AD33a
FNYQ
Input Signal Bandwidth
AD34a
ENOB
Effective Number of Bits
Note 1:
2:
3:
4:
-75
dB
68.5
69.5
dB
80
dB
250
kHz
11.09
11.3
bits
The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
These parameters are characterized, but are tested at 20 ksps only.
DS70283J-page 275

TABLE 24-44: ADC MODULE SPECIFICATIONS (10-BIT MODE)
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
ADC Accuracy (10-bit Mode) Measurements with external VREF+/VREF-(3)

AD20b
Nr
Resolution(4)
AD21b
INL
-1.5
+1.5
LSb
VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V
AD22b
DNL
>-1
<1
LSb

AVDD = VREFH = 3.6V
AD23b
GERR
Gain Error
LSb

AVDD = VREFH = 3.6V
AD24b
EOFF
Offset Error
LSb

AVDD = VREFH = 3.6V
AD25b
Monotonicity
10 data bits
bits
Guaranteed(1)
ADC Accuracy (10-bit Mode) Measurements with internal VREF+/VREF-(3)

AD20b
Nr
Resolution(4)
bits
AD21b
INL
-1
+1
LSb
10 data bits
AD22b
DNL
>-1
<1
LSb
AD23b
GERR
Gain Error
15
LSb
AD24b
EOFF
Offset Error
LSb
AD25b
Monotonicity

Guaranteed(1)
Dynamic Performance (10-bit Mode)(2)

AD30b
THD
Total Harmonic Distortion
-64
dB
AD31b
SINAD
Signal to Noise and

Distortion
57
58.5
dB
AD32b
SFDR
Spurious Free Dynamic

Range
72
dB
AD33b
FNYQ
550
kHz
AD34b
ENOB
Effective Number of Bits
9.16
9.4
bits
Note 1:
2:
3:
4:
The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
DS70283J-page 276

FIGURE 24-26:
ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS

(ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution
Set SAMP
Clear SAMP
SAMP
AD61
AD60
TSAMP
AD55
DONE
AD1IF
1 Software sets AD1CON. SAMP to start sampling.
5 Convert bit 11.
2 Sampling starts after discharge period. TSAMP is described in

in the dsPIC33F/PIC24H Family Reference Manual.
3 Software clears AD1CON. SAMP to start conversion.
6 Convert bit 10.
4 Sampling ends, conversion sequence starts.
9 One TAD for end of conversion.
7 Convert bit 1.
8 Convert bit 0.
TABLE 24-45: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Clock Parameters
Period(2)
AD50
TAD
ADC Clock
AD51
tRC
ADC Internal RC Oscillator

Period(2)
117.6
ns
250
ns
Conversion Rate
Time(2)
14 TAD
ns
500
Ksps
3.0 TAD
AD55
tCONV
Conversion
AD56
FCNV
Throughput Rate(2)
AD57
TSAMP
Sample Time(2)
Timing Parameters
AD60
tPCS
Conversion Start from Sample

Trigger(2)
2.0 TAD
3.0 TAD
Auto convert trigger not

selected
AD61
tPSS
Sample Start from Setting

Sample (SAMP) bit(2)
2.0 TAD
3.0 TAD
AD62
tCSS
Conversion Completion to
Sample Start (ASAM = 1)(2)
0.5 TAD
AD63
tDPU
Time to Stabilize Analog Stage

from ADC Off to ADC On(2)
20
Note 1:
2:
Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
DS70283J-page 277

FIGURE 24-27:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS

(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution Set SAMP
Clear SAMP
SAMP
AD61
AD60
AD55
TSAMP
AD55
DONE
AD1IF
1 Software sets AD1CON. SAMP to start sampling.
5 Convert bit 9.

3 Software clears AD1CON. SAMP to start conversion.
6 Convert bit 8.
7 Convert bit 0.
4 Sampling ends, conversion sequence starts.
FIGURE 24-28:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,

SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Set ADON
Execution
SAMP
TSAMP
AD55
TSAMP
AD55
AD55
AD1IF
DONE
1 Software sets AD1CON. ADON to start AD operation.
5 Convert bit 0.

3 Convert bit 9.

7 Begin conversion of next channel.
8 Sample for time specified by SAMC<4:0>.
4 Convert bit 8.
DS70283J-page 278

AC CHARACTERISTICS
Param
Symbol
No.

Characteristic
Min.
Typ(1)
Max.
Units
Conditions
Clock Parameters
(1)
AD50
TAD
ADC Clock Period
76
ns
AD51
tRC
ADC Internal RC Oscillator

Period(1)
250
ns
Conversion Rate
(1)
AD55
tCONV
Conversion Time
12 TAD
AD56
FCNV
Throughput Rate(1)
1.1
Msps
AD57
TSAMP
Sample Time(1)
2.0 TAD
Timing Parameters
AD60
tPCS
Conversion Start from Sample

Trigger(1)
2.0 TAD
3.0 TAD
AD61
tPSS
Sample Start from Setting

Sample (SAMP) bit(1)
2.0 TAD
3.0 TAD
AD62
tCSS
Conversion Completion to
Sample Start (ASAM = 1)(1)
0.5 TAD
AD63
tDPU
Time to Stabilize Analog Stage

from ADC Off to ADC On(1)
20
Note 1:
2:
Auto-Convert Trigger
not selected

Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
DS70283J-page 279

NOTES:
DS70283J-page 280

25.0
HIGH TEMPERATURE ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 electrical characteristics for
devices operating in an ambient temperature range of -40C to +150C.
Note:
Programming of the Flash memory is not allowed above 125C.
The specifications between -40C to +150C are identical to those shown in Section 24.0 Electrical Characteristics
for operation between -40C to +125C, with the exception of the parameters listed in this section.
Parameters in this section begin with an H, which denotes High temperature. For example, parameter DC10 in
Section 24.0 Electrical Characteristics is the Industrial and Extended temperature equivalent of HDC10.
Absolute maximum ratings for the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 high temperature devices are
listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional
operation of the device at these or any other conditions above the parameters indicated in the operation listings of this
specification is not implied.
Absolute Maximum Ratings(1)

Ambient temperature under bias(4) .........................................................................................................-40C to +150C
Storage temperature .............................................................................................................................. -65C to +160C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(5) .................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(5) .................................................... -0.3V to 3.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(5) .................................................... -0.3V to 5.6V
Maximum current out of VSS pin .............................................................................................................................60 mA
Maximum current into VDD pin(2) .............................................................................................................................60 mA
Maximum junction temperature............................................................................................................................. +155C
Maximum output current sunk by any I/O pin(3) ........................................................................................................1 mA
Maximum output current sourced by any I/O pin(3) ...................................................................................................1 mA
Maximum current sunk by all ports combined ........................................................................................................10 mA
Maximum current sourced by all ports combined(2) ................................................................................................10 mA
Note 1: Stresses above those listed under Absolute Maximum Ratings can cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods can affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 25-2).
3: Unlike devices at 125C and below, the specifications in this section also apply to the CLKOUT, VREF+,
VREF-, SCLx, SDAx, PGCx and PGDx pins.
4: AEC-Q100 reliability testing for devices intended to operate at 150C is 1,000 hours. Any design in which
the total operating time from 125C to 150C will be greater than 1,000 hours is not warranted without prior
written approval from Microchip Technology Inc.
5: Refer to the Pin Diagrams section for 5V tolerant pins.
DS70283J-page 281

25.1
High Temperature DC Characteristics
TABLE 25-1:
OPERATING MIPS VS. VOLTAGE

Max MIPS
Characteristic
VDD Range
(in Volts)
Temperature Range
(in C)
HDC5
3.0V to 3.6V
-40C to +150C
TABLE 25-2:
dsPIC33FJ16MC304
20
THERMAL OPERATING CONDITIONS

Rating
Symbol
Min
Typ
Max
Unit
TJ
-40
+155
TA
-40
+150
High Temperature Devices
Power Dissipation:
Internal chip power dissipation:
PINT = VDD x (IDD - IOH)
PD
PINT + PI/O
PDMAX
(TJ - TA)/JA
I/O Pin Power Dissipation:

I/O = ({VDD - VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 25-3:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Operating temperature -40C TA +150C for High Temperature
DC CHARACTERISTICS
Parameter
No.
Symbol
Characteristic
Min
Typ
Max
Units
3.0
3.3
3.6
Conditions
Operating Voltage
HDC10
Supply Voltage
VDD
TABLE 25-4:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS
Parameter
No.
-40C to +150C
Typical
Max
Units
Conditions
Power-Down Current (IPD)

HDC60e
250
2000
+150C
3.3V
Base Power-Down Current(1,3)
HDC61c
+150C
3.3V
Watchdog Timer Current: IWDT(2,4)
Note 1:
2:
3:
4:
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled to VSS. WDT, etc., are all switched off, and VREGS (RCON<8>) = 1.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
These currents are measured on the device containing the most memory in this family.
DS70283J-page 282

TABLE 25-5:
DC CHARACTERISTICS: DOZE CURRENT (IDD)

DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Operating Current (IPD)(1)

HDC20
19
35
mA
+150C
3.3V
10 MIPS
HDC21
27
45
mA
+150C
3.3V
16 MIPS
HDC22
33
55
mA
+150C
3.3V
20 MIPS
Note 1:
TABLE 25-6:
DC CHARACTERISTICS: DOZE CURRENT (IDOZE)

DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Doze
Ratio
Units
HDC72a
39
45
1:2
mA
HDC72f
18
25
1:64
mA
18
25
1:128
mA
HDC72g
Note 1:
+150C
3.3V
20 MIPS
Parameters with Doze ratios of 1:2 and 1:64 are characterized, but are not tested in manufacturing.
TABLE 25-7:
DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS
Param
No.
Conditions
Symbol
VOL
Characteristic
Min
Typ
Max
Units
Conditions
Output Low Voltage
HDO10
I/O ports
0.4
HDO16
OSC2/CLKO
0.4
VOH
Output High Voltage
HDO20
I/O ports
2.40
IOH = -1 mA, VDD = 3.3V
HDO26
OSC2/CLKO
2.41
IOH = -1 mA, VDD = 3.3V
DS70283J-page 283

TABLE 25-8:
DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)

Min
Typ
Max
Units
Conditions
10,000
E/W
-40 C to +150 C(2)
20
Year
1000 E/W cycles or less and no

other specifications are violated
Program Flash Memory

HD130 EP
Cell Endurance
HD134 TRETD
Characteristic Retention
Note 1:
2:
Programming of the Flash memory is not allowed above 125C.
DS70283J-page 284

25.2
AC Characteristics and Timing

Parameters
Parameters in this section begin with an H, which

denotes High temperature. For example, parameter
OS53 in Section 24.2 AC Characteristics and
Timing Parameters is the Industrial and Extended
temperature equivalent of HOS53.
The information contained in this section defines

AC characteristics and timing parameters for high
temperature devices. However, all AC timing
specifications in this section are the same as those in
Section 24.2 AC Characteristics and Timing
Parameters, with the exception of the parameters
listed in this section.
TABLE 25-9:
TEMPERATURE AND VOLTAGE SPECIFICATIONS AC

Operating voltage VDD range as described in Table 25-1.
AC CHARACTERISTICS
FIGURE 25-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 for all pins except OSC2
Load Condition 2 for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 25-10: PLL CLOCK TIMING SPECIFICATIONS

AC
CHARACTERISTICS Operating temperature -40C TA +150C for High Temperature
Param
No.
Symbol
Characteristic
CLKO Stability (Jitter)(1)
Min
Typ
Max
Units
-5
0.5
Conditions
Measured over 100 ms
period
HOS53
DCLK
Note 1:
These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time
bases or communication clocks use this formula:
D CLK
Peripheral Clock Jitter = ----------------------------------------------------------------------F OSC
-------------------------------------------------------------
Peripheral Bit Rate Clock
For example: Fosc = 32 MHz, DCLK = 5%, SPI bit rate clock, (i.e., SCK) is 2 MHz.
D CLK
5%
5%
SPI SCK Jitter = ------------------------------ = ---------- = -------- = 1.25%
4
16
32
MHz
--------------------
2 MHz
DS70283J-page 285

TABLE 25-11: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
AC
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
HSP35
TscH2doV,
TscL2doV

SCKx Edge
10
25
ns
HSP40
TdiV2scH,
TdiV2scL

to SCKx Edge
28
ns
HSP41
TscH2diL,
TscL2diL

to SCKx Edge
35
ns
Note 1:
TABLE 25-12: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

AC
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
HSP35

TscL2doV SCKx Edge
10
25
ns
HSP36
TdoV2sc,
TdoV2scL
35
ns
HSP40
TdiV2scH, Setup Time of SDIx Data Input

TdiV2scL to SCKx Edge
28
ns
HSP41
TscH2diL,
TscL2diL
35
ns
Note 1:

First SCKx Edge

to SCKx Edge
DS70283J-page 286

TABLE 25-13: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
AC
Param
No.
Characteristic(1)
Symbol
Min
Typ
Max
Units
Conditions
HSP35
TscH2doV,
TscL2doV

SCKx Edge
35
ns
HSP40
TdiV2scH,
TdiV2scL

to SCKx Edge
25
ns
HSP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input to

SCKx Edge
25
ns
HSP51
TssH2doZ
SSx to SDOx Output

High-Impedance
15
55
ns
Note 1:
2:
See Note 2

TABLE 25-14: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

AC
CHARACTERISTICS
Param
No.

Characteristic(1)
Symbol
Min
Typ
Max
Units
Conditions
HSP35

TscL2doV SCKx Edge
35
ns
HSP40
TdiV2scH, Setup Time of SDIx Data Input

TdiV2scL to SCKx Edge
25
ns
HSP41
TscH2diL,
TscL2diL

to SCKx Edge
25
ns
HSP51
TssH2doZ
SSx to SDOX Output

High-Impedance
15
55
ns
HSP60
TssL2doV

SSx Edge
55
ns
Note 1:
2:

See Note 2
TABLE 25-15: INTERNAL RC ACCURACY

AC CHARACTERISTICS
Param
No.
Characteristic

Operating temperature -40C TA +150C for Extended
Min
Typ
Max
Units
-70
+70
Conditions
LPRC @ 32.768 kHz(1,2)

HF21
Note 1:
2:
LPRC
-40C TA +150C
VDD = 3.0-3.6V
Change of LPRC frequency as VDD changes.

LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section 21.4 Watchdog
Timer (WDT) for more information.
DS70283J-page 287

TABLE 25-16: ADC MODULE SPECIFICATIONS
AC
CHARACTERISTICS
Param
No.
Symbol

Characteristic
Min
Typ
Max
Units
600
50
A
A
Conditions
Reference Inputs
HAD08
Note 1:
2:
IREF
Current Drain
250
ADC operating, See Note 1

ADC off, See Note 1
These parameters are not characterized or tested in manufacturing.

TABLE 25-17: ADC MODULE SPECIFICATIONS (12-BIT MODE)(3)

AC
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
ADC Accuracy (12-bit Mode) Measurements with External VREF+/VREF-(1)

HAD20a
Nr
Resolution(3)
HAD21a
INL
HAD22a
DNL
HAD23a
GERR
HAD24a
EOFF
12 data bits
bits
-2
+2
LSb

AVDD = VREFH = 3.6V
> -1
<1
LSb

AVDD = VREFH = 3.6V
Gain Error
-2
10
LSb

AVDD = VREFH = 3.6V
Offset Error
-3
LSb

AVDD = VREFH = 3.6V
ADC Accuracy (12-bit Mode) Measurements with Internal VREF+/VREF-(1)

HAD20a
Nr
Resolution(3)
12 data bits
HAD21a
INL
HAD22a
DNL
HAD23a
GERR
HAD24a
EOFF
bits
-2
+2
LSb
> -1
<1
LSb
Gain Error
20
LSb
Offset Error
10
LSb
Dynamic Performance (12-bit

HAD33a
FNYQ
Note 1:
2:
3:

DS70283J-page 288
Mode)(2)
200
kHz

TABLE 25-18: ADC MODULE SPECIFICATIONS (10-BIT MODE)(3)
AC
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
ADC Accuracy (10-bit Mode) Measurements with External VREF+/VREF-(1)

HAD20b Nr
Resolution(3)
HAD21b INL
HAD22b DNL
HAD23b GERR
HAD24b EOFF
10 data bits
bits
-3
LSb

AVDD = VREFH = 3.6V
> -1
<1
LSb

AVDD = VREFH = 3.6V
Gain Error
-5
LSb

AVDD = VREFH = 3.6V
Offset Error
-1
LSb

AVDD = VREFH = 3.6V
ADC Accuracy (10-bit Mode) Measurements with Internal VREF+/VREF-(1)

HAD20b Nr
Resolution(3)
HAD21b INL
HAD22b DNL
HAD23b GERR
HAD24b EOFF
10 data bits
Note 1:
2:
3:
-2
LSb
> -1
<1
LSb
Gain Error
-5
15
LSb
Offset Error
-1.5
LSb
Dynamic Performance (10-bit

HAD33b FNYQ
bits
Mode)(2)
400
kHz

DS70283J-page 289

AC
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
ns
400
Ksps
Clock Parameters
HAD50
TAD
ADC Clock Period(1)
HAD56
FCNV
Throughput Rate(1)
147
Conversion Rate
Note 1:

AC
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
ns
800
Ksps
Clock Parameters
HAD50
TAD
ADC Clock
Period(1)
104
Conversion Rate
Throughput Rate(1)
HAD56
FCNV
Note 1:
DS70283J-page 290

26.0
PACKAGING INFORMATION
26.1
Package Marking Information
28-Lead SPDIP
Example
dsPIC33FJ32MC
202-E/SP e3
0730235
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
dsPIC33FJ32MC
202-E/SO e3
0730235
33FJ32MC
202-E/SS e3
0730235
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
DS70283J-page 291

26.1
Package Marking Information (Continued)
28-Lead QFN-S
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
44-Lead QFN
33FJ32MC
202E/MM e3
0730235
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
dsPIC33FJ32
MC204-E/ML e3
0730235
dsPIC33FJ
32MC204
-E/PT e3
0730235
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
DS70283J-page 292

26.2
Package Details
28-Lead Skinny Plastic Dual In-Line (SP) 300 mil Body [SPDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
3
D
E
A2
b1
A1
eB
Units
Dimension Limits
Number of Pins
INCHES
MIN
NOM
MAX
28
Pitch
Top to Seating Plane
.200
Molded Package Thickness
A2
.120
.135
.150
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
.290
.310
.335
Molded Package Width
E1
.240
.285
.295
Overall Length
1.345
1.365
1.400
Tip to Seating Plane
.110
.130
.150
Lead Thickness
.008
.010
.015
b1
.040
.050
.070
.014
.018
.022
eB
Upper Lead Width

Lower Lead Width
Overall Row Spacing
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-070B
DS70283J-page 293
Note:
DS70283J-page 294
Note:
DS70283J-page 295
Note:
DS70283J-page 296

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DS70283J-page 297
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DS70283J-page 298

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DS70283J-page 299

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DS70283J-page 300

44-Lead Plastic Quad Flat, No Lead Package (ML) 8x8 mm Body [QFN]
Note:
D2
EXPOSED
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e
E
E2
b
2
2
1
N
1
N
NOTE 1
TOP VIEW
L
BOTTOM VIEW
A
A3
A1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
NOM
MAX
44
Pitch
Overall Height
0.80
0.65 BSC
0.90
1.00
Standoff
A1
0.00
0.02
0.05
Contact Thickness
A3
0.20 REF
Overall Width
Exposed Pad Width
E2
Overall Length
Exposed Pad Length
D2
6.30
6.45
6.80
0.25
0.30
0.38
Contact Length
0.30
0.40
0.50
Contact-to-Exposed Pad
0.20
Contact Width
8.00 BSC
6.30
6.45
6.80
8.00 BSC
Notes:
2. Package is saw singulated.
REF: Reference Dimension, usually without tolerance, for information purposes only.
DS70283J-page 301

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DS70283J-page 302

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NOM
MAX
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A2
0.95
1.00
1.05
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A1
0.05
0.15
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0.45
0.60
0.75
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L1
1.20
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Overall Width
12.00 BSC
Overall Length
12.00 BSC
Molded Package Width
E1
10.00 BSC
Molded Package Length
D1
10.00 BSC
3.5
Lead Thickness
0.09
0.20
Lead Width
0.30
0.37
0.45
Mold Draft Angle Top
11
12
13
Mold Draft Angle Bottom
11
12
13
Notes:
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
REF: Reference Dimension, usually without tolerance, for information purposes only.
DS70283J-page 303
Note:
DS70283J-page 304

APPENDIX A:
REVISION HISTORY
Revision A (February 2007)

This is the initial released version of this document.
Revision B (May 2007)

This revision includes the following corrections and
updates:
Minor typographical and formatting corrections
throughout the data sheet text.
New content:
- Addition of bullet item (16-word conversion
result buffer) (see Section 20.1 Key
Features)
Updated register map information for RPINR14
and RPINR15 (see Table 4-16)
Figure updates:
- Updated Oscillator System Diagram (see
Figure 8-1)
- Updated WDT Block Diagram (see
Figure 21-2)
Equation update:
- Serial Clock Rate (see Equation 17-1)
Register updates:
- Peripheral Pin Select Input Registers (see
Register 10-1 through Register 10-13)
- Updated ADC1 Input Channel 0 Select
register (see Register 20-5)
The following tables in Section 24.0 Electrical

Characteristics have been updated with
preliminary values:
- Updated Max MIPS for -40C to +125C
Temp Range (see Table 24-1)
- Updated parameter DC18 (see Table 24-4)
- Added new parameters for +125C, and
updated Typical and Max values for most
parameters (see Table 24-5)
- Updated parameter DI51, added parameters
DI51a, DI51b, and DI51c (see Table 24-9)
- Added Note 1 (see Table 24-11)
- Updated parameters OS10 and OS30 (see
Table 24-16)
- Updated parameter OS52 (see Table 24-17)
- Updated parameter F20, added Note 2 (see
Table 24-18)
- Updated parameter F21 (see Table 24-19)
- Updated parameter TA15 (see Table 24-22)
- Updated parameter TB15 (see Table 24-23)
- Updated parameter TC15 (see Table 24-24)
- Updated parameter IC15 (see Table 24-26)
- Updated parameters AD05, AD06, AD07,
AD08, AD10 through AD13 and AD17; added
parameters AD05a and AD06a; added Note
2; modified ADC Accuracy headings to
include measurement information (see
Table 24-38)
- Separated the ADC Module Specifications
table into three tables (see Table 24-38,
Table 24-39, and Table 24-40)
- Updated parameter AD50 (see Table 24-41)
- Updated parameters AD50 and AD57 (see
Table 24-42)
DS70283J-page 305

Revision C (June 2008)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in the following table.
TABLE A-1:
MAJOR SECTION UPDATES
Section Name
High-Performance, 16-bit Digital
Signal Controllers
Update Description
Added Extended Interrupts column to Remappable Peripherals in the
Controller Families table and Note 3 (see Table 1).
Added Note 1 to all pin diagrams, which references RPn pin usage by
remappable peripherals (see Pin Diagrams).
Section 1.0 Device Overview
Changed PORTA pin name from RA15 to RA10 (see Table 1-1).
Section 4.0 Memory Organization
Added SFR definitions (ACCAL, ACCAH, ACCAU, ACCBL, ACCBH, and

ACCBU) to the CPU Core Register Map (see Table 4-1).
Updated Reset value for CORCON (see Table 4-1).
Updated Reset values for the following SFRs: IPC1, IPC3-IPC5, IPC7,
IPC16, and INTTREG (see Table 4-4).
Updated all SFR names in QEI1 Register Map (see Table 4-10).
Updated the bit range for AD1CON3 from ADCS<5:0> to ADCS<7:0>) (see
Table 4-14 and Table 4-15).
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 4-23).
Section 6.0 Resets
Entire section was replaced to maintain consistency with other dsPIC33F

data sheets.
Section 8.0 Oscillator

Configuration
Removed the first sentence of the third clock source item (External Clock) in
Section 8.1.1.2 Primary.
Updated the default bit values for DOZE and FRCDIV in the Clock Divisor
Register (see Register 8-2).
Added the center frequency in the OSCTUN register for the FRC Tuning bits
(TUN<5:0>) value 011111 and updated the center frequency for bits value
011110 (see Register 8-4).
Section 9.0 Power-Saving

Features
Added the following two registers:
Section 10.0 I/O Ports
Added paragraph and Table 10-1 to Section 10.2 Open-Drain

Configuration, which provides details on I/O pins and their functionality.
PMD1: Peripheral Module Disable Control Register 1

Removed the following sections, which are now available in the related
section of the dsPIC33F/PIC24H Family Reference Manual:
9.4.2 Available Peripherals
9.4.3.3 Mapping
9.4.5 Considerations for Peripheral Pin Selection
Section 14.0 Output Compare
DS70283J-page 306
Replaced sections 13.1, 13.2, and 13.3 and related figures and tables with
entirely new content.

TABLE A-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Section 15.0 Motor Control PWM
Module
Update Description
Section 16.0 Quadrature Encoder

Interface (QEI) Module
Section 17.0 Serial Peripheral

Interface (SPI)
15.1 Quadrature Encoder Interface Logic

15.2 16-bit Up/Down Position Counter Mode
15.3 Position Measurement Mode
15.4 Programmable Digital Noise Filters
15.5 Alternate 16-bit Timer/Counter
15.6 QEI Module Operation During CPU Sleep Mode
15.7 QEI Module Operation During CPU Idle Mode
15.8 Quadrature Encoder Interface Interrupts
14.3 PWM Time Base

14.4 PWM Period
14.5 Edge-Aligned PWM
14.6 Center-Aligned PWM
14.7 PWM Duty Cycle Comparison Units
14.8 Complementary PWM Operation
14.9 Dead-Time Generators
14.10 Independent PWM Output
14.11 Single Pulse PWM Operation
14.12 PWM Output Override
14.13 PWM Output and Polarity Control
14.14 PWM Fault Pins
14.15 PWM Update Lockout
14.16 PWM Special Event Trigger
14.17 PWM Operation During CPU Sleep Mode
14.18 PWM Operation During CPU Idle Mode
16.1 Interrupts
16.2 Receive Operations
16.3 Transmit Operations
16.4 SPI Setup (retained Figure 17-1: SPI Module Block Diagram)
DS70283J-page 307

TABLE A-1:
Section Name
Section 18.0 Inter-Integrated
Circuit (I2C)
Update Description
17.3 I2C Interrupts

17.4 Baud Rate Generator (retained Figure 15-1: I2C Block Diagram)
17.5 I2C Module Addresses
17.6 Slave Address Masking
17.7 IPMI Support
17.8 General Call Address Support
17.9 Automatic Clock Stretch
17.10 Software Controlled Clock Stretching (STREN = 1)
17.11 Slope Control
17.12 Clock Arbitration
17.13 Multi-Master Communication, Bus Collision, and Bus Arbitration
17.14 Peripheral Pin Select Limitations
Section 19.0 Universal

Asynchronous Receiver Transmitter section of the dsPIC33F/PIC24H Family Reference Manual:
(UART)
18.1 UART Baud Rate Generator
18.2 Transmitting in 8-bit Data Mode
18.3 Transmitting in 9-bit Data Mode
18.4 Break and Sync Transmit Sequence
18.5 Receiving in 8-bit or 9-bit Data Mode
18.6 Flow Control Using UxCTS and UxRTS Pins
18.7 Infrared Support
Removed IrDA references and Note 1, and updated the bit and bit value
descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control
Register (see Register 19-2).
Section 20.0 10-bit/12-bit
Analog-to-Digital Converter (ADC)
Removed Equation 19-1: ADC Conversion Clock Period and Figure 19-2:
ADC Transfer Function (10-Bit Example).
Added ADC1 Module Block Diagram for dsPIC33FJ16MC304 and
dsPIC33FJ32MC204 Devices (Figure 20-1) and ADC1 Module Block
Diagram FOR dsPIC33FJ32MC202 Devices (Figure 20-2).
Added Note 2 to Figure 20-3: ADC Conversion Clock Period Block Diagram.
Updated ADC Conversion Clock Select bits in the AD1CON3 register from
ADCS<5:0> to ADCS<7:0>. Any references to these bits have also been
updated throughout this data sheet (Register 20-3).
Added device-specific information to Note 1 in the ADC1 Input Scan Select
Register Low (see Register 20-6), and updated the default bit value for bits
12-10 (CSS12-CSS10) from U-0 to R/W-0.
Added device-specific information to Note 1 in the ADC1 Port Configuration
Register Low (see Register 20-7), and updated the default bit value for bits
12-10 (PCFG12-PCFG10) from U-0 to R/W-0.
DS70283J-page 308

TABLE A-1:
Section Name
Section 21.0 Special Features
Update Description
Added FICD register information for address 0xF8000E in the Device
Configuration Register Map (see Table 21-1).
Added FICD register content (BKBUG, COE, JTAGEN, and ICS<1:0> to the
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Configuration Bits
Description (see Table 21-2).
Added a note regarding the placement of low-ESR capacitors, after the
second paragraph of Section 21.2 On-Chip Voltage Regulator and to
Figure 19-1.
Removed the words if enabled from the second sentence in the fifth
paragraph of Section 21.3 BOR: Brown-out Reset.
Section 24.0 Electrical

Characteristics
Updated Max MIPS value for -40C to +125C temperature range in

Operating MIPS vs. Voltage (see Table 24-1).
Removed Typ value for parameter DC12 (see Table 24-4).
Updated MIPS conditions for parameters DC24c, DC44c, DC72a, DC72f
and DC72g (see Table 24-5, Table 24-6, and Table 24-8).
Added Note 4 (reference to new table containing digital-only and analog pin
information to I/O Pin Input Specifications (see Table 24-4).
Updated Typ, Min and Max values for Program Memory parameters D136,
D137 and D138 (see Table 24-12).
Updated Max value for Internal RC Accuracy parameter F21 for -40C TA
+125C condition and added Note 2 (see Table 24-19).
Removed all values for Reset, Watchdog Timer, Oscillator Start-up Timer,
and Power-up Timer parameter SY20 and updated conditions, which now
refers to Section 21.4 Watchdog Timer (WDT) and LPRC parameter
F21a (see Table 24-21).
Updated Min and Typ values for parameters AD60, AD61, AD62 and AD63
and removed Note 3 (see Table 24-41).
Updated Min and Typ values for parameters AD60, AD61, AD62 and AD63
and removed Note 3 (see Table 24-42).
DS70283J-page 309

Revision D (December 2008)
The major changes are referenced by their respective
section in the following table.
TABLE A-2:
Section Name
Update Description
High-Performance, 16-bit Digital

Signal Controllers
Updated all pin diagrams to denote the pin voltage tolerance (see Pin
Diagrams).
Section 2.0 Guidelines for Getting

Started with 16-bit Digital Signal
Controllers
Added new section to the data sheet that provides guidelines on getting
started with 16-bit Digital Signal Controllers.
Updated 5V tolerant status for I/O pin RB4 from Yes to No (see Table 10-1).
Section 24.0 Electrical

Characteristics
Removed the maximum value for parameter DC12 (RAM Data Retention
Voltage) in Table 24-4.
Updated typical values for Operating Current (IDD) and added Note 3 in
Table 24-5.
Updated typical and maximum values for Idle Current (IIDLE): Core OFF
Clock ON Base Current and added Note 3 in Table 24-6.
Updated typical and maximum values for Power Down Current (IPD) and
added Note 5 in Table 24-7.
Updated typical and maximum values for Doze Current (IDOZE) and added
Note 2 in Table 24-8.
Added Note 3 to Table 24-12.
Updated minimum value for Internal Voltage Regulator Specifications in
Table 24-13.
Added parameter OS42 (GM) and Notes 4, 5 and 6 to Table 24-16.
Added Notes 2 and 3 to Table 24-17.
Updated typical value for parameter AD08 (ADC in operation) and added
Notes 2 and 3 in Table 24-38.
Updated minimum, typical, and maximum values for parameters AD23a,
AD24a, AD30a, AD32a, AD32a and AD34a, and added Notes 2 and 3 in
Table 24-39.
Updated minimum, typical, and maximum values for parameters AD23b,
AD24b, AD30b, AD32b, AD32b and AD34b, and added Notes 2 and 3 in
Table 24-40.
DS70283J-page 310

Revision E (June 2009)
Global changes include:
Changed all instances of OSCI to OSC1 and
OSCO to OSC2
Changed all instances of PGCx/EMUCx and
PGDx/EMUDx (where x = 1, 2 or 3) to PGECx
and PGEDx
Changed all instances of VDDCORE and VDDCORE/VCAP
to VCAP/VDDCORE
All other major changes are referenced by their
respective section in the following table.
TABLE A-3:

Section Name
Update Description
High-Performance, 16-bit Digital Signal

Controllers
Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin

diagrams, which references pin connections to VSS.
Section 7.0 Interrupt Controller
Updated addresses for interrupt vectors 80, 81, 82 and 83-125

(see Table 7-1).
Section 8.0 Oscillator Configuration
Updated the Oscillator System Diagram (see Figure 8-1).

Added Note 1 to the Oscillator Tuning register (OSCTUN) (see
Register 8-4).
Removed Table 10-1 and added reference to pin diagrams for I/O
pin availability and functionality.
Section 17.0 Serial Peripheral Interface (SPI) Added Note 2 to the SPIx Control Register 1 (see Register 17-2).
Section 19.0 Universal Asynchronous
Receiver Transmitter (UART)
Updated the UTXINV bit settings in the UxSTA register and

added Note 1 (see Register 19-2).
Section 24.0 Electrical Characteristics
Updated the Min value for parameter DC12 (RAM Retention

Voltage) and added Note 4 to the DC Temperature and Voltage
Specifications (see Table 24-4).
Updated the Min value for parameter DI35 (see Table 24-20).
Updated AD08 and added reference to Note 2 for parameters
AD05a, AD06a and AD08a (see Table 24-38).
DS70283J-page 311

Revision F (November 2009)
The revision includes the following global update:
Added Note 2 to the shaded table that appears at
the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
This revision also includes minor typographical and
TABLE A-4:

Section Name
Update Description

Controllers
Added information on high temperature operation (see

Operating Range:).
Changed the reference to digital-only pins to 5V tolerant pins in

the second paragraph of Section 10.2 Open-Drain
Configuration.
Section 19.0 Universal Asynchronous

Receiver Transmitter (UART)
Updated the two baud rate range features to: 10 Mbps to 38 bps
at 40 MIPS.
Section 20.0 10-bit/12-bit Analog-to-Digital

Converter (ADC)
Updated the ADC1 block diagrams (see Figure 20-1 and

Figure 20-2).
Updated the second paragraph and removed the fourth

paragraph in Section 21.1 Configuration Bits.
Updated the Device Configuration Register Map (see Table 21-1).
Updated the Absolute Maximum Ratings for high temperature

and added Note 4.
Updated the SPIx Module Slave Mode (CKE = 1) Timing
Characteristics (see Figure 24-17).
Updated the Internal RC Accuracy parameter numbers (see
Table 24-18 and Table 24-19).
Section 25.0 High Temperature Electrical

Characteristics
Added new chapter with high temperature specifications.
Product Identification System
Added the H definition for high temperature.
Revision G (November 2009)

TABLE A-5:

Section Name

Characteristics
DS70283J-page 312
Update Description
Updated MIPS rating from 16 to 20 for high temperature devices
in Operating Range: and in Table 25-1: Operating MIPS vs.
Voltage.

Revision H (February 2011)
This revision includes typographical and formatting
changes throughout the data sheet text. In addition, all
instances of VDDCORE have been removed.
TABLE A-6:

Section Name
Update Description

Controllers
Added the SSOP package information (see Packaging:, Table 1,

and Pin Diagrams).
Section 2.0 Guidelines for Getting Started

with 16-bit Digital Signal Controllers
Updated the title of Section 2.3 CPU Logic Filter Capacitor

Connection (VCAP).
The frequency limitation for device PLL start-up conditions was
updated in Section 2.7 Oscillator Value Conditions on Device
Start-up.
The second paragraph in Section 2.9 Unused I/Os was updated.
Section 3.0 CPU
Removed references to DMA in the CPU Core Block Diagram (see

Figure 3-1).
Section 4.0 Memory Organization
Updated the data memory reference in the third paragraph in

Section 4.2 Data Address Space.
All Resets values for the following SFRs in the Timer Register Map
were changed (see Table 4-5):
TMR1
TMR2
TMR3
Section 8.0 Oscillator Configuration
Added Note 3 to the OSCCON: Oscillator Control Register (see

Register 8-1).
Added Note 2 to the CLKDIV: Clock Divisor Register (see
Register 8-2).
Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see
Register 8-3).
Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see
Register 8-4).
Section 20.0 10-bit/12-bit Analog-to-Digital Updated the VREFL references in the ADC1 module block diagrams
Converter (ADC)
(see Figure 20-1 and Figure 20-2).
Added a new paragraph and removed the third paragraph in

Section 21.1 Configuration Bits.
Added the column RTSP Effects to the Configuration Bits
Descriptions (see Table 21-2).
DS70283J-page 313

TABLE A-6:

Section Name
Update Description
Added the 28-pin SSOP Thermal Packaging Characteristics (see
Table 24-3).
Removed Note 4 from the DC Temperature and Voltage
Updated the maximum value for parameter DI19 and added
parameters DI28, DI29, DI60a, DI60b, and DI60c to the I/O Pin Input
Updated Note 3 of the PLL Clock Timing Specifications (see
Table 24-17).
Removed Note 2 from the AC Characteristics: Internal RC Accuracy
(see Table 24-18).
Updated the characteristic description for parameter DI35 in the I/O
Timing Requirements (see Table 24-20).
Updated all SPI specifications (see Table 24-32 through Table 24-39
and Figure 24-14 through Figure 24-21).
Added Note 4 to the 12-bit mode ADC Module Specifications (see
Table 24-43).
Added Note 4 to the 10-bit mode ADC Module Specifications (see
Table 24-44).

Characteristics
Updated all ambient temperature and range values to +150C

throughout the chapter.
Updated the storage temperature and range to +160C.
Updated the maximum junction temperature from +145C to +155C.
Updated Note 1 in the PLL Clock Timing Specifications (see
Table 25-10).
Added Note 3 to the 12-bit Mode ADC Module Specifications (see
Table 25-17).
Added Note 3 to the 10-bit Mode ADC Module Specifications (see
Table 25-18).
Section 26.0 Packaging Information
Added the 28-Lead SSOP package information (see Section 26.1

Package Marking Information and Section 26.2 Package
Details).
Product Identification System
Added the SS definition for the SSOP package.
DS70283J-page 314

Revision J (July 2011)
This revision includes typographical and formatting
changes throughout the data sheet text.
TABLE A-7:

Section Name
Update Description
Added Note 3 to the Connections for the On-chip Voltage Regulator

diagram (see Figure 21-1).
Removed Note 3 and parameter DC10 (VCORE) from the DC

Temperature and Voltage Specifications (see Table 24-4).
Updated the Characteristics definition and Conditions for parameter
BO10 in the Electrical Characteristics: BOR (see Table 24-11).
Added Note 1 to the Internal Voltage Regulator Specifications (see
Table 24-13).
DS70283J-page 315

NOTES:
DS70283J-page 316

INDEX
A
AC Characteristics .................................................... 244, 285
ADC Module.............................................................. 288
ADC Module (10-bit Mode) ....................................... 289
ADC Module (12-bit Mode) ....................................... 288
Internal RC Accuracy ................................................ 246
Load Conditions ................................................ 244, 285
ADC
Initialization ............................................................... 201
Key Features............................................................. 201
ADC Module
ADC1 Register Map for dsPIC33FJ32MC202 ............ 44
ADC1 Register Map for dsPIC33FJ32MC204 and
dsPIC33FJ16MC304 .......................................... 45
Alternate Interrupt Vector Table (AIVT) .............................. 73
Analog-to-Digital Converter (ADC).................................... 201
Arithmetic Logic Unit (ALU)................................................. 27
Assembler
MPASM Assembler................................................... 230
B
Barrel Shifter ....................................................................... 31
Bit-Reversed Addressing .................................................... 53
Example ...................................................................... 54
Implementation ........................................................... 53
Sequence Table (16-Entry)......................................... 54
Block Diagrams
16-bit Timer1 Module ................................................ 147
A/D Module ....................................................... 202, 203
Connections for On-Chip Voltage Regulator............. 217
Device Clock ............................................................. 105
DSP Engine ................................................................ 28
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 .. 12
CPU Core ........................................................... 22
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PLL
107
Input Capture ............................................................ 155
Output Compare ....................................................... 157
PLL............................................................................ 107
PWM Module .................................................... 162, 163
Quadrature Encoder Interface .................................. 175
Reset System.............................................................. 65
Shared Port Structure ............................................... 121
SPI ............................................................................ 181
Timer2 (16-bit) .......................................................... 151
Timer2/3 (32-bit) ....................................................... 150
UART ........................................................................ 195
Watchdog Timer (WDT) ............................................ 218
C
C Compilers
MPLAB C18 .............................................................. 230
Clock Switching................................................................. 113
Enabling .................................................................... 113
Sequence.................................................................. 113
Code Examples
Erasing a Program Memory Page............................... 63
Initiating a Programming Sequence............................ 64
Loading Write Buffers ................................................. 64
Port Write/Read ........................................................ 122
PWRSAV Instruction Syntax..................................... 115
Code Protection ........................................................ 213, 220
Configuration Bits.............................................................. 213
Configuration Register Map .............................................. 213

Configuring Analog Port Pins............................................ 122
CPU
Control Register.......................................................... 24
CPU Clocking System ...................................................... 106
PLL Configuration..................................................... 106
Selection................................................................... 106
Sources .................................................................... 106
Customer Change Notification Service............................. 321
Customer Notification Service .......................................... 321
Customer Support............................................................. 321
D
Data Accumulators and Adder/Subtracter .......................... 29
Data Space Write Saturation ...................................... 31
Overflow and Saturation ............................................. 29
Round Logic ............................................................... 30
Write Back .................................................................. 30
Data Address Space........................................................... 35
Alignment.................................................................... 35
Memory Map for dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 Devices with 2 KBs RAM . 36
Near Data Space ........................................................ 35
Software Stack ........................................................... 50
Width .......................................................................... 35
DC Characteristics............................................................ 234
Doze Current (IDOZE)................................................ 283
High Temperature..................................................... 282
I/O Pin Input Specifications ...................................... 239
I/O Pin Output........................................................... 283
I/O Pin Output Specifications.................................... 242
Idle Current (IDOZE) .................................................. 238
Idle Current (IIDLE) .................................................... 237
Operating Current (IDD) ............................................ 236
Operating MIPS vs. Voltage ..................................... 282
Power-Down Current (IPD)........................................ 238
Power-down Current (IPD) ........................................ 282
Program Memory.............................................. 243, 284
Temperature and Voltage......................................... 282
Temperature and Voltage Specifications.................. 235
Thermal Operating Conditions.................................. 282
Development Support ....................................................... 229
Doze Mode ....................................................................... 116
DSP Engine ........................................................................ 27
Multiplier ..................................................................... 29
E
Electrical Characteristics .................................................. 233
AC..................................................................... 244, 285
Equations
Device Operating Frequency.................................... 106
Errata .................................................................................. 10
F
Fail-Safe Clock Monitor .................................................... 113
Flash Program Memory ...................................................... 59
Control Registers........................................................ 60
Operations .................................................................. 60
Programming Algorithm.............................................. 63
RTSP Operation ......................................................... 60
Table Instructions ....................................................... 59
Flexible Configuration ....................................................... 213
DS70283J-page 317

H
High Temperature Electrical Characteristics..................... 281
I
I/O Ports ............................................................................ 121
Parallel I/O (PIO)....................................................... 121
Write/Read Timing .................................................... 122
I2 C
Addresses ................................................................. 188
Operating Modes ...................................................... 187
Registers ................................................................... 187
Software Controlled Clock Stretching (STREN = 1).. 188
I2C Module
I2C1 Register Map ...................................................... 43
In-Circuit Debugger ........................................................... 219
In-Circuit Emulation........................................................... 213
In-Circuit Serial Programming (ICSP) ....................... 213, 219
Input Capture .................................................................... 155
Registers ................................................................... 156
Input Change Notification.................................................. 122
Instruction Addressing Modes............................................. 50
File Register Instructions ............................................ 50
Fundamental Modes Supported.................................. 51
MAC Instructions......................................................... 51
MCU Instructions ........................................................ 50
Move and Accumulator Instructions ............................ 51
Other Instructions........................................................ 51
Instruction Set
Overview ................................................................... 224
Summary................................................................... 221
Instruction-Based Power-Saving Modes ........................... 115
Idle ............................................................................ 116
Sleep ......................................................................... 115
Interfacing Program and Data Memory Spaces .................. 55
Internal RC Oscillator
Use with WDT ........................................................... 218
Internet Address................................................................ 321
Interrupt Control and Status Registers................................ 77
IECx ............................................................................ 77
IFSx............................................................................. 77
INTCON1 .................................................................... 77
INTCON2 .................................................................... 77
IPCx ............................................................................ 77
Interrupt Setup Procedures ............................................... 103
Initialization ............................................................... 103
Interrupt Disable........................................................ 103
Interrupt Service Routine .......................................... 103
Trap Service Routine ................................................ 103
Interrupt Vector Table (IVT) ................................................ 73
Interrupts Coincident with Power Save Instructions.......... 116
J
JTAG Boundary Scan Interface ........................................ 213
JTAG Interface .................................................................. 219
M
Memory Organization.......................................................... 33
Microchip Internet Web Site .............................................. 321
Modulo Addressing ............................................................. 52
Applicability ................................................................. 53
Operation Example ..................................................... 52
Start and End Address ................................................ 52
W Address Register Selection .................................... 52
Motor Control PWM........................................................... 161
Motor Control PWM Module
2-Output Register Map................................................ 42
DS70283J-page 318
6-Output Register Map for dsPIC33FJ12MC202........ 42

MPLAB ASM30 Assembler, Linker, Librarian ................... 230
MPLAB Integrated Development Environment Software.. 229
MPLAB PM3 Device Programmer .................................... 232
MPLAB REAL ICE In-Circuit Emulator System ................ 231
MPLINK Object Linker/MPLIB Object Librarian ................ 230
N
NVM Module
Register Map .............................................................. 49
O
Open-Drain Configuration................................................. 122
Oscillator Configuration .................................................... 105
Output Compare ............................................................... 157
P
Packaging ......................................................................... 291
Details....................................................................... 293
Marking ............................................................. 291, 292
Peripheral Module Disable (PMD) .................................... 116
Pinout I/O Descriptions (table)............................................ 13
PMD Module
Register Map .............................................................. 49
PORTA
Register Map for dsPIC33FJ32MC202....................... 47
Register
Map
for
dsPIC33FJ32MC204
and
dsPIC33FJ16MC304 .......................................... 47
PORTB
Register Map .............................................................. 48
PORTC
Register
Map
dsPIC33FJ32MC204
and
dsPIC33FJ16MC304 .......................................... 48
Power-on Reset (POR)....................................................... 70
Power-Saving Features .................................................... 115
Clock Frequency and Switching ............................... 115
Program Address Space..................................................... 33
Construction ............................................................... 55
Data Access from Program Memory Using
Program Space Visibility..................................... 58
Data Access from Program Memory
Using Table Instructions ..................................... 57
Data Access from, Address Generation ..................... 56
Memory Map............................................................... 33
Table Read Instructions
TBLRDH ............................................................. 57
TBLRDL.............................................................. 57
Visibility Operation ...................................................... 58
Program Memory
Interrupt Vector ........................................................... 34
Organization ............................................................... 34
Reset Vector ............................................................... 34
PWM Time Base............................................................... 164
Q
Quadrature Encoder Interface (QEI)................................. 175
Quadrature Encoder Interface (QEI) Module
Register Map .............................................................. 43
R
Reader Response............................................................. 322
Registers
AD1CHS0 (ADC1 Input Channel 0 Select ................ 211
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 209
AD1CON1 (ADC1 Control 1) .................................... 205

AD1CSSL (ADC1 Input Scan Select Low)................ 212
AD1PCFGL (ADC1 Port Configuration Low) ............ 212
CLKDIV (Clock Divisor)............................................. 110
CORCON (Core Control) ...................................... 26, 78
DFLTCON (QEI Control)........................................... 179
I2CxCON (I2Cx Control) ........................................... 189
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 193
I2CxSTAT (I2Cx Status) ........................................... 191
ICxCON (Input Capture x Control) ............................ 156
IEC0 (Interrupt Enable Control 0) ............................... 87
IFS0 (Interrupt Flag Status 0) ..................................... 82
INTCON1 (Interrupt Control 1).................................... 79
INTCON2 (Interrupt Control 2).................................... 81
INTTREG Interrupt Control and Status Register....... 102
IPC0 (Interrupt Priority Control 0) ............................... 92
IPC14 (Interrupt Priority Control 14) ........................... 99
IPC15 (Interrupt Priority Control 15) ......................... 100
NVMCON (Flash Memory Control) ............................. 61
NVMKEY (Nonvolatile Memory Key) .......................... 62
OCxCON (Output Compare x Control) ..................... 159
OSCCON (Oscillator Control) ................................... 108
OSCTUN (FRC Oscillator Tuning) ............................ 112
P1DC2 (PWM Duty Cycle 2)..................................... 173
P1DC3 (PWM Duty Cycle 3)..................................... 173
PDC1 (PWM Duty Cycle 1)....................................... 173
PLLFBD (PLL Feedback Divisor).............................. 111
PMD1 (Peripheral Module Disable Control
Register 1) ........................................................ 117
PMD1 (Peripheral Module Disable Control Register 1) ..
117
Register 2) ........................................................ 118
Register 3) ........................................................ 119
PMD3 (Peripheral Module Disable Control Register 3) ..
119
PTCON (PWM Time Base Control) .......................... 164
PTMR (PWM Timer Count Value)............................. 165
PTPER (PWM Time Base Period) ............................ 165
PWMxCON1 (PWM Control 1).................................. 167
PWMxCON2 (PWM Control 2).................................. 168
PxDTCON1 (Dead-Time Control 1) .......................... 169
PxDTCON2 (Dead-Time Control 2) .......................... 170
PxFLTACON (Fault A Control).................................. 171
PxOVDCON (Override Control) ................................ 172
PxSECMP (Special Event Compare)........................ 166
QEICON (QEI Control).............................................. 177
RCON (Reset Control) ................................................ 66
SPIxCON1 (SPIx Control 1)...................................... 183
SPIxCON2 (SPIx Control 2)...................................... 185
SPIxSTAT (SPIx Status and Control) ....................... 182
SR (CPU Status)................................................... 24, 78
T1CON (Timer1 Control) .......................................... 148

T2CON Control)........................................................ 152
T3CON Control......................................................... 153
UxMODE (UARTx Mode) ......................................... 196
UxSTA (UARTx Status and Control) ........................ 198
Reset
Illegal Opcode....................................................... 65, 72
Trap Conflict ......................................................... 71, 72
Uninitialized W Register ....................................... 65, 72
Reset Sequence ................................................................. 73
Resets ................................................................................ 65
S
Serial Peripheral Interface (SPI) ....................................... 181
Software Reset Instruction (SWR)...................................... 71
Software Simulator (MPLAB SIM) .................................... 231
Software Stack Pointer, Frame Pointer
CALLL Stack Frame ................................................... 50
Special Features of the CPU ............................................ 213
SPI Module
SPI1 Register Map ..................................................... 43
Symbols Used in Opcode Descriptions ............................ 222
System Control
Register Map .............................................................. 48
T
Temperature and Voltage Specifications
AC..................................................................... 244, 285
Timer1 .............................................................................. 147
Timer2/3 ........................................................................... 149
Timing Characteristics
CLKO and I/O ........................................................... 247
Timing Diagrams
10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 0, SSRC<2:0> = 000)......................... 278
10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 1, SSRC<2:0> = 111,
SAMC<4:0> = 00001)....................................... 278
12-bit ADC Conversion (ASAM = 0,
SSRC<2:0> = 000) ........................................... 277
Brown-out Situations .................................................. 71
External Clock .......................................................... 245
I2Cx Bus Data (Master Mode) .................................. 270
I2Cx Bus Data (Slave Mode) .................................... 272
I2Cx Bus Start/Stop Bits (Master Mode)................... 270
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 272
Input Capture (CAPx) ............................................... 253
Motor Control PWM .................................................. 255
Motor Control PWM Fault ......................................... 255
OC/PWM .................................................................. 254
Output Compare (OCx) ............................................ 253
QEA/QEB Input ........................................................ 256
QEI Module Index Pulse........................................... 257
Reset, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer ......................................... 248
Timer1, 2, 3 External Clock ...................................... 250
TimerQ (QEI Module) External Clock ....................... 252
Timing Requirements
ADC Conversion (10-bit mode) ................................ 290
ADC Conversion (12-bit Mode) ................................ 290
CLKO and I/O ........................................................... 247
External Clock .......................................................... 245
Input Capture............................................................ 253
SPIx Master Mode (CKE = 0) ................................... 286
SPIx Module Master Mode (CKE = 1) ...................... 286
SPIx Module Slave Mode (CKE = 0) ........................ 287
DS70283J-page 319

SPIx Module Slave Mode (CKE = 1)......................... 287
Timing Specifications
10-bit ADC Conversion Requirements ...................... 279
12-bit ADC Conversion Requirements ...................... 277
I2Cx Bus Data Requirements (Master Mode) ........... 271
I2Cx Bus Data Requirements (Slave Mode) ............. 273
Motor Control PWM Requirements ........................... 255
Output Compare Requirements ................................ 253
PLL Clock.......................................................... 246, 285
QEI External Clock Requirements ............................ 252
QEI Index Pulse Requirements................................. 257
Quadrature Decoder Requirements .......................... 256
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out
Reset Requirements ......................................... 249
Simple OC/PWM Mode Requirements ..................... 254
Timer1 External Clock Requirements ....................... 250
DS70283J-page 320
U
UART Module
UART1 Register Map.................................................. 43
Universal Asynchronous Receiver Transmitter (UART) ... 195
Using the RCON Status Bits............................................... 72
V
Voltage Regulator (On-Chip) ............................................ 217
W
Watchdog Time-out Reset (WDTR).................................... 71
Watchdog Timer (WDT)............................................ 213, 218
Programming Considerations ................................... 218
WWW Address ................................................................. 321
WWW, On-Line Support ..................................................... 10

THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance

through several channels:
Product Support Data sheets and errata,

application notes and sample programs, design
resources, users guides and hardware support
documents, latest software releases and archived
software
General Technical Support Frequently Asked
Questions (FAQs), technical support requests,
online discussion groups, Microchip consultant
program member listing
Business of Microchip Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchips customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under Support, click on
Customer Change Notification and follow the
registration instructions.
DS70283J-page 321

READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
Literature Number: DS70283J
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS70283J-page 322

PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC 33 FJ 32 MC2 02 T E / SP - XXX
Examples:
a)
Microchip Trademark
Architecture
dsPIC33FJ32MC202TE/SP:
Motor Control dsPIC33, 32 KB program
memory, 28-pin, Extended temp.,
SPDIP package.
Flash Memory Family

Program Memory Size (KB)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture:
33
16-bit Digital Signal Controller
Flash Memory Family: FJ
Flash program memory, 3.3V
Product Group:
MC2
MC3
=
=
Motor Control family

Motor Control family
Pin Count:
02
04
=
=
28-pin
44-pin
Temperature Range:
I
E
H
=
=
=
-40 C to+85 C (Industrial)

-40 C to+125 C (Extended)
-40 C to+150 C (High)
Package:
SP
SO
SS
ML
PT
MM
=
=
=
=
=
=
Skinny Plastic Dual In-Line - 300 mil body (SPDIP)

Plastic Small Outline - Wide - 7.50 mil body (SOIC)
Plastic Shrink Small Outline - 5.3 mm body (SSOP)
Plastic Quad, No Lead Package - 8x8 mm body (QFN)
Plastic Thing Quad Flatpack - 10x10x1 mm body (TQFP)
Plastic Quad, No Lead Package - 6x6 mm body (QFN-S)
DS70283J-page 323
Worldwide Sales and Service

AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office

Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
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Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
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Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
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Tel: 216-447-0464
Fax: 216-447-0643
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Tel: 972-818-7423
Fax: 972-818-2924
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Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
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Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hangzhou
Tel: 86-571-2819-3180
Fax: 86-571-2819-3189
Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Hong Kong SAR

Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Taiwan - Hsin Chu

Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS70283J-page 324
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
05/02/11

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2007-2011 Microchip Technology Inc.

Information contained in this publication regarding device

2007-2011 Microchip Technology Inc.

Up to 40 MIPS operation (@ 3.0-3.6V):

High-Performance DSC CPU:

Modified Harvard architecture

2007-2011 Microchip Technology Inc.

Peripheral pin Select functionality

On-Chip Flash and SRAM: