Intel MCS-51

of binary compatible microcontrollers.[2] While Intel no

longer manufactures the MCS-51, MCS-151 and MCS251 family, enhanced binary compatible derivatives made
by numerous vendors remain popular today. Some
derivatives integrate a digital signal processor (DSP).
Beyond these physical devices, several companies also
oer MCS-51 derivatives as IP cores for use in eldprogrammable gate array (FPGA) or application-specic
integrated circuit (ASIC) designs. ROM of 4KB and
RAM of 128 bytes
Intel P8051 microcontroller.

1 Important features and applications

Intel 8051 Microarchitecture

Vcc
Vss

RAM Addr.
Register

RAM

P0.0 - P0.7

P2.0 - P2.7

Port 0
Drivers

Port 2
Drivers

Port 0
Latch

Port 2
Latch

EPROM/
ROM
8

B
Register

Program
Address
Register

Stack
Pointer

ACC

TMP2

TMP1

ALU

Buffer

PC
Incrementer

Interrupt, Serial Port,

and Timer Blocks

Timing
and
Control

EA#/VPP
RST

Instruction
Register

PSW
PSEN#
ALE/PROG#

SAB-C515-LN by Inneon is based on the 8051

16

Program
Counter

DPTR

Port 1
Latch

Port 3
Latch

The Intel MCS-51 (commonly termed 8051) is an internally Harvard architecture, complex instruction set computing (CISC) instruction set, single chip microcontroller
(C) series developed by Intel in 1980 for use in
embedded systems.[1] Intels original versions were pop- i8051 microarchitecture
ular in the 1980s and early 1990s and enhanced binary
compatible derivatives remain popular today.
The 8051 architecture provides many functions (central
Intels original MCS-51 family was developed using processing unit (CPU), random access memory (RAM),
N-type metal-oxide-semiconductor (NMOS) technology read-only memory (ROM), input/output (I/O), interrupt
like its predecessor Intel MCS-48, but later versions, logic, timer, etc.) in one package:
identied by a letter C in their name (e.g., 80C51) used
complementary metaloxidesemiconductor (CMOS)
8-bit arithmetic logic unit (ALU) and accumulator,
technology and consume less power than their NMOS
8-bit registers (one 16-bit register with special
predecessors. This made them more suitable for batterymove instructions), 8-bit data bus and 216-bit
powered devices.
address bus/program counter/data pointer and reOSC.

XTAL1

The family was continued in 1996 with the enhanced

8-bit MCS-151 and the 8/16/32-bit MCS-251 family

Port 1
Drivers

Port 3
Drivers

P1.0 - P1.7

P3.0 - P3.7

XTAL2

lated 8/11/16-bit operations; hence it is mainly an

8-bit microcontroller
1

MEMORY ARCHITECTURE

Boolean processor with 17 instructions, 1-bit accumulator, 32 registers (4 bit-addressable 8-bit) and
up to 144 special 1 bit-addressable RAM variables
(18 bit-addressable 8-bit)[3]

MCS-51 based microcontrollers typically include one or

two UARTs, two or three timers, 128 or 256 bytes of internal data RAM (16 bytes of which are bit-addressable),
up to 128 bytes of I/O, 512 bytes to 64 KB of internal program memory, and sometimes a quantity of ex Multiply, divide and compare instructions
tended data RAM (ERAM) located in the external data
4 fast switchable register banks with 8 registers each space. External RAM and ROM share the data and address buses. The original 8051 core ran at 12 clock cy(memory mapped)
cles per machine cycle, with most instructions executing
Fast interrupt with optional register bank switching in one or two machine cycles. With a 12 MHz clock frequency, the 8051 could thus execute 1 million one-cycle
Interrupts and threads with selectable priority[4]
instructions per second or 500,000 two-cycle instructions
16
Dual 16-bit address bus It can access 2 x 2 mem- per second. Enhanced 8051 cores are now commonly
ory locations 64 KB (65,536 locations) each of used which run at six, four, two, or even one clock per
machine cycle, and have clock frequencies of up to 100
RAM and ROM
MHz, and are thus capable of an even greater number of
128 bytes of on-chip RAM (IRAM)
instructions per second. All Silicon Labs, some Dallas
and a few Atmel devices have single cycle cores.
4 KiB of on-chip ROM, with a 16-bit (64 KiB) address space (PMEM). Not included on 803X vari- 8051 variants may include built-in reset timers
with brown-out detection, on-chip oscillators, selfants
programmable Flash ROM program memory, built Four 8-bit bi-directional input/output port, bit ad- in external RAM, extra internal program storage,
dressable
bootloader code in ROM, EEPROM non-volatile data
storage, IC, SPI, and USB host interfaces, CAN or LIN
UART (serial port)
bus, ZigBee or Bluetooth radio modules, PWM generators, analog comparators, A/D and D/A converters,
Two 16-bit Counter/timers
RTCs, extra counters and timers, in-circuit debugging
Power saving mode (on some derivatives)
facilities, more interrupt sources, extra power saving
modes, more/less parallel ports etc. Intel manufactured
One feature of the 8051 core is the inclusion of a boolean a mask programmed version, 8052AH-BASIC, with a
processing engine which allows bit-level boolean logic op- BASIC interpreter in ROM, capable of running user
erations to be carried out directly and eciently on select programs loaded into RAM.
internal registers, ports and select RAM locations. This
In many engineering schools the 8051 microcontroller is
feature helped cement the 8051s popularity in industrial
used in introductory microcontroller courses.
control applications because it reduced code size by as
much as 30%. Another feature is the inclusion of four
bank selectable working register sets which greatly reduce the amount of time required to complete an interrupt 2 Family naming conventions
service routine. With one instruction, the 8051 can
switch register banks versus the time consuming task of 8051 is the original name by Intel with 4 KiB ROM and
transferring the critical registers to the stack, or desig- 128 byte RAM. Variants starting with 87 have a user pronated RAM locations. These registers also allowed the grammable EPROM memory, sometimes UV erasable.
8051 to quickly perform a context switch.
Variants with a C as the third character are some kind of
Once a UART, and a timer if necessary, has been cong- CMOS. 8031 and 8032 are ROM-less versions, with 128
ured, the programmer needs only write a simple interrupt and 256 bytes RAM. The last digit can indicate memroutine to rell the send shift register whenever the last bit ory size, e.g. 8052 with 8 KiB ROM, 87C54 16 KiB
is shifted out by the UART and/or empty the full receive EPROM, and 87C58 with 32 KiB EPROM, all with 256
shift register (copy the data somewhere else). The main RAM.
program then performs serial reads and writes simply by
reading and writing 8-bit data to stacks.

1.1

Derivate features

3 Memory architecture

The MCS-51 has four distinct types of memory internal

As of 2013, new derivates are still developed by many RAM, special function registers, program memory, and
major chipmakers, and major compiler suppliers such as external data memory.
IAR Systems, Keil and Altium Tasking continuously re- The 8051 is designed as a strict Harvard architecture; it
lease updates.
can only execute code fetched from program memory,

3.4

External data memory

and has no instructions to write to program memory.

accessed by the MOVC A, @DPTR instruction. Data is

Most 8051 systems respect this distinction, and so are un- fetched from the address specied in the 16-bit special
able to download and directly execute new programs. The function register DPTR.
strict Harvard architecture has the advantage of making Special jump and call instructions make access within the
such systems immune to most forms of malware, except same 2 KiB of program memory slightly smaller.
those that reuse existing program code.[5] Some 8051
systems have (or can be modied to have) some dualmapped RAM, making them act somewhat more like 3.4 External data memory
von Neumann architecture, as external ROM and RAM
share data and address buses and the mapping can be de- External data memory (XRAM) is a third address space,
signed to allow R/W data access to program memory. also starting at address 0, and allowing 16 bits of address
This (partial) von Neumann architecture has the advan- space. It can also be on- or o-chip; what makes it extertage of making it possible for a boot loader running on the nal is that it must be accessed using the MOVX (Move
8051 to write new native code to RAM and then execute eXternal) instruction. Many variants of the 8051 include
it, leading to faster incremental and interactive program- the standard 256 bytes of IRAM plus a few KB of XRAM
ming cycles than strict Harvard systems.[6][7]
on the chip.

3.1

Internal RAM

The rst 256 bytes of XRAM may be accesses using the

MOVX A,@R0, MOVX A,@R1, MOVX @R0, A, and
MOVX @R1, A instructions. The full 64K may be accessed using MOVX A,@DPTR and MOVX @DPTR,A.

Internal RAM (IRAM) has an 8-bit address space, allowed addresses 0 through 0xFF. IRAM from 0x00 to
0x7F can be accessed directly. The 8052 added IRAM
from 0x80 to 0xFF, which must be accessed indirectly; 4 Registers
the address is loaded into R0 or R1, and the memory is accessed using the @R0 or @R1 syntax. Most 8051 clones The only register on an 8051 that is not memory-mapped
also have a full 256 bytes of IRAM.
is the 16-bit program counter PC. This species the adThe 32 bytes from 0x000x1F memory-map the 8 regis- dress of the next instruction to execute. Relative branch
ters R0R7. 8 bytes are used at a time; 2 program status instructions supply an 8-bit signed oset which is added
to the PC.
word bits select between four possible banks,
The 16 bytes (128 bits) at IRAM locations 0x200x2F 8 general-purpose registers R0R7 may be accessed with
instructions 1 byte shorter than others. They are mapped
are bit-addressable.
to IRAM between 0x00 and 0x1F. Only 8 bytes of that
range are used at any given time, determined by the two
bank select bits in the PSW.
3.2 Special function registers
The following is a partial list of the 8051s registers,
Special function registers (SFR) are located in the same which are memory-mapped into the special function regaddress space as IRAM, at addresses 0x80 to 0xFF, and ister space:
are accessed directly using the same instructions as for the
lower half of IRAM. They can not be accessed indirectly
(0x81) Stack pointer SP. This is an 8-bit register
via @R0 or @R1; indirect access to those addresses will
used by subroutine call and return instructions. The
access the second half of IRAM.
stack grows upward; the SP is incremented before
16 of the SFRs (those whose addresses are multiples of
pushing, and decremented after popping a value.
8) are also bit-addressable.

3.3

Program memory

Program memory (PMEM, though less common in usage than IRAM and XRAM) is up to 64 KiB of readonly memory, starting at address 0 in a separate address
space. It may be on- or o-chip, depending on the particular model of chip being used. Program memory is readonly, though some variants of the 8051 use on-chip ash
memory and provide a method of re-programming the
memory in-system or in-application. In addition to code,
it is possible to store read-only data in program memory,

(0x8283) Data pointer DP. This is a 16-bit register

that is used for accessing PMEM and XRAM.
(0xD0) Program status word PSW. This contains
important status ags:
PSW.0: P Parity. Gives the parity (modulo-2
sum of the bits of) the accumulator, A.
PSW.1: UD User Dened. For general software use, not otherwise used by hardware.
PSW.2: OV Overow ag. Set when addition
produces a signed overow.

5 INSTRUCTION SET
PSW.3: RS0 Register select 0. The low-order The operations is as follows. Not all support all addressbit of the register bank. Set when banks at ing modes; the immediate mode in particular is unavail0x08 or 0x18 are in use.
able if the exible operand is written to. Instruction
PSW.4: RS1 Register select 1. The high-order mnemonics use destination, source operand order.
bit of the register bank. Set when banks at
0x10 or 0x18 are in use.
PSW.5: F0 Flag 0. For general software use,
not otherwise used by hardware.
PSW.6: AC auxiliary carry. Set when addition
produces a carry from bit 3 to bit 4.
PSW.7: C Carry bit. Often used as the general
register for bit computations, or the boolean
accumulator.
(0xE0) accumulator A. This register is used by most
instructions.
(0xF0) B register. This is used as an extension to the
accumulator for multiply and divide instructions.

256 single bits are directly addressable. These are the

16 IRAM locations from 0x200x2F, and the 16 special
function registers 0x80, 0x88, 0x90, , 0xF8. Any bit
of these bytes may be directly accessed by a variety of
logical operations and conditional branches.
Note that the PSW does not contain the common N (negative) and Z (zero) ags. Instead, because the accumulator is a bit-addressible SFR, it is possible to branch on its
most signicant bit directly. There is also an instruction
to jump if the accumulator is zero or non-zero. There
is also a compare and jump operation that takes two
operands.

Instruction set

Instructions are all 1 to 3 bytes long, consisting of an initial opcode byte, followed by up to 2 bytes of operands.
3/4 of the opcode bytes are assigned to 16 basic ALU
instructions. One operand is exible, while the second
(if any) is specied by the operation: the accumulator, an
immediate constant, or a RAM address. The most signicant nibble of the opcode byte species the operation, and
the least signicant nibble species one of the following
12 addressing modes for the exible operand:
x8xF: Register direct, R0R7
x6x7: Register indirect, @R0 or @R1
x5: Memory direct, a following byte species an
IRAM or SFR location
x4: Immediate, a following byte species an 8bit constant. In some cases where an immediate
operand is nonsensical, the accumulator is used.

0y: INC operand: Increment the specied operand.

Opcode 04 species INC A
1y: DEC operand: Decrement the specied
operand. Opcode 14 species DEC A
2y: ADD A,operand: Add the operand to the accumulator A.
3y: ADDC A,operand: Add the operand, plus the
C bit, to the accumulator.
4y: ORL A,operand: Logical OR the operand into
the A register.
5y: ANL A,operand: Logical AND the operand
into the A register.
6y: XRL A,operand: Logical exclusive-OR the
operand into the A register.
7y: MOV operand,#data: Move immediate data to
the operand. Opcode 74 species MOV A,#data.
8y: MOV address,operand: Move data to an IRAM
or SFR register.
9y: SUBB A,operand: Subtract the operand from
the accumulator, with borrow. Note there is no subtract without borrow.
Ay: MOV operand,address: Move data from an
IRAM or SFR register. Opcodes A4 and A5 are
not used.
By: CJNE operand,#data,oset: Compare operand
to the immediate data, and branch to PC+oset
if not equal. Opcodes B4 and B5 perform CJNE
A,operand,oset, for memory direct and immediate
operands. Note there is no compare and jump if
equal instruction.
Cy: XCH A,operand: Exchange (swap) the accumulator and the operand. Opcode C4 is not used.
Dy: DJNZ operand,oset: Decrement the operand,
and branch to PC+oset if the result is non-zero.
Opcodes D4, D6, and D7 are not used.
Ey: MOV A,operand: Move operand to the accumulator. Opcode E4 is not used. (Use opcode 74
instead.)
Fy: MOV operand,A: Move accumulator to the
operand. Opcode F4 is not used.

5
Only the ADD, ADDC and SUBB instructions set PSW
ags. The INC, DEC, and logical instructions do not. The
CJNE instructions modify the C bit only, to the borrow
that results from operand1operand2.

7 Related processors

The 64 opcodes x0x3, plus the few opcodes not used in

the above range, are used for other instructions with more
limited operand-specication capabilities:
One of the reasons for the 8051s popularity is its range
of operations on single bits. Bits are always specied by
absolute addresses; there is no register-indirect or indexed
addressing. Instructions that operate on single bits are:
SETB bit, CLR bit, CPL bit: Set, clear, or complement the specied bit
JB bit,oset: Jump if bit set
JNB bit,oset: Jump if bit clear
JBC bit,oset: Jump if bit set, and clear bit
MOV C,bit, MOV bit,C: Move the specied bit to
the carry bit, or vice versa

Intel 8031 processors

ORL C,bit, ORL C,/bit: OR the bit (or its complement) to the carry bit
The 8051s predecessor, the 8048, was used in the key ANL C,bit, ANL C,/bit: AND the bit (or its com- board of the rst IBM PC, where it converted keypresses
into the serial data stream which is sent to the main unit
plement) to the carry bit
of the computer. The 8048 and derivatives are still used
Although most instructions require that one operand is today for basic model keyboards.
the accumulator or an immediate constant, it is possible The 8031 was a cut down version of the original Intel
to perform a MOV directly between two internal RAM 8051 that had no internal program memory (read-only
locations.
memory (ROM)). To use this chip, external ROM had
to be added containing the program that the 8031 would
fetch and execute. An 8051 chip could be sold as a ROM6 Programming
less 8031, as the 8051s internal ROM is disabled by the
normal state of the EA pin in an 8031-based design. A
There are various high-level programming language com- vendor might sell an 8051 as an 8031 for any number of
pilers for the 8051. Several C compilers are available reasons, such as faulty code in the 8051s ROM, or simply
for the 8051, most of which allow the programmer to an oversupply of 8051s and undersupply of 8031s.
specify where each variable should be stored in its six The 8052 was an enhanced version of the original 8051
types of memory, and provide access to 8051 specic that featured 256 bytes of internal RAM instead of 128
hardware features such as the multiple register banks and bytes, 8 KB of ROM instead of 4 KB, and a third 16bit manipulation instructions. There are many commer- bit timer. The 8032 had these same features except for
cial C compilers.[8] Small Device C Compiler (SDCC) the internal ROM program memory. Most modern 8051is a popular open source C compiler.[9] Other high level compatible microcontrollers include these features.
languages such as C++, Forth,[6][7][10][11] BASIC, Object
its MCS-51 product line in March
Pascal, Pascal, PL/M and Modula-2 are available for the Intel discontinued
[12][13]
2007;
however,
there are plenty of enhanced 8051
8051, but they are less widely used than C and assembly.
products or silicon intellectual property added regularly
Because IRAM, XRAM, and PMEM (read only) all have from other vendors.
an address 0, C compilers for the 8051 architecture provide compiler-specic pragmas or other extensions to in- The 80C537 and 80C517 are CMOS versions, designed
dicate where a particular piece of data should be stored for the automotive industry. Enhancements mostly in(i.e. constants in PMEM or variables needing fast access clude new peripheral features and expanded arithmetic
in IRAM). Since data could be in one of three memory instructions. The 80C517 has fail-safe mechanisms, anaspaces, a mechanism is usually provided to allow deter- log signal processing facilities and timer capabilities and
mining to which memory a pointer refers, either by con- 8 KB on-chip program memory. Other features include:
straining the pointer type to include the memory space,
256 byte on-chip RAM
or by storing metadata with the pointer.

7 RELATED PROCESSORS
256 directly addressable bits

CORERIVER

External program and data memory expandable up

to 64 KB

Cybernetic Micro Systems

8-bit A/D converter with 12 multiplexed inputs

Arithmetic unit can make division, multiplication,
shift and normalize operations
Eight data pointers instead of one for indirect addressing of program and external data memory

CybraTech
Cypress Semiconductor
Daewoo
Dallas Semiconductor
Digital Core Design

Extended watchdog facilities

Dolphin Integration

Nine ports

Domosys

Two full-duplex serial interfaces with own baud rate

generators

easyplug

Four priority level interrupt systems, 14 interrupt

vectors

Evatronix

Three power saving modes

EnOcean

Fairchild Semiconductor (ON Semiconductor)

Genesis Microchip

7.1

Derivate vendors

Current vendors of MCS-51 compatible processors include more than 20 independent manufacturers including Atmel, Inneon Technologies (formerly Siemens
AG), Maxim Integrated Products (via its Dallas Semiconductor subsidiary), NXP (formerly Philips Semiconductor), Microchip Technology, Nuvoton (formerly
Winbond), ST Microelectronics, Silicon Laboratories
(formerly Cygnal), Texas Instruments, Ramtron International, Silicon Storage Technology, Cypress Semiconductor and Analog Devices.[14]
ICs or IPs compatible with the MCS-51 have been developed by:

Genesys Logic
Goal Semiconductor
Handshake Solutions
Honeywell
Hynix Semiconductor
Inneon (founded by Siemens)
InnovASIC
Intel
ISSI

Acer Labs

Lapis Semiconductor (formerly OKI Semiconductor)

Actel

Maxim (Dallas Semiconductor)

Aeroex UTMC

Megawin

Altium

Mentor Graphics

Analog Devices

Micronas

ASIX

Microsemi

Atmel

MXIC (Macronix)

AustriaMicroSystems

Myson Technology

AXSEM (ON Semiconductor)

Nordic Semiconductor

California Eastern Laboratories (CEL)

Nuvoton (Winbond)

Cast

NXP (founded by Philips)

CML Microcircuits

Oregano Systems

7
Palmchip
Prolic
Radio Pulse
Ramtron
RDC Semiconductor
Sanyo Semiconductor (ON Semiconductor)
Sharp
Sigma Designs

Modern 8051 cores are faster than earlier packaged versions. Design improvements have increased 8051 performance while retaining compatibility with the original
MCS 51 instruction set. The original Intel 8051 ran at
12 clock cycles per machine cycle, and most instructions
executed in one or two machine cycles. A typical maximum clock frequency of 12 MHz meant these old 8051s
could execute one million single-cycle instructions, or
500,000 two-cycle instructions, per second. In contrast,
enhanced 8051 silicon IP cores now run at one clock cycle per machine cycle, and have clock frequencies of up
to 450 MHz. That means an 8051-compatible processor
can now execute 450 million instructions per second.

Silicon Laboratories (Cygnal)

Siliconians

9 MCU based on 8051

SMSC
SST

Atmel: AT89C51, AT89S51, AT83C5134

STMicroelectronics

Inneon: XC800

SyncMOS
Synopsys
Syntek Semiconductor
Tekmos
Teridian Semiconductor
Texas Instruments

Mentor Graphics: M8051ew

NXP: NXP700 and NXP900 series
Silicon Labs: C8051 series
Texas Instruments CC111x, CC24xx and CC25xx
families of RF SoCs

Tezzaron Semiconductor
Triscend
Vitesse

10 Digital signal processor (DSP)

variants

Yitran
Zensys
Zilog
Zylogic Semiconductor

Use as intellectual property

Today, 8051s are still available as discrete parts, but

they are mostly used as silicon intellectual property cores.
Available in high-level language source code (VHDL or
Verilog) or FPGA netlist forms, these cores are typically
integrated within embedded systems, in products ranging
from USB ash drives to washing machines to complex
wireless communication systems on a chip. Designers use
8051 silicon IP cores, because of the smaller size, and
lower power, compared to 32 bit processors like ARM
Cortex-M series, MIPS and BA22.

Several variants with an additional 16-bit digital signal

processor (DSP) (for example for MP3 or OGG coding/decoding) with up to 675 million instructions per second (MIPS)[15] and integrated USB 2.0 interface[16] or as
intellectual property[17] exist.

11 Enhanced 8-bit binary compatible microcontroller: MCS-151

family
1996 Intel announced the MCS-151 family, an up to 6
times faster variant.[2] 8051 fully binary and instruction
set compatible, but with pipelined CPU, 16 bit internal
code bus and 6x speed. The MCS-151 family was also
discontinued by Intel, but is widely available in binary
compatible and partly enhanced variants.

15 FURTHER READING

12

8/16/32-bit binary compatible microcontroller: MCS-251

family

[9] Lewin A. R. W. Edwards. So, You Wanna be an Embedded Engineer: The Guide to Embedded Engineering,
from Consultancy to the Corporate Ladder. 2006. p. 51.
[10] 8051 SwiftX Forth development.

The 80251 8/16/32-bit microcontroller with 16 MB (24- [11] MPE VFX Forth 7 cross compilers.
bit) address-space and 6 times faster instruction cycle was [12] Ganssle, Jack (2006-05-29). Intel bows out, discontinues
introduced by Intel in 1996.[2][18] It can perform as an 8MCS-51.
bit 8051, has 24-bit external address space which is 16-bit
wide segmented and 32-bit ALU with mostly 8/16/32-bit [13] MCS 51, MCS 251 and MCS 96 Microcontroller Product Lines, the Intel 186, Intel386 and Intel486 Processors
wide data instructions (also Boolean processor with speProduct Lines, and the i960 32 Bit RISC Processor, PCN
cial registers/memory) and a large CISC instruction set,
106013-01, Product Discontinuance, Reason for Revi40 8/16/32-bit registers with 8 8-bit registers in 4 times
sion: Add Key Milestone information and revise descripfast switching memory banks (maximum 512 addressable
tion of change (PDF). Intel. 2006-05-02.
8-bit special registers).
It features extended instructions[19] see also the pro- [14] http://www.analog.com/static/imported-files/data_
sheets/ADUC832.pdf
grammers guide[20] and later variants with higher
[21]
performance,
also available as intellectual property [15] TI Delivers new low-cost, high-performance audio DSP
(IP).[22] It is 3-stage pipelined. The MCS-251 family was
for Home and Car w/ 8051
also discontinued by Intel, but is widely available in binary compatible and partly enhanced variants from many [16] Atmel AT85C51SND3 Audio DSP Data Sheet with USB
2.0
manufacturers.
[17] Integration of 8051 With DSP in Xilinx FPGA

13

[18] The 8051 microcontroller By Kenneth J Ayala Google

books

See also

SDK-51 System Design Kit

[19] Temic TSC80251 Architecture

[20] Atmel TSC80251 Programmers Guide

DS80C390

[21] DQ80251 32bit Microcontroller DCD

14

[22] R80251XC 32bit Microcontroller Evatronix

References

[1] John Wharton: An Introduction to the Intel MCS-51 SingleChip Microcomputer Family, Application Note AP-69,
May 1980, Intel Corporation.

15 Further reading
Books

[2] Intel MCS 151 and MCS 251 Microcontrollers

[3] John Wharton: Using the Intel MCS-51 Boolean Processing Capabilities Application Note AP-70, May 1980, Intel
Corporation.
[4] 8051 Tutorial: Interrupts
[5] Francillon, Aurlien; Castelluccia, Claude (2008-0101). Code Injection Attacks on Harvard-architecture
Proceedings of the 15th ACM ConferDevices.
ence on Computer and Communications Security.
CCS '08.
New York, NY, USA: ACM: 1526.
doi:10.1145/1455770.1455775. ISBN 9781595938107.
[6] Bradford J. Rodriguez. CamelForth/8051.
[7] Brad Rodriguez. Moving Forth Part 7: CamelForth for
the 8051.
[8] Han-Way Huang.
C8051. p. 238.

Embedded System Design with

Mazidi; McKinlay; Mazidi (2012). The 8051 Microcontroller: A Systems Approach. 648 pp. ISBN
978-0-13-508044-3.
Schultz, Thomas (2008). C and the 8051 (4th ed.).
464 pp. ISBN 978-0-9783995-0-4.
Steiner, Craig (2005). The 8051/8052 Microcontroller: Architecture, Assembly Language, and Hardware Interfacing. 348 pp. ISBN 978-1-58112-4590.
Calcutt; Cowan; Parchizadeh (2000). 8051 Microcontrollers: Hardware, Software and Applications.
329 pp. ISBN 978-0-340-67707-0.
Axelson, Jan (1994). The Microcontroller Idea
Book: Circuits, Programs, and Applications featuring the 8052-BASIC Microcontroller. 277 pp. ISBN
978-0-9650819-0-0.

9
Payne, William (December 19, 1990) [1990]. Embedded Controller FORTH for the 8051 Family
(hardcover). Boston: Academic Press. 528 pp.
ISBN 978-0-12-547570-9.
Intel
MCS-51 Microcontroller Family Users Manual; Intel; 1994; publication number 121517.
MCS-51 Macro Assembler Users Guide; Intel; publication number 9800937.
8-Bit Embedded Controllers; Intel; 1991; publication
number 270645-003.
Microcontroller Handbook; Intel; 1984; publication
number 210918-002.
8051 Microcontroller Preliminary Architectural
Specication and Functional Description; Intel; 44
pages; 1980.

16

External links

Complete tutorial for 8051 microcontrollers

the source website for tutorials and simulator for
8051
Basic 8051 Interfacing Circuits
Open source VHDL 8051 implementation (Oregano
Systems)
This article is based on material taken from the Free Online Dictionary of Computing prior to 1 November 2008
and incorporated under the relicensing terms of the
GFDL, version 1.3 or later.

10

17

17
17.1

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