VLSI ARCHITECTURE

ASSIGNMENT 2
MIPS Single Cycle Processor

ABUTURAB MOHAMMADI
ID-2013A8PS437G

TIME SPENT
6 to 7 hours

TABLE
Cycle

reset

pc

instr

branch

srca

srcb

aluresult

zero

pcsrc
0

write
data
x

mem
write
0

read
data
0

00

04

08

12

0C

addi $2,$0,5
20020005
addi $7,$0,3
20070003
addi $3,$0,0xc
2003000c
or $4, $7, $2
00e22025

12

12

10

and $5, $3, $4

00642824

14

add $5, $5, $4

00a42820

18

beq $5, $7, end

47

4C

10a70008
8

1C

20

10

28

11

2C

slt $6, $3, $4

0064302a
beq
$6,
around

$0,

10c00001
slt $6, $7, $2
00e2302a
add $7, $6, $5

00c53820
12

30

sub $7, $7, $2

00e23822
13

34

14

3C

j end
0800000f
sw $7, 71($2)
ac470047

Table 1. First fourteen cycles of executing assembly program test1.asm

What address will the final sw instruction write to and what value will it write?
The sw instruction will store the value of reg $7 in address 4C i.e the 12th data register.

CODE
module ctrlCkt(input [5:0] op, input [5:0] funct, output reg RegWrite, output reg RegDst, output reg ALUSrc, output reg Branch,
output reg MemWrite, output reg MemToReg, output reg Jump, output reg [2:0] ALUControl);
always @(op or funct)
begin
case(op)
6'b001000:begin
RegWrite=1;
RegDst=0;
Jump=0;
Branch=0;
MemWrite=0;
MemToReg=0;
ALUSrc=1;
ALUControl=3'b010;
end
6'b000000: begin
RegWrite=1;
RegDst=1;
ALUSrc=0;
MemToReg=0;
MemWrite=0;
Branch=0;
Jump=0;
case(funct)
6'b100000:ALUControl=3'b010;
6'b100010:ALUControl=3'b110;
6'b100100:ALUControl=3'b000;
6'b100101:ALUControl=3'b001;
6'b101010:ALUControl=3'b111;
endcase
end
6'b101011: begin
RegWrite=0;
ALUSrc=1;
MemWrite=1;
Branch=0;
Jump=0;
ALUControl=3'b010;
end
6'b100011: begin
RegDst=0;

RegWrite=1;
ALUSrc=1;
MemWrite=0;
MemToReg=1;
Jump=0;
Branch=0;
ALUControl=3'b010;
end
6'b000100: begin
RegWrite=0;
ALUSrc=0;
MemWrite=0;
Branch=1;
Jump=0;
ALUControl=3'b110;
end
6'b000010: begin
RegWrite=0;
MemWrite=0;
Jump=1;
end
endcase
end
endmodule
module D_ff(input d, input clk, input regWrite, input reset, output reg q);
always @(posedge clk)
begin
if(reset)
q<=1'b0;
else
begin
if(regWrite)
begin
q<=d;
end
end
end
endmodule
module register32bit(input clk, input reset, input regwrite, input [31:0] writedata, output [31:0] Rout );
D_ff d0(writedata[0],clk,regwrite,reset,Rout[0]);
D_ff d1(writedata[1],clk,regwrite,reset,Rout[1]);
D_ff d2(writedata[2],clk,regwrite,reset,Rout[2]);
D_ff d3(writedata[3],clk,regwrite,reset,Rout[3]);

D_ff d4(writedata[4],clk,regwrite,reset,Rout[4]);
D_ff d5(writedata[5],clk,regwrite,reset,Rout[5]);
D_ff d6(writedata[6],clk,regwrite,reset,Rout[6]);
D_ff d7(writedata[7],clk,regwrite,reset,Rout[7]);
D_ff d8(writedata[8],clk,regwrite,reset,Rout[8]);
D_ff d9(writedata[9],clk,regwrite,reset,Rout[9]);
D_ff d10(writedata[10],clk,regwrite,reset,Rout[10]);
D_ff d11(writedata[11],clk,regwrite,reset,Rout[11]);
D_ff d12(writedata[12],clk,regwrite,reset,Rout[12]);
D_ff d13(writedata[13],clk,regwrite,reset,Rout[13]);
D_ff d14(writedata[14],clk,regwrite,reset,Rout[14]);
D_ff d15(writedata[15],clk,regwrite,reset,Rout[15]);
D_ff d16(writedata[16],clk,regwrite,reset,Rout[16]);
D_ff d17(writedata[17],clk,regwrite,reset,Rout[17]);
D_ff d18(writedata[18],clk,regwrite,reset,Rout[18]);
D_ff d19(writedata[19],clk,regwrite,reset,Rout[19]);
D_ff d20(writedata[20],clk,regwrite,reset,Rout[20]);
D_ff d21(writedata[21],clk,regwrite,reset,Rout[21]);
D_ff d22(writedata[22],clk,regwrite,reset,Rout[22]);
D_ff d23(writedata[23],clk,regwrite,reset,Rout[23]);
D_ff d24(writedata[24],clk,regwrite,reset,Rout[24]);
D_ff d25(writedata[25],clk,regwrite,reset,Rout[25]);
D_ff d26(writedata[26],clk,regwrite,reset,Rout[26]);
D_ff d27(writedata[27],clk,regwrite,reset,Rout[27]);
D_ff d28(writedata[28],clk,regwrite,reset,Rout[28]);
D_ff d29(writedata[29],clk,regwrite,reset,Rout[29]);
D_ff d30(writedata[30],clk,regwrite,reset,Rout[30]);
D_ff d31(writedata[31],clk,regwrite,reset,Rout[31]);
endmodule
module decoder4to16(input [3:0] DstReg, output reg [15:0] decOut);
always@(DstReg)
case(DstReg)
4'b0000: decOut=16'b0000000000000001;
4'b0001: decOut=16'b0000000000000010;
4'b0010: decOut=16'b0000000000000100;
4'b0011: decOut=16'b0000000000001000;
4'b0100: decOut=16'b0000000000010000;
4'b0101: decOut=16'b0000000000100000;
4'b0110: decOut=16'b0000000001000000;
4'b0111: decOut=16'b0000000010000000;
4'b1000: decOut=16'b0000000100000000;
4'b1001: decOut=16'b0000001000000000;
4'b1010: decOut=16'b0000010000000000;
4'b1011: decOut=16'b0000100000000000;
4'b1100: decOut=16'b0001000000000000;

4'b1101: decOut=16'b0010000000000000;
4'b1110: decOut=16'b0100000000000000;
4'b1111: decOut=16'b1000000000000000;
endcase
endmodule
module mux16to1( input [31:0]
outR0,outR1,outR2,outR3,outR4,outR5,outR6,outR7,outR8,outR9,outR10,outR11,outR12,outR13,outR14,outR15, input [3:0] Sel, output reg
[31:0] outBus );
always@(outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7 or outR8 or outR9 or outR10 or outR11 or outR12
or outR13 or outR14 or outR15 or Sel)
case (Sel)
4'b0000: outBus=outR0;
4'b0001: outBus=outR1;
4'b0010: outBus=outR2;
4'b0011: outBus=outR3;
4'b0100: outBus=outR4;
4'b0101: outBus=outR5;
4'b0110: outBus=outR6;
4'b0111: outBus=outR7;
4'b1000: outBus=outR8;
4'b1001: outBus=outR9;
4'b1010: outBus=outR10;
4'b1011: outBus=outR11;
4'b1100: outBus=outR12;
4'b1101: outBus=outR13;
4'b1110: outBus=outR14;
4'b1111: outBus=outR15;
endcase
endmodule
module regFile(input clk, input reset, input [4:0] A1,A2,A3, input WE3, input [31:0] WD3, output [31:0] RD1, RD2);
wire[15:0] wr;
wire [31:0] Rd0,Rd1,Rd2,Rd3,Rd4,Rd5,Rd6,Rd7,Rd8,Rd9,Rd10,Rd11,Rd12,Rd13,Rd14,Rd15;
decoder4to16 dec1(A3[3:0],wr);
register32bit r0(clk,reset,1'b0,WD3,Rd0);
register32bit r1(clk,reset,wr[1]&WE3,WD3,Rd1);
register32bit r2(clk,reset,wr[2]&WE3,WD3,Rd2);
register32bit r3(clk,reset,wr[3]&WE3,WD3,Rd3);
register32bit r4(clk,reset,wr[4]&WE3,WD3,Rd4);
register32bit r5(clk,reset,wr[5]&WE3,WD3,Rd5);
register32bit r6(clk,reset,wr[6]&WE3,WD3,Rd6);
register32bit r7(clk,reset,wr[7]&WE3,WD3,Rd7);
register32bit r8(clk,reset,wr[8]&WE3,WD3,Rd8);
register32bit r9(clk,reset,wr[9]&WE3,WD3,Rd9);
register32bit r10(clk,reset,wr[10]&WE3,WD3,Rd10);

register32bit
register32bit
register32bit
register32bit
register32bit

r11(clk,reset,wr[11]&WE3,WD3,Rd11);
r12(clk,reset,wr[12]&WE3,WD3,Rd12);
r13(clk,reset,wr[13]&WE3,WD3,Rd13);
r14(clk,reset,wr[14]&WE3,WD3,Rd14);
r15(clk,reset,wr[15]&WE3,WD3,Rd15);

mux16to1 m1(Rd0,Rd1,Rd2,Rd3,Rd4,Rd5,Rd6,Rd7,Rd8,Rd9,Rd10,Rd11,Rd12,Rd13,Rd14,Rd15,A1[3:0],RD1);
mux16to1 m2(Rd0,Rd1,Rd2,Rd3,Rd4,Rd5,Rd6,Rd7,Rd8,Rd9,Rd10,Rd11,Rd12,Rd13,Rd14,Rd15,A2[3:0],RD2);
endmodule
module dff(input clk, input reset, input d, output reg q);
always@(posedge clk)
begin
q<=d;
if(reset)
q<=1'b0;
end
endmodule

module PCReg(input clk, input reset, input [31:0] PCin, output [31:0] PCout);
dff df0(clk,reset,PCin[0],PCout[0]);
dff df1(clk,reset,PCin[1],PCout[1]);
dff df2(clk,reset,PCin[2],PCout[2]);
dff df3(clk,reset,PCin[3],PCout[3]);
dff df4(clk,reset,PCin[4],PCout[4]);
dff df5(clk,reset,PCin[5],PCout[5]);
dff df6(clk,reset,PCin[6],PCout[6]);
dff df7(clk,reset,PCin[7],PCout[7]);
dff df8(clk,reset,PCin[8],PCout[8]);
dff df9(clk,reset,PCin[9],PCout[9]);
dff df10(clk,reset,PCin[10],PCout[10]);
dff df11(clk,reset,PCin[11],PCout[11]);
dff df12(clk,reset,PCin[12],PCout[12]);
dff df13(clk,reset,PCin[13],PCout[13]);
dff df14(clk,reset,PCin[14],PCout[14]);
dff df15(clk,reset,PCin[15],PCout[15]);
dff df16(clk,reset,PCin[16],PCout[16]);
dff df17(clk,reset,PCin[17],PCout[17]);
dff df18(clk,reset,PCin[18],PCout[18]);
dff df19(clk,reset,PCin[19],PCout[19]);
dff df20(clk,reset,PCin[20],PCout[20]);
dff df21(clk,reset,PCin[21],PCout[21]);
dff df22(clk,reset,PCin[22],PCout[22]);
dff df23(clk,reset,PCin[23],PCout[23]);

dff df24(clk,reset,PCin[24],PCout[24]);
dff df25(clk,reset,PCin[25],PCout[25]);
dff df26(clk,reset,PCin[26],PCout[26]);
dff df27(clk,reset,PCin[27],PCout[27]);
dff df28(clk,reset,PCin[28],PCout[28]);
dff df29(clk,reset,PCin[29],PCout[29]);
dff df30(clk,reset,PCin[30],PCout[30]);
dff df31(clk,reset,PCin[31],PCout[31]);
endmodule
module SignExt(input [15:0] in, output [31:0] out);
wire [31:0] wout;
genvar i;
for(i=0;i<16;i=i+1)
assign wout[i]=in[i];
for(i=16;i<32;i=i+1)
assign wout[i]=in[15];
assign out=wout;
endmodule
module mux2to1(input [31:0] a,b, input sel, output reg [31:0] out);
always@(a or b or sel)
begin
case(sel)
1'b0:out=a;
1'b1:out=b;
endcase
end
endmodule
module mux2to1_5bit(input [4:0] a,b, input sel, output reg [4:0] out);
always@(a or b or sel)
begin
case(sel)
1'b0:out=a;
1'b1:out=b;
endcase
end
endmodule
module D_ff_IM(input reset, input d, output reg q);
always@(reset)
if(reset)
q<=d;
endmodule

module register_IM(input reset,input [31:0] d_in, output [31:0] q_out);

D_ff_IM dim0(reset,d_in[0],q_out[0]);
D_ff_IM dim1(reset,d_in[1],q_out[1]);
D_ff_IM dim2(reset,d_in[2],q_out[2]);
D_ff_IM dim3(reset,d_in[3],q_out[3]);
D_ff_IM dim4(reset,d_in[4],q_out[4]);
D_ff_IM dim5(reset,d_in[5],q_out[5]);
D_ff_IM dim6(reset,d_in[6],q_out[6]);
D_ff_IM dim7(reset,d_in[7],q_out[7]);
D_ff_IM dim8(reset,d_in[8],q_out[8]);
D_ff_IM dim9(reset,d_in[9],q_out[9]);
D_ff_IM dim10(reset,d_in[10],q_out[10]);
D_ff_IM dim11(reset,d_in[11],q_out[11]);
D_ff_IM dim12(reset,d_in[12],q_out[12]);
D_ff_IM dim13(reset,d_in[13],q_out[13]);
D_ff_IM dim14(reset,d_in[14],q_out[14]);
D_ff_IM dim15(reset,d_in[15],q_out[15]);
D_ff_IM dim16(reset,d_in[16],q_out[16]);
D_ff_IM dim17(reset,d_in[17],q_out[17]);
D_ff_IM dim18(reset,d_in[18],q_out[18]);
D_ff_IM dim19(reset,d_in[19],q_out[19]);
D_ff_IM dim20(reset,d_in[20],q_out[20]);
D_ff_IM dim21(reset,d_in[21],q_out[21]);
D_ff_IM dim22(reset,d_in[22],q_out[22]);
D_ff_IM dim23(reset,d_in[23],q_out[23]);
D_ff_IM dim24(reset,d_in[24],q_out[24]);
D_ff_IM dim25(reset,d_in[25],q_out[25]);
D_ff_IM dim26(reset,d_in[26],q_out[26]);
D_ff_IM dim27(reset,d_in[27],q_out[27]);
D_ff_IM dim28(reset,d_in[28],q_out[28]);
D_ff_IM dim29(reset,d_in[29],q_out[29]);
D_ff_IM dim30(reset,d_in[30],q_out[30]);
D_ff_IM dim31(reset,d_in[31],q_out[31]);
endmodule
module IM(input
wire [31:0]
register_IM
register_IM
register_IM
register_IM
register_IM
register_IM
register_IM
register_IM
register_IM

reset, input [5:0] pc_6bits, output [31:0] IR);

Qout0,Qout2,Qout1,Qout3,Qout4,Qout5,Qout6,Qout7,Qout8,Qout9,Qout10,Qout11,Qout12,Qout13,Qout14,Qout15;
rIM0(reset, 32'h20020005, Qout0);
rIM1(reset, 32'h20070003, Qout1);
rIM2(reset, 32'h2003000c, Qout2);
rIM3(reset, 32'h00e22025, Qout3);
rIM4(reset, 32'h00642824, Qout4);
rIM5(reset, 32'h00a42820, Qout5);
rIM6(reset, 32'h10a70008, Qout6);
rIM7(reset, 32'h0064302a, Qout7);
rIM8(reset, 32'h10c00001, Qout8);

register_IM rIM9(reset, 32'h2005000a, Qout9);

register_IM rIM10(reset, 32'h00e2302a, Qout10);
register_IM rIM11(reset, 32'h00c53820, Qout11);
register_IM rIM12(reset, 32'h00e23822, Qout12);
register_IM rIM13(reset, 32'h0800000f, Qout13);
register_IM rIM14(reset, 32'h8c070000, Qout14);
register_IM rIM15(reset, 32'hac470047, Qout15);
mux16to1
mIM(Qout0,Qout1,Qout2,Qout3,Qout4,Qout5,Qout6,Qout7,Qout8,Qout9,Qout10,Qout11,Qout12,Qout13,Qout14,Qout15,pc_6bits[3:0],IR);
endmodule
module adder(input [31:0] in1,in2,output reg [31:0] sum);
always @(in1 or in2)begin
sum=in1+in2;
end
endmodule
module Dff_DM(input clk, input reset, input MW, input init, input d, output reg q);
always@(posedge clk or reset)
begin
if(MW)
q<=d;
if(reset)
q<=init;
end
endmodule
module register_DM(input clk, input reset, input MW, input [31:0] init, input [31:0] d_in, output [31:0] q_out);
Dff_DM dMem0(clk,reset,MW,init[0],d_in[0],q_out[0]);
Dff_DM dMem1(clk,reset,MW,init[1],d_in[1],q_out[1]);
Dff_DM dMem2(clk,reset,MW,init[2],d_in[2],q_out[2]);
Dff_DM dMem3(clk,reset,MW,init[3],d_in[3],q_out[3]);
Dff_DM dMem4(clk,reset,MW,init[4],d_in[4],q_out[4]);
Dff_DM dMem5(clk,reset,MW,init[5],d_in[5],q_out[5]);
Dff_DM dMem6(clk,reset,MW,init[6],d_in[6],q_out[6]);
Dff_DM dMem7(clk,reset,MW,init[7],d_in[7],q_out[7]);
Dff_DM dMem8(clk,reset,MW,init[8],d_in[8],q_out[8]);
Dff_DM dMem9(clk,reset,MW,init[9],d_in[9],q_out[9]);
Dff_DM dMem10(clk,reset,MW,init[10],d_in[10],q_out[10]);
Dff_DM dMem11(clk,reset,MW,init[11],d_in[11],q_out[11]);
Dff_DM dMem12(clk,reset,MW,init[12],d_in[12],q_out[12]);
Dff_DM dMem13(clk,reset,MW,init[13],d_in[13],q_out[13]);
Dff_DM dMem14(clk,reset,MW,init[14],d_in[14],q_out[14]);
Dff_DM dMem15(clk,reset,MW,init[15],d_in[15],q_out[15]);
Dff_DM dMem16(clk,reset,MW,init[16],d_in[16],q_out[16]);
Dff_DM dMem17(clk,reset,MW,init[17],d_in[17],q_out[17]);

Dff_DM
Dff_DM
Dff_DM
Dff_DM
Dff_DM
Dff_DM
Dff_DM
Dff_DM
Dff_DM
Dff_DM
Dff_DM
Dff_DM
Dff_DM
Dff_DM
endmodule

dMem18(clk,reset,MW,init[18],d_in[18],q_out[18]);
dMem19(clk,reset,MW,init[19],d_in[19],q_out[19]);
dMem20(clk,reset,MW,init[20],d_in[20],q_out[20]);
dMem21(clk,reset,MW,init[21],d_in[21],q_out[21]);
dMem22(clk,reset,MW,init[22],d_in[22],q_out[22]);
dMem23(clk,reset,MW,init[23],d_in[23],q_out[23]);
dMem24(clk,reset,MW,init[24],d_in[24],q_out[24]);
dMem25(clk,reset,MW,init[25],d_in[25],q_out[25]);
dMem26(clk,reset,MW,init[26],d_in[26],q_out[26]);
dMem27(clk,reset,MW,init[27],d_in[27],q_out[27]);
dMem28(clk,reset,MW,init[28],d_in[28],q_out[28]);
dMem29(clk,reset,MW,init[29],d_in[29],q_out[29]);
dMem30(clk,reset,MW,init[30],d_in[30],q_out[30]);
dMem31(clk,reset,MW,init[31],d_in[31],q_out[31]);

module decoder6to64(input [5:0] dst, output reg [63:0] decOut);

integer i;
always@(dst)
begin
for(i=0;i<64;i=i+1)
begin
if(dst==i)
decOut[i]=1;
else
decOut[i]=0;
end
end
endmodule
module mux64to1(input [31:0]
outR0,outR1,outR2,outR3,outR4,outR5,outR6,outR7,outR8,outR9,outR10,outR11,outR12,outR13,outR14,outR15,outR16,outR17,outR18,outR19,
outR20,outR21,outR22,outR23,outR24,outR25,outR26,outR27,outR28,outR29,outR30,outR31,outR32,outR33,outR34,outR35,outR36,outR37,outR
38,outR39,outR40,outR41,outR42,outR43,outR44,outR45,outR46,outR47,outR48,outR49,outR50,outR51,outR52,outR53,outR54,outR55,outR56,o
utR57,outR58,outR59,outR60,outR61,outR62,outR63,input [5:0] sel, output reg [31:0] outBus);
always@(outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7 or outR8 or outR9 or outR10 or outR11 or outR12
or outR13 or outR14 or outR15 or outR16 or outR17 or outR18 or outR19 or outR20 or outR21 or outR22 or outR23 or outR24 or outR25
or outR26 or outR27 or outR28 or outR29 or outR30 or outR31 or outR32 or outR33 or outR34 or outR35 or outR36 or outR37 or outR38
or outR39 or outR40 or outR41 or outR42 or outR43 or outR44 or outR45 or outR46 or outR47 or outR48 or outR49 or outR50 or outR51
or outR52 or outR53 or outR54 or outR55 or outR56 or outR57 or outR58 or outR59 or outR60 or outR61 or outR62 or outR63 or sel)
case (sel)
6'b0: outBus=outR0;
6'b1: outBus=outR1;
6'b10: outBus=outR2;
6'b11: outBus=outR3;

6'b100: outBus=outR4;
6'b101: outBus=outR5;
6'b110: outBus=outR6;
6'b111: outBus=outR7;
6'b1000: outBus=outR8;
6'b1001: outBus=outR9;
6'b1010: outBus=outR10;
6'b1011: outBus=outR11;
6'b1100: outBus=outR12;
6'b1101: outBus=outR13;
6'b1110: outBus=outR14;
6'b1111: outBus=outR15;
6'b10000: outBus=outR16;
6'b10001: outBus=outR17;
6'b10010: outBus=outR18;
6'b10011: outBus=outR19;
6'b10100: outBus=outR20;
6'b10101: outBus=outR21;
6'b10110: outBus=outR22;
6'b10111: outBus=outR23;
6'b11000: outBus=outR24;
6'b11001: outBus=outR25;
6'b11010: outBus=outR26;
6'b11011: outBus=outR27;
6'b11100: outBus=outR28;
6'b11101: outBus=outR29;
6'b11110: outBus=outR30;
6'b11111: outBus=outR31;
6'b100000: outBus=outR32;
6'b100001: outBus=outR33;
6'b100010: outBus=outR34;
6'b100011: outBus=outR35;
6'b100100: outBus=outR36;
6'b100101: outBus=outR37;
6'b100110: outBus=outR38;
6'b100111: outBus=outR39;
6'b101000: outBus=outR40;
6'b101001: outBus=outR41;
6'b101010: outBus=outR42;
6'b101011: outBus=outR43;
6'b101100: outBus=outR44;
6'b101101: outBus=outR45;
6'b101110: outBus=outR46;
6'b101111: outBus=outR47;
6'b110000: outBus=outR48;
6'b110001: outBus=outR49;

6'b110010:
6'b110011:
6'b110100:
6'b110101:
6'b110110:
6'b110111:
6'b111000:
6'b111001:
6'b111010:
6'b111011:
6'b111100:
6'b111101:
6'b111110:
6'b111111:

outBus=outR50;
outBus=outR51;
outBus=outR52;
outBus=outR53;
outBus=outR54;
outBus=outR55;
outBus=outR56;
outBus=outR57;
outBus=outR58;
outBus=outR59;
outBus=outR60;
outBus=outR61;
outBus=outR62;
outBus=outR63;

endcase
endmodule
module Data_Mem(input clk, input reset, input MemW, input [31:0] Address, input [31:0] WData, output [31:0] RData);
wire [63:0] decOut;
wire [31:0] Qout0, Qout1, Qout2, Qout3, Qout4, Qout5, Qout6, Qout7, Qout8, Qout9, Qout10, Qout11, Qout12, Qout13, Qout14,
Qout15, Qout16, Qout17, Qout18, Qout19, Qout20, Qout21, Qout22, Qout23, Qout24, Qout25, Qout26, Qout27, Qout28, Qout29, Qout30,
Qout31, Qout32, Qout33, Qout34, Qout35, Qout36, Qout37, Qout38, Qout39, Qout40, Qout41, Qout42, Qout43, Qout44, Qout45, Qout46,
Qout47, Qout48, Qout49, Qout50, Qout51, Qout52, Qout53, Qout54, Qout55, Qout56, Qout57, Qout58, Qout59, Qout60, Qout61, Qout62,
Qout63;
decoder6to64 decO(Address[5:0], decOut);
register_DM r0(clk,reset, MemW & decOut[0], 32'b0, WData, Qout0);
register_DM r1(clk,reset, MemW & decOut[1], 32'b0, WData, Qout1);
register_DM r2(clk,reset, MemW & decOut[2], 32'b0, WData, Qout2);
register_DM r3(clk,reset, MemW & decOut[3], 32'b0, WData, Qout3);
register_DM r4(clk,reset, MemW & decOut[4], 32'b0, WData, Qout4);
register_DM r5(clk,reset, MemW & decOut[5], 32'b0, WData, Qout5);
register_DM r6(clk,reset, MemW & decOut[6], 32'b0, WData, Qout6);
register_DM r7(clk,reset, MemW & decOut[7], 32'b0, WData, Qout7);
register_DM r8(clk,reset, MemW & decOut[8], 32'b0, WData, Qout8);
register_DM r9(clk,reset, MemW & decOut[9], 32'b0, WData, Qout9);
register_DM r10(clk,reset, MemW & decOut[10], 32'b0, WData, Qout10);
register_DM r11(clk,reset, MemW & decOut[11], 32'b0, WData, Qout11);
register_DM r12(clk,reset, MemW & decOut[12], 32'b0, WData, Qout12);
register_DM r13(clk,reset, MemW & decOut[13], 32'b0, WData, Qout13);
register_DM r14(clk,reset, MemW & decOut[14], 32'b0, WData, Qout14);
register_DM r15(clk,reset, MemW & decOut[15], 32'b0, WData, Qout15);
register_DM r16(clk,reset, MemW & decOut[16], 32'b0, WData, Qout16);
register_DM r17(clk,reset, MemW & decOut[17], 32'b0, WData, Qout17);
register_DM r18(clk,reset, MemW & decOut[18], 32'b0, WData, Qout18);
register_DM r19(clk,reset, MemW & decOut[19], 32'b0, WData, Qout19);

register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM
register_DM

r20(clk,reset,
r21(clk,reset,
r22(clk,reset,
r23(clk,reset,
r24(clk,reset,
r25(clk,reset,
r26(clk,reset,
r27(clk,reset,
r28(clk,reset,
r29(clk,reset,
r30(clk,reset,
r31(clk,reset,
r32(clk,reset,
r33(clk,reset,
r34(clk,reset,
r35(clk,reset,
r36(clk,reset,
r37(clk,reset,
r38(clk,reset,
r39(clk,reset,
r40(clk,reset,
r41(clk,reset,
r42(clk,reset,
r43(clk,reset,
r44(clk,reset,
r45(clk,reset,
r46(clk,reset,
r47(clk,reset,
r48(clk,reset,
r49(clk,reset,
r50(clk,reset,
r51(clk,reset,
r52(clk,reset,
r53(clk,reset,
r54(clk,reset,
r55(clk,reset,
r56(clk,reset,
r57(clk,reset,
r58(clk,reset,
r59(clk,reset,
r60(clk,reset,
r61(clk,reset,
r62(clk,reset,
r63(clk,reset,

MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW
MemW

&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&

decOut[20],
decOut[21],
decOut[22],
decOut[23],
decOut[24],
decOut[25],
decOut[26],
decOut[27],
decOut[28],
decOut[29],
decOut[30],
decOut[31],
decOut[32],
decOut[33],
decOut[34],
decOut[35],
decOut[36],
decOut[37],
decOut[38],
decOut[39],
decOut[40],
decOut[41],
decOut[42],
decOut[43],
decOut[44],
decOut[45],
decOut[46],
decOut[47],
decOut[48],
decOut[49],
decOut[50],
decOut[51],
decOut[52],
decOut[53],
decOut[54],
decOut[55],
decOut[56],
decOut[57],
decOut[58],
decOut[59],
decOut[60],
decOut[61],
decOut[62],
decOut[63],

32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,
32'b0,

WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,
WData,

Qout20);
Qout21);
Qout22);
Qout23);
Qout24);
Qout25);
Qout26);
Qout27);
Qout28);
Qout29);
Qout30);
Qout31);
Qout32);
Qout33);
Qout34);
Qout35);
Qout36);
Qout37);
Qout38);
Qout39);
Qout40);
Qout41);
Qout42);
Qout43);
Qout44);
Qout45);
Qout46);
Qout47);
Qout48);
Qout49);
Qout50);
Qout51);
Qout52);
Qout53);
Qout54);
Qout55);
Qout56);
Qout57);
Qout58);
Qout59);
Qout60);
Qout61);
Qout62);
Qout63);

mux64to1 mrd(Qout0, Qout1, Qout2, Qout3, Qout4,

Qout15, Qout16, Qout17, Qout18, Qout19, Qout20, Qout21,
Qout31, Qout32, Qout33, Qout34, Qout35, Qout36, Qout37,
Qout47, Qout48, Qout49, Qout50, Qout51, Qout52, Qout53,
Qout63, Address[5:0], RData);
endmodule

Qout5, Qout6, Qout7, Qout8, Qout9, Qout10, Qout11, Qout12, Qout13, Qout14,
Qout22, Qout23, Qout24, Qout25, Qout26, Qout27, Qout28, Qout29, Qout30,
Qout38, Qout39, Qout40, Qout41, Qout42, Qout43, Qout44, Qout45, Qout46,
Qout54, Qout55, Qout56, Qout57, Qout58, Qout59, Qout60, Qout61, Qout62,

module SingleCycle(input clk, input reset, output [31:0] Result);

wire RegWrite,RegDst,ALUSrc, Branch, MemWrite, MemToReg, Jump;
wire [2:0] ALUControl;
wire [31:0] PCin, PCout, Instr, SrcA, SrcB, RD2, ALUResult, ReadData,PCPlus4,ImmExt,ImmExt_shift,PCBranch,PCJump;
wire [31:0] pc_inter1;
wire [27:0] pc_inter2;
wire [4:0] WriteReg;
wire PCSrc;
wire ov,Zero;
PCReg pc(clk,reset,PCin,PCout);
IM instr(reset, PCout[7:2], Instr);
ctrlCkt ctrl(Instr[31:26],Instr[5:0],RegWrite,RegDst,ALUSrc, Branch, MemWrite, MemToReg, Jump,ALUControl);
regFile re(clk,reset,Instr[25:21],Instr[20:16],WriteReg, RegWrite, Result, SrcA, RD2);
ALU al(SrcA,SrcB,ALUControl,ov,Zero,ALUResult);
Data_Mem dmem(clk, reset, MemWrite, ALUResult, RD2, ReadData);
mux2to1 res(ALUResult, ReadData, MemToReg, Result);
mux2to1 bsrc(RD2, ImmExt, ALUSrc, SrcB);
mux2to1_5bit add3(Instr[20:16],Instr[15:11],RegDst, WriteReg);
adder pcadder(PCout,32'h4,PCPlus4);
SignExt ext(Instr[15:0],ImmExt);
assign ImmExt_shift=ImmExt<<2;
adder branchadd(ImmExt_shift,PCPlus4,PCBranch);
assign PCSrc=Branch & Zero;
mux2to1 p4orbrnch(PCPlus4,PCBranch,PCSrc,pc_inter1);
assign pc_inter2=Instr[25:0]<<2;
assign PCJump[27:0]=pc_inter2;
assign PCJump[31:28]=PCPlus4[31:28];
mux2to1 pcin(pc_inter1,PCJump,Jump,PCin);
endmodule

module SingleCycleTester;
reg clk;
reg reset;
wire [31:0] Result;
SingleCycle run(.clk(clk), .reset(reset), .Result(Result));
always
#20 clk=~clk;

initial
begin
clk=0; reset=1;
#73 reset=0;
end
endmodule

SIMULATION WAVEFORMS