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ASIC InterviewQuestions

The document discusses various topics related to SystemVerilog and UVM such as: 1. Configuring a virtual interface handle through the configuration database. 2. Writing constraints to randomize an address field to be a power of 2 and 4-byte aligned. 3. Instantiating an environment class in a test case. It provides example code snippets and answers to questions on these topics.

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Sandip Bhadani
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0% found this document useful (0 votes)
662 views

ASIC InterviewQuestions

The document discusses various topics related to SystemVerilog and UVM such as: 1. Configuring a virtual interface handle through the configuration database. 2. Writing constraints to randomize an address field to be a power of 2 and 4-byte aligned. 3. Instantiating an environment class in a test case. It provides example code snippets and answers to questions on these topics.

Uploaded by

Sandip Bhadani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1.Config_db:gettingandsettingvirtualinterfacehandlethoughconifg_db.

Ans:
uvm_config_db#(virtualpcie_monitor_phy_if)::set(this,phy_agent,pcie_monitor_phy_vif,
pcie_monitor_phy_vif_handle)
uvm_config_db#(virtualpcie_monitor_phy_if)::set(this,,pcie_monitor_phy_vif,
pcie_monitor_phy_vif_handle)

2.Writeconstrainttogetaddressfieldvalueforpowerof2,andalignedatboundaryof
4.data==address.
Ans:
(Didntgetwhatdoesdata==addresswanttoindicatehere,thoughIwillwriteansaspermyunderstanding)

randbit[31:0]addr
randinttemp[31:0]

constraintc_power_of_2{
addr[1:0]==2'b0//THiswillaligntheaddressatboundaryoffour.
temp.sum()==2'b01
foreach(temp[i]){
temp[i]==addr[i]
}
}

3.Instantiationofenvironmentclassintestcase.
Ans:
insv,
env=new()
env.build()
env.run()
orenv.start()whatevermethodwehavecreated

inuvm
env=my_env_class::type_id::create(env,this)

4.Establishingquestionbetweendriverandagent.
Ans:Driverhasportoftypeuvm_seq_item_pull_portandsequencerhasportoftype
uvm_seq_item_pull_export.Theyareconnectedinsideagent.Whenverdrivercallsget_next_itemmethodof
seq_item_pull_port,itultimatelycommandssequencertogenerateatransaction.

5.Implicitexecutionofsequencethroughconfigdb.
Ans:Everysubphaseofrun_phasecanhaveitsdefaultsequence.Defaultsequencecanbesetbyuser
withfollowingsyntax:
uvm_config_db#(uvm_object_wrapper)::set(this,path.to.sequencer.main_phase,default_sequence,
sequnce::type_id::get())

6.Drivercodetogetrequestandprocessrequest
.
seq_item_port.get_next_item(req)

item_done(rsp)
or

item_done()
seq_item_port.put_response(rsp)
or
rsp_port.write(rsp)

Coveragerelatedquestion:

Codecoverageandfunctionalcoverage.

Onecandidatewasasked:
Pleasefindthequestionsattachedherewith.questionswereaskedrelatedtothesetopicsandfurther
discussiononsame,likecrossquestioningonyourgivenanswer.

1)
Whatisfactory?
A:Factoryisusedtocreateobjectsbasedontypeorname.Forthattheuvm_componentsanduvm_objects
shouldberegisteredwithfactorysothatwheneverrequired,objectscanbecreatedusingfactory.
2)
whatdoes`uvm_component_does?
A:Registerstheclasswithfactoryandalsosamemacrocanbeutilizedtoimplementcopy/compare/printetc
defaultmethods.
3)
uvm_envhierarchy,whoisinstantiatedwhere?
A:
uvm_envcontainsuvm_agent,uvm_sequencer(virtualsequencers)
uvm_agentcontainsuvm_sequencer,uvm_driveranduvm_monitor

4)
howisdriver&sequencerconnected?
A:Alreadyansweredabove

5)
testplantoverifyasimplememorymodel?

6)
ifyouhaveatargetof100%coverage,whatwouldbeyourapproach?

Holesshouldbetargeted,basedonpriority,requiredtestsneedstobedebugged/developed,ifnot
present.

Exclusioncanbeusedtoeliminatelowprioritybinsandboostthecoveragenumber

Coveragemodelimplementationandsamplingmechanismshouldberecheckediftestisalready
presentforthemissingbin.

7)
whatiscodecoverage,explaintypesofcodecoverage?
A:CoverageofRTLcode,linecoverage,fsmcoverage(subtypes:statecoverageandtransitioncoverage),
togglecoverage

8)
whatdoesatypicaluvm_drivercontain?

Handletovirtualinterfacetobedriven

mechanismtodrivetheinterface(includingunpackingtransactionetcprocessesasperprotocol)

callbackimplementationtochangethetransactionthroughcallback

mechanismtoextracttheresponsefromthebus

mechanismtoprovideresponsetosequencer(anyoneoutof3methods)


9)
explainpolymorphism&whydoweneedit?
A:methodofsamenamescanhavedifferentfunctionalitybasedontheirimplementationindifferentclasses
ofsameheirarchy.weneeditsothatwecanoverridebaseclassmethodimplementationinanextended
classmethod.Itprovidesreusabilityofdesigns.

Asmallprojectwhere,linesofcodewasmissingandIamsupposedtofillthesame.
twoconstraintsindata_class,questionsrelatedtouvm_transaction_class,seq_item,etc
A:transactionclassisnotpreferredoverseq_itembecausesequencersdealinseq_itemtypeandnotin
uvm_Transactiontype.Sinceinanytb,seq_itemismostlyrequriedtoframethetransaction,
uvm_transactionbecomesobsolateanditisnotusedtoavoidunnecessarylevelofheirarcyintransactions.

connect_phasedriver&sequencerinagent
driver.seq_item_port.connect(sequencer.seq_item_export)
get_cfg_dbvirtualinterfaceinagent
instantiateenvintestcaseinuvm
filldrivercodefewlines.

Anothercandidatewasasked:
Subject:Re:UVMInterviewQuestions

11.Howcanyourandomizedynamicarraytogenerateuniquevalues.

randintd_arr[]
constraintc_dyn_arr{
d_arr.size()inside{[10:100]}
foreach(d_arr[i])
{
foreach(d_arr[j])
{
if(i!=j)d_arr[i]!=d_arr[j]
}
}
}

HerearetheUVMtestbenchinterviewquestions.
1. AskedquestionsaboutmyQualcommProject.Hespendgoodamountoftimehereasking
questions.
2. WhichSystemVerilogdatatypeyoucanusetogeneratesinewave.Answeris:Real
3. Howcanyourandomizerealdatatype.
a. Fractionandintgralpartscanberandomizedseparately.
randintfrac,inte
realr_num

constraintc_real{
fracinside{[10:100]}

inteinside{[30:300]}
}

functionpost_randomize()
r_num=inte+(frac/1000)//<<insteadoffixedvalueof1000,itcanalsobe
randomizedwithminvalueof1000tilllevelofdecimal
endfunction

b.
4. ExplainaboutUVMfactory.
5. Whatarethephasesoffactory.
Ans:uvm_factorydoesnthaveanyphase..ifitsaboutuvmsphasesthenwehavebuild,connect
etc.

6. LaterheaskedaboutquestionwhenIexplainedaboutfactory.
7. HowcanyoutakeanadvantageofPolymorphysm.
a. Overridingmethodsinextendedclasses.
8. Explainaboutfunctionalcoverage.Giveexamples
.
Ans:coverageofafeature,likeatypeoftransactionisfunctionalcoverage.
9. Whichproject/customeryouarecurrentlyworkingon.
Herearethe
PCIe
InterviewquestionsbyBroadcom.

PleaseletmeknowifyouwantmetodiscussANSWERSwiththeengineersneeded?

1. DoyouknowaboutDenaliPCIeVIP.
2. CanyouexplaindifferentlayersinPCIe.
3. DoyouknowwhatisMRRS.
Ans:MaxReadRequestSize,adeviceshouldnotsendareadrequestgreaterthanMRRS.Itis
introducedtocontrolthebandwidthoccupiedbyeachdevice.
4. LetssayEPwantstosenddatatoRC.EPwantstotransfer1KBytesofdatafromRC.But
RCsupportsonly256bytesoftransferatatime.Explainhowthistransferwillhappen.
Explaindifferentmajorfieldsaffectedduringthistransfer.
Ans:
EPsendsMrDpktwithLength=256,Addr=xyz
RCwillsplittheCPLandsendmin4CPLs.HereIwriteminbecausesplittingthecplrequiresRCto
complywitharulewhichsayssplittingcanbedoneatonlyaddresseswhicharenaturallyalignedmultiples
ofRCB(ReadCompletionBoundarywhcihcanbe64or128bytesforRC).withlengthofintermediate
packetshavingpayloadinmultiplesofRCB.
5. ExplainabovesamescenarioforReadtransaction.
Ans:aboveexamplewaswithreadonlybecauseepwantsdatafromRC,soithastoread.For
MemWrscenarioinstead,RCinitiateswritetransfertoEPwithmultipleMWrpacketsifMPSvalueisless
thantotalintendedpayload.
6. IftherearenotransfershappeningbetweentwoPCIedevices(sayRCandEP).Whatwill
beyourapproachtodebugthisissue.
Ans:Firstlinkshouldbechecked,thenDLLinkupshouldbecheckedandafterthatTLsBAR
registersshouldbecheckediftheyareproperlyconfiguredornot.

LetssayEPwantstoWritetoHostmemorywhichisconnectedtoRC.Everythingisfine
betweentwodevices,Linkisup.Onlytransferisnothappening.Whatdoyouthinkthe
problemwillbe?Howwillyoudebugthis?
Ans:BARmaynotbeconfiguredandifBARsareconfiguredproperlyaddressofTLPmightnotbe
fallinginsideRCsbarORitmightnotbefallingoutsideEPsBARs(Thesetwoconditionscanonlyroutethe
packetupstream,eitheraddressfallinginsideRCsBarORaddrfallingoutsidesenderdevicesownbar)
8. InParallelPCIeprotocol:therewassomeapproachlike..iRequestandiReady..Doyouknowifwe
havesomethingsimilartothatinPCIexpress?
9. Doyouknow"SlowControl"approach?
10. CanyouexplainCreditbasedflowcontrol?
Ans:Creditsareallocatedtoeachdevice.Theycannottransfermoredatathantheiravailable
credits.
11. WecurrentlyhavePCIeGen2VIPandtestcases..Doyouthinkwecanuseexistingtest
caseswhenwemovetoPCIeGen3?
Ans:
Yestheycanbeusedbutnewtestsneedstobedeveloped.
12. WhatarethingwewillhavetochangegoingfromPCIeGen2toPCIeGen3?
Ans:Phylayerneedstobechangedforfewthingslikeencodingmethod,scrambling,macneeds
changesasnewLTSSMstateofequalizationisintroducedinGen3,TLneedssomechangesforOBFF
msgsetc.
13. WhatisReplayBuffer?Explainhowitworks?
Ans:ReplaybufferstoresthetransmittedTLPanduponnotreceivingACKinstipulatedtimeOR
receivingNAKallthepacketsinReplaybufferforwhomACKisnotreceivedORNAKisreceivedare
retransmitted.Replaybuffercanbereplayed4timesmax.
14. DoyouknowwhatisASP?Explain..
Ans:DoyoumeanASPM?ItisActiveStatePowermanagement.Whichisoptionalfeature,if
enabledcanbeusedtoenterintolowpowerstatesaftersendingDLLPs.
15. HaveyouworkonLowpowerverificationside?
16. SincehowlongthatyouworkedonPCIelast?

Interviewer1:
1. Explainyourexperience.
2. WhatisyourrelevantexperienceinUVM.
3. ExplainthetestbenchingeneralinUVM.
4. HowDirverandSequencerisconnected.
Ans:Explainedinoneoftheabovequestions

5. HowSequencerandSequencescommunicate.

Ans:Whendrivercallsget_next_item,sequencercallsbodyofsequenceassociatedwithitatthat
time.
6. WhatarethephasesofOVM_DO.
Ans:explaininguvm_dobecauseIdontknowuvm_do.seq.randomize(),
seq.start(sequencer_handle)
7. Howtodoyoustartasequenceonaparticularsequencer.
Ans:seq.start(sequencer_handle),`uvm_do_on(seq,sequencer_handle)<<thiswillrandomizethe
sequencealso
8. Explainvirtualinterface.

7.

Ans:virtualinterfaceisahandle/pointertophysicalinterface.physicalinterfacecanbesynthesized
aspartofdesignwhilevirtualinterfacecannotbe.anditcanpointtoactualinterfaceandpointercanbe
changedruntimetoanotherphysicalinterfaceofsametype.
9. Whydowenotusephysicalinterfaceinsteadofvirtualinterface.
Ans:Testbenchusesclassesandclassesaredynamicdatatype(theygetcreatedanddestroyed
runtime)hencephysicalinterfacecannotbeusedinsideclassandweneedapointertophysicalinterface
whichisvirtualinterface.
10. Ifihavetomodifymyexistingdriverforsomeadditionalfunctionalityintheenvironment,howwillI
doit?Answeris:Factoryandthenaskedquestionsonfactory.
11. Howmonitorisconnectedwithothercomponents.answerisAnalysisport.
12. HowAnalysisportisdifferentthannormalportandexports.
Ans:itusesfunctionwhichcannotbeblocked(exitsatzerosimtime).therecanbeonetomany
connectionusinganalysisport.
13. Explainscoreboard.
Ans:Scoreboardcontainsqueuesoftransactionstobecompared.Dependinguponinorder
comparisonoroutofordercomparisonimplementation.Scoreboardcanhavethreechannels:Stimulus,
ExpectedandResponse.StimulusistakenfrommonitorattheinputofRTL,basedonStimulusqueue,
Expectedtransactionqueuesarecreatedandstored.MonitoratoutputinterfaceofRTLisstoredas
Response.Everytimestimulusqueueisupdated,EmulationmodeltakestheentryofStimulusqueueand
generatesExpectedtrasaction(predictsoutput).WHichiscomparedwhenOutputmonitordelivers
Responsetransaction.Transactionsareremovedeverytimeasuccessfulmatchhappens.Attheendof
simulation(incheckphaseamybe)allqueusarecheckedtobeempty.UponnonemptyqueueError
shouldbereported.
14. Shegaveoneexampleandaskedtobuildscoreboardforthesame.
followingarethesequenceoftransaction
Writewithaddr0
Writewithaddr1
Readwithadd0
Readwithaddr1
Onlyonemonitorisusedtocaptureallabovetransaction.Soinscoreboardhowwillyoumakesure
Writeofaddr0willbecomparedtoreadofaddr0only.
Sheaskedmostlyeverythingtoexplainonthewhiteboardwiththediagrams.

Interviewer2:

1. HowmuchhaveyouworkonUVMtestbenches.
2. Areyoucomfortablewithmodule,subsystemleveltestbenches?
3. Askedmetodrawentiretestbenchforsubsystemlevel.IdrewentiretestbenchstartingfromTest
plantoCodecoverageandfuntionalcoverageclosure.
VirtualsequencersandVirtualsequences.
Ans:Virtualsequencersarebasicallygenericsequencersandtheydontconnectthemselvestoanydriver
andhencedonotgenerateatransaction.Virtualsequencerscontroldifferentdatasequencers.Typicalcode
ofvirtualsequencercontainthehandlestodatasequencers.Sequencesrunningonvirtualsequencerscan
havehandlestodifferentdatasequencesanddatasequencersviap_sequencerhandle.Virtualsequence
caninitiatedifferentdatasequencesontheirrespectivedatasequencersandcontroleachofthem
individually.

PossibleBroadcomInterviewquestions

Followingarethequestionsthatwereaskedtooneofourengineers:

Thisroundwaskindofintroductionandprojectrelatedquerieslike,whatdidIworkon,whatwastestplan,
whatlanguage,scripting,etc.TherewasnotechnicalSV/UVMquestionsorPCIequestions.

2ndRound
1.Tellmeaboutyourself
2.WhatwouldyourateyourselfforUVMandSVoutof110ratings
3.PCIePHYLayerLTSSM,explainindetailwithSubstatedetails
4.WhatisuseofFTSsequence.
Ans:TogetoutofL0s,FTSistransmitted.NumberFTSOSdependsuponvalueofsymbol3ofTS1/2OS.
5.Why810bitencodingisrequired?
Toreducenumberofconsecutive1sand0sandhencetoavoidintersymbolinterference.
6.Howsynchronizationisdone?
7.
WhatislinkandlaneinPCIe?MaxLanenumbersupportedbyPCIe?
Ans:Link=numoflanes,32is
maxsupportedlanes
8.ExplainlastPCIeproject.Whatwasyourrole?
9.Whatkindoftestsyoudeveloped?
10.Whaterrorinjectionscenarios?
11.WhatistheroleofDataLinklayer?ExplainACK/NAKprotocol.
Ans:toolongtoexplainhereeverything.Inbrief:TLPswhenreachtoDLLofreceiverwithoutanyerror,
theyareACKedandifnotreceivedcorrectlyreceiverofTLPsendsNAK.IfTLPdoesntreachatallandlost
intransmissionline,theyareretransmittedfromtransmitteraftercertaintimeintervaliselapsed.
12.WhatwillbeseqnumberinACKpacketandNAKpacket?
Ans:LastgoodreceivedTLP.
13.HaveyouworkedonC++?WhatisdifferencebetweenC++andSVinrespecttomemory?
14.Example,explainwhatwillbeoutputandatwhatsimtime?
Clockisgeneratedforabout30timeunitsandposedgeis@5,15,25units
initialbegin
...
...

fork
@(posedgeclk)$display("Iamclk")

join
end
Ans:Iamclkwillbeprintedatthetimewhenforkiscalled(zerotimeifitiscalledatbeginingwithoutany
delay)andattheendofposedge,statementsafterjoinwillbeexecuted.
15.Inabovecode,explainsimulatorphases.Whichstatementwillbeexecutedinwhichregion?
16.Doesfork....joinblockanythingspecialonsimulatorphases?
17.DidyouworkonGatelevelsimulation?Whatkindofissuesobserved?Wasitincontrolpath/datapath?
18.WhatcausesXpropagationingatelevelsimulation?
19.WhatkindI2CandSPIprotocolyouworkedfor?WasitMaster/Slave?
20.WhatwereSPIinterfacesignals?


1.Tellaboutyourself.
2.Howfamiliarareyouinsystemveriloganduvm.
3.Explaintheuvmtestbench.
4
.Whatispolymorphism.
Ans:Explainedsomewhereabove
5
.Whatisqueueandmailboxanddifferencebetweenthem.
Ans:Queuehasdifferentmethodstosearchandgetetc,mailboxesdoesnthavesuchmechanism.Onecan
accessanylocationofqueue,contentsofmailboxesaremeanttobeaccessedinorder.Onecannotknow
thenumberoftransactionsinsidemailbox,whileonecaneasilyknowthesizeofqueue.Queuesarestatic
datatypes,mailboxarebasicallysvobjects,needstobecreatedusing=new()method.

2.round

1.Whatisavirtualinterfaceandwhatisaphysicalinterface.Whycantyoudirectlyconnectthe
interfaceassuchbyinstanstiainginthetoplevellikewriteitastop.tb.if??
Ans:Didntgetthequestionhere...
2.Fromwheredoesthesequencergetsthesequenceitem??Whogeneratesthisandhowisit
giventothesequencer.
whenasequenceisstartedonsequencer,apointertothesequenceiscontainedinsidesequencerandthe
seq_itemrelatedtothesequenceispushedintoafifo.Whendriverconnectedtothesequencercallsthe
get_next_itemofseq_item_port,sequencersqueueoftransactionischecked,ifqueueisempty,nullis
returnedanddriversexecutiongetshaltedatget_next_item.Ifthequeuehasanentry,itrandomizes
seq_itemandpassedtodriverandnowthestimulusreachestothedriver.
3.Whataredifferenttlmportshowaretheyimplemented??
get,put,tlm_Fifoetc.
4.Whattlmportisusedtoconnectbetweenamonitorandascoreboadandexplainhowitsdone.
Ans:analysisport.Writemethodisimplementedinsidescoreboardandaportisdeclaredinsidescoreboard.
thatportisconnectedtomonitorviaconnectmethodinsideconnect_phasefunction.
5.Whereexactlyistheinterfaceinstantiatedinagiventestbench.
Ans:Answeringaspermyunderstanding.InterfaceisinstantiatedinsidewrappermoduleofDUTwhich
connectsitssignalswithDUTsignalsanditispassedtoprogramblock(tbtop).tb_topandwrapperbothare
instantiatedinsidetopmodulecontainingclockgenerationmodule.
6.Isitrequiredtomanuallyconnecttheportsorisitreadilyavailableassuchinuvm.
Ans:Wehavetomanuallyconnectalltheports.Typesofportsarefixedfortheportsofdriversuchas
uvm_seq_pull_portwhichissameastypeoftransactionofdriver.Userdefinedportsneedstobeprovided
withtypeoftrnascation.
7.
Howdoudrivethestimulusfromthetestsandthenhowsitgiventothesequenceranddriver.
Ans:Testcasestartsthesequenceonasequencerhandlewhichmeansthesequencercannowprocessthe
sequenceeverytimeget_next_itemiscalledfromdriverconnectedtothatsequencer.Sincedrivers
executionishaltedatget_next_itemtillitgetsatransaction,sequenceruponstartcallgivesthe
sequence_itemgeneratedinsidethebodyofsequencetothedriverviauvm_seq_item_pull_port.
8.WhataredifferenttransfersinUSB2.0andwhatisthetransfersizeofaninterrupttransfer.
9.Howdoyouperformaninterrupttransferverification,explainwithatestcase.

1.Introduceyourself.

2.
WhatisRAL?
Ans:RALmeansRegisterAbstractionLayer.Whenthereisaregistermodeltobetested,equivalentRAL
modelisdevelopedintestbenchtocomparetheDUTsvalueswithexpectedvaluesandalsotoeasily
createreadingandwritingscenarios,RALcanbedeveloped.ItprovidesAPIattopabstractionlayerwhich
canbecalledinsidetestcasesandatlayerbelowRAL,sequencesortask/functionscanbecalledfor
reading/writing.RALgivesbetterunderstandabilityandfastertestingcapabilitybyprovidingAPIs.
3.Whatarethedifferentscenariosyouwritetoverifyregisterblock
?
Ans:Fromtestingperspectiveregistersaregroupedasperitsattributes(RO,RW,RW1C,ROC,RWS,ROS
etc).Firsttestshouldberesettestwhichcheckstheresetvaluesofregistersafterresetisapplied.Second
testingshoulddoneondifferentgroupsaspertheirattribute.likeROregistersshouldbecheckedthatafter
writingthemthroughbackdoor,theyarenotchangedandtheyremainasReadOnly.RW1Cshouldbe
checkedbywritingthroughbackdoorandthenreadingitcorrectlyandwriting1andreadingbacktocheckif
thevalueisclearedornot.etc.Therearemanysuchscenarios.
4.Whatexactlyyouverifyinwalking1sandwalking0stestwhileverifyingaregister?
Ans:
Walking1s:0to1and1to0successivetransitionsdoesntcorruptregister
walking0s:1to0and0to1successivetransitionsdoesntcorruptregister.
5.InterviewgaveadesignandaskedmetocreateatestbenchniUVM.
6.Variousquestionsaskedinthattestbench.
7.Whatisvirtualsequencerandvirtualsequence?
Ans:Explainedsomewhereabove
8.Whatisclockingblock?Whyitisused?
Ans:Clockingblockisusedtoalignanysignalwithaclockinsideinterfaceitself.Sothatwhoeveraccesses
thesignalthroughclockingblock,getsthesignalalignedtowhateverapplicableclockofclockingblock.
9.Haveyouworkedoncoverage?Haveyouworkedonassertions?

questionsasked.
1.Tellmeaboutyourself.
2.Whatarethemethodologiesyouused?
3.Tellmeaboutcreatingobjects.(inuvm)
Ans:handle=class_name::type_id::create(name)
4.Whatisafactory?
Ans:Explainedsomewhereabove
5.Whyfactoryneeded?
Ans:Explainedsomewhereabove
6.Haveyouworkedongatesim?
7.Whataretheissuesfacedingatesim?
8.HowgoodareyouindebugofARMprocessorissues?
9.Whataretheprotocolsyouknow?
10.
HowerrorhandlingdoneinAXI,AHBandAPB?
Ans:responsesignalisprovidedbyslavewhichsaysifitsanerrorrequestorOkayrequest.
11.Howgoodareyouinscripting?

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