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RTL Vs Technology Schematic

The RTL view shows a pre-optimized design using generic symbols like adders and gates, while the technology view shows an architecture-specific design optimized for the target device using technology-specific components like LUTs and I/O buffers. The technology view is preferred for viewing synthesized results as it reflects the optimized design. Disabling RTL schematic generation can speed up synthesis by setting the Generate RTL Schematic property to "No".

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vikramkolanu
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221 views1 page

RTL Vs Technology Schematic

The RTL view shows a pre-optimized design using generic symbols like adders and gates, while the technology view shows an architecture-specific design optimized for the target device using technology-specific components like LUTs and I/O buffers. The technology view is preferred for viewing synthesized results as it reflects the optimized design. Disabling RTL schematic generation can speed up synthesis by setting the Generate RTL Schematic property to "No".

Uploaded by

vikramkolanu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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Description

After XST synthesis is completed, I am able to view both RTL and technology sche
matic.I frequently observe discrepancies between these two schematics.
What is the difference between them?
Solution
RTL View
Viewing an RTL schematic opens an NGR file that can be viewed as a gate-level sc
hematic.
This schematic
ss. It shows a
mbols, such as
independent of

is generated after the HDL synthesis phase of the synthesis proce


representation of the pre-optimized design in terms of generic sy
adders, multipliers, counters, AND gates, and OR gates, that are
the targeted Xilinx device.

Technology View
Viewing a Technology schematic opens an NGC file that can be viewed as an archit
ecture-specific schematic.
This schematic is generated after the optimization and technology targeting phas
e of the synthesis process. It shows a representation of the design in terms of
logic elements optimized to the target Xilinx device or "technology"; for exampl
e, in terms of of LUTs, carry logic, I/O buffers, and other technology-specific
components. Viewing this schematic allows you to see a technology-level represen
tation of your HDL optimized for a specific Xilinx architecture, which might hel
p you discover design issues early in the design process.
You should always refer to technology schematic for synthesized result.
To disable RTL schematic generation to speed up synthesis, you can set XST prope
rty Generate RTL Schematic
(-rtlview) to "No".

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