INIC-1511 (Preliminary)

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INIC-1511
USB to PATA Bridge
Specification

Version 0.5
June 12, 2006
Initio Corporation

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Change History:

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Table of Contents

1. Introduction................................................................................................................................... 4
1.1
1.2
1.3

Feature Summary ...4

Firmware/Software Support...4
Devices Support.4

2. USB to ATA Block Diagram......................................................................................................... 5

3. Pin Signal Description: (48-pin package) ...................................................................................... 6
3.1 USB Interface.6
Serial Flash Interface.6
3.2
3.3 ATA Interface.6
3.4 System Interface.7
3.5 GPIO Interface...7
3.6 Power Regulator pins.7
3.7 Power/GND7
3.8 48 Pin Diagram8
4. NVRAM Program/Download procedure..........................9
4.1 CPU Write NVRAM .9
4.2 CPU Read NVRAM ..9
4.3 CPU Poll NVRAM.9
4.4 Host Read/Write 8051 data space from USB.9
4.5 NVRAM Download from USB10
5. Register Address Mapping.. ......................11
6. Register Descriptions.. 13
7. Electrical Information......................24

8. Packaging Specification...26

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INIC-1511 (Preliminary)

1.

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Introduction:

The INIC-1511 provides an advanced solution to connect ATAPI or EIDE devices to

USB interface with integrated CPU and embedded ROM. To provide a high performance
and cost effective solution, the INIC-1511 integrates USB-PHY, Mass Storage Class
Bulk-Only USB function, ATA control block and microprocessor into a single ASIC.
The INIC-1511 provides the data transfer rate of up to 60 MB/sec; its ATA interface
supports ultra DMA modes up to 100 MB/sec.
1.1

Feature Summary

1.2

USB Mass Storage Class Bulk-Only specification-compliant (version 1.0)

Two Bulk endpoints(IN and OUT) and one Interrupt endpoint(IN)
T13 1410D ATA/ATAPI-6 Compliant(3.3 V with 5V tolerance)
Support DMA mode 0-2, and UDMA mode 2, 3, 4 and 5 (up to 100MB/s)
Integrated internal CPU with embedded ROM
Implement the NVRAM download mechanism
Low power CMOS with 3.3Volts
48-pin LQFP package
Firmware/Software Support

1.3

USB Mass Storage Class Bulk-Only Transport support

Provide software utilities for downloading the upgraded NVRAM
Devices Support

Hard disk drives

CD-RW devices
DVDs
Removable media devices.

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2.

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USB to ATA Block Diagram:

Data FIFO

Data Flow Control

USB
PORT

Command/Status
Block

USB
PHY

ATA
DMA/
uDMA
Control
Block

Disk

Scratch SRAM
(2k Bytes)

USB
Core

Control Registers
Block

uP 8032

ROM
(12K Byte)

I2C
Interface

NVRAM
(2K bit)

Figure 1: INIC-1511 Block Diagram

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3. Pin Signal Description: (48-pin package)

3.1 USB Interface
Signal Name
DP

Pin Number
16

I/O
I/O

DM

17

I/O

RREF

14

Driver Type
USB high /full
speed buffer
(D+)
USB high/full
speed buffer
(D-)
Power

VBUS

13

PISW

XIN
XOUT

19
20

I
O

A
A

Pin Number
7

I/O
I/O

Driver Type
PBU4W

I/O

PBU4W

Description
High/Full speed D+ signal

High/Full speed D- signal

PLL voltage reference. Current source

for 330R(1%) resistor connected to
AVSS
Active HIGH. Indicates that VBUS is
present.
Crystal oscillator input (12MHz)
Crystal oscillator output (12MHz)

3.2 NVRAM Interface

Signal Name
I2C_SCL
I2C_SDA

Description
NVRAM Clock, or P3_3
Internal pullup
NVRAM Data., or P1_4
Internal pullup

3.3 ATA Interface (driving current 8mA-16mA controlled by Register 0x40A8[1:0])

Signal Name
ataD[15:0]

Pin Number
35, 37, 39, 41,
43, 45, 47, 1,
48, 46, 44, 42,
40, 38, 36, 34
27, 26, 25

I/O
I/O

Driver Type
PBSCUDSL

Description
ATA Data Bus

I/O

PBSCUDSL

ATA Device Address

I/O

PBSCUDSL

ATA Reset (Out)

ataCS[1:0]#

3, 2

I/O

PBSCUDSL

ATA Device Chip Select (Out)

ataDMARQ

33

I/O

PBSCUDSL

ATA DMA Request (In)

ataDMACK#

28

I/O

PBSCUDSL

ATA DMA Acknowledge (Out)

ataDA[2:0]
ataRST#

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ataDIOW#

32

I/O

PBSCUDSL

ATA I/O Write (Out)

ataDIOR#

30

I/O

PBSCUDSL

ATA I/O Read (Out)

ataIORDY

29

I/O

PBSCUDSL

ATA I/O ready (In)

ataINTR

I/O

PBSCUDSL

ATA Interrupt Request

Pin Number
12

I/O
I

Driver Type
PISW

11

PIDW

Description
Power On Reset. When this signal is
active, all of pins on ATA interface
should be tri-stated.
Test Mode Select. Default 0.
0-> Normal Operation Mode
1-> Test Mode

Pin Number
10

I/O
I/O

Driver Type
PBU4W

Description
uP8032 I/O port . Internal pullup

Pin Number

I/O

Driver Type

Description

23
24
22

I
I
O

Pin Number
9,31
6
15
18
21

I/O

3.4 System Interface

Signal Name
PORST#

TEST0

3.5 GPIO Interface

Signal Name
P1_0

3.6 Power Regulator pins

Signal Name
RV33I
RGND
RV18O

Internal regulator 3.3V input

Regulator ground
Internal regulator 1.8V output

3.7 Power/GND
Signal Name
VCC3
VSS3
VD33P
VS33P
VSSA

Driver Type

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Description
IO 3.3V
IO GND
3.3V, for VDD33P and VD33
USB IO Cell GND
VSSA for PLL

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3.8 48-Pin Diagram

a
t
a
D
0
7
|
4
8

a
t
a
D
0
9
|
4
7

a
t
a
D
0
6
|
4
6

a
t
a
D
1
0
|
4
5

a
t
a
D
0
5
|
4
4

a
t
a
D
1
1
|

a
t
a
D
0
4
|

4
3

4
2

a
t
a
D
1
2
|
4
1

a
t
a
D
0
3
|
4
0

a
t
a
D
1
3
|
3
9

a
t
a
D
0
2
|
3
8

a
t
a
D
1
4
|
3
7
36 --- ataD01

ataD08

--- 1

35 --- ataD15

ataCS0

--- 2

34 --- ataD00

ataCS1

--- 3

33 --- ataDMARQ

ataINTR

--- 4

32 --- ataDIOW#

ataRST#

--- 5

31 --- VCC3

VSS3

--- 6

30 --- ataDIOR#

I2C_SCL

--- 7

29 --- ataIORDY

I2C_SDA

--- 8

28 --- ataDMACK

VCC3

--- 9

27 --- ataA02

P1_0

--- 10

26 --- ataA01

TEST0

--- 11

25 --- ataA00

PORST#

-- 12

1
3

1
4

|
V
B
U
S

|
R
R
E
F

1
5
|
V
D
3
3
P

1
6
|
D
P

1
7
|
D
M

1
8
|
V
S
3
3
P

1
9
|
X
I
N

2
0

2
1

2
2

|
X
O
U
T

|
V
S
S
A

|
R
V
1
8
O

2
3
|
R
V
3
3
I

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2
4
|
R
G
N
D

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4. NVRAM Program/Download procedure

4.1 CPU Write NVRAM.
1. CPU write access address at register I2C_Addr(0x40E0).
2. CPU write data at register I2C_Data(0x40E1).
3. CPU write Control Code at register I2C_Ctrl(0x40E2).
4. CPU write Run and Read_Write direction(0) at register I2C_Comm(0x40E3).
5. CPU poll I2C_Comm bit 7, wait until cleared.
6. CPU may read register I2C_Status(0x40E4) to check write success or not.

4.2 CPU Read NVRAM.

1. CPU write access address at register I2C_Addr(0x40E0).
2. CPU write Control Code at register I2C_Ctrl(0x40E2).
3. CPU write Run and Read_Write direction(1) at register I2C_Comm(0x40E3).
4. CPU poll I2C_Comm bit 7, wait until cleared.
5. CPU read register I2C_Data(0x40E1).
6. CPU may read register I2C_Status(0x40E4) to check read success or not.

4.3 CPU Poll NVRAM.

After write data to NVRAM, NVRAM need certain time before next write operation can be
accepted. CPU may poll NVRAM to decide NVRAM ready or not. It is done same as a NVRAM read. If
I2C_Status(0x40E4) bit 0 is 1, the NVRAM not ready.

4.4 Host Read/Write 8051 data space from USB

1.
2.
3.

Host send READ_CHIP_ID packet through control channel to read chip-ID, which is
0x29C5_1511 here. Default hardware report PID is 0x1518.
Host send HOLD_CPU packet through control channel to set HOLD_CPU bit.
Host may send DATA_WRITE/DATA_READ packet through control channel to WRITE/READ
8051 data space.

DATA_WRITE setup packet format is,

offset
0
1
2
3
4
5
6
7

field
bmReqType
bReq
wValue

size
1
1
2

wIndex

wLength

value
0x40
0x81
Addr[7:0]
Addr[15:8]
Data[7:0]
0x00
0x00
0x00

Description
Vendor write
Data space write
Address to be writen

value
0xc0
0x82
Addr[7:0]
Addr[15:8]

data
Data from
Data space

Data space data

Dont care

DATA_READ setup packet format is,

offset
0
1
2
3

field
bmReqType
bReq
wValue

size
1
1
2

Description
Vendor read
Data read
Address to be writen

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4
5
6
7

wIndex

wLength

0x00
0x00
0x01
0x00

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Dont care
Dont care

READ_CHIP_ID setup packet format is:

Offset
0
1
2
3
4
5
6
7

Field
bmReqType
bReq
wValue

Size
1
1
2

wIndex

wLength

Value
0xc0
0x03
0x00
0x00
0x00
0x00
0x04
0x00

Data
Chip-ID
0x11,
0x15,
0xc9,
0x25

Value
0x40
0x04
0x00
0x00
0x00
0x00
0x00
0x00

Description
Vendor write
HOLD_CPU
Dont care

Description
Vendor read

Dont care
Dont care

HOLD_CPU setup packet format is:

Offset
0
1
2
3
4
5
6
7

Field
bmReqType
bReq
wValue

Size
1
1
2

wIndex

wLength

Dont care
Dont care
Dont care
Dont care

4.5 NVRAM Download from USB cable

The download utility may read/write NVRAM through access I2C registers similar as CPU does.
1.
2.

Host send READ_CHIP_ID packet through control channel to read chip-ID, which is
0x29C5_1511 here. Default hardware report PID is 0x1518.
Host send HOLD_CPU packet through control channel to set HOLD_CPU bit.

4.5.1 NVRAM Write.

3.
4.
5.
6.

Host send DATA_WRITE packet with wValue I2C_Addr(0x40E0) and wIndex[15:8] the
NVRAM address to be accessed
Host send DATA_WRITE packet with wValue I2C_Data(0x40E1) and wIndex[15:8] the value to
be write to NVRAM
Host send DATA_WRITE packet with wValue I2C_Ctrl(0x40E2) and wIndex[15:8] the Control
Code to be write to NVRAM
Host send DATA_WRITE packet with wValue I2C_Comm(0x40E3) and wIndex[15:8] the Run
bit[b7] and read/write direction 0 [b0]

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Host poll bit 7 of I2C_Comm(0x40E3) until this bit is cleared by sending DATA_READ packet
with wValue I2C_Comm(0x40BF)
Host send DATA_READ packet with wValue I2C_Status(0x40E4) to check write success or not

4.5.2 NVRAM Read.

9.
10.
11.
12.
13.
14.

Host send DATA_WRITE packet with wValue I2C_Addr(0x40E0) and wIndex[15:8] the
NVRAM address to be accessed
Host send DATA_WRITE packet with wValue I2C_Ctrl(0x40E2) and wIndex[15:8] the Control
Code to be write to NVRAM
Host send DATA_WRITE packet with wValue I2C_Comm(0x40E3) and wIndex[15:8] the Run
bit[b7] and read/write direction 1 [b0]
Host poll bit 7 of I2C_Comm(0x40E3) until this bit is cleared by sending DATA_READ packet
with wValue I2C_Comm(0x40E3)
Host send DATA_READ packet with wValue I2C_Data(0x40E1) to get the data from NVRAM.
Host send DATA_READ packet with wValue I2C_Status(0x40E4) to check write success or not

4.5.3 NVRAM Polling.

Same as NVRAM Read. If I2C_Status(0x40E4) bit 0 is 1, NVRAM not ready for next write.

5. Register Address Mapping:

5.1 USB Block (address area: 60xx)
Address
20h
21h
22h
25h
26h
30h
31h
32h
33h
34h
38-3F
40h
41h
50h
51h
52h
53h
60h
61h
70h
71h
72h
73h
74h
80h
81h
82h
83h

Read Value
Dev_Status
Funct_Adr
Test_mode
EpTxLength[7:0]
EpTxLength[15:8]
EP0_Status
EP0_Status
EP0_Status2
EP0_Status2
EP0TxLength
Hdr0-7
EP1_Status
EP1_Status
EP2_Status
EP2_Status
Usb_rxLength[7:0]
Usb_rxlength[15:8]
EP3_Status
EP3_Status
TotalCnt0
TotalCnt1
TotalCnt2
TotalCnt3
GTotalCnt0
GTotalCnt1
GTotalCnt2
GTotalCnt3

Write Value
Dev_Status
Funct_Adr
Test_mode
EpTxLength[7:0]
EpTxLength[15:8]
EP0_ Control (Set)
EP0_ Control (Clear)
EP0_ Control 2(Set)
EP0_ Control 2(Clear)
EP0TxLength
EP1_ Control (Set)
EP1_ Control (Clear)
EP2_ Control (Set)
EP2_ Control (Clear)
EP3_ Control (Set)
EP3_ Control (Clear)
TotalCnt0
TotalCnt1
TotalCnt2
TotalCnt3
LoadTotalCnt
GTotalCnt0
GTotalCnt1
GTotalCnt2
GTotalCnt3

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5.2 ATA Block: (address area: 40xx)

Address
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A2h
A3h
A4h
A5h
A6h
A8h
ACh
AFh
B0h
B1h
B4h
B5h
B6h
B7h
C0h,C2h-CEh
C1h,C3h-CFh
D6h
D7h
D8h
D9h
E0h
E1h
E2h
E3h
E4h
E8h
E9h
EAh
Note:

Read Value
Data[7:0]
Error
SectorCount
SectorNumber
CyclinderLow
CylinderHigh
Device/Head
Status
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AlternateStatus
Reserved
FIFO0D[7:0]
sgPCtl
FifoSt
gpioData
gpioCtl
TestCtl0
DrvCtl
upCtl
MiscCtl
LinkCtl
DmaCtl
sgDCtl
sgDCtl
AtaCtl
AtaStatus
RData[7:0]
RData[15:8]
ATA_Status_Hi
ATA_Status_Lo
UsbINT_En
UsbINT_Status
I2C_Addr[7:0]
I2C_Data
I2C_Ctrl
I2C_Comm
I2C_Status
OTB_Counter[7:0]
OTB_Ctrl[7:0]
OTB_INT_En

Write Value
Data[7:0]
Features
SectorCount
SectorNumber
CylinderLow
CylinderHigh
Device/Head
Command
Reserved
reserved
reserved
reserved
reserved
reserved
DeviceControl
reserved
FIFO0D[7:0]
sgPCtl
FifoSt
gpioData
gpioCtl
TestCtl0
DrvCtl
upCtl
MiscCtl (internal testing)
LinkCtl
DmaCtl
sgDCtl_Set
sgDCtl_Clr
AtaCtl
AtaStatus
WData[7:0]
WData[15:8]
ATA_Status_Hi
ATA_Status_Lo
UsbINT_En
UsbINT_Clr
I2C_Addr[7:0]
I2C_Data
I2C_Ctrl
I2C_Comm
OTB_Counter[7:0]
OTB_Ctrl[7:0]
OTB_INT_En

1. Every Read operation from any of 9Xh registers needs to be followed by another Read
operation on C0h.
2. Register C1h is used for accessing the high byte of 16-bit PIO data.

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5.3 CMD/DATA Block: (address area: 40xx)

Address
100h-13Fh (64 bytes)
140h-17Fh (64 bytes)
1C0h-1EFh (64 bytes)
240h-26Fh (64 bytes)
280h-2AFh (64 bytes)

Read Value
CmdRx0Buffer
CmdRx1Buffer
CmdTx1Buffer
CmdTx3Buffer
CmdTx4Buffer

Write Value
Can not be written by CPU
Can not be written by CPU
CmdTx1Buffer
CmdTx3Buffer
CmdTx4Buffer

5.4 DMA Block: (address area: 40xx)

Address
500h-53Fh

Read Value
sgList[3:0]

Write Value
sgList[3:0]

5.5 Data Space Mapping

Mapping Address
0000h-07FFh
4000h-47FFh
5000h-57FFh
6000h-60FFh

Type
Data
Data
Data
Data

Access Type
Read/Write
Read/Write
Read/Write
Read/Write

Mapping Block
Internal SRAM (2KB)
Internal Register/Buffers
SgBuffer (2KB)
USB registers

6. Register Descriptions:
The following are USB registers, based on 0x6000
6.1.1

Device Status (Dev_Status[7:0], 0x20)

Field name

rscu

bit #

reset
Description

RSVD

1b0

Reserved

Test_mode

rsu

1b0

Set when SET_FEATURE (TEST_MODE). Exit by cycle VBUS.

Attach

ru

1b1

Hardware reset default state. Clear if detect VBUS valid. Then set Power bit

Powered

ru

1b0

Set if VBUS=1 & previous state is Attach. Or, power interruption.

Suspend

ru

1b0

Default

ru

1b0

After bus IDLE for sometime, hardware set this bit. When RESUME detected,
hardware reset this bit and return to previous state
After bus reset, hardware set this bit.

Addressed

rscu

1b0

Set_Address or Set_Configuration(0)

Configured

rscu

1b0

Set_configuration

6.1.2

Function Address (Funct_Adr[7:0], 0x21)

Field name

rscu

bit #

reset
Description

RSVD

ru

1b0

Reserved

Adr

ru

6:0

7b0

Set_Address

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Test Mode (Test_mode[7:0], 0x22)

Field name

rscu

bit #

reset

RSVD

ru

7:4

4b0

Reserved

Test_mode

rwu

3:0

4b0

Test Mode Selectors(Table 9-7, USB2.0 spec)

4h1: Test_J
4h2: Test_K
4h4: Test_SE0_NAK
4h8: Test_Packet
others: RSVD

Description

6.1.4

End Point TX Data Length Low Bytes (Ep_TxLength[7:0], 0x25)

Field name

rscu

bit
#

reset

Ep_TxLength

rwu

7:0

8b0

6.1.5

Description
For EP1 (Bulk_IN): For ATA-Command-no-DMA-involved, this field
indicates how many bytes sent back to host. Maximum 512-bytes

End Point TX Data Length High Bytes (Ep_TxLength[15:8], 0x26)

Field name

rscu

bit
#

reset

RSVD

7:2

6b0

Reserved

Ep_TxLength

rwu

1:0

2b0

High bytes

6.1.6

Description

End Point 0 Status/Control (EP0_Status[7:0], 0x30: Set, 0x31: Clear)

Field name

rscu

bit
#

reset

Suspend_gnt

rsc

1b0

Description
Suspend-request granted

Usb_busRst

rcu

1b0

Set by hardware after an usb bus reset detected. Clear by firmware.

Bulk_only_Rst

rcu

1b0

RSVD

ru

4:3

2b0

Set by hardware, read and cleared by firmware after firmware responds

bulk-only-reset command done.
Reserved

EP0_speed

ru

1b0

1HS, 0--FS

Remote_wakeup

rscu

1b0

Set/Clr by firmware. Remote wakeup request.

Halt

rscu

1b0

1-EP0 halt. Function STALL. Device reset is require to clear this bit

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End Point 0 Status/Control2 (EP1_Status2[7:0], 0x32: Set, 0x33: Clear, BulkIN)

Field name

rscu

bit #

reset

FW_RDY

rsc

1b0

Description

RSVD

6:4

3b0

0: Default value as no firmware installed. Hardware response all control packet

for firmware download in most case.
1: Firmware controls some setup packet response.
Reserved

EP0_StatRun

rsu

1b0

Set by firmware if device ready to go to control status stage.

EP0_OUT

rcu

1b0

EP0_Run

rsu

1b0

EP0_Setup

rcu

1b0

Set by hardware if a control command-data is received. Clear by firmware after

processing.
Set by firmware. When firmware set this bit, the data will be transferred from
data buffer to USB. How many bytes transferred is based on the data transfer
length in the Ep_TxLength( 0x25, 0x26)
Set by hardware if a control command is received. Clear by firmware after
processing.

6.1.8

End Point TX Data Length Low Bytes (Ep0TxLength[7:0], 0x34)

Field name

rscu

bit
#

reset
Description

RSVD

1b0

Reserved

Ep0TxLength

rwu

6:0

7b0

For EP0 (Control): This field is filled by firmware. When firmware taking
control setup packet response, firmware write this field to inform hardware the
data length to be send back to host. Maximum 64-bytes.

6.1.9

Setup Packet (Hdr0Hdr7[7:0], 0x380x3F)

Field name

rscu

Hdr

ru

bit
#

reset

7:0

8bx

Description
8 bytes setup packet.

6.1.10 End Point 1 Status/Control (EP1_Status[7:0], 0x40: Set, 0x41: Clear, BulkIN)
Field name

rscu

bit #

reset
Description

GTotalCntEq
0
TotalCntEq0

Short_IN

1b0

1-> Ata Global TotalCnt equ 0

0-> else
1-> Ata TotalCnt equ 0
0-> else
1-> the last sent packet is a short packet. For bulk-in packet only

RSVD

1b0

Reserved

CSW_Run

rscu

1b0

RSVD

1b0

Set by firmware when firmware ready to send CSW. Clear by hardware after
CSW is sent successfully.
Reserved

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EP1_Run

rscu

1b0

Halt

rscu

1b0

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Set by firmware. When firmware set this bit, the data will be transferred from
data buffer to USB. How many bytes transferred is based on the data transfer
length in the Ep_TxLength( 0x25, 0x26)
1-EP1 halt.

6.1.11 End Point 2 Status/Control (EP2_Status[7:0], 0x50: Set, 0x51 Clear, BulkOUT)
Field name

rscu

bit #

reset
Description

FS_En

rw

1b0

1-> force device to Full Speed mode only

RSVD

1b0

Reserved

Short_OUT

1b0

1-> the last received packet is a short packet. For bulk-out packet only

RX_DONE

rsc

2b0

1->brdge received all data from host. Ready for CSW transmit. Auto-clear
after Rxed CBW
1-> bridge Rxed 2K bytes. Auto-clear after Rxed CBW

RX_2K

rsc

1b0

EP2_Rx

rcu

1b0

EP2_CBW

rcu

1b0

Set by hardware after the bulk out packet received. The number of total data
length received will be shown in Usb_rxLength register. This bit is used by
firmware to monitor the data transfer between USB and internal data buffer.
This bit is cleared by firmware or automatically cleared by hardware after the
next CBW received or sg0Run bit set by firmware.
Set by hardware if a valid CBW received. Clear after processing by firmware.

Halt

rscu

1b0

1-EP2 halt.

6.1.12 Usb_rxLength(usb_rxLength[7:0], 0x52, Bulk-OUT)

Field name

rscu

bit #

reset

rxLength

rwu

7:0

8b0

Description
The low byte of data length received. This register is used to show how many
date received from USB to internal data buffer.

6.1.13 Usb_rxLength(usb_rxLength[15:8], 0x53, Bulk-OUT)

Field name

rscu

bit #

reset

rxLength

rwu

7:0

8b0

Description
The high byte of data length received. This register is used by firmware to
show how many data received from USB to internal data buffer.

6.1.14 End Point 3 Status/Control (EP3_Status[7:0], 0x60: Set, 0x61: Clear, INTRIN)
Field name

rscu

bit #

reset

RSVD

7:3

5b0

EP3_run

rsu

1b0

1packet ready. Cleared by hardware after Tx completed

RSVD

1b0

Reserved

Description
Reserved

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INIC-1511 (Preliminary)
Halt

rscu

1b0

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1-EP3 halt.

6.1.15 End Point TX Data Length Low Bytes (Ep3TxLength[7:0], 0x62)

Field name

rscu

bit
#

reset

RSVD

1b0

Reserved

Ep3TxLength

rwu

6:0

7b0

For EP3 (INT_IN): This field is filled by firmware. Firmware writes this field
to inform hardware the data length to be sent back to host. Maximum 64bytes.

Description

6.1.16 Total Count0 (TotalCnt[7:0], 0x70 TotalCnt0)

Field name

rscu

bit #

reset

TotalCnt0

rwu

7-0

8b0

Description
TotalCnt[7:0]

6.1.17 Total Count1 (TotalCnt[15:8], 0x71 TotalCnt1)

Field name

rscu

bit #

reset
Description

TotalCnt1

rwu

7-0

8b0

TotalCnt[15:8]

6.1.18 Total Count2 (TotalCnt[23:16], 0x72 TotalCnt2)

Field name

rscu

bit #

reset
Description

TotalCnt2

rwu

7-0

8b0

TotalCnt[23:16]

6.1.19 Total Count3 (TotalCnt[31:24], 0x73 TotalCnt3)

Field name

rscu

bit #

reset

TotalCnt3

rwu

7-0

8b0

Description
TotalCnt[31:24]

6.1.20 Load Total Count (Load TotalCnt, 0x74)

Field name

rscu

bit #

reset
Description

Reserved

7-1

7b0

Reserved

LoadTotalCnt

1b0

Write an 1 to this bit will re-load the value from register 0x73-0x70s
TotalCnt[31:0] to internal counter.

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6.1.21 Global Total Count0 (GTotalCnt[7:0], 0x80 GTotalCnt0)

Field name

rscu

bit #

reset
Description

GTotalCnt0

rwu

7-0

8b0

GTotalCnt[7:0]

6.1.22 Global Total Count1 (GTotalCnt[15:8], 0x81 GTotalCnt1)

Field name

rscu

bit #

reset
Description

GTotalCnt1

rwu

7-0

8b0

GTotalCnt[15:8]

6.1.23 Global Total Count2 (GTotalCnt[23:16], 0x82 GTotalCnt2)

Field name

rscu

bit #

reset

GTotalCnt2

rwu

7-0

8b0

Description
GTotalCnt[23:16]

6.1.24 Global Total Count3 (GTotalCnt[31:24], 0x83 GTotalCnt3)

Field name

rscu

bit #

reset

GTotalCnt3

rwu

7-0

8b0

Description
GTotalCnt[31:24]

The following are general registers, and are in address area: 40XX
6.2.1

FIFO 0 Data Register (FIFO0D[7:0], 0x0A0)

Field name

rscu

bit #

reset
Description

Fifo0Data

6.2.2

rw

7:0

8h0

DMA FIFO 0 Data register. Software can access DMA FIFO 0 through this
register.

sgPioCmd Control Register (sgPCtl, 0x0A2)

Field name

rscu

bit #

reset
Description

Reserved
Pio0Run

6.2.3

r
rw

7-1
0

6b0
1b0

Reserved.
After set. Before set this bit, the firmware needs to disable AtaDMAEn bit on
DMA Control register, write the package header into the segment of sgCMD
buffer, set RUN bit on sgCMD Control register, and fill data into FIFO data
register.

FIFO Status Register (FifoST, 0x0A3)

Field name
Reserved
Fifo0Rst

rscu
r
rw

bit #
7-1
0

reset
6b0
1b0

Description
Reserved.
DMA FIFO 0 Reset. This bit is used to reset DMA FIFO 0. This bit is selfcleared by hardware after set.

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INIC-1511 (Preliminary)
6.2.4

GPIO Data Register (gpioDATA, 0x0A4)

Field name
VBUS
AtaRST0#
GPIOD[5:0]

6.2.5

bit #
7
6
5-0

reset
1b0
1b1
6h0

rscu
rw
r
rw

bit #
7
6
5-0

reset
1b0
1b0
6h0

rscu
rw
rw
r

bit #
7
6:4
3:0

reset
1b0
3b0
4h0

Description
GPIO mode enable.
Reserved.
General Purpose I/O Control 5-0. When set, the GPIO data is output.

Description
Ata request reset. When set, it will reset the current Ata request.
Reserved.
Revision ID. These 4 bits are read only.

ATA I/O Cell Driving Control Register (DrvCtl, 0x0A8)

Field name
CFEn

rscu
rw

bit #
7

reset
1b0

CFReq

rw

1b0

Reserved
AtaTSEn

r
rw

5-3
2

4h0
1b0

DrvSel

rw

1-0

2h3

6.2.8

Description
Read: USBs VBUS status
ATA channel 0 reset signal. When clear, it will reset the ATA device.
Write: GPIOOut[5:0], Read: GPIOIn[5:0]

Test Control 0 Register (TestCtl0, 0x0A6)

Field name
RstAtareq_
Reserved
RevID

6.2.7

rscu
r
w
rw

GPIO Control Register (gpioCtl, 0x0A5)

Field name
GPIOEn
Reserved
GPIOCtl[5:0]

6.2.6

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Description
Compact Flash Mode Enable. When set, the ATA engine will run in pseudo
DMA mode enabling fast compact flash access.
Compact Flash Request. When set, it indicates to the ATA engine that
compact flash has requested data transfer.
Reserved.
ATA Bus Tristate Enable. Clear this bit to 0 will put the INI1430 ATA bus in
tristate mode.
ATA Output Driving:
00:
8 mA
01:
10 mA
10:
12 mA
11:
16 mA

uP Control Register (upCtl, 0x0AC)

Field name
Reserved
usbWakeupEn
Reserved

6.2.9

rscu
r
rw
r

bit #
7-2
1
0

reset
6b0
1b0
1b0

Description
Reserved.
1-> enable external interrupt wake up host
Reserved.

MiscCtl register (0x0AF)

Field name

rscu

bit #

reset

Description

Reserved

rw

1b0

Reserved.

NewMode

rw

1b0

Set_usbClkEn
Enum
HidEn

rw
rw
rw

5
4
3

1b0
1b1
1b0

0: inic1530 mode
1: enhance mode
1: usb clock free run
0: disconnect device from usb host
0: endp will be IN(1)OUT(2)INTR(3)
1: endp will be IN(8)OUT(2)INTR(1)

Reserved

rw

3b0

Reserved.

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INIC-1511 (Preliminary)
OUT_ABORT_En
CSW_ACK_En

rw
rw

1
0

1b0
1b0

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1->wait all data sent from host done.

1-> Fw dont have to do the following things after CSW sent,
* write totalCnt to 0
*set Flush

6.2.10 sgCmd Definition

31 30 29 28

27 26 25 24

23 22 21 20 19 18 17 16

sgList[3-0]

L. Mo
seg re

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

dir
Reserved

Reserved
Reserved

Reserved

dataLength
Figure 2: sgCmd format

Field name

width

quadlet

Bit #

Description

L. seg

21

More

20

Dir

19

If the command is the last one of S/G segments, this bit should be
set by firmware.
If the number of commands in SgCmd buffer is more than one, this
bit should be set by firmware.
When 0, the DMA data are transferred from P1394 bus to ATA
device.
When 1, the DMA data are transferred from ATA device to P1394
bus.

6.2.11 Link Control Register (linkCtl, 0x0B0)

Field name

rscu

bit #

reset

Reserved

7-2

6b0

HW_RESET

1b0

softReset

rwu

1b0

Description
Reserved.
1->Reset whole chip. Function same as RC_RESET pin. Auto clear by
hardware.
When set to 1, all Host Controller state is reset, all FIFOs are flushed, and
Host Controller registers is reset.
The read value of this bit is 1 while a soft reset or hard reset is in progress.
The read value of this bit is 1 when neither soft reset nor hard reset is in
progress. Software can use the value of his bit to determine when a reset has
completed and the Host Controller is safe to operate.

6.2.12 DMA Control register (DmaCtl, 0x0B1)

Field name
Reserved
DIOW#

rscu
r
rw

bit #
7-4
3

reset
1h0
1b1

DIOR#

rw

1b1

DMACK#

rw

1b1

Flush/Abort

rw

1b0

Description
Reserved.
When DMA FIFO is underrun, this bit is used by firmware to toggle
DIOW# signal.
When DMA FIFO is underrun, this bit is used by firmware to toggle
DIOR# signal.
When DMA FIFO is underrun, this bit is used by firmware to toggle
DMACK# signal.
When DMA FIFO is overrun, this bit is used by firmware to flush data

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out for outgoing data or abort the DMA operation for incoming data.
This bit is self-cleared by hardware.

6.2.13 Channel Clear Register (cmdCtl_Clr, 0x0B3)

Field name
Reserved
CmdTx4Run
(for HID_out)
CmdTx3Run
(for CSW_out)
Reserved
CmdTx1Run
(for Control_out)
Reserved
CmdTx1Run
(for CBW)
CmdTx1Run
(for Setup-Packet)

rscu
r
rwu

bit #
7
6

reset
7b0
1b0

rwu

1b0

r
rwu

4
3

1b0
1b0

r
rwu

2
1

1b0
1b0

rwu

1b0

Description
Reserved
When the Clear register is set by software, the corresponding channel is
cleared.
When the Clear register is set by software, the corresponding channel is
cleared.
Reserved
When the Clear register is set by software, the corresponding channel is
cleared.
Reserved
When the Clear register is set by software, the corresponding channel is
cleared.
When the Clear register is set by software, the corresponding channel is
cleared.

6.2.14 sgDma Control Register (sgCtl_Set, 0x0B4) (sgCtl_Clr, 0x0B5)

Field name
Reserved

rscu
r

bit #
7:1

reset
7b0

Description
Reserved.

Sg0Run

rwu

1b0

When Set register is set by software, the corresponding channel is ready to

be transmitted. The hardware clears these bits when the transfer is completed.
Software can set bit[3:0] on Clear register to clear the corresponding bit.
When Clear register is written by software, the DMA channels will be reset to
idle. (USB bulk transfer will only use sg0Run)

6.2.15 ATA Control register (AtaCtl, 0x0B6)

Field name
AtaDMAEn
pioReq/pioGnt
dmaMode

pioMode

rscu
rw
rw
rw
rw
rw
rw
rw
rwu

bit #
7
6
5
4
3
2
1
0

reset
1b1
1b0
1b0
1b0
1b0
1b0
1b0
1b0

Description
When 1, ataDMA is enabled.
Write 1 for PIO request. PIO grant status when read.
0-2: DMA mode 0 - 2
4-7: UDMA mode 2, 3, 4 and 5 (up to uDMA100)
0-4: PIO mode 0-4

6.2.16 ATA Control/Status register (ataStatus, 0x0B7)

Field name
Reserved

rscu
r

bit #
7

reset
1b0

AtaCh0En

rw

1b0

PioXEn

rw

1b0

Description
Reserved
Ata Channel Enable.
PIO transfer engine enable. When set, the PIO engine will transfer data
to/from the ATA bus using PIO transfer mechanism.

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INIC-1511 (Preliminary)
Reserved

AtaIORDY0
Reserved

AtaINTRQ0

r
ru
r
ru

4:3
2
1
0

2b0

1bx
1b0
1bx

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Reserved.
Ata channel IORDY line.
Reserved
Ata channel INTRQ line.

6.2.17 ATA_Status_Low Register (0x0D6)

Field name

rscu

bit
#

reset

Description

ATA_Status[7:0]

rw

7-0

8h0

CPU writes the ATA status to this register

6.2.18 ATA_Status_High Register (0x0D7)

Field name

rscu

bit
#

reset

Description

ATA_Status[15:8]

rw

7-0

8h0

CPU writes the ATA status to this register

6.2.19 usb_INT_Enable Register (0x0D8)

Field name

rscu

Usb_busRst_INT_En rw
Usb_bulkOnlyRst_IN rw
Usb_Ep0Req_INT_E rw
Usb_CBW_INT_En rw
Usb_wakeup_INT_E rw
Usb_suspendINT_En rw
VBUS_P__INT_En rw
VBUS_N__INT_En rw

bit
#

reset

Description

7
6
5
4
3
2
1
0

1b0
1b0
1b0
1b0
1b0
1b0
1b0
1b0

1: Enable Usb_busRst to trigger sysINT.

1: Enable Usb_bulkOnlyRst to trigger sysINT.
1: Enable Usb_ Ep0Req to trigger sysINT.
1: Enable Usb_CBW to trigger sysINT.
1: Enable Usb_wakeup to trigger sysINT.
1: Enable Usb_suspend to trigger sysINT.
1: Enable positive of VBUS to trigger sysINT.
1: Enable negative of VBUS to trigger sysINT.

6.2.20 usb_INT_Status/Clear Register (0x0D9)

Field name

rscu

bit
#

reset

Description

Usb_busRst

rw

1b0

Usb_bulkOnlyRst

rw

1b0

Usb_Ep0Req

rw

1b0

Usb_CBW

rw

1b0

Usb_wakeup

rw

1b0

Usb_suspend

rw

1b0

VBUS_P__INT

rw

1b0

VBUS_N__INT

rw

1b0

Read: 1: indicates this interrupt event occurred

Write 1: will clear this status bit
Read: 1: indicates this interrupt event occurred
Write 1: will clear this status bit.
Read: 1: indicates this interrupt event occurred
Write 1: will clear this status bit
Read: 1: indicates this interrupt event occurred
Write 1: will clear this status bit
Read: 1: indicates this interrupt event occurred
Write 1: will clear this status bit
Read: 1: indicates this interrupt event occurred
Write 1: will clear this status bit
Read: 1: indicates this interrupt event occurred
Write 1: will clear this status bit
Read: 1: indicates this interrupt event occurred
Write 1: will clear this status bit

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6.2.21 I2C_Addr Register (0x0E0)

Field name

rscu

bit
#

reset

Description

I2C_Addr

rw

7-0

8h0

CPU writes the to-be executed NVRAM address to this

register.

6.2.22 I2C_Data Register (0x0E1) (I2C Data port)

Field name

rscu

bit
#

reset

Description

I2C_Data

rw

7-0

8h0

This is the data port for CPU to access NVRAM

A: To Write to NVRAM:
CPU Writes a 8-bit data to this port, Hardware will send
this data to NVRAM
B: To Read from NVRAM:
CPU reads this port to get data from NVRAM

6.2.23 I2C_Ctrl Register (0x0E2) (I2C Control Code)

Field name

rscu

bit
#

reset

Description

Reserved
Control_Code
Block_Select

w
rw
rw

7
6:3
2:0

1b0
4b0

reserved
Control Code
I2C device block select bits

3b0

6.2.24 I2C_COMM Register (0x0E3)

Field name

rscu

bit
#

reset

Description

I2C_TX_START

rw

1b0

reserved
Rd_nWr

rw
wr

6:1
0

6b0
1b0

1-> Hardware start to Read/Write NVRAM. Clear by

hardware when finished.
reserved
0-> write to NVRAM
1-> read data from NVRAM

6.2.25 I2C_Status Register (0x0E4)

Field name

rscu

bit
#

reset

Description

reserved
Data_Ack

rw
r

7-3
0

5b0
1b0

Addr_Ack

1b0

Ctrl_Ack

1b0

reserved
0-> NVRAM ACK with Data write phase
1->NVRAM NACK with Data write phase
0-> NVRAM ACK with Address write phase
1->NVRAM NACK with Address write phase
0-> NVRAM ACK with Contrl Code write phase
1->NVRAM NACK with Contrl Code write phase

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6.2.26 OTB_Counter Register (0x0E8)

Field name

rscu

bit
#

reset

Description

OTB_Counter

rw

7:0

8b0

How many push-release done. Clear after FW read.

6.2.27 OTB_Ctrl Register (0x0E9)

Field name

rscu

bit
#

reset

Description

P1_4_OTB_en

rw

7:6

2b0

reserved
Debouncing time

rw
rw

6:3
1:0

5b0
2b0

00->I2C mode
01->OTB mode
1x->I2C_SCL as P3_3, I2C_SDA as P1_4
reserved
2b00-> 36ms
2b01->72ms
2b10->108ms
2b11->144ms

6.2.28 OTB_INT_Enable Register (0x0EA)

Field name

rscu

bit
#

reset

Description

OTB_Counter_INTE
OTB_pos_INTE
OTB_neg_INTE
reserved

rw
rw
rw
rw

7
6
5
4:0

1b0
1b0
1b0

1: Enable OTB_Counter<>0 trigger sysINT.

1: Enable button RELEASE trigger sysINT
1: Enable button PUSH trigger sysINT
reserved

5b0

7.

Electrical Information:

7.1

Absolute Maximum Ratings

Symbol
Vcc
Vin
Vout
Tstg

7.2

Parameter
Power Supply
Input Voltage
Output Voltage
Storage Temperature

Min
-0.3
-0.3
-0.3
-55

Max
3.6
Vcc+0.3
Vcc+0.3
150

Units
V
V
V
C

Recommended Operating Conditions

Symbol
Vcc
Vin
Tj

Parameter
Power Supply
Input Voltage
Commercial Junction Operating Temperature
Industrial Junction Operation Temperature

Min
3.0
0
0
-40

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Typ
3.3
25
25

Max
3.6
Vcc
115
125

Units
V
V
C
C

24

INIC-1511 (Preliminary)

7.3

www.DataSheet4U.com

General DC Characteristics

Symbol
Iil
Ioz
Cin
Cout
Cbid

7.4

Parameter
Input Leakage Current
Tristate Leakage Current
Input Capacitance
Output Capacitance
Bi-directional Buffer Capacitance

Min
-1
-1

Typ

Max
1
1
4.9
4.9

Units
A
A
pF
pF
pF

Max
0.3*Vcc
0.3*Vcc

Units
V
V

2.8
2.7
2.7

DC Electrical Characteristics for 3.3V Operation

(Under Vcc=3.0-3.6V, Tj=0-115C)

Symbol
Vil

Vih

Vol
Voh
Ri
Icc

Parameter
Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage
Input Pullup/pulldown Resistance
Operating Supply Current

Conditions
CMOS
CMOS Schmitt
Trigger
CMOS
CMOS Schmitt
Trigger
Ioh-2-24mA
Ioh=2-24mA
Vil=0/Vih=Vcc
Vcc=3.3V

Min

Typ
1.20

0.7*Vcc

V
V

2.10
0.4
2.4

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75
40

60

V
V
k
mA

25

8. Packaging Specification
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4
A3
2005.09.06

LQFP48 (7x7mm)
PACKAGE OUTLINE
Footprint 2.0mm
10 : 1
1 OF 1