TISP820xHDM Overvoltage Protectors

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*R

oH

CO

PL

IA

NT

TISP8200HDM BUFFERED P-GATE SCR DUAL


TISP8201HDM BUFFERED N-GATE SCR DUAL
COMPLEMENTARY BUFFERED-GATE SCRS
FOR DUAL POLARITY SLIC OVERVOLTAGE PROTECTION

TISP820xHDM Overvoltage Protectors


High Performance Protection for SLICs with +ve & -ve
Battery Supplies

TISP8200HDM 8-SOIC (210 mil) Package (Top View)


(Tip)

TISP8200HDM Negative Overvoltage Protector


Wide -20 to -110 V Programming Range
Low +15 mA Max. Gate Triggering Current
High -150 mA Min. Holding Current

K1 (Tip)

(Ground)

NC

(Ground)

(Ring) K2

K2 (Ring)

K1

(-V(BAT)) G

TISP8201HDM Positive Overvoltage Protector


Wide +20 to +110 V Programming Range
Low -15 mA Max. Gate Triggering Current
+20 mA Min. Holding Current

NC - No internal connection
Terminal typical application names shown in parenthesis
MD-8SOIC(210)-007-a

Rated for International Surge Wave Shapes

TISP8200HDM Device Symbol


K1

IPPSM

Wave Shape

Standard

2/10

GR-1089-CORE

500

10/700

ITU-T K.20/21/45

150

10/1000

GR-1089-CORE

100

K1

A
G
A

..................................................UL Recognized Component

Circuit Application Diagram

K2

SLIC
PROTECTION

K2

SD-TISP8-001-a

TISP8201HDM 8-SOIC (210 mil) Package (Top View)

Tip

(Tip)
C2
220 nF

A1

(+V(BAT)) G

(Ring)
C1
220 nF

A1 (Tip)

(Ground)

NC

(Ground)

A2

A2 (Ring)

NC - No internal connection
Terminal typical application names shown in parenthesis
MD-8SOIC(210)-008-a

TISP8201HDM Device Symbol

Ring
TISP8200HDM TISP8201HDM

A1

+V BAT

A1

- VBAT
AI-TISP8-002-b

K
G
K

*RoHS Directive 2002/95/EC Jan 27 2003 including Annex


OCTOBER 2005 REVISED MAY 2007
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.

A2

A2

SD-TISP8-002-a

TISP820xHDM Overvoltage Protectors


Description
The TISP8200HDM/TISP8201HDM combination has been designed to protect dual polarity supply rail monolithic SLICs (Subscriber Line
Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. Protection against negative
overvoltages is given by the TISP8200HDM. Protection against positive overvoltages is given by the TISP8201HDM. Both parts are in 8-SOIC
(210 mil) surface mount packages.
The TISP8200HDM has an array of two buffered P-gate SCRs with a common anode connection. Each SCR cathode and gate has a separate
terminal connection. The NPN buffer transistors reduce the gate supply current. In use, the cathodes of the TISP8200HDM SCRs are connected
to the two conductors of the POTS line. The gates are connected to the appropriate negative voltage battery feed of the SLIC driving the line
conductor pair, so that the TISP8200HDM protection voltage tracks the SLIC negative supply voltage. The anode of the TISP8200HDM is
connected to the SLIC common. Negative overvoltages are initially clipped close to the SLIC negative supply by emitter follower action of the
NPN buffer transistor. If sufficient clipping current flows, the SCR will regenerate and switch into a low voltage on-state condition. As the
overvoltage subsides the high holding current of the SCR helps prevent d.c. latchup.
The TISP8201HDM has an array of two buffered N-gate SCRs with a common cathode connection. Each SCR anode and gate has a separate
terminal connection. The PNP buffer transistors reduce the gate supply current. In use, the anodes of the TISP8201HDM SCRs are connected
to the two conductors of the POTS line. The gates are connected to the appropriate positive voltage battery feed of the SLIC driving that line
pair, so that the TISP8201HDM protection voltage tracks the SLIC positive supply voltage. The cathode of the TISP8201HDM is connected to
the SLIC common. Positive overvoltages are initially clipped close to the SLIC positive supply by emitter follower action of the PNP buffer
transistor. If sufficient clipping current flows the SCR will regenerate and switch into a low voltage on-state condition. As the overvoltage subsides the SLIC pulls the conductor voltage down to its normal negative value and this commutates the conducting SCR into a reverse biased
condition.

How to Order
Device
TISP8200HDM
TISP8201HDM

Package
8-SOIC (210 mil)

Order As

Marking Code

TISP8200HDMR-S

8200H

TISP8201HDMR-S

8201 H

Carrier
Embossed Tape Reeled

Standard Quantity
2000

TISP8200HDM Absolute Maximum Ratings, TA = 25 C (Unless Otherwise Noted)


Sy mbol

Value

U nit

Repetitive peak off-state voltage, VGK = 0

R at i n g

VDRM

-120

Repetitive peak reverse voltage, VGA = -70 V

VRRM

120

IPPSM

-500
-150
-100

ITSM

60
14
7
3.5

TJ

-55 to +150

Tstg

-65 to +150

Non-repetitive peak impulse current (see Notes 1, 2 and 3)


2/10 s (Telcordia GR-1089-CORE, 2/10 s voltage wave shape)
5/310 s (ITU-T K.44, 10/700 s voltage wave shape used in K.20/21/45)
10/1000 s (Telcordia GR-1089-CORE, 10/1000 s voltage wave shape)
Non-repetitive peak on-state current, 50/60 Hz (see Notes 1, 2, 3 and 4)
10 ms
1s
7s
900 s
Junction temperature
Storage temperature range

NOTES: 1. Initially the device must be in thermal equilibrium with TJ = 25 C. The surge may be repeated after the device returns to its initial
conditions.
2. These non-repetitive rated currents are peak values. The rated current values may be applied to any cathode-anode terminal pair.
3. Rated currents only apply if pins 1 & 8 (K1,Tip) are connected together, pins 4 & 5 (K2, Ring) are connected together and pins
6 & 7 (A, Ground) are connected together.
4. These non-repetitive rated terminal currents are for the TISP8200HDM and TISP8201HDM together. Device (A)-terminal positive
current values are conducted by the TISP8201HDM and (K)-terminal negative current values by the TISP8200HDM.

OCTOBER 2005 REVISED MAY 2007


Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.

TISP820xHDM Overvoltage Protectors


TISP8201HDM Absolute Maximum Ratings, TA = 25 C (Unless Otherwise Noted)
Sy m b o l

Value

U nit

Repetitive peak off-state voltage, VGA = 0

R at i n g

VDRM

120

Repetitive peak reverse voltage, VGK = 70 V

VRRM

-120

IPPSM

500
150
100

ITSM

60
14
7
3.5

TJ

-55 to +150

Tstg

-65 to +150

Non-repetitive peak impulse current (see Notes 5, 6 and 7)


2/10 s (Telcordia GR-1089-CORE, 2/10 s voltage wave shape)
5/310 s (ITU-T K.44, 10/700 s voltage wave shape used in K.20/21/45)
10/1000 s (Telcordia GR-1089-CORE, 10/1000 s voltage wave shape)
Non-repetitive peak on-state current, 50/60 Hz (see Notes 5, 6, 7 and 8)
10 ms
1s
7s
900 s
Junction temperature
Storage temperature range

NOTES: 5. Initially the device must be in thermal equilibrium with TJ = 25 C. The surge may be repeated after the device returns to its initial
conditions.
6. These non-repetitive rated currents are peak values. The rated current values may be applied to any cathode-anode terminal pair.
7. Rated currents only apply if pins 1 & 8 (A1, Tip) are connected together, pins 4 & 5 (A2, Ring) are connected together and pins
6 & 7 (K, Ground) are connected together.
8. These non-repetitive rated terminal currents are for the TISP8200HDM and TISP8201HDM together. Device (A)-terminal positive
current values are conducted by the TISP8201HDM and (K)-terminal negative current values by the TISP8200HDM.

Recommended Operating Conditions


See Figure 3

Mi n

C1, C2 Gate decoupling capacitor

Typ

Max

220

Unit
nF

TISP8200HDM Electrical Characteristics, TA = 25 C (Unless Otherwise Noted)


Parameter

Test Conditions

Min

Typ Max Unit

IDRM

Repetitive peak off-state current

VD = VDRM, VGK = 0

-5

IRRM

Repetitive peak reverse current

VR = VRRM, VGA = -70 V

V(BO)

Breakover voltage

- 82

-90

V(BO)

Impulse breakover voltage

IH

Holding current

IGT

Gate trigger current

CO

Off-state capacitance

dv/dt = -250 V/ms, RSOURCE = 300

VGA = -80 V

dv/dt -1000 V/s, Linear voltage ramp,


Maximum ramp value = -500 V
di/dt = -20 A/s, Linear current ramp,
Maximum ramp value = -10 A
VGA = -80 V
(IK) IT = -1 A, di/dt = 1 A/ms, VGA = -80 V
(IK) IT = -5 A, tp(g)

f = 1 MHz, Vd = 1 V rms, Gate open

OCTOBER 2005 REVISED MAY 2007


Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.

- 15 0

20 s, VGA = -80 V

mA
15

VD = -2 V

65

VD = -50 V

30

mA
pF

TISP820xHDM Overvoltage Protectors


TISP8201HDM Electrical Characteristics, TA = 25 C (Unless Otherwise Noted)
Max

Unit

IDRM

Repetitive peak off-state current

Parameter
VD = VDRM, VGA = 0

IRRM

Repetitive peak reverse current

VR = VRRM, VGK = 70 V

-5

V(BO)

Breakover voltage

82

90

V(BO)

Impulse breakover voltage

IH

Holding current

IGT

Gate trigger current

CO

Off-state capacitance

Test Conditions

dv/dt = 250 V/ms, RSOURCE = 300

Min Typ

VGK = 80 V

dv/dt 1000 V/s, Linear voltage ramp,


Maximum ramp value = 500 V
di/dt = 20 A/s, Linear current ramp,
Maximum ramp value = 10 A
VGK = 80 V
(IA) IT = 1 A, di/dt = -1 A/ms, VGK = 80 V
(IA) IT = 5 A, tp(g)

20

mA

20 s, VGK = 80 V

f = 1 MHz, Vd = 1 V rms, Gate open

- 15
VD = 2 V

50

VD = 50 V

30

mA
pF

Thermal Characteristics
Parameter
RJA
NOTE

Junction to ambient thermal resistance

Test Conditions
EIA/JESD51-7 PCB, EIA/JESD51-2 Environment, PTOT = 4 W
(See Note 9)

Min Typ Max

U nit

55

C/W

9. EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths.

OCTOBER 2005 REVISED MAY 2007


Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.

TISP820xHDM Overvoltage Protectors


Parameter Measurement Information
+i

Quadrant I
Blocking
Characteristic

V GK(BO)
V GA

-v

VD

IR

IRRM
ID

VR

V RRM

+v

IH
V(BO)
ITSM
Quadrant III
IPPSM

Switching
Characteristic

PM8XACBa

-i

Figure 1. TISP8200HDM KA Terminal Characteristic

+i
Quadrant I

IPPSM

Switching
Characteristic
ITSM
V(BO)
IH

-v

V RRM

VR

ID
IR

IRRM

+v
VD

V GK
V GA(BO)

Quadrant III
Blocking
Characteristic

-i

Figure 2. TISP8201HDM AK Terminal Characteristic


OCTOBER 2005 REVISED MAY 2007
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.

PM8XABBa

TISP820xHDM Overvoltage Protectors


Applications Information
Overcurrent
Protection

SLIC
SLIC
PROTECTION

Tip
C2
220 nF

C1
220 nF

Ring
TISP8200HDM

TISP8201HDM

100 k
R2
D2

D1

D3

100 k
+V BAT

-VBAT

R1

Figure 3. Typical Application Circuit

GR-1089-CORE
Overcurrent Protection 1

GR-1089-CORE
Overcurrent Protection 2

F1a
B1250T
Fuse (Bourns)

Telcordia
GR-1089-CORE Issue 3
compliant LFR (Custom)

F1b
B1250T
AI-TISP8-001-b

Figure 4. Typical Overcurrent Protection

OCTOBER 2005 REVISED MAY 2007


Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.

Bourns Sales Offices


Region
The Americas:
Europe:
Asia-Pacific:

Phone
+1-951-781-5500
+41-41-7685555
+886-2-25624117

Fax
+1-951-781-5700
+41-41-7685510
+886-2-25624116

Phone
+1-951-781-5500
+41-41-7685555
+886-2-25624117

Fax
+1-951-781-5700
+41-41-7685510
+886-2-25624116

Technical Assistance
Region
The Americas:
Europe:
Asia-Pacific:

www.bourns.com
Bourns products are available through an extensive network of manufacturers representatives, agents and distributors.
To obtain technical applications assistance, a quotation, or to place an order, contact a Bourns representative in your area.

TISP is a trademark of Bourns, Ltd., a Bourns Company, and is Registered in U.S. Patent and Trademark Office.
Bourns is a registered trademark of Bourns, Inc. in the U.S. and other countries.
COPYRIGHT 2006, BOURNS, INC. LITHO IN U.S.A. e 09/06 TSP0620

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