8255 Ppi Examples
8255 Ppi Examples
PPI is abbreviation for Programmable Peripheral Interface. It is an I/O port chip used for
interfacing I/O devices with microprocessor. It is a very commonly used peripheral chip.
Knowledge of 8255 essential for students in the Microprocessors lab for interfacing
experiments.
A7
A6
Port A
PA7-0
RD*
A5
WR*
A4
CS*
A3
D7-0
A2
A1
A0
Reset
NC
M/IO*
Port C
Control Port
Port B
PC7-4
PC3-0
PB7-0
There are 3 ports in 8255 from users point of view - Port A, Port B and Port C.
Port C is composed of two independent 4-bit ports : PC7-4 (PC Upper) and PC3-0 (PC
Lower)
Selection of Ports
A1
0
0
1
1
A0
0
1
0
1
Selected port
Port A
Port B
Port C
Control port
There is also a Control port from the Processor point of view. Its contents decides the
working of 8255. When CS (Chip select) is 0, 8255 is selected for communication by the
processor. The chip select circuit connected to the CS pin assigns addresses to the ports
of 8255.
For the chip select circuit shown, the chip is selected when A7=0, A6=1, A5=1, A4=1,
A3=1, A2=1, and M/IO*= 0. Port A, Port B, Port C and Control port will have the
addresses as 7CH, 7DH, 7EH, and 7FH respectively.
There are 3 modes of operation for the ports of 8255. Mode 0, Mode 1, and Mode 2.
Mode 0 Operation
It is Basic or Simple I/O. It does not use any handshake signals. It is used for interfacing
an i/p device or an o/p device. It is used when timing characteristics of I/O devices is well
known.
Mode 1 Operation
It uses handshake I/O. 3 lines are used for handshaking. It is used for interfacing an i/p
device or an o/p device. Mode 1 operation is used when timing characteristics of I/O
devices is not well known, or used when I/O devices supply or receive data at irregular
intervals.
Handshake signals of the port inform the processor that the data is available, data transfer
complete etc. More details about mode 1 operation is provided later.
Mode 2 Operation
It is bi-directional handshake I/O. Mode 2 operation uses 5 lines for handshaking. It is
used with an I/O device that receives data some times and sends data sometimes. Ex.
Hard disk drive. Mode 2 operation is useful when timing characteristics of I/O devices is
not well known, or when I/O devices supply or receive data at irregular intervals.
Port A can work in Mode 0, Mode 1, or Mode 2
Port B can work in Mode 0, or Mode 1
Port C can work in Mode 0 only, if at all
Port A, Port B and Port C can work in Mode 0
Port A and Port B can work in Mode 1
Only Port A can work in Mode 2
Where are the Handshake signals?
We have already listed all the 40 pins of 8255. Port C pins act as handshake signals,
when Port A and Port B are configured for other than Mode 0. Port A in Mode 2 and Port
B in Mode 1 is possible, as it needs only 5+3 = 8 handshake signals. After Reset of 8255,
Port A, Port B, and Port C are configured for Mode 0 operation as input ports.
PC2-0 are used as handshake signals by Port B when configured in Mode 1. This is
immaterial whether Port B is configured as input or output port.
PC5-3 are used as handshake signals by Port A when configured as input port in Mode 1.
PC7, 6, 3 are used as handshake signals by Port A when configured as output port in
Mode 1.
PC7-3 are used as handshake signals by Port A when configured in Mode 2.
There are 2 control words in 8255
Mode Definition (MD) Control word and
Port C Bit Set / Reset (PCBSR) Control Word
M2A
M1A
I/P A
Means Mode
Definition control
word
I/P CU
M1B
1 - PCU as input
0 - PCU as output
1 - PA as input
0 - PA as output
M2A M1A
0
Port A in Mode 0
Port A in Mode 1
0/1
Port A in Mode 2
I/P B
I/P CL
1 -PCL as input
0 -PCL as output
1 - PB as input
0 - PB as output
1 - PB in Mode 1
0 - PB in Mode 0
Ex. 1: Configure Port A as input in Mode 0, Port B as output in mode 0, Port C (Lower)
as output and Port C (Upper) as input ports.
Required MD control word:
1
MD control word
98H
PC Lower as output
PA in Mode 0
PB as output
PA as input
PB in Mode 0
PC Upper as input
Ex. 2: Configure Port A as input in Mode 1, Port B as output in mode 1, Port C7-6 as
input ports. (PC5-0 are handshake lines, some are input lines and others are output. So
they are shown as X)
Required MD control word:
1
MD control
BCH or BDH
PB as output
PA as input
PB in Mode 1
PC Upper (C7-6) as input
MD control
C4H / C5H..
PC3-0 as handshake
PA in Mode 2
PA bidirectional
Dont cares
SB2
SB1
SB0
S/R*
Select bit of PC to
be set / reset
0
0
:
:
1
0
0
:
:
1
0
1
:
:
1
1 - Set to 1
0 - Reset to 0
Bit 0 of Port C
Bit 1 of Port C
Bit 7 of Port C
09H
Set to 1
Dont cares
Bit 4 of Port C
Dont cares
Bit 6 of Port C
0CH
Reset to 0
8255
Port B
PB7-0
STB*B
(PC2)
IBFB INT B
(PC1) (PC0)
Waveforms for Handshake Interrupt input port
STB*
IBF
INT
RD*
Data from
I/O dev.
When input device has data to send it checks if IBF (input buffer full) signal is 0. If 0, it
sends data on PB7-0 and activates STB* (Strobe) signal. STB* is active low. When STB*
goes high, the data enters the port and IBF gets activated. If the Port interrupt is enabled,
INT is activated. This interrupts the processor. Processor reads the port during the ISS.
Then IBF and INT get deactivated.
Handshake interrupt output port
For Port A as handshake interrupt output port:
INTA is PC3
ACK*A is PC6
OBF*A is PC7
8255
Port B
OBF*B INT B
(PC1) (PC0)
Waveforms for Handshake interrupt output port
WR*
OBF*
INT
ACK*
PB7-0
When output device wants to receive data it checks if OBF* (output buffer full) signal is
0. If 0, it receives data on PB7-0 and activates ACK* (Acknowledge) signal. ACK* is
active low. When ACK* goes high, the data goes out of the port and OBF* is set to 1. If
the Port interrupt is enabled, INT is activated. This interrupts the processor. Processor
sends another byte to the port during the ISS. Then OBF* and INT are reset to 0.
Handshake Status Check I/O
For this operation, interrupt is disabled for the port using PCBSR control word. Even if
new data is entered into input buffer by I/O device INT output is not going to be activated
for input operation. Then, how processor knows that the input buffer has new data?
Similarly, even if I/O device has emptied the output buffer, INT output is not going to be
activated for output operation. Then, how the processor knows that the output buffer is
empty?
This is solved by the processor reading the status of the port for this purpose.
PC provides status information of PA and PB when they are not in Mode 0
PC7
OBF*
PC6
INTE
PC5
IBF
PC4 PC3
INTE INT
PC2 PC1
PC0
INTE IBF/OBF* INT
PA status in Mode 2
Handshake status check input port
Suppose Port B is in mode 1 status check input. Processor reads bit 1 (IBF) of Port C
repeatedly till it is set and then the processor reads Port B, as shown below.
AGAIN: IN AL, 7EH; Read Port C
ROR AL, 1;
ROR AL, 1; Check bit 1 of Port C
JNC AGAIN; If it is 0, repeat checking
IN AL, 7DH; Read from Port B
Handshake status check output port
Suppose Port B is in mode 1 status check output. Processor reads bit 1 (OBF*) of Port C
repeatedly till it is set and then the processor writes to Port B.
ADC 0808
PA7-0
PC7
Out7-0
EOC
D7-0
PC0
SOC
PB0
PB1
PB2
i/p 2
Port A
D7-0
PA7-0
Current/Voltage
con.
converter
I out
V out
OUT 7CH, AL; Next 4 instructions generate rising portion of triangular waveform
INC AL;
CMP AL, FFH;
JB UP
DOWN: OUT 7CH, AL; Next 4 instructions generate falling portion of triangular waveform
DEC AL;
CMP AL, 00;
JA DOWN
JMP UP; repeat generation of waveform