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Design of Carry Lookahead Adders

carry look ahead

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gdeepthi
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50 views2 pages

Design of Carry Lookahead Adders

carry look ahead

Uploaded by

gdeepthi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Design of Carry Lookahead Adders :

To reduce the computation time, there are faster ways to add two binary numbers by using carry
lookahead adders. They work by creating two signals P and G known to be Carry
Propagator andCarry Generator. The carry propagator is propagated to the next level whereas the
carry generator is used to generate the output carry ,regardless of input carry. The block diagram of a
4-bit Carry Lookahead Adder is shown here below -

The number of gate levels for the carry propagation can be found from the circuit of full adder. The
signal from input carry Cin to output carry Cout requires an AND gate and an OR gate, which constitutes
two gate levels. So if there are four full adders in the parallel adder, the output carry C 5would have 2 X
4 = 8 gate levels from C1 to C5. For an n-bit parallel adder, there are 2n gate levels to propagate
through.

Design Issues :
The corresponding boolean expressions are given here to construct a carry lookahead adder. In the
carry-lookahead circuit we ned to generate the two signals carry propagator(P) and carry generator(G),
Pi = Ai Bi
Gi = Ai Bi
The output sum and carry can be expressed as
Sumi = Pi Ci
Ci+1 = Gi + ( Pi Ci)

Having these we could design the circuit. We can now write the Boolean function for the carry output
of each stage and substitute for each Ci its value from the previous equations:
C1 = G0 + P0 C0
C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0
C3 = G2 + P2 C2 = G2 P2 G1 + P2 P1 G0 + P2 P1 P0 C0
C4 = G3 + P3 C3 = G3 P3 G2 P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0

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