September 24, 2003

E&CE 427 Handout 4:

Cadence NC-VHDL
Simulator Tutorial
Sanjay Singh
[email protected]
with advice from Mark Aagaard, Jason Higgins,
Manisha Shah, & Mohamed El-Gebaly

Use this document to learn Cadences NCVHDL for E&CE 427. Please E-mail the
author with suggestions and commentary.

Table of Contents

Table of Contents
Introduction
Prerequisite Knowledge Required..................................................................... 3
Overview of the Digital Design Process ........................................................... 3
Overview of the Cadence NC-VHDL Simulator............................................... 5
Setup
Modifying the .cshrc file on Solaris .................................................................. 5
Problems with Setup: path too long............................................................... 7
Help & Online Documentation
Accessing the Cadence Online Documentation ................................................ 7
Help System Problems: Access Denied .......................................................... 10
Analysis and Elaboration
Begin Your Project: Create the Folders for the Design ................................... 11
Setting up Special Cadence Configuration Files ............................................. 12
Error Messages Related to cds.lib and hdl.var ................................................ 13
Writing VHDL Code and Testbench ............................................................... 14
Analyzing the VHDL Code in General ........................................................... 15
NCVHDL: Analyzing the Design ................................................................... 15
NCELAB: Elaborating the Design .................................................................. 16
Simulation
Initiating the Design Simulator ....................................................................... 16
Invoking the Waveform View.......................................................................... 20
Running the Simulation................................................................................... 21
Some Additional Words about the Command Window .................................. 24
Multi-Level VHDL Design: Half-Adder Circuit............................................. 24
Half-Adder: Compiling, Elaborating, and Simulating .................................... 27
Invoking the Design Simulator for Half-Adder Entity.................................... 28
Examining the Waveform................................................................................ 30
Exercise for the Student: Exploring Scope in VHDL ..................................... 31
Conclusion of the NC VHDL Tutorial ............................................................ 34

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

Prerequisite Knowledge Required

Prerequisite Knowledge Required

Welcome to the NC-VHDL Tutorial. Before we begin, we need to discuss some
things that you should know. Otherwise things might take longer than they
should for you to complete the tutorial material.
We presume a basic familiarity with Solaris and Sun workstations. If you are not
comfortable with Unix, see the assigned lab instructor to help get you familiar
with Unix, or to request a tutorial document. Also see the E&CE 427 website at:
ECE 427 WEB SITE

http://ece.uwaterloo.ca/~ece427

Also, we assume a general familiarity with hardware description languages

from earlier courses such as E&CE 223 and E&CE 324.

Overview of the Digital Design Process

ABOUT CADENCE AND
ELECTRONIC DESIGN
AUTOMATION

The Cadence Design System, like tools from Synopsys and Mentor Graphics
which you may have heard of or used in the past, is a powerful set of applications and utilities for Electronic Design Automation (EDA). As the term
implies, the goal here is to use this software to design, simulate, and validate
complex digital systems much more quickly1 and reliably than earlier methods.

FACT: LEGENDARY
SUPERCOMPUTER
DESIGNER SEYMOUR
CRAYS MOST POWERFUL
TOOLS WHEN DESIGNING A
NEW ARCHITECTURE
WERE A PENCIL AND PAD
OF PAPER

Advanced combinatorial and numerical algorithms are employed by these tools

to automate and tirelessly compute good design configurations and component
placements that would otherwise incur much higher costs and effort if done
manually. However, having said that, its good to remind the reader that the very
best digital design is still done by people. One of the roles of a good design
manager is to find the best balance between automated design and highly optimized manual design, for a given project.
Figure 1 on page 4 illustrates the major steps in using an EDA suite when using
a hardware description language, such as Verilog or in our case, VHDL. Take
note that this is a somewhat simplified description in that it is a waterfall diagram, implying that these steps are done in succession without any backtracking. In reality, to get a large design to work properly, many people are involved
who must co-ordinate their actions to do the best possible design and validation,

1. As if technology doesnt move fast enough already!

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

Overview of the Digital Design Process

simulation, testing, and implementation. Most design projects will involve multiple people working on multiple things while trying to keep everything in sync.
Requirements

Modify
Algorithm
Analyze
Modify
High-Level Model
Analyze
Modify
Synth. RTL Code
Analyze
Modify
Opt. RTL Code
Analyze
Modify
Implementation
Analyze

Hardware

FIGURE 1.

The major stages of digital system design with an HDL.

Lets talk about Figure 1 in more detail. After you have defined your general
requirements, such as how fast you would like it to run, and perhaps power consumption, you model the architecture as a general algorithm first, using state
descriptions and other representations that are abstract. The high-level model is
more specific and takes the form of a block-level diagram, with VHDL code for
each block, and well defined interactions between these blocks of code. At this
point, you can simulate your design and see if your design is functionally correct. Once you are satisfied that you have achieved functional correctness, you
can then produce a synthesizable register-transfer-level design. This is a design
that is mapped to a specific hardware implementation technology, but has not
been optimized. Unlike the simulation of the high-level model, however, this
design has a physical geometry associated with it from the choosing of a target
device such as an FPGA, and the simulation now can give you a more realistic
simulation that takes into account timing differences due to the geometry of the
design implementation on a given target. You can then simulate with timing
delays and again verify correct functionality of your design. After this, you want
to optimize your design as much as possible for speed or other performance criteria, and again test for correctness. Lastly, you will download your design into
the FPGA, and test again.

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

Overview of the Cadence NC-VHDL Simulator

Overview of the Cadence NC-VHDL Simulator

The NC-VHDL simulator is a VHDL digital logic simulator that combines the
high-performance of native compiled code simulation with the accuracy, flexibility, and debugging capabilities of event-driven simulation.
STANDARDS COMPLIANCE

The simulator is fully compliant with the IEEE 1076-1987 and IEEE 1076-1993
standards. The simulator is also compliant with the IEEE 1076.4, 2000VITAL
ASIC Modeling Specification.

SIMVISION ANALYSIS
ENVIRONMENT

The NC-VHDL simulator is packaged with the SimVision analysis environment, which includes debugging, waveform viewing, database comparison,
code coverage, and IP packaging tools. The simulator also includes a C interface, an OMI-compliant socket that allows you to use external models, and an
interface based on the emerging VHDL programming language interface
(VHPI).
In a native compiled code (NCC) simulator, a parser produces an intermediate
representation of the input source text. This intermediate representation is then
processed by a code generator that produces relocatable machine code that runs
directly on the host processor.
The NCC approach to simulation has several benefits over interpreted and compiled code techniques:
Improved throughput, because the intermediate translation steps required by interpreted and compiled code simulators are bypassed.
Significantly reduced time in setting up the simulation run because the use of the C
compiler is avoided.
More efficient use of memory.

NCC is optimized for use throughout the entire design cycle. It offers both fast
design change turnaround, which is critical early in the design cycle, and a combination of fast simulation run time with the accuracy of full functional simulation, which is essential later in the process.
FIRST THINGS FIRST!!

Modifying the .cshrc file on Solaris

IF YOU HAVENT USED NCVHDL BEFORE, READ THIS

SECTION PLEASE.

Before you can use NC-VHDL, you need to make some changes to your Unix
shell environment. Dont worry, it is as easy as some basic text file editing. In
this section, we presume the choice of /bin/csh as the default command line
shell. It is possible, of course, to choose another shell and modify the corresponding configuration file, but I will assume that the user who can do this can
also adapt the information presented here to their own shell, be it Bourne (/bin/
sh), Korne (/bin/ksh), GNU bash (/bin/bash), etc.

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

Modifying the .cshrc file on Solaris

To edit your .cshrc file, open your .cshrc and add the following line(s):
SOURCE THE CADENCE
SETUP FILE FROM .CSHRC

##################################
# ECE 427 Environment Settings
##################################
source /home/ece427/setup-ece427.csh

*ADD THESE LINES TO THE

END OF THE .CSHRC FILE!

This last line tells your shell to go and read these files for additional environment variables that will tell your shell how to find the Cadence tools. Remember
to save your changes to the .cshrc file.
At this point, you can either log out and log back in again, or in a Terminal window, you can type:
source ~/.cshrc
rehash

The first line will tell the shell to re-read the .cshrc file, and your new references
will be read in and remembered. The rehash command refreshes any internal
hashing tables (remember E&CE 250?) used by the shell that contain the contents of directories.
Please note however, that this affects only the shell in that particular terminal
window. Other terminal windows you have opened will not be affected. But at
your next login, these changes will apply to all future shell invocations you do
during a Unix session.
Now, next time you login, the .cshrc file will reference the necessary information to find ncvhdl and related tools so you can use them.
USING BASH (BOURNE
AGAIN SHELL)

For those that prefer to use /bin/bash as their default command shell, put the following line in your .bashrc file in your home directory:
/home/ece427/setup-ece427.sh

If necessary, you might have to create the .bashrc file if it does not already exist.
STARTING THE TOOLS

If you correctly implemented the instructions in section First things first!! If

you havent used NC-VHDL before, read this section please. on page 5, you
should now be able to start the Cadence tool required for the E&CE 427 course
from a Solaris terminal window.
Verify this by typing:
which ncvhdl ncelab ncsim

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

Problems with Setup: path too long

in a Terminal window, as shown in Figure 2 on page 7. If you get the output that
shows where each program is, your PATH shell environment variable has been
correctly setup to allow the shell to start the NC-VHDL. Congratulations!

FIGURE 2.

Verifying the search paths can find NC-VHDL tools.

Problems with Setup: path too long

If you get a message stating that your path is too long, this probably means that
your .cshrc file is sourcing configuration files pertaining to other courses you
may have already taken, and the PATH environment variable is not able to hold
everything, because there is a length limit.
SOLUTION: REMOVE OLD
SOURCE COMMANDS
FROM YOUR .CSHRC

What you should do is go back and remove source commands in your .cshrc
that apply to software you are no longer using, and this message should go
away. Example:
source /home/ece223/setup-ece223.csh

Consult a lab instructor or system administrator if you cannot fix this yourself.

Accessing the Cadence Online Documentation

When learning and using NC-VHDL, you will want a large volume of online
help at your fingertips to do your work more effectively. NC-VHDL has various

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

Accessing the Cadence Online Documentation

kinds of documentation, all of which is accessible from the Cadence Design

System Documentation utility: cdsdoc.
To start cdsdoc, simply type:
cdsdoc

[enter]

in a Terminal window, and a new window should appear titled Cadence Documentation, as shown below:

FIGURE 3.

Cadence Documentation via cdsdoc; user selecting NC-VHDL Guide.

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

Accessing the Cadence Online Documentation

Once you select the guide and open it, a web browser will open, containing the
Virtuoso Schematic Composer VHDL Interface User Guide:

FIGURE 4.

Verifying the search paths can find NC-VHDL tools.

This page is being served to you from a web server process started by cdsdoc,
on the workstation you are currently logged onto. For example, if you were
logged onto the machine kilby (named after Jack Kilby - remember him from
the first lecture?) the browser URL would be:
http://kilby:9000//home/cadence/t/c/IC/doc/compvhdluser
/compvhdluserTOC.html

If you prefer PDF, you can also open PDF documents from this browser page by
clicking on View|Print PDF shown on the black banner at the top of the page.

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

Help System Problems: Access Denied

Help System Problems: Access Denied

Usually, the help system works fine, but occasionally, it denies you access to the
online help you need. Sometimes you might see a rather unfriendly web
browser window that is much less appealing than the one in Figure 4. You
would see something like this:

FIGURE 5.

10

Cadence Documentation via cdsdoc; user selecting NC-VHDL Guide.

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

Begin Your Project: Create the Folders for the Design

The solution to this is to kill the http server that the help system spawns when it
help is requested, as shown here:

process ID number(s)

command & parameters

of process ID
22: finding the https process ID
23: kill the process with level 9 signal
24: verifying the process is no longer there
Finding unwanted https processes, terminating them with kill -9,
verifying they have left the building once and for all.
FIGURE 6.

TELLING HTTP PROCESSES

TO STOP WHAT THEY ARE
DOING AND GO HOME

The idea is to simply find the process ID(s) of the https process(es) that might
still be running, send them a termination signal, and verify that they are truly
gone. Your procedure, if you have to do this will be something like the one
shown in Figure 6, starting with the ps -ef ... command.

Begin Your Project: Create the Folders for the Design

Before you do anything else, first make yourself a folder to keep your VHDL
project in. Open a new Terminal window by right-clicking the mouse on the
desktop (but not on an icon or existing window). A little box titled Workspace
Menu will appear. Move the mouse to the Tools menu. And from there, select
Terminal. To summarize: Workspace Menu > Tools > Terminal
In the terminal type:
mkdir Tutorial

and press Enter. You dont have to call it Tutorial. You can give it another name
if you like, but this document will assume you are using a project directory
called Tutorial.
Now, change into this directory with the cd command:
cd Tutorial

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

11

Setting up Special Cadence Configuration Files

MAKING THE WORK

DIRECTORY

Now that you are inside the Tutorial folder, you have to make one more folder
called WORK. See the next section for a fuller explanation of what this directory is, and why its important.
Type:
mkdir WORK

You have made a WORK directory to be used by the analyzer, elaborator, and
simulator. See Intermediate Objects and the WORK Directory on page 15.

Setting up Special Cadence Configuration Files

To start using the Cadence tools one needs to source a script which contains all
the necessary path and setup information to invoke the tool.
Two other setup files, listed below, are required before you can start using the
tools. Copy the contents from here into your design folder. These files specify
the path to libraries and also create a user work library. In this case the user
work library has been called WORK but can be given other names provided the
following files are changed to reference it.
ABOUT THE HDL.VAR FILE

The hardware description language variable file, known as hdl.var is an ASCII

text file that contains:
Configuration variables, which determine how your design environment is configured. These include variables that you can use to specify the work library where the
compiler stores compiled objects and other derived data. For VHDL, use the WORK
variable.
Variables that allow you to define compiler, elaborator, and simulator command-line
options and arguments.
Variables that specify the locations of support files and invocation scripts.

YOU CAN ALSO COPY

HDL.VAR FROM:
/HOME/ECE427/LIB/NCVHDL

Do not concern yourself too much with this file, since the necessary settings are
already in place for your course work. But be aware that it must be in your
project directory, otherwise you cannot use Cadence properly, if at all.
The contents of the hdl.var file are as follows (disregard the line break below; its
all meant to be one line, OK?):
SOFTINCLUDE /home/cadence/tools/cadence.2002a/LDV.34.ISR/
tools.sun4v/inca/files/hdl.var
DEFINE WORK WORK

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Error Messages Related to cds.lib and hdl.var

OPTIONAL HDL.VAR
CUSTOMIZATIONS YOU CAN
MAKE

Now, take note that if you want to, you can add these lines in to define your
default text editor. If you are familiar with Unix, you will have heard of the vi
text editor, a remarkably powerful text editor for its size, but not the easiest to
use if you are used to Microsoft type text editors. Even more powerful than vi is
emacs, but if you know how to use emacs, you dont need me to explain any
more about text editors. Anyway, these lines will choose vi as your text editor
when using Cadence:
DEFINE EDITOR vi
DEFINE CDS_TEXT_EDITOR vi

ABOUT THE CDS.LIB FILE

The cds.lib file is an ASCII text file that defines which libraries are accessible
and where they are located. The file contains statements that map logical library
names to their physical directory paths. During initialization, all tools that need
to understand library names read the cds.lib file and compute the logical to
physical mapping.

YOU CAN ALSO COPY

CDS.LIB FROM:
/HOME/ECE427/LIB/NCVHDL

As with the hdl.var file, the contents primarily reference a customized configuration file located elsewhere, but you do have the option of adding environment
variables and settings if you need to. But the existing contents will meet the
needs of E&CE 427:

*THIS LINE IS MEANT TO BE

ON ONE LINE ONLY, NOT 2!

SOFTINCLUDE /home/cadence/tools/cadence.2002a/LDV.34.ISR/
tools.sun4v/inca/files/cds.lib
DEFINE WORK ./WORK

Error Messages Related to cds.lib and hdl.var

If you see messages like the following when you are trying to run ncvhdl, this
means that you are missing some key files that the Cadence Design System
needs in order to orient itself:
MISSING CDS.LIB AND
HDL.VAR FILES

ncvhdl: v03.40.(s018): (c) Copyright 1995 - 2003 Cadence Design

Systems, Inc.
ncvhdl: *W,DLNOCL: Unable to find a cds.lib file to load in.
ncvhdl: *W,DLNOHV: Unable to find an hdl.var file to load in.
ncvhdl_p: *W,DLNOCL: Unable to find a cds.lib file to load in.
ncvhdl_p: *W,DLNOHV: Unable to find an hdl.var file to load in.
ncvhdl_p: *F,NOWORK: logical library name WORK must be bound to a
design library

You must make these configuration files yourself, as discussed in the preceding
two sections; or get a copy of these files from:
/home/ece427/lib/ncvhdl

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

13

Writing VHDL Code and Testbench

Writing VHDL Code and Testbench

In this example we are working with a design file named trial.vhd that has the
following VHDL code:
TRIAL.VHD

library IEEE;
use IEEE.std_logic_1164.all;
entity trial is
port(
request_data
ttl_clock_n
count0
);
end trial;

:
:

in std_logic;
in std_logic;

out std_logic

architecture trial_rtl of trial is

begin
count0

<= not(request_data and ttl_clock_n);

end trial_rtl;
TEST_TRIAL.VHD

The testbench for the design file, test_trial.vhd , has the following listing:
library ieee;
use ieee.std_logic_1164.all;
entity test_trial is
end test_trial;
architecture tb_arch of test_trial is
component trial
port (
request_data
ttl_clock_n
count0
);

:
:
:

in std_logic;
in std_logic;
out std_logic

end component;
signal request_data : std_logic;
signal ttl_clock_n : std_logic ;
signal count0 : std_logic ;
begin
UUT : trial
port map
(

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E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

Analyzing the VHDL Code in General

request_data
ttl_clock_n
count0

=>
=>
=>

request_data,
ttl_clock_n,
count0

);
--Add your stimulus here..
request_data <= 1 after 10 ns, 0 after 100 ns, 1 after 250
ns;
ttl_clock_n <= 1 after 25 ns, 0 after 50 ns, 1 after 80 ns,
0 after 300
ns;
end tb_arch;

Analyzing the VHDL Code in General

On the Unix prompt all design files and testbench need to be analyzed and elaborated. The analyzer: ncvhdl, encapsulates two tools:
the VHDL parser
the code generator.

This is similar to the design of a compilers which you learned in E&CE 251.
The parser performs syntactic and static semantic checking on the input source
files. If no errors are found, compilation produces an internal representation for
each HDL design unit in the source files.
INTERMEDIATE OBJECTS
AND THE WORK
DIRECTORY

These intermediate objects are stored in a library directory. This library directory is defined in the cds.lib file, as WORK and therefore there must always
be a WORK subdirectory in your project directory.

NCVHDL: Analyzing the Design

GENERAL FORM OF
ANALYSIS COMMAND:
NCVHDL <FILENAME.VHD>
TIP: NCVHDL -HELP

Analyze the design with the following commands:

ncvhdl trial.vhd
ncvhdl test_trial.vhd

An example session in a terminal window would look like this:

{kilby:16} ncvhdl -linedebug trial.vhd
ncvhdl: v03.40.(s018): (c) Copyright 1995 - 2003 Cadence Design
Systems, Inc.
{kilby:17} ncvhdl -linedebug test_trial.vhd
ncvhdl: v03.40.(s018): (c) Copyright 1995 - 2003 Cadence Design
Systems, Inc.

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

15

NCELAB: Elaborating the Design

*VERY IMPORTANT!

When you compile with ncvhdl, use the -linedebug switch to allow you to
probe signals. This will turn on full debugging access to the file being compiled.
Make sure you remove the switch when you have debugged a particular block in
the design - the simulation will run a lot faster. If you forget to use this switch
when analyzing, you will encounter scoping problems when you get to the
graphical simulation phase of the tutorial.

NCELAB: Elaborating the Design

The elaborator: ncelab, does what the name implies and adds details, i.e. elaborates on the objects produced from the VHDL analysis, taking it from the
abstract to the more concrete. Specifically, elaboration constructs a design hierarchy based on the instantiation and configuration information in the design,
establishing signal connectivity, and computes initial values for all objects in the
design. The elaborated design hierarchy is stored in a simulation snapshot file,
which is used by the simulator. See Figure 1 on page 4, and the accompanying
discussion below it, for the overall picture of VHDL design flow.
GENERAL FORM OF
ELABORATION COMMAND:
NCELAB LIB.TOP:BEHAV
TOP = NAME OF DESIGN
BEHAV = NAME OF DESIGN
ARCHITECTURE
TIP: NCELAB - HELP

PLEASE NOTE:

Elaborate the design with the following:

ncelab WORK.trial:trial_rtl
ncelab WORK.test_trial:tb_arch

An example of elaboration is shown below:

{kilby:59} ncelab WORK.trial:trial_rtl
ncelab: v03.40.(s018): (c) Copyright 1995 - 2003 Cadence Design
Systems, Inc.
{kilby:60} ncelab WORK.test_trial:tb_arch
ncelab: v03.40.(s018): (c) Copyright 1995 - 2003 Cadence Design
Systems, Inc.
{kilby:61}

The design file(s) needs to be analyzed and elaborated before the testbench file,
because the testbench file refers to them.

Initiating the Design Simulator

At this stage your design has been successfully compiled (analyzed & elaborated). Now we would like to simulate the design to see whether it is functionally correct.
COMMAND LINE:
NCSIM VHDLFILE

Simulation can be initiated from the command line in a terminal window, with,
or without a graphical interface to use. If you happen to be working remotely,

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Initiating the Design Simulator

such as from home over an SSH connection, your only real option is to work
from the command line. You will see results similar to the following:
PLEASE NOTE: YOU CAN
USE X11 TUNNELING TO
SEE WAVEFORMS, AS
DESCRIBED IN TUTORIAL 1.
BUT DEPENDING ON
WHETHER YOU ARE ONCAMPUS OR USING
BROADBAND INTERNET OR
DSL FROM OFF-CAMPUS,
THE BANDWIDTH
REQUIRED FOR XWINDOWS MAY BE TOO
HIGH FOR X-SESSIONS
FROM OFF-CAMPUS.
IF YOU FIND THIS TO BE
THE CASE, USE A TEXTBASED SESSION SUCH AS
SECURE SHELL (SSH)
FROM OFF-CAMPUS.

GRAPHICAL INTERFACE
BASED COMMAND

FIGURE 7.

Verifying the search paths can find NC-VHDL tools.

Most people, however would prefer to work with a GUI, since the simulators
options are there and can be explored while learning how to use it. Following
the command line example is the command to invoke the simulator with a GUI:

FIGURE 8.

Verifying the search paths can find NC-VHDL tools.

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

17

Initiating the Design Simulator

The main difference is the addition of the: -gui switch to the ncsim command,
that starts the simulator. If you look carefully, you might see a smaller window
momentarily appear, with a blue bar, indicating the loading of the elaborated
testbench entity.
*PLEASE NOTE...

Please take note, however that we are simulating only the testbench. The design
itself was declared as a component in the testbench, and the testbench processes
will send known signals and values to the entity we have crafted that implements our design logic in VHDL.
Using a testbench has the advantage that it is more portable (i.e. does not
depend on the simulator). Other EDA applications do allow for driving the circuit from a stimulus file, but the syntax will need to be changed each time you
change simulators. In addition, there is a much larger and more powerful range
of commands which can be used with the testbench approach.
Finally, since everything else in E&CE 427 uses a testbench, this approach will
be consistent with all the other 427 examples/code.
A few seconds after entering the ncsim -gui command you should see a simulator window as shown below:

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Initiating the Design Simulator

set scope

scope up

set breakpoint
signal flow browse
set force

single
step
run
show value
step
over

edit source
show execution

cycle view
waveform
view
hide/show
source
watch
objects
navigator

{source code panel}

panel
resizer
Scope/Subscope drop down menu
{command line panel}

FIGURE 9.

Cadence ncsim Graphical User Interface

TEXT WINDOW CONTENT

OF NCSIM...

Notice that the window in Figure 9 displays the architecture of the testbench
file. The menus of this tool are quite extensive and provide the user with a lot of
debugging facilities like setting breakpoints and watch values, which should
sound familiar to users of C/C++ debuggers.

NCSIM>
COMMAND PROMPT

Another thing to note is that the lower portion of the window gives a command
prompt (ncsim>). This allows you to type a command rather than choosing
options from the menu. For larger designs with many hierarchical VHDL files it
is also possible to write scripts to do a complete design starting from compile to

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

19

Invoking the Waveform View

simulation. However, for our simple design we will move on to the displaying
the waveform for our design.

Invoking the Waveform View

FIRST, SELECT THE
SIGNALS YOU WANT TO
SEE

Before invoking the SimVision Waveform Viewer, it is important to select the

signals as shown in Figure 10 to display on the waveform. Choose Select > Signals from the menu of the simulator, as shown below. Once the signal selection
has been done your window should appear as shown in Figure 10:.

FIGURE 10.

20

Selecting the signals to see in the Waveform View.

E&CE 427 Handout 4: Cadence NC-VHDL Simulator Tutorial

Running the Simulation

SELECTING SPECIFIC
SIGNALS, INSTEAD OF ALL
OF THEM

You can use the Control key to toggle individual signals on and off, if you are
only interested in seeing a specific set of signals from your simulation. This may
be less distracting than having to look at all the signals that your design may
use, and it will allow you to focus on just those that you need to.
To invoke SimVision click on the Waveform Viewer button in the upper right
corner, as shown in Figure 9, Cadence ncsim Graphical User Interface, on
page 19. You should see the SimVision Window with the signals you have
selected. But since the simulation has not been started, there are no traces for
you to look at yet.

simulation cursors

selected
signals

FIGURE 11.

signal
values

waveform window

SimVision allows the user to view waveforms and signal values.

Running the Simulation

To start the simulation click on the run button in the simulator window. This will
run the simulation to the end of the test vectors provided in the testbench file. In
general, it will run until the simulation finishes or until the next breakpoint.
In the command window, at the bottom half of the screen, you should see something like the following:
ncsim> run
ncsim: *W,RNQUIE: Simulation is complete.
ncsim>

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Running the Simulation

In addition to this, the waveform window will now display the updated signals,
as shown in Figure 12, SimVision shows the results of the simulation after 300
ns., on page 23. This is because the stimulus commands at the end of the section test_trial.vhd on page 14 specify values for signals up to 300 ns. If you
need to review that section, its right after the comment:
--Add your stimulus here..
SINGLE STEP / STEP OVER

There are run options to single step through the code or step over. When you are
debugging your VHDL to fix logic errors, you will be making use of these buttons more frequently.
The upper button, single step, advances the simulation to the next executable in
any scope and steps into subprogram calls. It implements the equivalent of run
-step in the ncsim command panel.
The lower button, step over, advances the simulation to the next executable line
in the current scope. Steps over subprogram calls, not into them, Implements the
same actions as run -next in the command panel.

RUNNING THE SIMULATION

FOR SPECIFIC TIME
INTERVALS

Another nice way of running simulation is to specify the absolute or relative

time of run. The following example runs the simulation for 500 additional nanoseconds.
ncsim > run 500 ns

Bear in mind that if you were to just type:

ncsim > run 500

This would be interpreted to mean 500 femtoseconds, which is several orders of

magnitude smaller than nanoseconds. The simulator does not look at your
VHDL code and assume any kind of default time unit based on any directives
you may have had in your testbench, such as:
after 10 ns

The simulator will not work in nanoseconds, even if the last thing it saw was
using nanoseonds. So to ensure that you are in the right time unit, when simulating, specify the time unit as well, or else you may get results that do not make
sense, since they apply only to a very tiny fraction of time, than what you are
thinking of. See the table below for a comparison of the different timing intervals used in digital design.

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Running the Simulation

.
TABLE 1. VHDL

Debugger Time Unit options

Frequency

Time
Unit

Standard
Term

Exponential

Qualitative

PHz

FS

femtosecond

10 15

1 millionth of a nanosecond
- very short laser pulses

THz

PS

picosecond

GHz

NS

nanosecond

MHz

US

microsecond

kHz

MS

millisecond

Hz

SEC

second

floppy drive access times

RPM

MIN

minute

60

archival storage retrieval

time

12

trillionth of a second future microprocessors?

billionth of a second - RAM

access speeds, current
CPUs

millionth of a second - early

8-bit microprocessors

thousandth of a second hard drive access speeds

network latencies

10
10

10

10

After having completed the simulation the SimVision window displays the
waveform of each individual signal:

FIGURE 12.

SimVision shows the results of the simulation after 300 ns.

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23

Some Additional Words about the Command Window

Some Additional Words about the Command Window

THE COMMAND AREA IS A
UNIX SHELL ENVIRONMENT

The bottom half of the simulator window is a full-fledged unix command shell,
with tcl (Tool Command Language) support.

TIPS:
TYPE !! AT THE NCSIM >
PROMPT TO REPEAT YOUR
LAST COMMAND
TYPE HISTORY TO SEE
YOUR COMMAND HISTORY
AND TYPE:
!<NUMBER> TO INVOKE A
COMMAND FROM YOUR
HISTORY FILE, IE !23 TO
USE THE 23RD COMMAND
IN YOUR COMMAND
HISTORY

FIGURE 13.

Invoking online help for the simulator command window.

You can therefore create scripts of simulation commands, and invoke them
when you wish. A discussion of script creation is beyond the scope of an introductory tutorial, but consult the online help if you want to know more.

Multi-Level VHDL Design: Half-Adder Circuit

A
AND
B
E
AND

Complexity in digital systems comes from arranging large numbers of welldefined units together to implement higher level functionality that becomes
intelligible to other technical people, and ultimately the average person. Starting
from Boolean logic, digital systems can be designed with the ability to do arithmetic, compare numbers, process signals, and other more complex forms of
computation. But it all begins by first learning to connect a few simple digital
devices together and simulate them.

C
OR
D

ECE427_AND.VHD

This example illustrates a multi-level hierarchical design style. Three separate

VHDL source files will be analyzed, and the top-level entity will make references to the lower-level files. The two bottom-level files specify the entityarchitecture pairs for an AND gate and a OR gate respectively. The top-level
entity consists of a combinational logic circuit consisting of two AND gates and
a single OR gate.
First, create a file1 called ece427_and.vhd with the following contents:
library ieee;
use ieee.std_logic_1164.all;

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Multi-Level VHDL Design: Half-Adder Circuit

entity ece427_and is
port(A,B : in std_logic ; OUTPUT : out std_logic);
end ece427_and;
architecture and_arch of ece427_and is
begin
OUTPUT <= A and B after 5 ns;
end and_arch;
ECE427_OR.VHD

Now, make a file called ece427_or.vhd with the following VHDL statements in
it:
library ieee;
use ieee.std_logic_1164.all;
entity ece427_or is
port(A,B : in std_logic ; OUTPUT : out std_logic);
end ece427_or;
architecture or_arch of ece427_or is
begin
OUTPUT <= A or B after 5 ns;
end or_arch;

ECE427_HALFADDER.VHD

Youre doing great! This next file is called ece427_halfadder.vhd will be the
top-level design entity with the following contents:
library ieee;
use ieee.std_logic_1164.all;
entity ece427_halfadder is
port(A,B,C,D : in std_logic; E : out std_logic);
end ece427_halfadder ;
architecture halfadder_arch of ece427_halfadder is
-- declare the components found in our entity
component ece427_and
port(A, B : in std_logic; OUTPUT : out std_logic);
end component;
component ece427_or
port(A, B : in std_logic; OUTPUT : out std_logic);

1. This is a good time to make you aware of some issues concerning entity naming and the naming conventions of some VHDL compilers and synthesis tools. Some suites such as Alteras
VHDL tools, expect that the filename containing the source code and the VHDL entity contained in it must match exactly, otherwise they will not be referenced correctly. (Those familiar
with Java may recall that the .class files created correspond to the classes in the .java files,
rather than the names used for the source files.) Not every VHDL tool requires this kind of
strongly typed naming convention at the file system level. But you may wish to consider
adopting this within the context of the course project if you expect to use Altera tools in the
future.

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Multi-Level VHDL Design: Half-Adder Circuit

end component;
-- declare signals used to interconnect components
signal s1, s2 : std_logic;
-- declare configuration specification
for U1, U3 : ece427_and use entity WORK.ece427_and(and_arch);
for U2: ece427_or use entity WORK.ece427_or(or_arch);
begin
U1 : ece427_and port map(A => A , B => B , OUTPUT => s1 );
U2 : ece427_or port map(A => C, B => D, OUTPUT => s2 );
U3 : ece427_and port map(A => s1, B => s2, OUTPUT => E);
end halfadder_arch;
ECE427_TESTBENCH.VHD

Lastly, create a file called ece427_testbench.vhd which contains the following:

library ieee;
use ieee.std_logic_1164.all;
entity ece427_testbench is
end ece427_testbench;
architecture test_arch of ece427_testbench is
component ece427_halfadder
port (A, B, C, D : in std_logic ; E : out std_logic);
end component;
signal A, B, C, D, E : std_logic;
begin
UUT : ece427_halfadder
port map
(
A => A
B => B
C => C
D => D
E => E
);

,
,
,
,

--Add your stimulus here..

A
B
C
D

<=
<=
<=
<=

1
0
1
1

after
after
after
after

0
0
0
0

ns
ns
ns
ns

,
,
,
,

0
1
0
0

after
after
after
after

10
10
10
10

ns,
ns,
ns,
ns,

1
1
1
1

after
after
after
after

end test_arch;

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20
20
20
20

ns
ns
ns
ns

;
;
;
;

Half-Adder: Compiling, Elaborating, and Simulating

Half-Adder: Compiling, Elaborating, and Simulating

Note how the entity ece427_halfadder, whose architecture is specified in the file
ece427_halfadder.vhd, makes references to entities whose architecture is
defined in separate files. Specifically, the two components ece427_and and
ece427_or are specified in two separate files, ece427_and.vhd and
ece427_or.vhd respectively.
VHDL ENTITIES WITH NO
REFERENCES TO OTHER
ENTITIES SHOULD BE
COMPILED FIRST

Moreover, the rules specifying the order of compilation of VHDL units require
that the two files ece427_and.vhd and ece427_or.vhd be compiled prior to the
compilation of the file ece427_halfadder.vhd, which in turn, must be compiled
before the ece427_testbench.vhd file.

ANALYSING VHDL FILES

FOR HALFADDER CIRCUIT

Thus, we would analyze these files in the following order:

ncvhdl
ncvhdl
ncvhdl
ncvhdl

-linedebug
-linedebug
-linedebug
-linedebug

ece427_and.vhd
ece427_or.vhd
ece427_halfadder.vhd
ece427_testbench.vhd

As in earlier examples, it is possible to put all four files on one line:

ncvhdl -linedebug ece427_and.vhd ece427_or.vhd
ece427_halfadder.vhd ece427_testbench.vhd

FIGURE 14.

Using ncvhdl to analyze files comprising half-adder.

An actual example of using ncvhdl is shown above in Figure 14.

ELABORATION OF ENTITIES
AND ARCHITECTURE

Elaboration involves specifying not only the VHDL entity in question, but also
the specific architecture associated with that entity as well. The general form of
elaboration is:
ncelab {LIBRARY}.{entityname}.{architecture}

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27

Invoking the Design Simulator for Half-Adder Entity

However, since the Cadence configuration files already specify WORK as the
working location, i.e. your design library location, you dont have to specify the
library when elaborating entities you have already analyzed. However, if you
were using third party VHDL entities external to your project, then you might
have to include the library of interest as well as the entity and architecture.
ELABORATION COMMANDS

To elaborate, do the following:

ncelab
ncelab
ncelab
ncelab

ece427_and:and_arch
ece427_or:or_arch
ece427_halfadder:halfadder_arch
ece427_testbench:test_arch

FIGURE 15.

Using ncelab to elaborate files comprising half-adder.

An actual example of using ncelab is shown in Figure 15.

Invoking the Design Simulator for Half-Adder Entity

From the previous sections, you know that the logical AND, and logical OR
entities are used by the halfadder entity, and this entity is used by the testbench
entity, as diagrammed below:
AND
> HALFADDER > TESTBENCH
OR
FIGURE 16.

The hierarchy of VHDL entities for the half-adder circuit.

NOTE: A GIVEN VHDL

ENTITY CAN HAVE MORE
THAN ONE ARCHITECTURE
ASSOCIATED WITH IT

So, the entity that must be chosen when starting the simulator is the testbench
entity. Now, since there is only one architecture associated with the testbench
entity, the simulator will select this architecture for you. But if you did have dif-

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Invoking the Design Simulator for Half-Adder Entity

ferent architectures associated with a given entity, such as one for simulation,
and another for synthesis, then you would have to specify which one you
intended to use. It might be good practice to get into the habit of specifying the
architecture at the time you start the simulator, such as the following:
ncsim -gui ece427_testbench:test_arch

But, you can also use:

ncsim -gui ece427_testbench

And it will also work fine, since there is only one architecture, associated with
the ece427_testbench entity. The result of this command will give you the following screen:

FIGURE 17.

Using ncsim to examine the ece427_testbench entity/architecture.

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29

Examining the Waveform

Remember to select the signals, as discussed previously. See Invoking the

Waveform View on page 20. Then click the Waveform View button.

Examining the Waveform

After you press the Run button, on the simulator, you will see 30 ns of simulation, as directed in the testbench architecture description. You may review this
code if you need to. See ece427_testbench.vhd on page 26.

FIGURE 18.

SimVision shows the results of the simulation after 31 ns.

Now, if you look again at the command panel in Figure 17 on page 29, you will
see an additional command, put in to run the simulation for just 1 nanosecond
longer. The reason for this is to show the final values of the simulation graphically. The E signal goes high exactly at the 30 ns time, but since the simulation run ends at 30 ns, the final values can only be seen in the signal values
panel as shown in Figure 11 on page 21. So the command run 1 ns shown in
Figure 17, moves the simulation just a little further, so that the final values can
be seen. You could also simply adjust the commands in the testbench itself.
SIMULATION CURSORS

You can also move the red simulation cursors back and forth along the simulation time line and you will see the values change in the simulation values
panel to the left of the main wave form panel. This will allow you to easily follow the value transitions through time.

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Exercise for the Student: Exploring Scope in VHDL

Experiment with the different buttons that are there. Most of it is fairly intuitive,
and you can always consult the online help if you need to.

Exercise for the Student: Exploring Scope in VHDL

When a VHDL simulation is being run that consists of multiple entities joined
together, there are several levels at which one can look to see what is happening.
As the simulation proceeds, the simulation tools traverse the design hierarchy.
In the parlance of Cadence, the scope changes as the simulation recurses
through the VHDL structures that define the design.
Metaphorically, think of scope as a kind of window that the simulator sees of
the signal interfaces as it navigates through an arbitrarily complex VHDL
design linking many entities input and output signals.
While the half-adder is quite simple, more advanced designs could involve hierarchies dozens or hundreds of levels deep. As the simulator moves through the
Boolean logic, signal interfaces come into or out of scope1, or context of simulation.
NAVIGATING A
HIERARCHICAL DESIGN
WITH NCSIM

Even the simplest circuits will exhibit some hierarchy, and it is useful to move
around through this hierarchy to examine the values of signals which are contained in different parts of the design.
We will now explore various techniques used to navigate a hierarchical design.
The ncsim simulator makes traversing a hierarchical design very simple. Like
other simulator software, it uses a file system metaphor to derive its set of navigation commands, as the command panel of Figure 19 on page 32 will show.
However, you can also see the drop-down menus as well, and these are probably
easier for most people to navigate through their design.
Observe the command panel and the scope navigation drop-down menus. Use
these in conjunction with the single step and step over to recurse through a
complex design hierarchy when debugging.

1. Consider this physical analogy: moving a telescope across the sky has stars coming into and
out of its field of view, that is, its optical scope.

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Exercise for the Student: Exploring Scope in VHDL

OBSERVE THE COMMAND

PANEL AND THE SCOPE
NAVIGATION DROP-DOWN
MENUS.
USE THESE IN
CONJUNCTION WITH THE
SINGLE STEP AND STEP
OVER TO RECURSE
THROUGH A COMPLEX
DESIGN HIERARCHY WHEN
DEBUGGING.

FIGURE 19.

Using ncsim to examine the ece427_testbench entity/architecture.

We will leave it as an optional exercise for the student to experiment with simulation scope1, and how it can be used to follow signal propagation through a

1. Another example of scope: Most people with programming experience are familiar with the
idea of variables in a programming language being in scope when they are declared within a
particular function block of code, but that the variable cannot be referenced outside of the
function in which it is declared, because in effect it cannot be seen outside of the block in
which it was declared. In a similar way, when you change into a particular directory, and list
the contents your scope is limited to only the contents of that directory. You cannot see files or
directories deeper than where you currently are, because the scope of the directory tool is limited to what is in the current directory. Cadence ncvhdl has similar scoping rules when navigating the structures and interfaces of the VHDL circuit description.

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Exercise for the Student: Exploring Scope in VHDL

hierarchical design. This can be a valuable skill when debugging VHDL code.
Try to get comfortable with the idea of burrowing deep into a design hierarchy
and sampling signals buried within entities to make sure that you have your
VHDL logic expressed correctly.
Consider the following figure, and note the additional signals, s1 and s2. You
are no longer looking at things from the perspective of the testbench entity,
which used processes to drive some signals. Instead, you are some place else in
the hierarchy.
USE THE SCOPING MENUS
OR THE NAVIGATOR
BUTTON TO CHANGE
SCOPE AND MOVE
AROUND IN THE
HIERARCHY!

Since you have already written the VHDL for this exact entity, use the scoping
drop-down menus, or the Navigator to find your way to this entity, select the
signals, and run a simulation of it, so you can see the role played by the s1 and
s2 glue logic signals.

FIGURE 20.

SimVision shows the results of the simulation after 31 ns.

And if you are feeling adventurous, try milling about and starting more simulations and SimVision probes in different parts of the design hierarchy to get
really comfortable with things.
I have tried to make this tutorial as independent of actually being at the computer as possible, but not to replace going to the computer and trying things out.
Seriously, the best way to learn is not by reading, but by doing.

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33

Conclusion of the NC VHDL Tutorial

Conclusion of the NC VHDL Tutorial

This concludes the tutorial for using NC-VHDL tools in Cadence. The online
documentation for NC-VHDL is very good and extensive. Refer to this for any
detailed description on using the advanced options for compiling, simulation
and waveform viewing.
SEND COMMENTS TO
SANJAY!

And lastly, send comments, questions and suggestions to: [email protected] to improve this document.

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