THE 8088 AND 8086

MICROPROCESSORS AND
THEIR MEMORY AND
INPUT/OUTPUT INTERFACES

The 8088 And 8086 Microprocessors And

Their Memory And Input/output Interfaces
8.1 The 8088 and 8086 Microprocessors
8.2 Minimum-Mode and Maximum-Mode
System
8.3 Minimum-Mode Interface
8.4 Maximum-Mode Interface
8.5 Electrical Characteristics
8.6 System Clock
8.7 Bus Cycle and Time States
8.8 Hardware Organization of the Memory
Address Space
611 37100 Lecture 08-2

The 8088 And 8086 Microprocessors And

Their Memory And Input/output Interfaces
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18

Memory Bus Status Codes

Memory Control Signals
Read and Write Bus Cycles
Memory Interface Circuits
Programmable Logic Arrays
Types of Input/Output
An Isolated Input/Output Interface
Input/Output Data Transfer
Input/Output Instructions
Input/Output Bus Cycles

611 37100 Lecture 08-3

8.1 The 8088 and 8086

Microprocessors
The 8086, announced in 1978, was the first 16-bit

microprocessor introduced by Intel Corporation.

8086 and 8088 are internally 16-bit MPU. However,
externally the 8086 has a 16-bit data bus and the
8088 has an 8-bit data bus.

The 8088 microprocessor

611 37100 Lecture 08-4

8.1 The 8088 and 8086

Microprocessors
8086 and 8088 both have the ability to address up to

1 Mbyte of memory and 64K of input/output port.

The 8088 and 8086 are both manufactured using
high-performance metal-oxide semiconductor
(HMOS) technology.
The 8088 and 8086 are housed in a 40-pin dual inline package and many pins have multiple functions.

Intel D8086-1 Microprocessor

Processor Speed: 10.00 MHz
Bus Speed: 10.00 MHz
FPU: no
SOURCE:http://cpu-museum.de/

611 37100 Lecture 08-5

8.1 The 8088 and 8086

Microprocessors

8088
CPU

Pin layout of the 8086 and 8088 microprocessor

611 37100 Lecture 08-6

8.2 Minimum-Mode and MaximumMode System

The 8086 and 8088 microprocessors can be

configured to work in either of two modes:

The minimum mode The maximum mode -

MN/MX = 1
MN/MX = 0

The mode selection feature lets the 8088 or 8086

better meet the needs of a wide variety of system

requirement.
Minimum mode 8088/8086 systems are typically
smaller and contain a single processor.
Depending on the mode of operation selected, the
assignment for a number of the pins on the
microprocessor package are changed.
611 37100 Lecture 08-7

8.2 Minimum-Mode and MaximumMode System

Signals common to both minimum and maximum mode

611 37100 Lecture 08-8

8.2 Minimum-Mode and MaximumMode System

Unique minimum-mode signals

611 37100 Lecture 08-9

8.2 Minimum-Mode and MaximumMode System

Unique maximum-mode signals

611 37100 Lecture 08-10

8.2 Minimum-Mode and MaximumMode System

EXAMPLE
Which pins provide different signal functions in the
minimum-mode 8088 and minimum-mode 8086?

Solution:
(a) Pins 2 through 8 on the 8088 are address lines A14

through A8, but on the 8086 they are address/data

lines AD14 through AD8.
(b) Pin 28 on the 8088 is IO/M output and on the 8086
it is the M/IO output.
(c) Pin 34 of the 8088 is the SSO output, and on the
8086 this pin supplies the BHE/S7.
611 37100 Lecture 08-11

8.3 Minimum-Mode Interface

Block diagram of the minimum-mode 8088 MPU

611 37100 Lecture 08-12

8.3 Minimum-Mode Interface

Block diagram of the minimum-mode 8086 MPU

611 37100 Lecture 08-13

8.3 Minimum-Mode Interface

The minimum-mode signals can be divided into the

following basic groups:

Address/Data bus
Status signals
Control signals
Interrupt signals
DMA interface signals

611 37100 Lecture 08-14

8.3 Minimum-Mode Interface

Address/Data bus
The address bus is used to carry address
information to the memory and I/O ports.
The address bus is 20-bit long and consists of
signal lines A0 through A19.
A 20-bit address gives the 8088 a 1 Mbyte
memory address space.
Only address line A0 through A15 are used when
addressing I/O. This give an I/O address space of
64 Kbytes.
The 8088 has 8 multiplexed address/data bus
lines (A0~A7) while 8086 has 16 multiplexed
address/data bus lines (A0~A15).
611 37100 Lecture 08-15

8.3 Minimum-Mode Interface

Status signals
The four most significant address, A19 through A16
are multiplexed with status signal S6 through S3.
Bits S4 and S3 together form a 2-bit binary code
that identifies which of the internal segment
registers was used to generate the physical
address. S5 is the logic level of the internal
interrupt flag. S6 is always at the 0 logic level.
S4

S3

Address Status

Alternate (relative to the ES segment)

Stack (relative to the SS segment)

Code/None (relative to the CS segment or a default of zero

Data (relative to the DS segment)

611 37100 Lecture 08-16

8.3 Minimum-Mode Interface

Control signals
The control signals are provided to support the memory
and I/O interfaces of the 8088 and 8086.
ALE Address Latch Enable
IO/M IO/Memory (8088)
M/IO Memory/IO (8086)
DT/R Data Transmit/Receive (8088/8086)
SSO System Status Output (8088)
BHE Bank High Enable (8086)
RD Read (8088/8086)
WR Write (8088/8086)
DEN Data Enable (8088/8086)
READY Ready (8088/8086)
611 37100 Lecture 08-17

8.3 Minimum-Mode Interface

Interrupt signals
The interrupt signals can be used by an external
device to signal that it needs to be serviced.

INTR Interrupt Request

INTA Interrupt Acknowledge
TEST Test (can be use to synchronize MPU)
NMI Nonmaskable Interrupt
RESET Reset (hardware reset of the MPU)

611 37100 Lecture 08-18

8.3 Minimum-Mode Interface

DMA interface signals
When an external device wants to take control of
the system bus, it signals this fact to the MPU by
switching HOLD to the 1 logic level.
When in the hold state, signal lines AD0 through
AD7, A8 through A15, A16/S3 through A19/S6, SSO,
IO/M, DT/R, RD, WR, DEN, and INTR are all put
into high-Z state.
The 8088 signals external devices that the signal
lines are in the high-Z state by switch its HLDA
output to the 1 logic level.

611 37100 Lecture 08-19

8.4 Maximum-Mode Interface

The maximum-mode configuration is mainly

used for implementing a

multiprocessor/coprocessor system
environment.
Global resources and local resources
In the maximum-mode, facilities are provided
for implementing allocation of global
resources and passing bus control to other
microprocessors sharing the system bus.

611 37100 Lecture 08-20

10

8.4 Maximum-Mode Interface

8288 bus controller

8088 maximum-mode block diagram

611 37100 Lecture 08-21

8.4 Maximum-Mode Interface

8288 bus controller

8086 maximum-mode block diagram

611 37100 Lecture 08-22

11

8.4 Maximum-Mode Interface

8288 bus controller
In the maximum-mode, 8088/8086 outputs a
status code on three signal line, S0, S1, S2, prior to
the initialization of each bus cycle.
The 3-bit bus status code identifies which type of
bus cycle is to follow and are input to the external
bus controller device, 8288.
The 8288 produces one or two command signals
for each bus cycle.

611 37100 Lecture 08-23

8.4 Maximum-Mode Interface

8288 bus controller
Status Inputs

CPU Cycle

8288 Command

S2

S1

S0

Interrupt Acknowledge

INTR

Read I/O Port

IORC

Write I/O Port

IOWC, AIOWC

Halt

None

Instruction Fetch

MRDC

Read Memory

MRDC

Write Memory

MWTC, AMWC

Passive

None

Bus status code

611 37100 Lecture 08-24

12

8.4 Maximum-Mode Interface

8288 bus controller

Block diagram and pin layout of 8288

611 37100 Lecture 08-25

8.4 Maximum-Mode Interface

Lock signal
The lock signal (LOCK) is meant to be output
(logic 0) whenever the processor wants to lock out
the other processor from using the bus.
Local bus control signals
The request/grant signals (RQ/GT0, RQ/GT1)
provide a prioritized bus access mechanism for
accessing the local bus.

611 37100 Lecture 08-26

13

8.4 Maximum-Mode Interface

Queue status signals
The 2-bit queue status code QS0 and QS1 tells the
external circuitry what type of information was removed
form the queue during the previous clock cycle.
QS1

QS0

Queue Status

0 (low)

No Operation. During the last clock cycle,

nothing was taken form the queue.

First byte. The byte taken from the queue

was the first byte of the instruction.

1 (high)

Queue Empty. The queue has been

reinitialized as a result of the execution of a
transfer of instruction.

Subsequent Byte. The byte taken from the

queue was a subsequent byte of the
instruction.

Queue status code

611 37100 Lecture 08-27

8.4 Maximum-Mode Interface

EXAMPLE
If the bus status code S2S1S0 equals 101, what type of bus
activity is taking place? Which command output is produced by the
8288?

Solution:
Looking at the bus status table, we see that bus status code
101 identifies a read memory bus cycle and causes the MRDC
output of the bus controller to switch to logic 0.

611 37100 Lecture 08-28

14

8.5 Electrical Characteristics

Power is applied between pin 40 (Vcc) and pins 1

(GND) and 20 (GND).

The nominal value of Vcc is specified as +5V dc with a
tolerance of 10%.
Both 8088 and 8086 draw a maximum of 340mA from
the supply.
Symbol

Meaning

Minimum

Maximum

VIL

Input low voltage

-0.5 V

+0.8 V

VIH

Input high voltage

+2.0 V

Vcc+ 0.5 V

VOL

Output low voltage

VOH

Output high voltage

+0.45 V
+2.4 V

Test
condition

IOL=2.0 mA
IOH=-400 A

I/O voltage levels

611 37100 Lecture 08-29

8.6 System Clock

The time base for synchronization of the internal and

external operations of the microprocessor in a

microcomputer system is provided by the clock (CLK)
input signal.
The standard 8088 operates at 5 MHz and the 80882 operates at 8 MHz.
The 8086 is manufactured in three speeds: 5-MHz
8086, 8-MHz 8086-2, and the 10-MHz 8086-1.
The CLK is externally generated by the 8284 clock
generator and driver IC.

611 37100 Lecture 08-30

15

8.6 System Clock

Block diagram of the 8284 clock generator

611 37100 Lecture 08-31

8.6 System Clock

Connecting the 8284 to the 8088

15- or 24MHz
crystal

Typical value of
CL when used
with 15MHz
crystal is 12pF

611 37100 Lecture 08-32

The fundamental crystal

frequency is divided by 3
within the 8284 to give either
a 5- or 8-MHz clock signal

16

8.6 System Clock

CLK waveform
The signal is specified at Metal Oxide
Semiconductor (MOS)-compatible voltage level.
The period of the 5-MHz 8088 can range from 200
ns to 500 ns, and the maximum rise and fall times
of its edges equal 10 ns.

611 37100 Lecture 08-33

8.6 System Clock

PCLK and OSC signals
The peripheral clock (PCLK) and oscillator clock
(OSC) signals are provides to drive peripheral ICs.
The clock output at PCLK is half the frequency of
CLK. The OSC output is at the crystal frequency
which is three times of CLK.

611 37100 Lecture 08-34

17

8.6 System Clock

EXAMPLE
If the CLK input of an 8086 MPU is to be driven by a 9-MHz
signal, what speed version of the 8086 must be used and what
frequency crystal must be attached to the 8284

Solution:
The 8086-1 is the version of the 8086 that can be run at 9-MHz.
To create the 9-MHz clock, a 27 MHz crystal must be used on the
8284.

611 37100 Lecture 08-35

8.7 Bus Cycle and Time States

A bus cycle defines the basic operation that a

microprocessor performs to communicate with

external devices.
Examples of bus cycles are the memory read,
memory write, input/output read, and input/output
write.
The bus cycle of the 8088 and 8086 microprocessors
consists of at least four clock periods.
If no bus cycles are required, the microprocessor
performs what are known as idle states.
When READY is held at the 0 level, wait states are
inserted between states T3 and T4 of the bus cycle.

611 37100 Lecture 08-36

18

8.7 Bus Cycle and Time States

Bus cycle clock periods, idle state, and wait state

611 37100 Lecture 08-37

8.7 Bus Cycle and Time States

EXAMPLE
What is the duration of the bus cycle in the 8088-based
microcomputer if the clock is 8 MHz and the two wait states are
inserted.

Solution:
The duration of the bus cycle in an 8 MHz system is given by
tcyc = 500 ns + N x 125 ns
In this expression the N stands for the number of waits states. For
a bus cycle with two wait states, we get
tcyc = 500 ns + 2 x 125 ns = 500 ns + 250 ns
= 750 ns

611 37100 Lecture 08-38

19

8.8 Hardware Organization of the

Memory Address Space
1M BYTES

FFFFF
FFFFF

2
1
0

A19 A0

D7 D0

1Mx8 memory bank of the 8088

611 37100 Lecture 08-39

8.8 Hardware Organization of the

Memory Address Space

A19 A1

512K BYTES

512K BYTES

FFFFF
FFFFD

FFFFE
FFFFC

D15 D8

BHE

D7 D0

A0

High and low memory banks of the 8086

611 37100 Lecture 08-40

20

8.8 Hardware Organization of the

Memory Address Space
Transfer X

X+1
(X)

A19 A0

D7 D0

Byte transfer by the 8088

611 37100 Lecture 08-41

8.8 Hardware Organization of the

Memory Address Space
First bus cycle

A19 A0

Second bus cycle

X+1

X+1

(X)

(X)

D7 D0

A19 A0

D7 D0

Word transfer by the 8088

611 37100 Lecture 08-42

21

8.8 Hardware Organization of the

Memory Address Space
Transfer X

A19 A1

Y+1

X+1

(X)

D15 D8

BHE (HIGH)

D7 D0

A0 (LOW)

Even address byte transfer by the 8086

611 37100 Lecture 08-43

8.8 Hardware Organization of the

Memory Address Space
Transfer X+1

A19 A1

Y+1

(X+1)

D15 D8

BHE (LOW)

D7 D0

A0 (HIGH)

Odd address byte transfer by the 8086

611 37100 Lecture 08-44

22

8.8 Hardware Organization of the

Memory Address Space
Transfer X, X+1

A19 A1

Y+1

(X+1)

(X)

D15 D8

BHE (LOW)

D7 D0

A0 (LOW)

Even address word transfer by the 8086

611 37100 Lecture 08-45

8.8 Hardware Organization of the

Memory Address Space
First bus cycle

A19 A1

Second bus cycle

X+3

X+2

X+3

X+2

(X+1)

(X)

(X+1)

(X)

D15 D8

BHE (LOW)

D7 D0

A0 (HIGH)

A19 A1

D15 D8

BHE (HIGH)

D7 D0

A0 (LOW)

Odd-address word transfer by the 8086

611 37100 Lecture 08-46

23

8.8 Hardware Organization of the

Memory Address Space
EXAMPLE
Is the word at memory address 0123116 of an 8086-based
microcomputer aligned or misaligned? How many cycle are
required to read it from memory?

Solution:
The first byte of the word is the second byte at the aligned-word
address 0123016. Therefore, the word is misaligned and required
two bus cycles to be read from memory.

611 37100 Lecture 08-47

8.9 Address Bus Status Codes

Whenever a memory bus cycle is in progress, an

address bus status code S4S3 is output by the

processor.
S4S3 identifies which one of the four segment
register is used to generate the physical address in
the current bus cycle:
S4S3=00 identifies the extra segment register
S4S3=01 identifies the stack segment register
S4S3=10 identifies the code segment register
S4S3=11 identifies the data segment register

The memory address reach of the microprocessor

can thus be expanded to 4Mbytes.

611 37100 Lecture 08-48

24

8.10 Memory Control Signals

Minimum-mode memory control signals

Minimum-mode 8088 memory interface

611 37100 Lecture 08-49

8.10 Memory Control Signals

Minimum-mode memory control signals (8088)
ALE Address Latch Enable used to latch the address in
external memory.
IO/M Input-Output/Memory signal external circuitry
whether a memory of I/O bus cycle is in progress.
DT/R Data Transmit/Receive signal external circuitry
whether the 8088 is transmitting or receiving data over the
bus.
RD Read identifies that a read bus cycle is in progress.
WR Write identifies that a write bus cycle is in progress.
DEN Data Enable used to enable the data bus.
SSO Status Line identifies whether a code or data
access is in progress.

611 37100 Lecture 08-50

25

8.10 Memory Control Signals

The control signals for the 8086s minimum-mode

memory interface differs in three ways:

IO/M signal is replaced by M/IO signal.
The signal SSO is removed from the interface.
BHE (bank high enable) is added to the interface
and is used to select input for the high bank of
memory in the 8086s memory subsystem.

611 37100 Lecture 08-51

8.10 Memory Control Signals

Maximum-mode memory control signals

Maximum-mode 8088 memory interface

611 37100 Lecture 08-52

26

8.10 Memory Control Signals

Maximum-mode memory control signals
MRDC Memory Read Command
MWTC Memory Write Command
AMWC Advanced Memory Write Command
Status Inputs

CPU Cycle

8288 Command

S2

S1

S0

Interrupt Acknowledge

INTA

Read I/O Port

IORC

Write I/O Port

IOWC, AIOWC

Halt

None

Instruction Fetch

MRDC

Read Memory

MRDC

Write Memory

MWTC, AMWC

Passive

None

611 37100 Lecture 08-53

8.11 Read and Write Bus Cycle

Read cycle

Minimum-mode memory read bus cycle of the 8088

611 37100 Lecture 08-54

27

8.11 Read and Write Bus Cycle

Read cycle

Minimum-mode memory read bus cycle of the 8086

611 37100 Lecture 08-55

8.11 Read and Write Bus Cycle

Read cycle

Maximum-mode memory read bus cycle of the 8086

611 37100 Lecture 08-56

28

8.11 Read and Write Bus Cycle

Write cycle

Minimum-mode memory write bus cycle of the 8088

611 37100 Lecture 08-57

8.11 Read and Write Bus Cycle

Write cycle

Maximum-mode memory write bus cycle of the 8086

611 37100 Lecture 08-58

29

8.12 Memory Interface Circuit

Address bus latches and buffers
Bank write and bank read control logic
Data bus transceivers/buffers
Address decoders

611 37100 Lecture 08-59

8.12 Memory Interface Circuit

Memory interface block diagram

611 37100 Lecture 08-60

30

8.12 Memory Interface Circuit

Address bus latches and buffers
Operation of the 74F373
Inputs

Output

OC

Enable C

Q0

Block diagram of a D-type latch

611 37100 Lecture 08-61

8.12 Memory Interface Circuit

Address bus latches and buffers

Circuit diagram of the 74F373

611 37100 Lecture 08-62

31

8.12 Memory Interface Circuit

Address bus latches and buffers

Address latch circuit

611 37100 Lecture 08-63

8.12 Memory Interface Circuit

Bank write and bank read control logic

Bank write control logic

Bank read control logic

611 37100 Lecture 08-64

32

8.12 Memory Interface Circuit

Bank write and bank read control logic

Block diagram and circuit diagram of the

74F245 octal bus transceiver
611 37100 Lecture 08-65

8.12 Memory Interface Circuit

Bank write and bank read control logic

Data bus transceiver circuit

611 37100 Lecture 08-66

33

8.12 Memory Interface Circuit

Address decoder

Address bus configuration with address decoding

611 37100 Lecture 08-67

8.12 Memory Interface Circuit

Address decoder

INPUTS
ENABLE

OUTPUTS

SELECT

Y0

Y1

Y2

Y3

Block diagram and operation of the 74F139 decoder

611 37100 Lecture 08-68

34

8.12 Memory Interface Circuit

Address decoder

Circuit diagram of the 74F139 decoder

611 37100 Lecture 08-69

8.12 Memory Interface Circuit

Address decoder

Address decoder circuit using 74F139

611 37100 Lecture 08-70

35

8.12 Memory Interface Circuit

Address decoder

Block diagram and operation of the 74F138 decoder

611 37100 Lecture 08-71

8.12 Memory Interface Circuit

Address decoder

Circuit diagram of the 74F138 decoder

611 37100 Lecture 08-72

36

8.12 Memory Interface Circuit

Address decoder

Address decoder circuit using 74F138

611 37100 Lecture 08-73

8.13 Programmable Logic Arrays

Programmable logic array, PLA, are general-

purpose logic devices that have the ability to perform

a wide variety of specialized logic functions.
A PLA contains a general-purpose AND-OR-NOT
array of logic gate circuits.
The process used to connect or disconnect inputs of
the AND gate array is known as programming, which
leads to the name programmable logic array.

611 37100 Lecture 08-74

37

8.13 Programmable Logic Arrays

PLAs, GALs, and EPLDs
Early PLA devices were all manufactured with the
bipolar semiconductor process.
Bipolar devices are programmed with an
interconnect pattern by burning out fuse links
within the device.
PLAs made with bipolar technology are
characterized by slower operating speeds and
higher power consumption.
Two kinds of newer PLA, manufactured with the
CMOS process, are in wide use today: the GAL
and EPLD.
611 37100 Lecture 08-75

8.13 Programmable Logic Arrays

Block diagram of a PLA
The logic levels applied at inputs I0 through I15 and the
programming of the AND array determine what logic levels
are produced at outputs F0 through F15.
The capacity of a PLA is measured by three properties: the
number of inputs, the number of outputs, and the number of
product terms (P-terms)

Block diagram of a PLA

611 37100 Lecture 08-76

38

8.13 Programmable Logic Arrays

Architecture of a PLA

611 37100 Lecture 08-77

8.13 Programmable Logic Arrays

Architecture of a PLA

(a) Typical PLA architecture. (b) PLA with output latch

611 37100 Lecture 08-78

39

8.13 Programmable Logic Arrays

Standard PALTM device
A PAL, programmable array logic, is a PLA in
which the OR array is fixed; only the AND array is
programmable.
The 16L8 is a widely used PAL IC. It is housed in
a 20-pin package. It has 10 dedicated input, 2
dedicated outputs, and 6 programmable I/O lines.
The 16L8 is manufactured with bipolar technology.
It operates from a +5V10% dc power supply and
draw a maximum of 180mA.
The 20L8 has 20 inputs, 8 outputs and 64 P-terms.
The 20R8 is the register output version of 20L8.
611 37100 Lecture 08-79

8.13 Programmable Logic Arrays

Standard PALTM device

16L8 circuit diagram and pin layout

611 37100 Lecture 08-80

40

8.13 Programmable Logic Arrays

Standard PALTM device

20L8 circuit diagram and pin layout

611 37100 Lecture 08-81

8.13 Programmable Logic Arrays

Standard PALTM device

16R8 circuit diagram and pin layout

611 37100 Lecture 08-82

41

8.13 Programmable Logic Arrays

Standard PALTM device

20R8 circuit diagram and pin layout

611 37100 Lecture 08-83

8.13 Programmable Logic Arrays

Expanding PLA capacity

Expanding output word length

611 37100 Lecture 08-84

Expanding input word length

42

8.14 Types of Input/Output

Isolated input/output
When using isolated I/O in a microcomputer
system, the I/O device are treated separate from
memory.
The memory address space contains 1 M
consecutive byte address in the range 0000016
through FFFFF16; and that the I/O address space
contains 64K consecutive byte addresses in the
range 000016 through FFFF16.
All input and output data transfers must take place
between the AL or AX register and I/O port.

611 37100 Lecture 08-85

8.14 Types of Input/Output

Isolated input/output

8088/8086 memory and I/O address spaces

611 37100 Lecture 08-86

43

8.14 Types of Input/Output

Memory-mapped input/output
In the case of memory-mapped I/O, MPU looks at
the I/O port as though it is a storage location in
memory.
Some of the memory address apace is dedicated
to I/O ports.
Instructions that affect data in memory are used
instead of the special I/O instructions.
The memory instructions tend to execute slower
than those specifically designed for isolated I/O.

611 37100 Lecture 08-87

8.14 Types of Input/Output

Memory-mapped input/output

Isolated I/O ports

611 37100 Lecture 08-88

44

8.14 Types of Input/Output

Memory-mapped input/output

Memory mapped I/O ports

611 37100 Lecture 08-89

8.15 Isolated Input/Output Interface

I/O devices:
Keyboard
Printer
Mouse
82C55A, etc.

Functions of interface circuit:

Select the I/O port
Latch output data
Sample input data
Synchronize data transfer
Translate between TTL voltage levels and those required to
operate the I/O devices.

611 37100 Lecture 08-90

45

8.15 Isolated Input/Output Interface

Minimum-mode interface

Minimum-mode 8088 system I/O interface

611 37100 Lecture 08-91

8.15 Isolated Input/Output Interface

Minimum-mode interface

Minimum-mode 8086 system I/O interface

611 37100 Lecture 08-92

46

8.15 Isolated Input/Output Interface

Maximum-mode interface

Maximum-mode 8088 system I/O interface

611 37100 Lecture 08-93

8.15 Isolated Input/Output Interface

Maximum-mode interface

Maximum-mode 8086 system I/O interface

611 37100 Lecture 08-94

47

8.15 Isolated Input/Output Interface

Maximum-mode interface
Status Inputs

CPU Cycle

8288 Command

S2

S1

S0

Interrupt Acknowledge

INTA

Read I/O Port

IORC

Write I/O Port

IOWC, AIOWC

Halt

None

Instruction Fetch

MRDC

Read Memory

MRDC

Write Memory

MWTC, AMWC

Passive

None

I/O bus cycle status codes

611 37100 Lecture 08-95

8.16 Input/Output Data Transfers

Input/output data transfers in the 8088 and 8086

microcomputers can be either byte-wide or word-wide.

I/O addresses are 16 bits in length and are output by
the 8088 to the I/O interface over bus lines AD0
through AD7 and A8 through A15.
In 8088, the word transfers is performed as two
consecutive byte-wide data transfer and takes two
bus cycle.
In 8086, the word transfers can takes either one or
two bus cycle.
Word-wide I/O ports should be aligned at evenaddress boundaries.

611 37100 Lecture 08-96

48

8.17 Input/Output Instructions

Mnemonic
IN

OUT

Meaning

Operation

Flags affected

Input direct

IN Port, Acc

(Acc) (Port)
Acc = AL or AX

Input indirect (variable)

IN DX, Acc

(Acc) ((DX))

Output direct

OUT Port, Acc

(Port) (Acc)

Output indirect (variable) OUT DX, Acc

611 37100 Lecture 08-97

((DX)) (Acc)

8.17 Input/Output Instructions

EXAMPLE
Write a sequence of instructions that will output the data FF16
to a byte-wide output port at address AB16 of the I/O address space.

Solution:
First, the AL register is loaded with FF16 as an immediate
operand in the instruction
MOV AL, 0FFH
Now the data in AL can be output to the byte-wide output port with
the instruction
OUT 0ABH, AL

611 37100 Lecture 08-98

49

8.17 Input/Output Instructions

EXAMPLE
Write a series of instructions that will output FF16 to an output
port located at address B00016 of the I/O address space.

Solution:
The DX register must first be loaded with the address of the
output port. This is done with the instruction
MOV DX, 0B000H
Next, the data that are to be output must be loaded into AL with the
instruction
MOV AL, 0FFH
Finally, the data are output with the instruction
OUT DX, AL

611 37100 Lecture 08-99

8.17 Input/Output Instructions

EXAMPLE
Data are to be read in from two byte-wide input ports at
addresses AA16 and A916 and then output as a word-wide output
port at address B00016. Write a sequence of instructions to perform
this input/output operation.

Solution:
First read in the byte at address AA16 into AL and move it into AH.
IN
AL, 0AAH
MOV AH, AL
Now the other byte can be read into AL by the instruction
IN
AL, 09AH
And to write out the word of data
MOV DX, 0B000H
OUT DX, AX

611 37100 Lecture 08-100

50

8.18 Input/Output Bus Cycle

Input bus cycle of the 8088

611 37100 Lecture 08-101

8.18 Input/Output Bus Cycle

Output bus cycle of the 8088

611 37100 Lecture 08-102

51

8.18 Input/Output Bus Cycle

Input bus cycle of the 8086

611 37100 Lecture 08-103

8.18 Input/Output Bus Cycle

Output bus cycle of the 8086

611 37100 Lecture 08-104

52