Design Flow of Nios Ii Processopr Using Qsys: Software and Hardware Requirements
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Soundarya SvsDesign Flow of Nios Ii Processopr Using Qsys: Software and Hardware Requirements
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Soundarya SvsDESIGN FLOW OF NIOS II PROCESSOPR USING QSYS
In this session explains about design flow of Nios II processor and Quartus II
software to implementation for digital picture viewer in a cyclone III FPGA. For this
we need system specifications for both software as well as hardware.
Software and Hardware Requirements:
NEEK development board
Quartus II software v11.0, including the following items:
o Quartus II FPGA synthesis and compilation tool
o Qsys system integration tool
o Mega Core IP library
o Nios II EDS, featuring the Nios II Software Build Tools (SBT) for
Eclipse
Design flow Qsys:
48.1 Figure for design flow
In this flow, you specify the system definition using Qsys. After you define
the Qsys system, Qsys generates the following two kinds of output.
o
The HDL files that the Quartus II software compiles to generate the
configuration file for the FPGA. This Quartus II compilation process is the
hardware flow.
A system description that the software development tools use to generate a
system library specific to the Qsys system. This system library, also called
a board support package, supports the Nios II processor in running the
software. The Nios II SBT for Eclipse provides an environment in which
you can develop software applications for your system. This Nios II SBT
development process is the software flow.
The output of the hardware flow is an FPGA image that configures the target
device. The output of the software flow is an executable file that the Nios II
processor can run.
In this tutorial you perform the following
steps:
1. Build Qsys system
o
Open the Quartus II
o
o
project.
Start Qsys.
Select and configure system components, including IP Mega Core
o
o
o
functions.
Make connections.
Assign clocks and set base addresses.
Set interrupt and arbitration priorities.
2. Generate the system to create the following items:
HDL for the entire Qsys system.
A system description files that software development tools use to build
the hardware drivers and other relevant system information for the
software application.
3. Complete the Quartus II project:
Add the Qsys system to the top level of the Quartus II
project.
Add pin assignments.
Compile the project to generate an SRAM Object File
(.sof).
Use the Quartus II Programmer to download the .sof to the
FPGA.
4. Develop the software application:
Start the Nios II SBT for Eclipse.
Add source files.
Configure build properties.
Build the application to generate the Executable and
Linking Format File (.elf).
5. Use the Flash Programmer to convert the image files to flash memory image files
(.flash) and download the flash image data to CFI flash memory.
6. Use the Nios II SBT for Eclipse to download and run the .elf for the
software application.
Block diagram of Digital picture viewer:
48.2 block diagram of Qsys
Hardware components and their performance:
Component Component Instance
Nios II
Cpu
Name
Processor
Generic Tri-State Flash
Compo
Runs the software that controls
nent the system.
Controls the timing for driving read and writes
transactions on the external CFI flash memory. The
CFI flash memory device stores the JPEG images for
Tri-State Conduit
Bridge
DDR
flash_bridge
Connects the flash memory controller to the external
SDRAM
ddr_sdram
Stores execute code and data in the frame buffers.
Controller
Allows the Nios II_SBT to verify that the software
System ID
Avalon-MM
Sysid
Clock
slow_clock_crossing_br domain to the slower-frequency peripherals.
is built for the correct hardware version.
Connects the processor in the high-frequency
PIO (Parallel I/O) lcd_i2c_scl
idge
PIO (Parallel I/O) lcd_i2c_en
PIO (Parallel I/O) lcd_i2c_sdat
interface includes, a clock signal, and an enable signal.
PIO (Parallel I/O) pio_id_eeprom_scl
Two-wire EEPROM ID interface components. The I2C
PIO (Parallel I/O) pio_id_eeprom_dat
serial EEPROM ID chip stores information about the
Refer to Implementing an LCD Controller.
board,
including
the touch
screen calibration
SPI (3 Wire
touch_panel_spi
Touch screen
interface
components.
Refer to data.
PIO
(Parallel I/O) touch_panel_pen_irq Implementing an LCD Controller.
Serial)
_n
JTAG UART
jtag_uart
Enables software to access a debug serial port.
Enables software to perform periodic interrupts for
Interval timer
Scatter-Gather
sys_clk_timer
maintenance and to maintain software application
DMA
Sgdma
timing requirements.
Controls the video pipeline components.
Controller
Avalon-ST
Timing
On-Chip
Avalon-ST
Memory
timer_adapter_0
Fifo
timer_adapter_1
Timing
Pixel Converter
(BGR0 -> BGR) pixel_converter
Avalon-ST Data
Video pipeline components. Refer to
Format Adapter data_format_adapter Implementing an LCD Controller.
Video Sync
video_sync_generato
48.1
Generator
r table for components and their functioning
Specify the External Clocks and Clock Connections:
In this section, you connect each component to the correct clock.
The clock source for the full digital picture viewer is the 50-MHz oscillator
on the NEEK board. The 50-MHz oscillator is also the reference clock frequency
for the DDR SDRAM controller, which runs at 100 MHz. The 100-MHz clock from
the DDR SDRAM is used by most components in the system, including the
processor, the flash controller, and the video subsystem. Only the slow-frequency
components in the peripheral subsystem run at 50 MHz, using the oscillator clock.
48.3 show the Qsys Clock Settings tab with available clocks for the system.
Specify the Reset Connections:
This design has a single reset coming into the Qsys system, namely, the
clk_reset port of osc_clk. Connect the components in the system to this main reset
by clicking on the connection dot between the clk_reset port of osc_clk and the
following component ports:
The reset port of flash_bridge
The reset_50 port of peripheral_subsystem
The reset_100 port of peripheral_subsystem
The reset port of sysid
The reset_n port of cpu
The soft_reset_n port of ddr_sdram
The global_reset_n port of ddr_sdr
he reset port of flash
The reset_n port of video_subsystem
Reassign the Component Base Addresses to Eliminate Memory Conflicts:
To reassign component base addresses to eliminate undesired overlap
between the address spaces of different components, perform the following steps:
1. On the System menu, click Assign Base Addresses. Qsys assigns
appropriate base addresses for the components.
2. Reassign the following base addresses to the Avalon Memory-Mapped
(Avalon-MM) slave ports of the following components
For the jtag_debug_module port of cpu, type 0x1000000.
For the uas port of flash, type 0x00000000.
For the s1 port of ddr_sdram, type 0x2000000.
For the sgdma_csr port of video_subsystem, type 0x5000000.
For the slow_clock_crosing_bridge port of peripheral_subsystem, type
0x4000000.
For the control_slave port of sysid, type 0x10008000.
Set the Interrupt Priorities:
To render images on the LCD screen smoothly, the sgdma component of
the video subsystem must continuously service the frame buffer without stalling.
When the sgdma component completes a transaction, it must be updated
immediately by the Nios II processor. Therefore, sgdma must have the highest
interrupt priority, followed by the timer, jtag_uart, and touch-screen components.
The lowest interrupt value indicates the highest interrupt priority. Assign interrupt
priorities to the system components by performing the following steps for each
interrupt-request (IRQ) port listed in Table 48.2:
1. Click the System Contents tab.
2. On the left edge of the System Contents tab, click the filter icon. The
Filters dialog box appears.
3. In the Filter list, select All Interfaces.
4. Close the Filters dialog box.
5. For each port specified in Table 48.2, perform the following steps:
In the IRQ column, double-click the connection dot.
Type the interrupt priority value from Table 48.2.
48.2 Table for interrupt priority.
Set the Arbitration Priorities:
To ensure that the video pipeline operates smoothly, you must assign the
highest arbitration priority to sgdma accesses to ddr_sdram. In addition, because
the heap memory is located in DDR SDRAM, you must increase the arbitration
priority of the Nios II processor for ddr_sdram to support more back-to-back data
transactions.
To assign arbitration priorities among the components in your system,
perform the following steps:
1. Right-click anywhere on the System Contents tab, and click Show
Arbitration Shares. The connection panel displays the arbitration priority of each
master for each slave to which it is connected. By default, Qsys assigns arbitration
priority 1 for each connected master-slave pair.
3. For each master-slave connection in Table 48.3, double-click the box that
represents the connection and type the new value from the table.
