Microwave

Office®
For Modules
 The combination of the integrated Microwave Office
Advancing the State environment and accurate Cree device models enabled
of High-Frequency me to achieve a design in a matter of days that
Design Automation simulated to within a few percent of my measured
output power and achieved greater than 85% PAE.
Michael Boers, Macquarie University

System Speed and innovation. Work harder faster. These are the goals that AWR
Design
adheres to for our flagship Microwave Office design environment. We are RF/
microwave engineers ourselves, and we know all too well the demanding RF
module design requirements you must meet, and the intense pressure you
Circuit are under to deliver solutions that work at frequency and deliver the innovative
Design
features your customers demand. And not only do you have to produce complex
LVS/DRC
designs that meet specs, you also have to deliver them fast – before design
windows shrink or competitors beat you to it. Outside-the-box thinking is required
if you want your modules to perform better than the competition. Miss the
design window – in time or features--and you’re left out of the game.
Simulation
Extraction & Analysis For you and for AWR, successful module design is about orchestrating a variety
of independently-designed circuits to work together harmoniously where the whole
Layout is greater than the sum of the parts. Each individual circuit may be a masterpiece
in its own right, but if improperly used or designed in isolation, is likely to result
Much more than a design tool, Microwave in a suboptimal module. Successful module design requires co-design -- co-design
Office software is a complete design flow of at least one monolithic microwave integrated circuit (MMIC) die, sometimes
offering all of the essential technologies: several, and in multiple process technologies, in a package of yet another process
linear and nonlinear circuit simulators, EM technology, and, finally, perhaps even onto the printed circuit board (PCB).
analysis tools, layout-vs.-schematic checks,
the awr module design flow edge
statistical design capabilities, and parametric
cell libraries with built-in DRC. The Microwave Office design environment delivers the industry’s most innovative
tools for RF module design, with the most intuitive user interface, and the most
complete integration with third party point tools and technologies—enabling
engineers to solve tough, modern design problems and maintain their competitive
advantage against fierce competition. The AWR user experience is not just a
collection of tools and technology but rather an integrated, cohesive design flow
engineered from ‘Day One’ to maximize productivity and minimize the need for time
investment, manual intervention, and training.

Schematic “and” layout - not schematic “or” layout Many tool vendors believe
that if you can just electrically simulate the whole design then you are on your
way to a successful module design. Not necessarily so. The issue with this train
of thought is that as increasingly challenging RF module performance criteria
push the boundaries of electrical design, layout dependencies increase, and,
consequently, competitive module design now requires more than simply an all-out
electrical simulation. Under these circumstances, co-design, or, more accurately,
multi-domain concurrency, means that simulation, layout, and electromagnetic
(EM) must work in unison, as well as integrating with system simulation, design
rule check (DRC), and layout-vs.-schematic (LVS).

Co-design of the Module Modules are first and foremost defined by the space
they are allotted, and today’s handset power amplifier/front-end modules (PA/
FEMs) are arguably the area where the boundaries are being
 Microwave Office, with APLAC simulation
technology, is renowned for its speed and
convergence, allowing module designers to
power through the most complex simulations.

pushed more than anyplace else when it comes to minimal space. Mm-wave modules
are challenging in their own right because of the need to appropriately size and
separate features. While the MMICs in the module may be designed in a very top-
down, schematic-driven methodology, the module interconnects are so constrained
for space and the electrical performance criteria so demanding that layout-driven
simulation seems a natural approach. Designers need to do much more than just
update schematic parameter values from the layout for microstrips--they need to
use powerful, layout-based model generation and fast EM simulation, followed by
accurate EM analysis for post-layout verification. And trade-offs among MMIC or RFIC
functionality, matching, and performance require a similar layout-based approach to
fit within form-factor and manufacturing constraints. With so many circuits coming
together, and the necessity for it all to be done in the schematic, layout, EM, and
verification stages, only AWR’s Microwave Office software – with it’s trend-setting
ease-of-use and real-time tuning and optimization, schematic-driven EM, and access
to all the industry-leading technology you need – can take you through IC design and
module integration, and into manufacturing quickly and efficiently.

user-flexible design Environment

While other software tools hold customers captive to their way of doing things,
AWR has built Microwave Office from the ground up based on the idea of a flexible
architecture that encourages additional and alternative solutions that empower
successful module design. Your flow demands the flexibility to continue using, or to add
third-party point tools, and to integrate to adjacent flows like test or enterprise PCB.
All of these requirements are possible with the Microwave Office module design flow.

Multi-technology PDKs - At the core of the Microwave Office software is a Unified

Data Model™ (UDM) that is neither an IC nor PCB database, but instead takes
on the form needed based on the process design kits
(PDKs) loaded into it. If just a gallium arsenide (GaAs)
heterojunction biopolar transistor (HBT) PDK is loaded,
than the UDM is a complete design environment across
all the design flow domains—schematic, simulation,
layout, EM and extraction, DRC and LVS—for MMIC
design. If a four-layer laminate PDK is added to the HBT
PDK, then the two can be co-designed through simulation
and layout, with complete representations available at
all times. Multiple IC PDKs, including silicon germanium
(SiGe) or silicon complimentary metal oxide semiconductor
(Si CMOS), can be added along with other MMIC
technologies and surface mount device (SMD) passives
and packaging to achieve total circuit and system,
schematic and layout co-design.

Microwave Office software simultaneously loads all necessary PDKs to

represent various technologies used in designing this power amplifier.
 www.awrcorp.com
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USA A HOST OF INNOVATIVE TECHNOLOGIES

Corporate Headquarters
AWR Corporation APLAC® harmonic balance and transient The incomparable APLAC circuit
1960 E. Grand Avenue, Suite 430 simulator combines linear and nonlinear frequency-domain simulation with

El Segundo, CA 90245 time-domain transient. Renowned for its speed and convergence on the

+1 310 726 3000

toughest problems, APLAC simulates in minutes where others take hours, if,
in fact, they converge at all. Large problems, like full-up module verification,
+1 310 726 3005 (fax)
are no problem for APLAC.
Japan The EXTRACT™ flow The EXTRACT flow within AWR’s Microwave Office design
AWR Japan KK
environment makes life so much easier by allowing EM and circuit extraction
Level 5, 711 Building
to be controlled by the schematic; there is no need to go to the layout and
7-11-18 Nishi-Shinjuku, Shinjuku-ku launch EM as a separate step from the schematic and the resulting high
Tokyo 160-0023 Japan port-count S-parameter file does not need to magically and manually
+81 3 5937 4803 be knit back into the schematic. Consequently, there are no errors
in “integrating” EM back into the circuit and system simulation.
Korea
With the EXTRACT flow, EM is a seamless and integral part of
AWR Korea Co. Ltd.
tuning, optimization, and statistical analysis, ultimately saving
B-1412, Intellige-II, 24 Jeongja-dong,
you hours or days of time.
Bundang-gu, Seongnam-si,
Gyeonggi-do, South Korea, 463-811 ACE™ circuit extraction ACE, AWR’s unique automated

+82.31.603.7772~3 circuit extraction technology, is another breakthrough AWR

technology that essentially creates netlists of distributed
UK models, many containing optimized EM solvers, from
AWR UK arbitrary interconnects. Using AWR’s interconnect (Intelligent
2 Hunting Gate Net™) routing technology combined with microstrip lines,
Hitchin, Herts discontinuities, and even printed inductors. Diagnosing critical
SG4 0TJ, UK couplings is a breeze with ACE. By creating parameterized netlists
+44 (0) 1462 428 428 using distributed models, ACE powers through your layout to create the
same models you would have created in the schematic, but 10,000x faster
Finland than any alternative approach.
AWR – APLAC
AXIEM™ 3D planar EM technology The revolutionary AXIEM product is the
Lars Sonckin kaari 16
industry’s first solver to enable to enable user-discretion – speed and accuracy
FI-02600 Espoo, Finland
trade-offs of the design from DC up through millimeter wave. AXIEM’s flexibility
+358 10 834 5900
as both an in-situ EM solver for modeling as well as post-layout electrical
France verification means that there’s no need to change any setup information other
AWR France than specifying accuracy and speed as the design progresses from concept
140 Avenue Champs Elysees to final layout. AXIEM reduces cycle time with and saves infrastructure costs
75008 Paris, France because it is the only planar 3D EM solver needed.
+33 1 70 36 19 63

Copyright © 2010 AWR Corporation. All rights reserved. AWR and the AWR logo, Microwave Office and
APLAC are registered trademarks and Visual System Simulator, AXIEM, ACE, AWR Design Environment,
EXTRACT, Unified Data Model, and Intelligent Net are trademarks of AWR Corporation.
All others are the property of their respective holders.
BR-MWO-MODULE-2010.5.10