1.

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(14 points) Mark each of the following statements as either (T)rue or (F)alse.
a)

_____________

In a load/store architecture, arithmetic operations can operate on data located in

memory.

b)

_____________

To store a given amount of data, direct mapped caches are typically smaller than
either set associative or fully associative caches, assuming that the block size for
each cache is the same

c)

___________

A machine with 32 general purpose registers requires 6 bits to encode a register

number

d)

____________

DRAMs usually save pins by sharing the row and column address inputs on the
same pins

e)

____________

A RISC computer will typically require more instructions than a CISC computer
to implement a given program.

f)

____________

Adding two signed numbers of the same sign will never cause an overflow.

g)

___________

Memory address register (MAR)contains a word of data to be written to memory

or the word most recently read

h)

____________

DRAMs need to be refreshed periodically (~milliseconds) so that their data does

not dissipate.

i)

____________

Direct mapping technique maps each block of main memory into more than one
possible cache line.

j)

____________

With one-address instruction, the accumulator is the only general purpose

register used.

k)

____________

SRAM is generally faster, denser, and more expensive than DRAM.

l)

____________

RISC ISAs allow for more compact code.

m)

____________

The range of negative integers in n-bit 2s complement representation is

from 1 to 2n-1

n)

____________

DRAM is made with cells that store data as charge on capacitors

Computer Architecture

Final Exam

2. (10 points) Matching game

a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
k)
l)
m)

Register addressing
Immediate addressing
Indirect Address
Floating point
Direct mapping
Instruction fetch
Direct access
Overflow
Amdahls Law
Addressing
Underflow
Address space
Mantissa

On the left side, write the letter corresponding to the word that best fits the definition to the right. Not all
words will be used.
Maps each block of main memory into only one possible cache line.
When a result is too large to be represented in a given format.
The address field refers to a register that contains the operand.
The mode or modes by which the address of an operand is specified
The value of the operand is in the instruction.
Individual blocks or records have a unique address based on
physical location
Read instruction from its memory location into the processor
An address of a storage location that contains an address
The range of addresses (memory, I/O) that can be referenced
Speedup is limited by the fraction which is not optimized

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Computer Architecture

Final Exam

3. (10 points) Given the bit pattern

1111 0000 0000 0000 0000 0000 0000 0000
What does it represent assuming that it is?
a. (2 points) A twos complement integer

b. (2 points) An unsigned integer

c. (3 points) An IEEE 754 single-precision floating point number

d. (3 points) Show the IEEE 754 binary representation of the number 3.75 in single precision.

4. (10 points) Below are two sets of 6-bit twos complement numbers.

(a)

Convert the numbers to decimal

Perform the addition
Indicate whether there is a carry out
Indicate if an overflow has occurred
100011
+111101

Decimal Value: _____________

Decimal Value: _____________

Total
Carry Out _________
Overflow __________
(b)

101101
+110001

Decimal Value: _____________

Decimal Value: ______________

Total
Carry Out _________
Overflow ________

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Computer Architecture

Final Exam

5. (15 points) Internal Memory

a. (5 points) In the table below, place an X for the best match between a property in the first column
and either DRAM or SRAM in the top row.
DRAM

SRAM

Fast access
Slow reading
High costs
Slow access
Large area
Low power
Fast switching
High power
Small area
Low costs
b. (6 points) Fill in the cells of the following table.
Memory Chip

Total # of bytes

# of address lines
to decode address

# data lines

64M x 16
2G x 8

c. (4 points) Given 64K x 8 is the only memory chip available, how many chips are needed for
designing a 16M x 32 memory

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Computer Architecture

Final Exam

6. (6 points) Match the address mode to its corresponding addressing mode diagram
Address Mode
Diagram

Address Mode
Immediate
Direct
Indirect
Register
Register Indirect
Displacement (Indexed)
Instruction
Opcode

Instruction

Address A

Opcode

Memory

Address A

Memory
Pointer to operand

Operand

Operand

(b)

(a)
Instruction
Opcode Register R Address A

Memory
Instruction

Registers

Opcode

Pointer to Operand

Operand

Operand

(d)

(c)
Instruction
Opcode

Instruction

Register Address R

Registers

Opcode

Register Address R

Memory

Registers

Operand

Pointer to Operand

(f)

(e)

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Operand

Computer Architecture

Final Exam

7. (6 points) Consider a three stage pipeline (fetch, decode, execute) instruction. Draw the timing diagram
to show how many time units are needed for executing a program with 5 instructions. Assume no
branches in the program and that all stages execute in equal time.
a. (2 points) What is the execution time of the program in the absence of pipelining

b. (2 points) What is the execution time (in time units) of the program with pipelining

c. (2 points) What is the performance improvement

8. (6 points) Given the following assembly program, how many cycles does it take to execute on:
i) a multi-cycle machine (no pipelining)
ii) an 8-stage pipelined machine

label

add
sub
lw
slt
sw

$1,$2,$3
$2,$3,$4
$1,0x00($10)
$20,$21,$22
$22,0x00($30)
Instruction Type
Arithmetic
Load
Store
Branch
Logical

Number of
Cycles to Execute
5
7
6
9
11

Execution time for multi-cycle machine: ________________________

Execution time for pipelined machine: __________________________

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Computer Architecture

Final Exam

9. (6 points) Consider the following MIPS code and the initial content of the registers and the memory.
Show the contents of registers and memory after the code is executed.

exit:

lw
lw
srl
bne
add
add
sw

$1, 0($1)
$1, 0($1)
$3, $1, 4
$2, $3, exit
$1, $2, $0
$2, $3, $0
$1, 0($4)
BEFORE

REGISTERS
$0
0
$1
116
$2
32
$3
0
$4
104

MEMORY
100
0
104
0
108
514
112
0
116
108
AFTER

REGISTERS
$0
$1
$2
$3
$4

MEMORY
100
104
108
112
116

10. (5 points) Show the binary equivalent of the following MIPS instructions by filling in the space
provided below (all registers are specified using their register number $0-$31). Also mark the
boundaries between the fields (e.g., opcode, etc.) and show the names of the fields.
sub

$5, $6, $7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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Computer Architecture

Final Exam

11. (6 points) Consider a machine with a byte accessible main memory of 256K bytes and block size of 4
bytes. Assume a direct mapped cache consisting of 128 lines in used with this machine
a. How is the memory address divided into tag, line number, and byte number? Illustrate with a
diagram

b. Into what line would bytes with each of the following addresses be stored? The addresses are in hex.
Give your answers in hex.
2C96
61FB c. Suppose the byte with address A043 (in hex) is stored in the cache. What are the addresses of the
other bytes stored along with it? Give your answer in hex.

12. (6 points) Consider a machine with a byte accessible main memory of 64K bytes and block size of 4
bytes. Assume that a 4-way set associative cache with 8K bytes is used with this machine.
d. How is a 16-bit memory address divided into tag, line/set number, and byte/word number?

e. Into what line/set will bytes with each of the following addresses (in hex) be stored? The addresses
are in hex. Give your answers in hex.
5AE3
81CD
f. Suppose the byte with address 1234 (in hex) is stored in the cache. What are the addresses of the
other bytes stored along with it? Give your answer in hex.

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Computer Architecture

Final Exam

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Computer Architecture

Final Exam

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Computer Architecture

Final Exam