THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

ECNG 3016
ADVANCED DIGITAL ELECTRONICS
http://myelearning.sta.uwi.edu/course/view.php?id=686
Semester II 2010

1.

GENERAL INFORMATION
Lab #:
Name of the Lab:

Practical 3
Using a Keypad Encoder to Illustrate Writing Testbenches in VHDL using Xilinx
ISim Simulator
0%
Estimated total study
3
hours1:

Lecture

Online
 Lab

Other

Lab Weighting:
Delivery mode:

Venue for the Lab:

Microprocessor Laboratory

Lab Dependencies2

The theoretical background to this lab is provided in ECNG 3016

Theoretical content link: given at top of page
Pre-Requisites ECNG 2004
To undertake this lab, students should be able to:
1. Use of Xilinx ISE in the implementation of digital system
2. VHDL for synthesis and simulation

Recommended prior
knowledge and
skills3:
Course Staff

Position/Role

Cathy Radix

Lecturer

E-mail

[email protected]

Azim Abdool

Instructor

[email protected]

Phone

x3157

x2636

Office

Office
Hours
Rm
321, Mon/Tue
Blk 1
11am 2pm
Rm 341/ Mon/
RTSG, Blk 1 Thu
11am12pm

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

2.

LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to:
1. Create VHDL testbenches using the ISim simulator in Xilinx ISE to test simple
VHDL circuits

2. Use the property of self checking testbenches to verify simple VHDL

designs
3. Design and implement a keypad encoder in VHDL to meet a required
specification.

3.

Cognitive Level
Ap
Ap
Ap, Sy

PRE-LAB

Due Date:
Submission
Procedure:
Estimated time to
completion:

NA
-

3.1. Required Reading Resources

Xilinx Application Note 199: Writing Effective Testbenches.

3.2. Pre-Lab Exercise

Create a project in Xilinx ISE Webpack. The project should conform to the project settings as illustrated.

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

Figure 1: Project Settings

Be sure when creating your project the simulator options should be set as shown. For this lab we are
utilizing the ISim simulator in VHDL.
You are first required to build a keypad encoder module in VHDL that would conform to the specifications as
given by the following table.

Table 1 below shows the data format that is recognized by the keypad encoder:

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

Table 1: Keypad Character Code

Create an encoder module that would take as input the 12 bit code output of the keypad module as an
input and produce a 4-bit coded word output that represents the key pressed. If either a * or # was pressed,
output 0. The module should latch the last key pressed. Use the language template version of an encoder
module as a guide.

Synthesize your design. Ensure that there are no synthesis errors or warnings. Read the generated timing
report.

For the project (so far) what is the maximum synthesizable frequency?

Would this meet the constraint imposed by the 50MHz clock on the Spartan 3 development board?

What must the setup time and hold time constraints be, according to the timing report?

Now well move on to testing your design using a VHDL written testbench using the ISim simulator.

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

Add a VHDL testbench to your design.

The webpack should automatically generate a file with template code filled.

This testbench file acts as a driver module which would present a set of inputs to your DUT (device under
test), in this case, the encoder module. There should be two main processes generated, one which controls
the toggling of the clock signal and the other for you to fill out with the stimulus which you are providing.
For the first process, the clock signal generation, fill in the constraint for the clock period. What is the clock
period on the Spartan 3 development board? Since we will be using this board for testing, well utilize this
constraint within the simulator.

For the stimulus process that is generated, fill in the following:

-- Stimulus process
stim_proc: process
begin
wait for clk_period*10;
reset <= '1';
wait for 40 ns;
reset<= '0';
keys_i <= "001000000000";
wait for 100 ns;
keys_i <= "000000000000";
wait;
end process;

Note that the above is a simple example of an absolute time test. Now we can also in our simple example
create a self checking testbench.

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

Fill in another process which verifies the behaviour with a file.

chk_results: process
variable tmpkeysout: std_logic_vector(3 downto 0);
variable l: line;
variable good_val, good_number, errordet: boolean;
variable r : real;
variable vector_time: time;
variable space: character;
file vector_file: text is in "values.txt";
variable err_cnt : integer := 0;
begin
err_cnt := 0;
while not endfile(vector_file) loop
readline(vector_file, l);
read(l, r, good => good_number);
next when not good_number;
vector_time := r * 1 ns;
if (now < vector_time) then
wait for vector_time - now;
end if;
read(l, space);
read(l, tmpkeysout, good_val);
assert good_val REPORT "bad output value of key_enc_o in file";
if (tmpkeysout /= key_enc_o) then
err_cnt := err_cnt + 1;
assert errordet REPORT "vector mismatch";
end if;
end loop;
if (err_cnt = 0) then
report "Simulation successful. No errors detected.";
else
report "Simulation has errors detected. Deviation from golden vector file.";
end if;
wait;
end process;

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

The file which it verifies with is named values.txt and should be put into the working directory. The content
of the file is given as:

-- Vector file containing expected results

220 0000
240 0000
251 0100
289 0100
340 0100
400 0100
460 0100
520 0100
580 0100
640 0100
700 0100
760 0100
820 0100
880 0100
940 0100
1000 0100
Draw a testbench output to verify that this is the behaviour that is truly expected and there were no errors
in its conception.

Run the testbench simulation model at the behavioural simulation level. If everything was done correctly to
this point there should be a successful simulation output.

View the testbench waveform. Ensure that you can run the model from the ISim window and zoom in and
out of the result waveform. Look at the console output and verify that the testbench reported that there
were no deviations from the given simulation file.

Try next running at the Post Place and Route simulation level. Does this simulation still meet the expected
output given in the values.txt file?

What went wrong?

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

Why do you think this is?

Look at the report summary for the Post Place and Route Static Timing Report. For the particular net that
we are investigating, what are the timing analysis reports? Pay particular attention to the clock to pad
section within the report. For that matter, what is a clock to pad time? Do the numbers presented here
correlate with what is seen on the testbench output?

If this is the case, what should your golden vector file truly represent?

Rewrite your testbench to fully test the encoder module. What test vectors should you run? For each key?
What if multiple keys are pressed?

It is important that you plan ahead and know what you want before you test for it. This is to ensure that
your final design meets some predetermined constraints. For example, what if this were a design which had
to run on a 100MHz clock in the end. After adding all of your modules, would it meet that constraint?

After you have finally finished creating your module and testing to ensure that it meets the constraint of the
50MHz clock on the Spartan 3 board, create a decoder module which would take as an output your 4bit
coded output and decode it to match a 7-segment display output.

The idea would be to display your result on one of the 4 seven segment displays on the Spartan 3
development board. You can use the language templates to assist with this.

Draw a diagram depicting the interconnections between your encoder and decoder modules. Be sure to
show all of the inputs and outputs. Be sure to set only one of the anodes as being on all of the time while
taking off all of the others. For simplicity, we can create this decoder module as a totally asynchronous
module.

Create testbenches for the decoder module and ensure that this module meets functional requirements.

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

Map the encoder and decoder together and ensure that the final system meets your requirements.
Create a ucf which has the following constraints:

Design Port

FPGA Pin to be mapped to

Clk
Reset
keys(0)
keys(1)
keys(2)
keys(3)
keys(4)
keys(5)
keys(6)
keys(7)
keys(8)
keys(9)
keys(10)
keys(11)
anode(0)
anode(1)
anode(2)
anode(3)
seg(0)
seg(1)
seg(2)
seg(3)
seg(4)
seg(5)
seg(6)

T9
any available pushbutton
D11
R10
C12
T7
D12
R7
E11
N6
B16
M6
R3
C15
D14
G14
F14
E13
Dependent on your encoding scheme
Dependent on your encoding scheme
Dependent on your encoding scheme
Dependent on your encoding scheme
Dependent on your encoding scheme
Dependent on your encoding scheme
Dependent on your encoding scheme

Table 2: Pin Configuration for the Keypad Encoder system

What is the maximum static post PAR timing that you would expect from any of the seven segment PADs?
What is the maximum frequency at which you can run your system?
Does this meet the constraint of the Spartan 3 development board?

Lab 1c: Keypad Encoding

4.

IN-LAB

Allotted Completion
Time:
Required lab
Equipment:

3 hours
1 Computer
1 Spartan 3 Toolkit
1 keypad + 40-pin ribbon cable circuit(completely wired)

4.1. In-Lab Procedure

Now we have simulated the design up till this point. However, there are some hardware constraints
which must be taken into consideration when completing your design.
At this point we know that our design would take a key that is pressed according to the one-hot keypad
output and be translated to a 7-segment output.
However, what about the specific voltages and currents that are presented to the FPGA pin?
Consult your datasheet. What is the maximum permissible current and voltage levels which can be
sourced/sunk by the FPGA pins?
Do the keypad output pins need debouncing? What would be an appropriate debounce time?
Add in a module to debounce the switches at the debounce rate that you have determined.
You can use the language templates to assist with this (VHDL -> Synthesis Constructs -> Coding Examples
-> Misc -> Debounce).
After mapping together your entire system, download on to the Spartan 3 development board.
Does it work as expected?

10

Lab 1c: Keypad Encoding

Proceed to post-lab exercise.

11

Lab 1c: Keypad Encoding

5.

POST-LAB

A signed plagiarism declaration form must be submitted with your assignment.

Due Date:
Submission
Procedure:
Deliverables:

NA
-

End of Practical 3: Simple

Testbenches

12