INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT162
Presettable synchronous BCD
decade counter; synchronous reset
Product specification December 1990
File under Integrated Circuits, IC06
Philips Semiconductors Product specification

Presettable synchronous BCD decade

74HC/HCT162
counter; synchronous reset

FEATURES that the set-up and hold time requirements for PE are met).
Preset takes place regardless of the levels at count enable
• Synchronous counting and loading
inputs (CEP and CET).
• Two count enable inputs for n-bit cascading
For the “162” the clear function is synchronous.
• Positive-edge triggered clock
A LOW level at the master reset input (MR) sets all four
• Synchronous reset outputs of the flip-flops (Q0 to Q3) to LOW level after the
next positive-going transition on the clock (CP) input
• Output capability: standard
(provided that the set-up and hold time requirements for
• ICC category: MSI MR are met). This action occurs regardless of the levels at
PE, CET and CEP inputs.
This synchronous reset feature enables the designer to
GENERAL DESCRIPTION modify the maximum count with only one external NAND
The 74HC/HCT162 are high-speed Si-gate CMOS devices gate.
and are pin compatible with low power Schottky TTL The look-ahead carry simplifies serial cascading of the
(LSTTL). They are specified in compliance with JEDEC counters. Both count enable inputs (CEP and CET) must
standard no. 7A. be HIGH to count. The CET input is fed forward to enable
The 74HC/HCT162 are synchronous presettable decade the terminal count output (TC). The TC output thus
counters which feature an internal look-ahead carry and enabled will produce a HIGH output pulse of a duration
can be used for high-speed counting. approximately equal to a HIGH level output of Q0. This
Synchronous operation is provided by having all flip-flops pulse can be used to enable the next cascaded stage.
clocked simultaneously on the positive-going edge of the The maximum clock frequency for the cascaded counters
clock (CP). is determined by the CP to TC propagation delay and CEP
The outputs (Q0 to Q3) of the counters may be preset to a to CP set-up time, according to the following formula:
HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the 1
fmax = --------------------------------------------------------------------------------------------------------
data at the data inputs (D0 to D3) to be loaded into the t P ( max ) ( CP to TC ) + t SU (CEP to CP)
counter on the positive-going edge of the clock (providing

QUICK REFERENCE DATA Notes

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 1. CPD is used to determine the
dynamic power dissipation
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT (PD in µW):
HC HCT PD = CPD × VCC2 × fi +
tPHL propagation delay CL = 15 pF; ∑ (CL × VCC2 × fo)
CP to Qn VCC = 5 V 19 20 ns where:
CP to TC 21 26 ns fi = input frequency in MHz
CET to TC 11 15 ns
fo = output frequency in MHz
tPLH propagation delay
∑ (CL × VCC2 × fo) = sum of
CP to Qn 19 20 ns
outputs
CP to TC 21 19 ns
CET to TC 11 10 ns CL = output load capacitance in
pF
fmax maximum clock 63 32 MHz
frequency VCC = supply voltage in V
CI input capacitance 3.5 3.5 pF 2. For HC the condition is
CPD power dissipation notes 1 and 2 37 37 pF VI = GND to VCC
capacitance per package For HCT the condition is
VI = GND to VCC − 1.5 V

December 1990 2
Philips Semiconductors Product specification

Presettable synchronous BCD decade

74HC/HCT162
counter; synchronous reset

ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 MR synchronous master reset (active LOW)
2 CP clock input (LOW-to-HIGH, edge-triggered)
3, 4, 5, 6 D0 to D3 data inputs
7 CEP count enable input
8 GND ground (0 V)
9 PE parallel enable input (active LOW)
10 CET count enable carry input
14, 13, 12, 11 Q0 to Q3 flip-flop outputs
15 TC terminal count output
16 VCC positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3
Philips Semiconductors Product specification

Presettable synchronous BCD decade

74HC/HCT162
counter; synchronous reset

Fig.4 Functional diagram.

FUNCTION TABLE

INPUTS OUTPUTS
OPERATING MODE
MR CP CEP CET PE Dn Qn TC
reset (clear) I ↑ X X X X L L
parallel load h ↑ X X I I L L
h ↑ X X I h H (1)

count h ↑ h h h X count (1)

hold h X I X h X qn (1)

(do nothing) h X X I h X qn L
Notes
1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH).
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition

December 1990 4
Philips Semiconductors Product specification

Presettable synchronous BCD decade

74HC/HCT162
counter; synchronous reset

Fig.5 State diagram.

Fig.6 Typical timing sequence: reset outputs to zero; preset to BCD seven; count to eight, nine, zero, one, two
and three; inhibit.

December 1990 5
Philips Semiconductors Product specification

Presettable synchronous BCD decade

74HC/HCT162
counter; synchronous reset

Fig.7 Logic diagram.

December 1990 6
Philips Semiconductors Product specification

Presettable synchronous BCD decade

74HC/HCT162
counter; synchronous reset

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

Tamb (°C) TEST CONDITIONS

74HC
SYMBOL PARAMETER UNIT VCC WAVEFORMS
+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay 58 190 240 285 ns 2.0 Fig.8
CP to Qn 21 38 48 57 4.5
17 32 41 48 6.0
tPHL/ tPLH propagation delay 69 215 270 325 ns 2.0 Fig.8
CP to TC 25 43 54 65 4.5
20 37 46 55 6.0
tPHL/ tPLH propagation delay 39 150 190 225 ns 2.0 Fig.9
CET to TC 14 30 38 45 4.5
11 26 33 38 6.0
tTHL/ tTLH output transition 19 75 95 110 ns 2.0 Figs 8 and 9
time 7 15 19 22 4.5
6 13 16 19 6.0
tW clock pulse width 80 22 100 120 ns 2.0 Fig.8
HIGH or LOW 16 8 20 24 4.5
14 6 17 20 6.0
tsu set-up time 100 28 125 150 ns 2.0 Figs 9 and 11
MR, Dn to CP 20 10 25 30 4.5
17 8 21 26 6.0
tsu set-up time 135 39 170 205 ns 2.0 Fig.9
PE to CP 27 14 34 41 4.5
23 11 29 35 6.0
tsu set-up time 200 69 250 300 ns 2.0 Fig.12
CEP, CET to CP 40 25 50 60 4.5
34 20 43 51 6.0
th hold time 0 −17 0 0 ns 2.0 Figs 9, 11 and
Dn, PE, CEP, 0 −6 0 0 4.5 12
CET, MR to CP 0 −5 0 0 6.0
fmax maximum clock 6.0 19 4.8 4.0 MHz 2.0 Fig.8
pulse 30 57 24 20 4.5
frequency 35 68 28 24 6.0

December 1990 7
Philips Semiconductors Product specification

Presettable synchronous BCD decade

74HC/HCT162
counter; synchronous reset

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

MR 0.95
CP 0.80
CEP 0.25
Dn 0.25
CET 1.50
PE 0.30

December 1990 8
Philips Semiconductors Product specification

Presettable synchronous BCD decade

74HC/HCT162
counter; synchronous reset

AC CHARACTERISTICS FOR HCT

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

Tamb (°C) TEST CONDITIONS

74HCT
SYMBOL PARAMETER +25 −40 to +85 −40 UNIT VCC WAVEFORMS
to +125 (V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay 24 43 54 65 ns 4.5 Fig.8
CP to Qn
tPHL propagation delay 30 51 64 77 ns 4.5 Fig.8
CP to TC
tPLH propagation delay 22 45 56 68 ns 4.5 Fig.8
CP to TC
tPHL propagation delay 18 35 44 53 ns 4.5 Fig.9
CET to TC
tPLH propagation delay 12 24 30 36 ns 4.5 Fig.9
CET to TC
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 8 and 9

tW clock pulse width 16 7 20 24 ns 4.5 Fig.8

HIGH or LOW
tsu set-up time 20 9 25 30 ns 4.5 Fig.9
Dn to CP
tsu set-up time 35 16 44 53 ns 4.5 Fig.9
PE to CP
tsu set-up time 40 23 50 60 ns 4.5 Fig.12
CEP, CET to CP
tsu set-up time 20 12 25 30 ns 4.5 Fig.11
MR to CP
th hold time 0 −10 0 0 ns 4.5 Figs 9, 11 and 12
Dn, PE, CEP,
CET, MR to CP
fmax maximum clock 17 29 14 11 MHz 4.5 Fig.8
pulse frequency

December 1990 9
Philips Semiconductors Product specification

Presettable synchronous BCD decade

74HC/HCT162
counter; synchronous reset

AC WAVEFORMS

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.8 Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the
output transition times and the maximum clock frequency.

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.9 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times.

The shaded areas indicate when the input is permitted to

change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.10 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input (PE).

December 1990 10
Philips Semiconductors Product specification

Presettable synchronous BCD decade

74HC/HCT162
counter; synchronous reset

The shaded areas indicate when the input is permitted to

change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.11 Waveforms showing the MR set-up and hold times.

The shaded areas indicate when the input is permitted

to change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.12 Waveforms showing the CEP and CET set-up and hold times.

APPLICATION INFORMATION
The HC/HCT162 facilitate designing counters of any modulus with minimal external logic.
The output is glitch-free due to the synchronous reset.

Fig.13 Modulo-5 counter.

PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990 11
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