Session A1 Communication Networks and Services Research Conference 2003 1

Integrated RF/DSP Designs Using Software Radios:

A Modern Approach to Radio Engineering
[Overview Paper]
Jacek Ilow
Dalhousie University
Department of Electrical and Computer Eng.
Halifax, Nova Scotia, B3J 2S4
[email protected]

ABSTRACT 1. INTRODUCTION
Software defined radios (SDRs) represent a major change The basic concepts behind software radios have been re-
in the wireless transceiver design paradigm in which a large searched and implemented in practice for more than a de-
portion of the transceiver functionality is implemented thr- cade [1]—[4]. During the 1980’s and the 1990’s the ad-
ough programmable digital signal processors or field pro- vances in DSP and ADCs allowed to have the baseband
grammable gate arrays (FPGAs). A software radio approach signal processing implemented on specialized DSP proces-
reduces the content of radio frequency (RF) and other ana- sors for voiceband telephone modems. There is currently a
log components of traditional radios and emphasizes digital resurgence of interest in software defined radios as the ever
signal processing (DSP) to enhance overall transceiver flex- increasing sampling rates of ADC and clock rates of DSP
ibility. cores allow to move the DSP functions closer to antenna
In the past, the choice for the software/digital hardware and the IF stages of transceivers [5], [6].
platforms to implement SDRs was mainly determined by A software radio is a transceiver whose channel modu-
the processor clock rates and the speeds of analog-to-digital lation waveforms are defined in software and implemented
converters (ADC), though lately there are additional vari- on a DSP or FPGA platform using DACs [7]—[9]. Fig. 1
ables that influence this decision. To bridge the gap be- shows the architecture of a generic software radio. Software
tween system engineering and hardware design in matching defined radios (SDRs) are designed for applications ranging
the transceiver complexity to real-time processing capability from low-power hand-held devices to fixed basestations. As
of digital hardware, design tools have been developed that a result, at present, they employ different technologies and
automate the translation from system algorithms to silicon architectures. One of the driving objectives underlying SDR
design flows. These Electronic Design Automation (EDA) concepts today is the desire to have a single platform capable
tools enable rapid prototyping of transceivers and are be- of servicing a number of radio environments. In general, the
coming critical factors in the quest to reduce design costs hardware platforms have the following components: (i) I/O
and time to market. subsystems; (ii) the transmission methodology; and (iii) the
The objective of this paper is to elaborate on some aspects programming environment. The SDR platform focused in
of this new RF/DSP design paradigm. this paper (i) provides a framework for the investigation
into the baseband and IF stages of radio transceivers with
Categories and Subject Descriptors signal bandwidths up to 20MHz and (ii) is versatile enough
B.4 [Input/Output and Data Communications]: Data to demonstrate proof-of-concept for a number of radio in-
Communications Devices; C.2.1 [Network Architecture terfaces.
and Design]: Wireless communication Software radio research has been primarily motivated by
interoperability problems that result from the implemen-
General Terms tation of radios in dedicated hardware [10]. In advanced
Algorithms, Design applications, in addition to more traditional tasks of (de)
modulating waveforms at the baseband, SDRs (i) probe and
Keywords characterize radio channels; (ii) adaptively select power lev-
Software defined radios, EDA, rapid prototyping els and steers antenna; (iii) recognize the mode of incoming
transmission; and (iv) null interferes and combine multi-
path signals. For example, in order to improve the spectrum
Permission to make digital or hard copies of all or part of this work for utilization and to achieve robust communications, the At-
personal or classroom use is granted without fee provided that copies are lantic Innovation Fund (AIF) project lead by this author
not made or distributed for profit or commercial advantage and that copies in the area of SDRs will investigate the implementation
bear this notice and the full citation on the first page. To copy otherwise, to
republish, to post on servers or to redistribute to lists, requires prior specific of algorithms able to exploit and manage the characteris-
permission and/or a fee. tics of the channel and variable data transfer demands us-
CNSR 2003 Conference, May 15-16, 2003, Moncton, New Brunswick, ing advanced channel coding techniques. Even though the
Canada. clock-rates of DSP systems are significantly increasing every
Copyright 2003 CNSR Project 1-55131-080-5 ...$5.00.
2 CNSR 2003, Moncton, New Brunswick, Canada Session A1

Figure 1: Generic Software Radio Architecture.

year, the more sophisticated algorithms and more complex the market. This shows a trend that DSPs are becoming
software invariably require the use of parallel and sequen- ubiquitous in electronics, and that more and more support
tial partitioning of algorithms to get the required processing and/or sophisticated functions are performed by DSPs.
power. The integrated software and hardware tools devel- Fortunately, when dealing with these complex DSP chips
oped within the AIF project should be efficient in realizing and DSP platforms, thanks to an array of preconfigured and
these latest trends of multitasking and multiprocessing in customizable DSP boards and related software, the designer
embedded system designs. is not starting from scratch. Reuse of Intellectual Property
(IP) cores becomes a necessity to benefit from more com-
2. SOFTWARE/HARDWARE PLATFORMS plex hardware platforms. Representative examples of wire-
less designs using DSP processors are discussed in [11], with
Determining the digital hardware composition of a SDR
the DSP lead chip TMS320C6xxx from TI [12]. The most
is a key design step. Basically, three major factors define
exciting development in the DSP boards is not the boards
the choice of the digital hardware platform:
themselves, but rather, it is the support that companies offer
1. flexibility and configurability of hardware/software com- surrounding their products.
ponents;
2.2 FPGA DSP Systems
2. price and performance trade-offs; FPGAs are high-speed configurable logic circuits pack-
aged as high-density commodity chips. Configuration of
3. scalability and support for real-time operation. FPGAs is typically performed when the system is powered
Real-time SDR hardware can be built using a variety of dig- on so that during the operation the FPGA configuration
ital hardware consisting of ASICs, DSPs and FPGAs. The is usually fixed, although there are examples, e.g., Xilinx
design of digital hardware typically involves computer-aided XC6200 series, of FPGAs that can do dynamic reconfigura-
design of logic, construction of the schematic diagram, and tion [13]. The cellular array of logic cells in the FPGA is
building the printed circuit board. DSP processors present configured for fast local communications and when properly
the most generalized type of hardware that can be pro- configured to exploit algorithm parallelisms, an FPGA can
grammed to perform almost any function, while an FPGA provide a much greater computational advantage than the
can be configured using logic gates with static functionality. general purpose DSP processor.
ASICs are the most specialized piece of hardware and are Introducing FPGA components into DSP system imple-
not considered in this paper. mentations creates an assortment of challenges across sys-
tem architecture and logic design. Where system architects
2.1 Digital Signal Processors may be available, skilled logic designers are a scarce re-
As the DSP business has matured, there is a variety of source. There is a growing need for tools to allow system
DSP processors with different functionalities. e.g., (i) fixed architects to be able to implement FPGA-based platforms
vs. float point arithmetics, (ii) Harvard and very long in- with limited input from logic designers. Getting FPGA de-
struction word architectures, (iii) various addressing modes; signs translated from software algorithms to hardware im-
(iv) pipelining; (v) peripherals; (vi) multiprocessing, etc. plementations follows the process:
In the non-OS (Operating System) approach (traditional 1. Model the circuit in VHDL or Verilog;
approach with DSP), the main process executes in a syn-
chronous manner; that is the signal processing calculations 2. Verify the functionality of the models through simula-
are done between each sample (or group of samples, often re- tions;
ferred to as frames). An important note is the fact that since 3. Build a netlist from the VHDL code;
we have real-time processes, all calculations MUST be done
within this time interval or we loose real-time performance. 4. Generate the bit files and download them on the target
Recently, specialized real-time OSs for DSPs appeared on device;
Session A1 Communication Networks and Services Research Conference 2003 3

FPGA Chip DSP chip

Programming Language VHDL, Verilog C, Assembly Language
Ease of software Fairly easy. However, a programmer needs to Easy
programming understand the hardware architecture
Performance Very fast if an appropriate architecture is Speed is limited by clock speed of DSP chip
implemented
Reconfigurability SRAM-type FPGAs can be reconfigurable Can be reconfigurable by changing program
infinite times
Reconfiguration method Reconfiguration is done by downloading Reconfiguration is done by simply reading
configuration data to chip electronically a program at a different memory address
Areas where FGPAs can FIR and IIR filters, correlator, convolver, FFT A signal processing of sequential nature
outperform DSPs
Power Consumption minimized if the circuit is designed to save Power consumption does not depend
power, or the power is dynamically controlled on the size of the program
as long as memory is the same
Implementation Parallel multiplier/adder or distributed Repeated operation of MAC function
method of MAC arithmetic
Parallelism Can be parallelized to achieve high DSP chip programming is usually sequential
performance

Table 1: A comparison of FPGA and DSP chips.

5. Test the performance. Eventually, only a final system implementation can pro-
vide realistic metrics of the overheads associated with soft-
The comparison between FPGA and DSP chips is shown in ware and hardware configurations in a real-world design.
Table 1.

3. RAPID PROTOTYPE DESIGN 4. PRACTICAL REALIZATIONS AND

Communication equipment manufacturers, to speed up TRADE-OFFS
their development time and reduce necessary investments Resources critical to SDR architectures include I/O band-
to convert their designs to products, resort to embedded width, memory, and processing capacity. A good demand
DSP systems. Software radio is an example of such a wire- estimation of these resources and a proper partitioning may
less technology. The construction of seamless communica- alleviate many bottlenecks in the design of such systems.
tion systems, combining reprogrammable software and re-
configurable hardware poses a number of new challenges. 4.1 ADC
Co-design and co-simulation must be used during the early ADCs are key components of DSP and may even dictate
stages of the design flow to consider interaction between re- system architectures due to the limited sampling rates and
configurable and fixed system functions. A DSP example of the (quantization) resolutions. The ADC determines the
an EDA system is the eXpressDSP real-time DSP software quality of the digital signal available for subsequent pro-
environment that simplifies and streamlines the DSP prod- cessing. The ADCs cover a variety of implementations from
uct development process offering a choice of reusable soft- parallel (flash), which is the fastest, through integrating,
ware components [12]. An example of the rapid prototyping which is the most accurate.
DSP/FPGA hardware platform for DSP-FPGA (C67x/Virtex) Advances in ADC technology are still required to sup-
architecture in SDR processing applications is the Signal- port the high dynamic range requirements of wideband radio
Masters from LSP of Quebec which allows the user to de- front-ends. Advances are also needed in the area of config-
velop and test DSP algorithms and perform hardware/software urable high-bandwidth analog signal processing for realizing
co-design in a real-time environment [14]. The critical point the RF and IF stages of a radio. Micro-electro-mechanical
in all these EAD systems is to be compatible with the most systems (MEMs) appear to be a promising technology for
popular system-level tools such as Matlab Simulink from addressing in-system configurable analog signal processing.
MathWorks, Xilinx’s System Generator or Signal Process-
ing Workstation from Cadence. 4.2 Memory
The diagram in Fig. 2 represents a complete system-level In an embedded system such as a radio terminal there
design flow process for the LSP DSP-FPG Electronic De- are usually memory issues to be considered, the normal de-
sign Automation tool. First, a model of a process is done in sire being for more memory than the design or commercial
Simulink. Then, the model, in whole or in part, is gradually constraints allow.
moved towards an optimized real-time target DSP/FPGA
implementation using code generators, code development 4.3 Processing Demands
IDEs, real-time I/O boards, optimized DSP libraries, etc. One of the implementation problems facing SDR designers
The reader is referred to LSP documentation and applica- is the concept of real time. An efficient utilization of pro-
tion notes for a more in-depth description of this highly ef- cessing power is the key to meet throughput and response
fective development approach [14]. time specifications. There are always bottlenecks on differ-
4 CNSR 2003, Moncton, New Brunswick, Canada Session A1

4.4 Performance Tuning

5. CONCLUSIONS

6. REFERENCES