Analog/Mixed-Signal Design

ADC/BUFFER COMBINATION

Choosing the
optimum ADC/buffer
combination
The ADC/buffer
combination you choose
should be compatible
with the target system.
Consider overall performance, the ADCs input
structure, and its effect
on the buffer.

Progress in the development of

ADCsincluding ever-increasing
speed and resolution, switchedcapacitor input structures, and
single-supply operationis forcing
system designers to carefully
evaluate the associated drive amplifier (buffer). This buffer must
provide a low source impedance and
sufficient output current to drive the
ADC inputs, and its high-frequency
output impedance must be sufficiently low to avoid excessive
conversion error. For many sampling
ADCs, it also must amplify extremely low-level signals.

By Walter Sangalli

The effect of noise

Application Director
Maxim Integrated Products

that of the ADC. As a minimum

condition for avoiding excess system
noise, the SNR of the source should
be better than the theoretical limit of
the ADC. Fortunately, the noise
performance of all new-generation op
amps is better than 12bits, with
devices providing good 16bit noise
performance not difficult to find. Note
that noise powers of the amplifier and
ADC are additive.
Figure 1 is an example of a lownoise, low-distortion interface between
a 16bit successive-approximation ADC
and its input drive amplifier. You can
calculate the total RMS noise contributed by the buffer using information
from its data sheet.

Ideally, an op amp signal source

should contribute no error beyond

Input voltage-noise density:

en@f = 30kHz = 7.9nVHz,

+5V

Input current-noise density:

in@f = 1kHz = 0.5fAHz
V DD

50k
2

MAX195

7
6

VIN

MAX4256

5k

AIN

(16-BIT ADC)
DOUT
Serial
Interface

SCLK

SHDN
V SS
-5V

CS
REF

4.096V

SHDN

Figure 11: This interface between a drive amplifier and 16bit ADC offers low noise and
low distortion.

2 Electronics Engineer February 2000

Because the effective noise bandwidth of a single-pole filter is 1.57

times the -3dB corner frequency, the
buffers noise bandwidth is GBW/
1.57AV. In addition to voltage noise
and current noise sources in the IC,
each resistor in the circuit contributes
a noise voltage. Thus, the total
equivalent input-referred noise is:

et

e N 2 + i n ( R1 / R 2 (

+ (e r (

Analog/Mixed-Signal Design

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ADC/BUFFER COMBINATION

Selecting the right op amp

for your application

Final entry into

error band

Overshoot

Error
band

Final value

Improving the performance

of an ADC
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content.php3?article_id=8800009989

+FS

Amplitude

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content.php3?article_id=8800009951

Input
step
at
t=0

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Slew-rate
limiting
0

Settling
time

Time

Figure 2
2: Output settling time is defined with respect to an error band about the final settled value.

Total noise is equivalent to:

=

To simplify calculations, remember

that the noise generated by a 1k
resistor in a 1Hz bandwidth is
4nVrms. That information reduces the
formula to:

er = 4n V/ Hz

) (BW

R eq /1k ;

where, Req(BW) is the equivalent

resistance in a specified bandwidth.
Assuming a bandwidth of 20kHz for
this typical AF application, and
bearing in mind the sampling rate
(85KSPS), the result is
en = 8.7nVHz.
Note that the MAX4256s input
current noise of (0.5fAHz) is
insignificant in comparison. Total
output noise referred to the op amp
circuits bandwidth is:

ET

BW 1 / )

et

( 8.7nV /

RMS
17V

Hz

20kHz( 1.57)(11)

3 Electronics Engineer February 2000

To determine total noise power for

the ADC/op amp combination, first
convert the ADC SINAD values
from dB to voltage. Then, calculate
the square root of the sum of the
squares and convert the value back to
dB. In this case, we use the
minimum-guaranteed SINAD value
of 87dB. Converting to voltage
(44.7V) and combining with ET
results in a total noise power of
86.4dBa degradation of only
0.6LSB in the ADCs SNR. A series
of these calculations can demonstrate
the effect of a given drive amplifier
on the overall performance.

Distortion
Distortion also degrades dynamic
performance, but you can minimize
this effect with an amplifier whose
distortion is much less than the
converters THD. Another way to
evaluate op amps as drive amplifiers
is to compare their numerical specifications to the weight (step size) of the
ADCs LSB in volts.
As an example, the LSB for a 16bit
ADC with a 5V unipolar input range
is 76V. To get an idea of the

amplifiers error contribution, compare that number to the amplifiers

input offset voltage, drift, and noise,
all multiplied by its closed-loop gain.
Thus, a closed-loop gain of 11 and an
offset of 70V produce an error of
770V, which for a 16bit application
is 10LSBs. If dc accuracy is important, the buffers offset must either be
much less than the ADCs maximum
offset, or it should be trimmed via
hardware or software.

Bandwidth and settling time

To determine speed requirements for
the drive amplifier, match its settling
time to the ADCs acquisition time.
That is, the conversion results will be
accurate if the ADC samples the input
signal for an interval longer than the
amplifiers worst-case settling time. By
definition, settling time is the interval
between the application of an input
voltage step and the point at which the
output signal reaches and stays within
a given error band about the resulting
steady-state output level (figure 2).
For large input steps, the amplifiers
slew-rate limit restricts the speed with
which its output can change. The
result, for a given input amplitude and
for an amplifier with a given slew
rate, is a maximum at the frequency
that can be faithfully reproduced:
fMAX = SR/2Vp;
Vp = peak output voltage

Analog/Mixed-Signal Design
ADC/BUFFER COMBINATION
You can make a first-order approximation of settling time (tS) if the
following conditions apply: the input
signal does not cause the amplifier
output to enter slew-rate limiting; the
amplifiers -3dB corner frequency is
known; and its output amplitude rolls
off at 20dB/decade for at least one
decade of frequency above f-3dB. Then,
(1) tS = -1/2f-3dB[ln(VO/VS - 1)].
To calculate settling to within +LSB
at N-bit resolution, replace VO/VS
with the expression (2N -+)/2N, where
N is the number of bits. Equation (1)
now becomes:
(2) tS = 0.11(1 + N)/f-3dB
Finding an amplifier that meets the
requirements of ones application may
be difficult. Numerous op amps can
operate satisfactorily with 12bit ADCs,
but only a few are suitable for driving
14bit and 16bit ADCs above 500kHz.
The choice involves tradeoffs among
the parameters of noise, distortion, and
settling time. Settling time poses a
problem, because few op amp manufacturers test this specification at levels
equivalent to 16bit performance
(0.001percent).
Consider bandwidth and settling
time for the drive amplifier in figure
1. For its typical slew rate of 2.1V/s,
the maximum frequency it can handle
with an input amplitude of 2Vp-p is
fMAX = SR/2pVp = 167kHz. Similarly
for settling time, you can solve
equation (2) for the f-3dB frequency
after substituting the 16bit settling
time (1.6s at 0.001percent) for tS.
Though just an approximation, the
surprising result is 1.17MHz.
Bandwidth requirements for highresolution settling time can be much
higher than expected, and designers
often underestimate the bandwidth
necessary to sustain gain accuracy.
Insufficient gain over the input-signal
bandwidth can easily introduce errors
greater than 1LSB.
4 Electronics Engineer February 2000

The ADC input structure

In general, flash converters with their
high levels of nonlinear input
capacitance are the most difficult to
drive, but the more recent switchedcapacitor architectures also require
close attention. The task of driving a
switched-capacitor ADC is made
simpler if you recognize that the
ADC draws a small transient of input
current at the end of each conversion,
when the internal sampling capacitors switch back to the input for
acquisition of the next sample. To
avoid error, the buffer circuitry must
recover from this transient and settle
before the next conversion starts.
This can be accomplished in either of
two ways.
One way is to drive the ADC with
an op amp that settles from a load
transient in less than the ADCs
acquisition timemany new
ADCs include such wideband
sample/holds on chip. Fortunately,
most op amps settle from a load
transient much more quickly than
from an input step, so this requirement is not too difficult to meet with
an external buffer.

A second way is to add an RC filter

at the input, whose capacitor is much
larger than the ADCs input capacitance. This larger capacitor eliminates
the transient by providing charge for
the sampling capacitor (figure 3). A
capacitor of 1,000pF or more between
the ADC input and ground is often
recommended.
An RC filter also reduces the
possibility of amplifier-stability
problems when driving a capacitive
load. A small resistor in series with
the capacitor helps in preventing
ringing and oscillation. At higher
capacitive loads, the ac performance
is controlled by interaction of the load
capacitance and the isolation resistor.
Another key concern is to ensure
that the amplifier maintains low
output impedance over all input
frequencies of interest. Op amps with
high output impedance cannot
respond quickly to changes in the
ADCs input capacitance. Nor can
they handle the transient currents
kicked back by the ADC.
Nonlinearities result when the op amp
does not settle in time for the next
conversion.

510

+5V

0.1F

22

AIN

MAX410
IN

0.01F

0.1 F
-5V
Figure 3
3: The 22/0.1F output filter absorbs transients from the ADC and helps stabilize the
amplifier.

Analog/Mixed-Signal Design
ADC/BUFFER COMBINATION
1/ noise gain, (100dB - (40dB) =
60dB). For a given value of , you
will observe that as frequency increases, the loop gain A decreases.
To obtain a greater amount of loop
gain at higher frequencies, you will
need to either increase the open-loop
gain of the amplifier or increase the
feedback factor .
This leads us to a key equation in
feedback systems. Referring to the
unity-gain non-inverting amplifier,

100

80

A v (dB)

60

Avo

Avo

40

(3) ACL = Vout/Vout = 1/(1 +1/A)

20

10
-20

10

10

10

10

10

10

Frequency (Hz)

-40
Figure 4
4: Output impedance generally rises with frequency.

Remember that high loop gain is

necessary for low output impedance,
according to the equation
ROUT = RO/(1 + AVO)
where RO is the open-loop output
impedance and AVOb is the loop gain.
AVOb decreases as you approach the
op amps unity-gain crossover
frequency, leading to increased output
impedance (figure 4). Higher output
impedance causes difficulty for the
amplifier in handling current spikes
from the ADC.
Thus, the low-impedance requirement leads to a requirement for wide
bandwidth. Because higher-bandwidth op amps have higher loop gain
and, therefore, lower output impedance at higher frequencies, it makes
sense to use a 500MHz op amp in
front of a 50MSPS ADC. The highbandwidth op amp more effectively
swamps out the ADC kickback
5 Electronics Engineer February 2000

signals than does a lower-bandwidth

amplifier.

Limited loop-gain error

The Bode diagram of figure 4 also
depicts, for the non-inverting circuit,
the relationships among open-loop
gain (A), the feedback-attenuation
factor (), noise gain (1/), and loop
gain (A, or AVO at dc), as functions
of frequency.
Shown is the variation of open-loop
gain vs. frequency for a typical
operational amplifier. At very low
frequencies, the dc open-loop gain
(AVO) is near 100dB. Also note, the
logarithm of the feedback-attenuation
factor is negative because it represents
a reduction in the signal amplitude.
Loop gain is depicted in the figure
as the sum of the open-loop gain and
the feedback attenuation factor
(100dB + (-40dB) = 60dB at low
frequency), or as the difference
between the open-loop gain and the

This equation indicates that the

closed-loop gain (ACL) depends on
both the open-loop gain and the
feedback factor. Both of these quantities are functions of frequency, so
loop gain is a function of frequency as
well. The amount of loop gain at the
operating frequency is the key
measure of how closely an amplifier
configuration approaches the ideal.
Consider a practical example based
on equation (3). Assuming an op amp
with 40dB open-loop gain at the
frequency of interest, the closed-loop
gain has an error of 1percent. This
error drops to 0.1percent at 60dB
gain, and to 0.01percent at 80dB gain.
Therefore, 80dB is the minimum
allowable open-loop gain that will
maintain unity closed-loop gain while
properly driving a 12bit ADC. To
accommodate a higher closed-loop
gain, modify equation (3) as follows:
(4) ACL = Vout/Vin = (1/(1 +1/
Ab))(RF +RI)/RI.
RF and RI are the feedback and
input resistors, respectively. Thus,
depending on the level of closed-loop
gain required, even higher open-loop
gain may be needed to maintain the
required accuracy.
You may e-mail your comments on this
article to Walter Sangalli at
E-mail: walter_sangalli_maxim_it
@compuserve.com.