EE115C Spring 2013

Digital Electronic Circuits

Lecture 2:

MOS Transistor:
IV Model

Levels of Modeling

Analytical
CAD analytical
Switch-level sim
Transistor-level sim
complexity
Different complexity, accuracy, speed of convergence
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MOS Transistor Modeling

Our goal is to model

delay and energy
not current

But have to start

with current

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MOSFET, Notations
G

tox

xd

Leff

Ld

xd

Hand-analysis I-V formulas:

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L = Leff
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Important Concepts to Understand

Threshold voltage (VT)

Velocity saturation
Channel length modulation (channel pinch-off)

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Threshold Voltage, VT
VSB = 0

VT0 is approx 0.2V for our process

= + ( | + | | |)

VT

VSB
B
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NMOS:
VSB > 0 (RBB)
VSB < 0 (FBB)
PMOS:
VSB > 0 (FBB)
VSB < 0 (RBB)
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Outline

MOS Transistor
Basic Operation
Modes of Operation
Deep sub-micron MOS

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The Drain Current in Linear Regime

Combining velocity and charge:

Integrating over the channel:

Transconductance:
Gain factor:
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Small VDS ignore quadratic

term linear VDS dependence
L = effective L = Ld 2xd
8

Velocity Saturation
Carrier velocity saturates when critical field is reached
v
105 m/s

vsat

c
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Simple Model

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A More General Model

Approximate velocity:

A more general model:

for c
for c

we use n = 1

And integrate current again:

In deep submicron, there are four regions of operation:

(1) cutoff, (2) resistive, (3) saturation and (4) velocity saturation
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Including Velocity Saturation in the ID Formula

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Calculating Velocity Saturation, VDSAT

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Vsat Occurs at LOWER VDS than Sat

VDS = kVGT

VDS = VGT

ID

Vsat

Sat

k = k(VGT)

VDS
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Vsat: Less Current for Same VGS

ID

Sat (Long-L)
VGS = VDD

Vsat (Short-L)

VDSAT
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VGT

VDS

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Channel Length Modulation (CLM)

Channel pinch-off

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Modeling Channel Length Modulation (CLM)

Many empirical models
Goal: get a simple model that is convenient for hand analysis
Here is a possible modeling approach:

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MOS in Saturation with CLM

Another model: DV instead of Lp

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CLM Holds in Vsat

VDS > VDSAT
S

VDS
Leff

Lp

VDSAT
VDS
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Saturation vs. Velocity Saturation

V-Sat occurs for lower VDS than Sat

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Simulation: Long vs. Short Channel (90nm)

IDSat(VGS) quadratic, IDVsat(VGS) linear
Stronger CLM in short-L than long-L
IDVsat < IDSat only for large VGS
2.4m/0.5m
0.48m/0.1m

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Simplification: VDSAT = Constant

Const
VDSAT

Simplifies hand
calculations

ID

BUT

VDS
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Regions of Operation
Const
VDSAT

Simplification
introduces Sat
region for low VGS

ID

VGT < VDSAT, the

Lin

VSat

device appears
to be in Sat

VGT = VDSAT
Sat
VDS
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Unified Model vs. SPICE Simulation

VDS = VDSAT

simulation
model

Transition

0.25

ID (mA)

0.2

Lin

lin/v-sat:
largest
modeling
error

VSat

0.15

0.1

VGT = VDSAT

0.05
0
0

Sat
0.2

VDS = VGT

0.4

0.6

0.8

VDS / VREF
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MOS Regions of Operation

Nano-scale MOS devices operate in velocity saturation
Saturation still possible for low VGS values (up to VDSAT)

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MOS I-V Model: Active Region

VGT = VGS VT
Active region (VGT 0) Lin, Sat, V-Sat

ID
B

2
V
W
ID = k (VGTVmin min )(1 + VDS)
2
L

Vmin = min(VDS, VGT, VDSAT)

Lin Sat V-Sat

Neglect CLM in linear region

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Model Parameters: Active Region

VT0 : Threshold voltage
: Body effect
VDSAT : Velocity saturation
k : Transconductance (k = Cox)
: Channel-length modulation (CLM)

CLM term (1 + VDS) also included for linear region

Empirical, no physical justification
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Typical Values for 90nm

ox 0 = 3.5 1011 F/m (ox = 3.9)
tox = 2.3 nm
Cox = ox / tox = 15.2 fF/um2
For W/L = 430nm/120nm
Cg = 0.65 fF
Leff = 70nm
c = 4V/um
Vdsat = cL = 0.3V

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Unified Model: Observations

CLM term (1 + lVDS) also included for linear region
Empirical, not grounded in physical considerations

Five parameters: VT0, g, VDSAT, k, l

Can determine from physics

Or choose values that best match simulation/measured data
(match the best in regions that matter the most)
Use different model for L >> Lmin
(in EE115C we assume L = Lmin unless otherwise specified)

Lets see how do we extract these parameters from the I-V curves
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140

ID (mA)

120
The Meaning
of Model Parameters: VT0
100

MOS in80saturation
ID (mA)

60

B
A

40
20

0.4
0.5
0.7
1
0.4BB
0.5BB
0.7BB
1BB

VGS=0.5V
VGS=0.4V

0
0.0

0.2

0.4

0.6

0.8

1.0

VDS (V)

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The Meaning of Model Parameters: g

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The Meaning of Model Parameters: l

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The Meaning of Model Parameters: k

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Sub-threshold Current

This is another topic of crucial importance in digital

design (and not considered in EE115A models)
We need to consider sub-threshold current, because digital
designs have many millions of transistors and when these are
inactive, we may get some surprise power consumption

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Sub-threshold ID versus VGS is Exponential

x 10-4
6

Long Channel
5

ID (A)

quadratic

Sub-threshold

linear

Short Channel

exp quadratic
0

0.5

1.5

2.5

VGS (V)
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Modeling the Sub-threshold Behavior

G

S
n+

D
Cox

C n+

=
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Cd

Parasitic BJT

=1+

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Sub-threshold ID vs. VGS

Physical
model

0 =

DIBL

Empirical
model

= () [mV/dec]
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The Sub-threshold Slope Parameter

= () [mV/dec]
Change in VGS that gives 10x change in IDS
n=1
60 mV/dec
(ideal)
n = 1.5 90 mV/dec
(typical)

S: increases with temperature ( )

n: intrinsic to device topology / structure

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Drain Induced Barrier Lowering (DIBL)

Effective VT

Long-L
Short-L
decreasing L
VDS

Field lines from the drain affect charge in the channel

Typically derived for small VDS, holds for large VDS
Even if we neglect CLM, IDS will increase b/c of VT drop
Device turned off by VGS (below VT) may turn on by VDS

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MOS I-V Model: Subthreshold

Subthreshold region (VGT 0)

VGT = VGS VT

W VGS VT + DVDS
ID = I0 10
S
W0

ID
B

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Model parameters
I0 : Nominal leakage current
S : Subthreshold slope
D : DIBL factor

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90nm Simulation: Sub-threshold ID vs. VGS

PMOS

NMOS

VDS : 0 to 0.4V

10x
90mV

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= ()

90mV/dec
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90nm Simulation: Sub-threshold ID vs. VDS

PMOS

480nm/100nm

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NMOS

VGS : 0 to 0.3V

240nm/100nm

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MOS I-V Model: Summary

Subthreshold region (VGT 0)

VGT = VGS VT

W VGS VT + DVDS
ID = I0 10
S
W0

ID
B

Active region (VGT 0) Lin, Sat, V-Sat

2
Vmin

W
ID = k (VGTVmin
)(1 + VDS)
2
L
Vmin = min(VDS, VGT, VDSAT)
Lin Sat V-Sat

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.MODEL Parameters MOS1 (Basic Parameters)

.MODEL Modname NMOS/PMOS <VT0=VT0>

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In Reality: GPDK090 Model (gpdk090_mos.scs)

section TT_s1v
parameters
+ s1v_rs_ne =
0.000000e+000 s1v_vsat_ne = 1.120000e+005
+ s1v_uc1_ne = 3.700000e-010 s1v_u0_ne =
2.000000e-002
+ s1v_rsc_ne = 4.082483e-014 s1v_cgbo_ne = 1.482000e-011
+ s1v_rdc_ne = 4.082483e-014 s1v_vth0_ne = 1.692662e-001
+ s1v_cgdo_ne = 2.667600e-010 s1v_ckappa_ne =4.605336e+000
+ s1v_k1_ne =
2.825346e-001 s1v_cgsl_ne = 1.111500e-010
+ s1v_js_ne =
3.366667e-006 s1v_hdif_ne = 1.400000e-007
+ s1v_jsw_ne = 3.366667e-010 s1v_tox_ne =
2.330000e-009
+ s1v_cjsw_ne = 4.790122e-011 s1v_ldif_ne =
1.000000e-008
+ s1v_rd_ne =
0.000000e+000 s1v_pb_ne =
9.918524e-001
+ s1v_lint_ne = 1.500000e-008 s1v_cjswg_ne = 1.995884e-011
+ s1v_u0_pe = 1.200000e-002 s1v_nch_pe =
4.000000e+017
+ s1v_cgbo_pe = 1.392363e-011 s1v_rdc_pe =
2.886751e-014
+ s1v_k2_pe =
0.000000e+000 s1v_cgdo_pe = 2.506253e-010
+ s1v_wint_pe = 5.000000e-009 s1v_k1_pe =
2.637520e-001
+ s1v_js_pe =
3.350000e-006 s1v_hdif_pe =
1.400000e-007
+ s1v_jsw_pe = 3.350000e-010 s1v_tox_pe =
2.480000e-009
+ s1v_cjsw_pe = 4.747351e-011 s1v_ldif_pe =
1.000000e-008
+ s1v_rd_pe =
0.000000e+000 s1v_pb_pe =
1.009805e+000
+ s1v_lint_pe = 1.500000e-008 s1v_cjswg_pe = 1.978063e-011
+ s1v_rs_pe =
0.000000e+000 s1v_vsat_pe =
1.000000e+005
include "gpdk090_mos.scs" section = s1v_mos
endsection TT_s1v

s1v_pldd_surf =
6.000000e+019
s1v_nch_ne =
5.200000e+017
s1v_prt_ne =
1.000000e+001
s1v_k2_ne =
0.000000e+000
s1v_wint_ne =
6.000000e-009
s1v_nldd_surf =
3.000000e+019
s1v_rdsw_ne =
3.900000e-006
s1v_cj_ne =
7.983537e-004
s1v_xj_ne =
2.500000e-008
s1v_cf_ne =
4.594612e-011
s1v_rsh_ne =
1.000000e+001
s1v_rsc_pe =
2.886751e-014
s1v_vth0_pe =
-1.359511e-001
s1v_ckappa_pe =
1.043477e+001
s1v_cgsl_pe =
1.044272e-010
s1v_rdsw_pe =
7.800000e-006
s1v_cj_pe =
7.912252e-004
s1v_xj_pe =
2.500000e-008
s1v_cf_pe =
4.527118e-011
s1v_rsh_pe =
2.000000e+001

This model continues on the next slide

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GPDK090 Model (section s1v_mos)

section s1v_mos
model gpdk090_nmos1v bsim3v3 type = n
+ lmin =
0.0
lmax =
1.0
+ wmax = 1.0
tnom =
25.0
+ tox =
s1v_tox_ne
toxm =
s1v_tox_ne
+ nch =
s1v_nch_ne
lln =
1.0000000
+ wln =
1.0000000
wwn =
-1.0000000
+ ll =
0.00
lw =
0.00
+ wint =
s1v_wint_ne
wl =
0.00
+ wwl =
0.00
mobmod = 1
+ xl =
0
xw =
0
+ dwb =
0.00
acm =
12
+ hdif =
s1v_hdif_ne
rsh =
s1v_rsh_ne
+ rs =
s1v_rs_ne
rsc =
s1v_rsc_ne
+ vth0 =
s1v_vth0_ne k1 =
s1v_k1_ne
+ k3 =
-2.3000000
dvt0 =
3.86366
+ dvt2 =
5.0299990E-02 dvt0w =
0.00
+ dvt2w = 0.00
nlx =
1.2517999E-07
+ k3b =
0.5576769
ngate =
4.0E20
+ ua =
-6.1879500E-10 ub =
1.8806652E-18
+ rdsw =
s1v_rdsw_ne prwb =
0.00
+ wr =
1.0000000
u0 =
s1v_u0_ne
+ keta =
-3.1429991E-02 a1 =
0.00
+ ags =
0.8900000
b0 =
0.00

wmin =
0.0
version =
3.2
xj =
s1v_xj_ne
lwn =
1.0000000
lint =
s1v_lint_ne
lwl =
0.00
ww =
0.00
binunit =
2
dwg =
0.00
ldif =
s1v_ldif_ne
rd =
s1v_rd_ne
rdc =
s1v_rdc_ne
k2 =
s1v_k2_ne
dvt1 =
1.2
dvt1w =
0.00
w0 =
-7.1353000E-09
vsat =
s1v_vsat_ne
uc =
1.3823546E-10
prwg =
0.00
a0 =
2.3750000
a2 =
0.9900000
b1 =
0.00

And many more parameters... (compare to our 5-parameter model)

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Spectre Netlist (NMOS, PMOS)

section s1v_mac
subckt s1v_ckt_nch (n11 n2 n33 n4)
parameters l=0.1u w=10u multi=1 factor=1 nrd=s1v_hdif_ne/factor/w nrs=s1v_hdif_ne/factor/w
+ Tox_ratio = 3.0e-9 / (s1v_tox_ne*s1v_tox_ne*s1v_tox_ne)
MAIN (n1 n2 n3 n4) gpdk090_nmos1v w=w l=l nrd=nrd nrs=nrs multi=multi
GDF1 (n2 n1) bsource i = w*0.6*s1v_xj_ne*4.97232*Tox_ratio*v(n2,n1)*v(n2,n3)*exp(-4.85669e11*s1v_tox_ne*
GDF2 (n2 n3) bsource i = w*0.6*s1v_xj_ne*4.97232*Tox_ratio*v(n2,n3)*sqrt( (v(n2,n3) - 0.026*log(4.0e20
20 / s1v_nldd_surf)) + 1.0e-4 )*exp(-4.85669e11*s1v_tox_ne*(0.43-0.054*sqrt( (v(n2,n3) - 0.026*log(4.0e20
.0e20 / s1v_nldd_surf)) + - 0.026*log(4.0e20 / s1v_nldd_surf))*(v(n2,n3) s1v_nldd_surf)) + 1.0e-4 )))
rdn (n1 n11) resistor r= 6.8 *nrd/multi
rsn (n3 n33) resistor r= 6.8 *nrs/multi
ends s1v_ckt_nch
subckt s1v_ckt_pch (p11 p2 p33 p4)
parameters l=0.1u w=10u multi=1 factor=1 nrd=s1v_hdif_pe/factor/w nrs=s1v_hdif_pe/factor/w
+ Tox_ratio = 3.0e-9/(s1v_tox_pe*s1v_tox_pe*s1v_tox_pe)
MAIN (p1 p2 p3 p4) gpdk090_pmos1v w=w l=l nrd=nrd nrs=nrs multi=multi
GDF1 (p2 p1) bsource i = w*0.6*s1v_xj_pe*3.42537*Tox_ratio*v(p2, p1)*sqrt( (v(p2, p1)0.026*log(9.32E19/s1v_pldd_surf))*(v(p2, p1)-0.026*log(9.32E1
9/s1v_pldd_surf)) + 1.0e-4 )*exp(-7.0645e11*s1v_tox_pe*(0.31-0.024*sqrt( (v(p2, p1)0.026*log(9.32E19/s1v_pldd_surf))*(v(p2, p1)-0.026*log(9.32E19 s1v_pldd_surf)) + 1.0e-4 ))*(1.0+0.03*sqrt( (v(p2, p1)0.026*log(9.32E19/s1v_pldd_surf))*(v(p2, p1)-0.026*log(9.32E19/s1v_pldd_surf)) + 1.0e-4 )))
GDF2 (p2 p3) bsource i = w*0.6*s1v_xj_pe*3.42537*Tox_ratio*sqrt( (v(p2, p3)-0.026*log(9.32E19/)) + 1.0e-4 )))
rdp (p1 p11) resistor r = 7.1 * nrd / multi
rsp (p3 p33) resistor r = 7.1 * nrs / multi
ends s1v_ckt_pch
endsection s1v_mac
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