MODULE

Introduction to MTS-86C Microprocessor Training System

MODULE OUTLINE:

Objectives
Introduction to Microprocessor Systems
Microprocessor Architecture (Sample)
8086 General Operation
Introduction to MTS-86C
Executing Demo Programs

Prepared By:
Engr. Cristine Jin DS. Estrada

MODULE

Objectives
PRE-LAB DISCUSSION
To give an overview of the microprocessor systems, its components and
architecture
To introduce the general operation of the 8086 processor

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INTRODUCTION
Three Main Components of a
Basic Computer Organization
A. CPU or Microprocessor performs
many operations and controls the
computer.
B. Memory Subsystem used to store
programs being executed by the CPU,
along with the programs data.
C. Input/Output Subsystem allows
the CPU to interact with input and output
devices, such as the keyboard and
monitor.

GENERIC COMPUTER ORGANIZATION

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INTRODUCTION
What is a System Bus?
A System Bus is a set of wires or a
physical group of signal lines that has a
related function within a microprocessor
system.
It is used to send information from one
component into another.

How is the system bus classified?

A.

B.

C.

Address Bus a unidirectional bus used to locate a

memory location or an I/O device connected to the
system.
Control Bus a bus (collection of individual control
signals) used by the microprocessor to send its
generated control signals to any element of the
computer system
Data Bus a bidirectional bus that carries data back
and forth to a specified location with basis to the
address location provided by the address bus.

GENERIC COMPUTER ORGANIZATION

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INTRODUCTION
What is a Microprocessor?
A Microprocessor is considered to be the
Central Processing Unit (CPU) or the
brain of all computers and electronic
devices. It acts as a complete computation
engine that is fabricated on a single chip.

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MICROPROCESSOR ARCHITECTURE
BASIC MICROPROCESSOR
STRUCTURE
A.
B.

C.

D.

Bus Unit has the job of

establishing communication with
the external unit
Arithmetic Logic Unit (ALU)
performs data processing
operations specified during the
execution phase of the
instruction being interpreted
Control Unit generates the
set of timings and control signals
necessary to activate different
parts of the circuit
Register Set set of data
holding places

ACCUMULATOR

PROGRAM
COUNTER

ALU
GENERAL PURPOSE
REGISTER

INSTRUCTION
REGISTER
CONTROL
UNIT

STATUS
REGISTER

MEMORY
ADDRESS
REGISTER

MEMORY
DATA
REGISTER

MICROPROCESSOR BLOCK DIAGRAM

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MICROPROCESSOR ARCHITECTURE
A. Bus Unit
Data Bus
A bidirectional bus that
carries data back and forth to
a specified location with basis
to the address location
provided by the address bus.
NOTE:
The width of a data bus refers to the
number of bits (electrical wires) that
make up a bus.
e.g. 1-, 4-, 8-, 16-, 32-, and 64-bit

BASIC STRUCTURE OF MICROPROCESSOR

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MICROPROCESSOR ARCHITECTURE
A. Bus Unit
Address Bus
It is a group of wires or lines that
are used to transfer the addresses
of Memory or I/O devices. It is
bidirectional.
NOTE:
A 16-bit address bus can transfer
maximum address which means it can
address 65,536 different memory
locations.
The number of bits of address bus
determines the maximum size of memory
which the processor can access.

BASIC STRUCTURE OF MICROPROCESSOR

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MICROPROCESSOR ARCHITECTURE
Structure of Data
Storage
For multiple byte data
items to be stored in the
memory, there is a need
to know how the order
is done.
Otherwise, problem may
occur when transferring
data between machines.
The order of storage of
data can be classified
into two: the Little
Endian and Big Endian

LITTLE ENDIAN vs. BIG ENDIAN

What is the difference between
these two storage structures?
LITTLE ENDIAN the least
significant 8 bits (byte) are to be
stored in a lower address.

addr4
addr3
addr2
addr1

Byte 4
Byte 3
Byte 2
Byte 1

BIG ENDIAN the most

significant 8 bits (byte) are to be
stored in a lower address.

addr4

Byte 1

addr3

Byte 2

addr2

Byte 3

addr1

Byte 4
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MICROPROCESSOR ARCHITECTURE
B. Arithmetic Logic Unit (ALU)
It contains the microprocessors data
processing major logic.
Performs arithmetic and logic
operations.
Composed of adders/subtracters,
comparators, and different
combinational circuits.

ALU

NOTE:
Example of arithmetic operations are:
1. addition/subtraction
2. increment/decrement
3. shift left/right, circular shift left/right

Example of logic operations are: AND, OR,

XOR, and NOT.

MICROPROCESSOR BLOCK DIAGRAM

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MICROPROCESSOR ARCHITECTURE
C. Control Unit
Made up of instruction decoder,
timing circuits, and control logic
1. Instruction Decoder the circuit
responsible for synthesizing and
decoding the instructions fed or
received by the microprocessor.
2. Timing Circuits used to
synchronize the operation of the
different parts of the
microprocessor.
3. Control Logic send the control
signals flowing in the control bus
to enable the different parts of the
microprocessor unit.

CONTROL
UNIT

MICROPROCESSOR BLOCK DIAGRAM

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MICROPROCESSOR ARCHITECTURE
D. Register Set
In the given structure, the
register set is composed of
the following:
1. General Purpose
Registers A and B
2. Accumulator
3. Status Register
4. Instruction Register
5. Program Counter
6. Memory Data Register
7. Memory Address Register

ACCUMULATOR

PROGRAM
COUNTER
GENERAL PURPOSE
REGISTER

INSTRUCTION
REGISTER

STATUS
REGISTER

MEMORY
ADDRESS
REGISTER

MEMORY
DATA
REGISTER

MICROPROCESSOR BLOCK DIAGRAM

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MICROPROCESSOR ARCHITECTURE
D. Register Set
2. Accumulator
The register that works very
closely with the ALU.
All results of the processes
performed by the ALU is
stored in this register.
This is the major register that
holds data for manipulation.
It is considered as the most
versatile register because its
content always changes.

ACCUMULATOR

MICROPROCESSOR BLOCK DIAGRAM

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MICROPROCESSOR ARCHITECTURE
D. Register Set
1. General Purpose
Registers (A and B)
They are generally used as
data storage and are
directly connected to the
data bus.
NOTE:
The more the number of GPR,
the more powerful the
microprocessor is.

GENERAL PURPOSE
REGISTER

MICROPROCESSOR BLOCK DIAGRAM

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MICROPROCESSOR ARCHITECTURE
D. Register Set
3. Status Register
It is sometimes referred to as Flag
Register, Condition Code
Register, or the Indicator
Register.
It is used to hold the status of the
microprocessor after performing an
operation.
Commonly Used Flags:
CARRY end carry of the parallel adder.
ZERO if the result of the ALU are all
zero
SIGN if the MSB in a signed operation
has a value of 1
OVERFLOW if the result of ALU
operation exceeds the defined range of
numbers
PARITY used for error detection

STATUS
REGISTER

MICROPROCESSOR BLOCK DIAGRAM

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MICROPROCESSOR ARCHITECTURE
D. Register Set
4. Instruction Register
It is used to hold the
instruction code or
operation code (opcode).
NOTE:
The outputs of this register
are the inputs to the
instruction decoder.

INSTRUCTION
REGISTER

MICROPROCESSOR BLOCK DIAGRAM

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MICROPROCESSOR ARCHITECTURE
D. Register Set
5. Program Counter
It contains the address of
the next instruction to be
performed by the MPU.
It automatically increments
as soon as it is finished
with the memory location.

PROGRAM
COUNTER

MICROPROCESSOR BLOCK DIAGRAM

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MICROPROCESSOR ARCHITECTURE
D. Register Set
6. Memory Data Register
This is where the data to be
stored to or retrieved from the
memory are placed.
This register also loads the
fetched instruction from the
memory going to instruction
register.
7. Memory Address Register
This is where the addresses
of data and instructions can
be located.

MEMORY
ADDRESS
REGISTER

MEMORY
DATA
REGISTER

MICROPROCESSOR BLOCK DIAGRAM

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MTS-86C
HARDWARE OVERVIEW
MTS-86C is an Intel 8086 based
microprocessor training system
designed for teaching purposes.
It is composed of 5 parts:

MPU (8086)
Memory
Chip Sets
I/Os
External Interface

MPU
Memory
8086 I/Os
External Interface

Chip Sets

MTS-86C FUNCTION BLOCKS

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MTS-86C
HARDWARE OVERVIEW
MPU
The MPU of the MTS-86C is an
Intel based 8086 microprocessor
which has the following elements:

16-bit internal data bus

20-bit address bus
Control bus
Execution Unit
Bus Interface Unit

MPU
Memory
8086 I/Os
External Interface

Chip Sets

MTS-86C FUNCTION BLOCKS

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MTS-86C
HARDWARE OVERVIEW
MEMORY
ROM (Read Only Memory)
The memory has two 27,256 UV
EPROM (32Kb x 8), serving as the
storage of demo programs and
system monitoring program.
RAM (Random Access Memory)
The memory also has two 62,256
SRAM (32Kb x 8), serving as the
storage of user programs/data and
interrupt vector table.
USER MEMORY
The user memory allows the user to
store programs in their own ROM or
RAM. (Optional)

MPU
Memory
8086 I/Os
External Interface

Chip Sets

MTS-86C FUNCTION BLOCKS

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MTS-86C
HARDWARE OVERVIEW
CHIP SETS
8255 General purpose
programmable parallel
input/output interface (3 sets)
8251 Serial data
communications interface (2
sets)
8259 Programmable Interrupt
Control Unit
8253 Programmable
timer/counter

MPU
Memory
8086 I/Os
External Interface

Chip Sets

MTS-86C FUNCTION BLOCKS

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MTS-86C
HARDWARE OVERVIEW
CHIP SETS
8279 Programmable
keypad/display interface

74LS373 Octal D-Type

latches
DAC0808 8-bit multiplying
digital to analog converter
ADC0809 8 channels 8-bit
analog to digital converter

MPU
Memory
8086 I/Os
External Interface

Chip Sets

MTS-86C FUNCTION BLOCKS

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MTS-86C
HARDWARE OVERVIEW
I/Os
Switch 8-bit logic TACT
switch
LED 8-BIT logic LED
FND 1 Flexible Numeric
Display
Keypad 4x6 keys
Display 16x2 line LCD
Speaker 2 W Speaker
ADC Input microphone,
variable resistor, thermistor,
and phototransistor

MPU
Memory
8086 I/Os
External Interface

Chip Sets

MTS-86C FUNCTION BLOCKS

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MTS-86C
HARDWARE OVERVIEW
External Interface
PPI-1 1st Prototyping area for
8225 parallel port
PPI-2 2nd Prototyping area for
8225 parallel port
PIT/PIC/AD/DA External
interface for 8259, AD/DA
Converter, and 8253,
respectively
System Bus connects to 8086
CPU
RS232-1 First serial port
interface for 8251
RS232-2 Second serial port
interface for 8251

MPU
Memory
8086 I/Os
External Interface

Chip Sets

MTS-86C FUNCTION BLOCKS

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MTS-86C
MEMORY MAP
Monitor Program allows user to
control and examine the
microprocessor from the keyboard
Demo Program stores demo
programs
User Memory allows user to
store/load programs in their own
ROM or RAM (Optional)
Program and Data user codes
and data are stored in this section
Interrupt Vector Table reserved
location for interrupt vector table

FFFFFH

Monitor Program
F8000H

Demo Program
F0000H

User Memory
E0000H

Non-Use
10000H

Program and Data

00400H

64KB EPROM
System Memory
27256 x 2
ROM, RAM
(Optional)
OPEN
64KB SRAM
Program Memory
62256 x 2

Interrupt Vector Table

00000H

MTS-86C MEMORY MAP

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MTS-86C
ADDRESSING MODE PHYSICAL vs. LOGICAL ADDRESS
Recall the elements of the
8086 processor:
The MPU of the MTS-86C is an Intel
based 8086 microprocessor which
has the following elements:

16-bit internal data bus

20-bit address bus
Control bus
Execution Unit
Bus Interface Unit

What is the difference between these two

address?

LOGICAL ADDRESS address generated

by the CPU and can be also referred to as
virtual address.
PHYSICAL ADDRESS address seen by
the memory unit.
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MTS-86C
ADDRESSING MODE
The physical address of the 8086 system is 20
bits in width. Hence, the generation of the
physical address requires the combination of
a 16-bit offset value and a 16-bit base value
located in one of the four segment registers:
Code Segment (CS) holds the program
instruction codes
Data Segment (DS) stores data for the
program
Stack Segment (SS) stores interrupt
subroutine return address
Extra Segment (ES) an extra data
segment often used for shared data

Width = 16 bits

CODE SEGMENT (CS)

DATA SEGMENT (DS)
STACK SEGMENT (SS)
EXTRA SEGMENT (ES)
SEGMENT REGISTERS

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MTS-86C
How to generate a physical
address?
To generate a physical address, the value
in the segment register is shifted left by 4
bits with its

LSB filled with 0s

SEGMENT ADDRESS

OFFSET ADDRESS
F

Width = 16 bits

Width = 20 bits

Width = 16 bits

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EXECUTING DEMO PROGRAMS

EXPERIMENT

TABLE 4-1. DEMO PROGRAMS

Fill out the remarks of

Table 4-1 Demo
Programs by exploring
MTS-86C.

OBJECTIVES

To introduce the
hardware devices of
MTS-86C
To introduce the memory
map of MTS-86C
And to learn how to
execute the demo
programs in MTS-86C
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