DEVELOPMENT OF THE ARM ARCHITECTURE

ARM has introduced many processors. Each set or groups of processors are having different
core and different Features. Development of the ARM Architecture is started with 26 bit
processors and nowadays it reaches up to 64 bit. We cannot classify general development of
ARM products on any particular fact, there is only one way to understand ARM based
products is on its Architectural version profile.

ARM Classic series

The classical ARM series refers to processors starting from ARM7 to ARM11. This is the
series which gives market boost to ARM because of its core features like Data Tightly
Coupled

memory,

cache,

MMU,

MPU,

etc.

Typical

examples

of

this

series

are ARM7TDMI, ARM926EJ-S, ARM11 MPCore, etc.

Cortex-A series: A-profile, the Application profile

In this Cortex architecture, we port different embedded OS and design embedded system by
OS system programming. The core feature of this profile is Highest performance at low
power, Trust Zone and Jazelle-RCT for a safe and extensible system. Practical development
platform of this types of profile is Friendly ARM, Raspberry Pi, etc.

Cortex-R series: R-profile, the Real-time profile:

This is Cortex architecture which mostly used for real time purpose where application abort is
critical situation contain core features like Protected memory (MPU), Low latency and
predictability real-time needs.

Cortex-M series: M-profile, the Microcontroller profile:

This profile is specially dedicated for microcontroller purpose only. The core feature of this
profile is like Lowest gate count entry point, Deterministic and predictable behaviour a key
priority, deeply embedded use. Typical example of this kind of profile architecture is
Hercules TMS470M, STM32F429, etc.

PROCESSOR MODES

All these modes indicate its special work and execute under certain condition with its own
stack and a different subset of registers. Modes other than User mode are collectively known
as privileged modes. Your program or application generally runs under User mode. Privileged
modes are used to service interrupts or exceptions, or to access protected resources.

THE ARM REGISTER SET

CPSC Current program status register

SPSR Saved program status register
LR Link register
SP Stack Pointer
PC Program Counter
ARM7 has a load and store architecture so in order to perform any data
processing the data has to be first moved from the memory store to the central
set of registers, the data processing instruction has to be executed and then data
processing instruction has to be executed and then the data is stored back into
the memory.

There are some CPU based registers present in the ARM7 CPU
1. CSPR- current program status register

T Bit (Bit 5)

Condition code flags (Bit 28 to 31)

V = ALU operation oVerflowed

C = ALU operation Carried out

Z = Zero result from ALU

N = Negative result from ALU

Architecture 5TE and later only

Indicates

saturation

has

occurred

T = 1: Processor in Thumb state

Introduced in Architecture 4T

Architecture 5TEJ and later only

J = 1: Processor in Jazelle state

Interrupt Disable bits (Bit 6 Bit 7)

I = 1: Disables IRQF = 1:
Disables FIQ

Specify the processor mode

New bits in V6 (Bit 10 to 19)

GE[3:0] used by some SIMD

instructions

J bit (Bit 24)

T = 0: Processor in ARM state

Mode bits (Bit 0 to 4)

Sticky Overflow flag Q flag (Bit 27)

if

bit

controls

load/store

endianness

A bit disables imprecise data

aborts

IT [abcde] IF THEN conditional

execution of Thumb-2 instruction

groups

ARM INSTRUCTION SET

All instructions are 32 bits long / many execute in a single cycle

Instructions are conditionally executed

A load / store architecture

Example data processing instructions

SUB r0,r1,#5

r0 = r1 5

ADD r2,r3,r3,LSL #2

r2 = r3 + (r3 * 4)

ADDEQ r5,r5,r6

IF EQ condition true r5 = r5 + r6

Example branching instruction

B
<Label
>

Branch forwards or backwards relative to current

PC (+/- 32MB range)

Example memory access instructions

LDR r0,[r1]

Load word at address r1 into r0

STRNEB r2,[r3,r4]

STMFD sp!,{r4-r8,lr}

IF NE condition true, store bottom byte of r2 to

address r3+r4
Store registers r4 to r8 and lr on stack. Then update
stack pointer

THUMB INSTRUCTION SET

Thumb is a 16-bit instruction set

Optimized for code density from C code (~65% of ARM code size)

Improved performance from narrow memory

Subset of the functionality of the ARM instruction set

Thumb is not a regular instruction set because that targeted at compiler generation,
not hand coding.

An application code compiled in Thumb is 30% smaller on average than the same
code compiled in ARM and normally 30% faster when using narrow 16-bit memory
systems.

THUMB-2 INSTRUCTION SET

Thumb-2 is a major extension to the Thumb ISA

Adds 32-bit instructions to implement almost all of the ARM ISA functionality

Retains the complete 16-bit Thumb instruction set

Compiler automatically selects mix of 16 and 32 bit instructions

THE INSTRUCTION PIPELINE

The ARM7TDMI uses a 3-stage pipeline in order to increase the speed of the flow of
instructions to the processor which allows several operations to be performed simultaneously,
rather than sequentially. The basic steps of any operation is

Fetch :- Instruction fetched from memory

Decode :- Decoding of registers used in instruction
Execute :- Register(s) read from Register Bank, Shift and ALU operation, Write register(s)
back to Register Bank.

In ARM architecture, pipe-lining is possible because of its RISC feature in which all
instruction size is same so we can take advantage of pipe-lining. As you can see on above
figure when ADD instruction is executing we fetched and start decoding next instruction
SUB and at the same time we fetched the ORR instruction. So in the time of single
instruction execution, we performing 3 instruction. Therefore, this is called three stage pipelining.

EXCEPTION HANDLING

When an exception occurs, the core:

Copies CPSR into SPSR_<mode>

Sets appropriate CPSR bits

Change to ARM state

Change to exception mode

Disable interrupts (if appropriate)

Stores the return address in LR_<mode>

Sets PC to vector address

To return, exception handler needs to:

Restore CPSR from SPSR_<mode>

Restore PC from LR_<mode>

TERMS ASSOCIATED WITH ARM

EMBEDDEDICE
In order to provide a powerful debugging environment for ARM-based applications
the EmbeddedICE logic was developed and integrated into the ARM core architecture. It is a
set of registers providing the ability to set hardware breakpoints or watch-points on code or
data. The EmbeddedICE logic monitors the ARM core signals every cycle to check if a
break-point

or watch-point

has

been

hit.

Communication with the EmbeddedICE logic from the external world is provided
via the test access port or TAP, controller and a standard IEEE 1149.1 JTAG connection. The
advantage of on-chip debug solutions is the ability to rapidly debug software, especially
when the software resides in ROM or Flash.
AMBA Bus
The Advanced Micro-controller Bus Architecture on-chip bus is freely available from
ARM and offers an established, open specification that serves as a framework for SoC
designs.

Reference www.arm.com

The design of the AMBA bus specification is focused on low power consumption and high
performance. A typical AMBA-based SoC consists of an advanced high-performance system
bus(AHB), and an advanced low power peripheral bus(APB). As seen in above pic

On the performance critical side of the bus is the ARM core, Memory Controller, Test
Interface Controller (TIC), the LCD Controller, on-chip IP, custom logic, and
specialized functions.

On the low power side of the bus is the Smart Card interface, audio codec, UART,
PWM, Timers, GPIO, etc.

This is an excellent example of how the AHB and APB buses work in conjunction to
provide a complete system solution.

These bus protocols are independent of the ARM processor and generalized for SoC
application. The AMBA test methodology provides a mechanism to give an external tester
access to the on-chip AMBA bus. This enables the tester to take control of the bus and check
each component separately.

MMU
The Memory Management Unit works with the cache memory system to control accesses to
and from external memory. The MMU also controls the translation of Virtual Addresses to
physical addresses and access permission checks for the instruction and data ports of
Processors. An MMU mitigates the problem of fragmentation of memory too.
MPU
A separate Memory Protection Unit feature has been introduced in ARM by Cortex-M3 cores
which provide a way to control memory access rights to applications. This prevents a bug
within a process from affecting other processes, or the operating system itself, and instead
results in a segmentation fault or storage violation exception, generally causing termination
of the process. In ARM core, separate registers are provided by which you can configure
certain portion of memory and its access rights.

Why beginning with LPC2148 to start ARM ?

ARM7 is greatest success family in embedded system application. So here we learn

ARM7TDMI based NXPs controller.

ARM7 is balance between new Cortex series and old start up. it is neither too old
technology nor latest

ARM7 family is excellent for beginners as per my opinion, because it gives real depth
idea about hardware and software implementation & integration by using appropriate IDE.
Features of LPC2148

LPC2148 is the widely used IC from ARM-7 family. It is manufactured by Philips (NXP) and
it is pre-loaded with many inbuilt peripherals making it more efficient and a reliable option
for the beginners as well as high end application developer.

8 to 40 kB of on-chip static RAM

32 to 512 kB of on-chip flash program memory.

128 bit wide interface/accelerator enables high speed 60 MHz operation.

In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.

Embedded ICE RT and Embedded Trace interfaces offer real-time debugging with the
on-chip Real Monitor software and high speed tracing of instruction execution.

USB 2.0 Full Speed compliant Device Controller with 2 KB of endpoint RAM. In
addition, the LPC2146/8 provides 8 kB of on-chip RAM accessible to USB by DMA.

One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of
6/14analog inputs, with conversion times as low as 2.44 us per channel.
Single 10-bit D/A converter provides variable analog output.

Two 32-bit timers/external event counters (with four capture and four compare
channels each), PWM unit (six outputs) and watchdog.

Low power real-time clock with independent power and dedicated 32 kHz clock
input.

Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus(400
kbps), SPI and SSP with buffering and variable data length capabilities.

Vectored interrupt controller with configurable priorities and vector addresses.

Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.

Up to nine edge or level sensitive external interrupt pins available.

Power saving modes include Idle and Power-down.

Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out
Detect (BOD) or Real-Time Clock (RTC).

Single power supply chip with Power-On Reset (POR) and BOD circuits: CPU
operating

voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.

PIN-OUT OF LPC 2148

ARM IDENTIFICATION

For Example : ARM 7 TDMI (LPC2148)

ARM 7 MODES
1.
2.

User mode all normal application run under this mode

FIQ mode all fast interrupt data transfer or channel process service
provided under this mode
3.
IRQ mode vectored(priority based) interrupt handler
4.
Supervision mode protected mode for the operating system
5.
System mode all operating related task
6.
Abort mode entered after a data or instruction Pre-fetch Abort
exception
7.
Undefined mode entered when an undefined instruction is
executed.
All these mode indicates its special work and execute
under certain condition. Modes other than User mode are collectively
known as privileged modes. your program or application generally runs
under User mode. Privileged modes are used to service interrupts or
exceptions, or to access protected resources.

SYSTEM PERIPHERALS
MEMORY MAP
Despite the internal buses, the LPC2000 has a complete linear map. The general
map is as below:

The on-chip flash is fixed at 0X00000000 upwards with the user RAM fixed at 0X40000000
upwards. The LPC2000 is a pre-programmed at manufacture with a FLASH bootloader and
the ARM real monitor debug program. These programs are placed in the region
0X7FFFFFFF-0X80000000. The region between 0X80000000 and 0XE0000000 is reserved
for external memory. Currently the LPC2000 can be used to address external memory via
four chip-selects each with 16mb page.

The user peripherals are located on the VPB are all mapped onto the region between
0XE0000000 and 0XE2000000 and each peripheral is located at a 16k memory page. The
vectored interrupt unit is located on top of the address range at 0XFFFFF000.
If the user tries to access a memory region outside the defines memory region then an abort
exception is generated by the controller.

REGISTER PROGRAMMING

Each underlying SFR (special function register) is controlled by 3 ser registers. A

set register which is used to set the bits, a clear register which is used to clear
the bits of the register by writing logic 1 to the register and the status register is
used to read the current contents of the register

MEMORY ACCELERATOR MODULE

The memory accelerator module (MAM) is the key to high instruction execution
rate of the LPC2100 family. The MAM is present on the local bus and sits
between the FLASH memory and the ARM7CPU.

One of the constrain in designing a high performance, single chip microcontroller

based ARM7 is access time to the on-chip FLASH memory. The ARM CPU is
capable of running at 80MHz however the on-chip FLASH has an access time of
50ns. Consequently running out of flash would limit the execution speed to 20
MHz. To solve this problem
1. Load all the critical sections of the code RAM and run out of RAM. RAM has
much faster access time, overall performance is greatly increased. The downside
in this onchip RAM is a finite and precious resource. Using it to hold instruction
can greatly reduce the area for storing application code which could run.

2. Another approach is to use on chip cache. A cache is a small region placed

between the processor and the memory store which stores regions of recently
referenced main memory. If a well defined cache, the processor will use the
cache memory for reducing the bottleneck imposed by slow memory. However a
full cache is a complex peripheral which demand a lot of gates and lot of die
area.
Thus, the memory accelerator module is a compromise between full cache and
direct access to flash. Like cache MAM attempts to have the next ARM instruction
in its local memory in time for the CPU to execute. The flash is divided into two
banks of128bits and can independently be accessed i.e. a single flash can load 4
ARM or 8 THUMB instructions. User code is interleaved between the two banks
and is fetched from one bank into the MAM is being executed then the next
instruction will be ready for execution. In case of trails and jumps the MAM has
trail buffers which hold recently executed instruction which can be re-executed if
registered.

PHASE LOCKED LOOP (PLL):

The PLL can take an external oscillator frequency from 10MHz- 25MHz from the
fundamental crystal frequency and multiply the frequency to a maximum of
60MHz to provide on-chip clocks for ARM7 CPU and peripherals. This allows the
LPC21XX to work at low values external oscillator , thus minimizing the EMC
emissions. The PLL output frequency can also be changed dynamically, allowing
a device to throttle back its execution speed to conserve power when the device
is idle.

Within the PLL it has two constants which must be programmed in order to
determine the clock for the CPU and AHB. This is called the CCLK. The first
constant is the straight forward multiplier of the external oscillator The output
frequency of the PLL is given by
CCLK = M X Osc (frequency of the crystal)
The Feedback path is a current controlled oscillator must operate in the range of
152MHz - 320 MHz. The second constant acts as a programmable divider which
ensures that the CCO is kept in specification. The operating frequency of the CCO
is defined as
FCCO = CCLK x 2 x P

The programming interface for the PLL is as shown below:

The values are written into SFR's are not transferred to the PLL until the feed
sequence is written into the PLL feed register. Once updated the PLLCON and
PLLCFG registered must be written with the sequences 0X000000AA followed by
0X00000055 these values are written on consecutive cycles. To set up the PLL
values must be written to the P and M of the PLLCFG registers. Then using
PLLCON registers the PLL is enabled. There is a finite startup time before the PLL
is stable enough to start the CCLK source. The status of the PLL can be
monitored by reading the LOCK bit of the PLLSTATUS register. Once the LOCK bit
is set the PLL can be used to maintain the main clock source.
An interrupt can be generated in the PLL when the PLL locks so as to carry out
other tasks while the PLL starts. Once the PLL is locked
as a stable clock
source it can replace the external oscillator as a source of CCLK this is done via
the PLLC and PLLCON bit.

Care should be taken for the values stored in the PLLCONFG register. The P and
M bits should never be 0. The value of M is 5 bit long so the value of P is not on
an even nibble boundary. If a simple mistake is done while setting up the PLL the
chip will enter a power down mode and is disconnected. A wake up mode does
not exist in the PLL so the same start up sequence must be followed each time
the chip enters a power down mode.

User Peripherals:
General Purpose I/O:

On reset the pin connect block configures all the peripherals to be general IO
pins. The GPIO pins are controlled by 4 registers.
IOPIN - gives the value stored of the registers
IOSET - sets the pin to accept values
IOCLR: clears the values of the registers
IODIR: defines the direction of the pin allows each pin to be configured as wither
input (0) or output (1).

INTERFACING ARM7 WITH LED:

CIRCUIT DIAGRAM:

#include<lpc21xx.h> // header file for lpc2148 controller

void delay(); // initialization of delay function
int main()
{
PINSEL0=0X00000000; // SELECT PORT0 PIN0 TO PIN 15 AS GPIO
MODE
IO0DIR=0XFFFFFFFF; // MAKE PORT0 PIN AS OUTPUT MODE
while(1)
{
IO0SET=0XFFFFFFFF; // SET THE PORT0 PINS
delay();
// HAULT FOR SOME TIME
IO0CLR=0XFFFFFFFF; // CLEAR THE PORT0 PINS
delay();
//HAULT FOR SOME TIME
}
}
void delay() // initialization of delay function
{
int i,j;
for(i=0;i<1000;i++)
for(j=0;j<1000;j++);
}

INTERFACING LCD WITH ARM7:

#include<lpc21xx.h>
#define
#define
#define
#define
void
void
void
void

LCD (0xff<<16)
RS (1<<13)
RW (1<<14)
EN (1<<15)

delay_fv(unsigned int x,int y);

lcd_display(unsigned int x);
cmd(unsigned char m);
lcd_ini();

int main()
{
PINSEL0=0X00000000;
IO0DIR=0XFFFFFFFF;
lcd_ini();
while(1)
{
lcd_ini();
lcd_display(' ');
lcd_display('W');
delay_fv(1000,400);
lcd_display('E');
delay_fv(1000,400);
lcd_display('L');

delay_fv(1000,400);
lcd_display('C');
delay_fv(1000,400);
lcd_display('O');
delay_fv(1000,400);
lcd_display('M');
delay_fv(1000,400);
lcd_display('E');
delay_fv(1000,400);
lcd_display(' ');
delay_fv(1000,400);
lcd_display('T');
delay_fv(1000,400);
lcd_display('O');
delay_fv(1000,400);
cmd(0x0c0);
lcd_display('F');
delay_fv(1000,400);
lcd_display('I');
delay_fv(1000,400);
lcd_display('R');
delay_fv(1000,400);
lcd_display('M');
delay_fv(1000,400);
lcd_display('C');
delay_fv(1000,400);
lcd_display('O');
delay_fv(1000,400);
lcd_display('D');
delay_fv(1000,400);
lcd_display('E');
delay_fv(1000,400);
lcd_display('S');
delay_fv(1000,400);
lcd_display('.');
delay_fv(1000,400);
lcd_display('C');
delay_fv(1000,400);
lcd_display('O');
delay_fv(1000,400);
lcd_display('M');
delay_fv(1000,400);
}
}
void delay_fv(unsigned int x,int y)
{
unsigned int i,j;
for(i=0;i<x;i++)
for(j=0;j<y;j++);
}
void lcd_display(unsigned int x)
{

IO0CLR|=(RS|RW|EN|LCD);
IO0SET|=(x<<16);
IO0SET|=RS;
IO0CLR|=RW;
IO0SET|=EN;
delay_fv(100,10);
IO0CLR|=EN;
delay_fv(10,10);
}
void cmd(unsigned char m)
{
IO0CLR|=(RS|RW|EN|LCD);
IO0SET|=(m<<16);
IO0CLR|=RS;
IO0CLR|=RW;
IO0SET|=EN;
delay_fv(100,100);
IO0CLR|=EN;
delay_fv(100,10);
}
void lcd_ini()
{
cmd(0X38);
cmd(0X0e);
cmd(0X06);
cmd(0X01);
cmd(0X80);
}

RS232 WITH ARM 7

#include<lpc21xx.h>

void delay(void);
void receive(void);
void transmit(void);
char c;
void lcd(unsigned char a,int b);
int main(void)
{
PINSEL0|=(1<<0)|(1<<2); //Selecting pin functions
PINSEL2=0;
IODIR1=0x03ff0000;
//Setting Directions for LCD
lcd(0x38,0);
lcd(0x0f,0);
U0LCR=(1<<7);
//Making DLAB bit as '1'
U0DLL=0x21;
//Baud Rate Value
U0LCR=0x03;
//DLAB as 0 and word length
selection
delay();
transmit();
while(1)
{
receive();
//Infinite receive loop
}
}
void delay(void)
//Software Delay
{
unsigned int i;
for(i=0;i<=3000;i++);
}
void lcd(unsigned char a,int b)
//LCD subroutine
{
IOSET1=a<<16;
IOSET1=b<<24;
IOSET1=1<<25;
delay();
IOCLR1=1<<25;
IOCLR1=b<<24;
IOCLR1=a<<16;
}
void receive(void)
//Receive subroutine
{
while(!(U0LSR&(1<<0)));
//Status check
c=U0RBR;
lcd(c,1);
}
void transmit(void)
//Transmit subroutine for "SND"
{
U0THR='S';
while(!(U0LSR&(1<<5))); //Status check
U0THR='N';
while(!(U0LSR&(1<<5)));
U0THR='D';
while(!(U0LSR&(1<<5)));
}

INTERFACING TIMER WITH ARM7:

#include<lpc21xx.h>
# define PRESCALAR 60000

// define prescalar as 60000

void pll();
void timer0_ini();
void delay(unsigned long int ms);
int main()
{
PINSEL0=0x00000000; // select gpio pin
IO0DIR=0XFFFFFFFF; // make gpio as output pin
pll();
// calling pll function
timer0_ini();
// calling timer function
while(1)
{
IO0SET=0XFFFFFFFF; // led on
delay(0x000000fF); // delay using timer 0
IO0CLR=0XFFFFFFFF; // led off
delay(0x000000fF); // delay using timer 0
}
return 0;
}
void pll()
{
//PLL IS CONFIGURED TO GET 60HZ pCLK
PLLCFG=0X24;
// SET PSEL=2 AND MSEL=5

PLLCON=0X01;
//PLL IS ACTIVE BUT NOT YET CONNECT
PLLFEED=0XAA;
//FEED SEQUENCE
PLLFEED=0X55;
//FEED SEQUENCE
while((PLLSTAT & 0X400)==0); //WAIT FOR FEED SEQUENCE TO BE
INSERTED
PLLCON=0X03;
VPBDIV=0X00;
PLLFEED=0XAA;
PLLFEED=0X55;

// PLL HAS BEEN ACTIVE AND BEING CONNECTRD

// SET PCLK SAME AS FCCLK
//FEED SEQUENCE
//FEED SEQUENCE

}
void timer0_ini()
{
T0TCR=0X0; // to stop timer
T0PR=PRESCALAR-1; //load the timer value
T0TCR=0X02;
//reset timer
}
void delay(unsigned long int ms)
{
T0TC=0x00000000; // t0 reset timer counting
T0TCR=0X02; // reset the timer
T0TCR=0X01; // start timer
while(T0TC<=ms); // check the condition
T0TCR=0X00; // stop timer
}

SQUARE WAVE
#include<lpc21xx.h>
# define PRESCALAR 60000

// define prescalar as 60000

void pll();
void timer0_ini();
void delay(unsigned long int ms);
int main()
{
PINSEL0=0x00000000; // select gpio pin
IO0DIR=0XFFFFFFFF; // make gpio as output pin
pll();
// calling pll function
timer0_ini();
// calling timer function
while(1)
{
IO0SET=0X01; // high level
delay(0x0000000F); // delay using timer 0
IO0CLR=0X01; // low level
delay(0x0000000F); // delay using timer
0

}
return 0;
}
void pll()
{
//PLL IS CONFIGURED TO GET 60HZ pCLK
PLLCFG=0X24;
// SET PSEL=2 AND MSEL=5
PLLCON=0X01;
//PLL IS ACTIVE BUT NOT YET CONNECT
PLLFEED=0XAA;
//FEED SEQUENCE
PLLFEED=0X55;
//FEED SEQUENCE
while((PLLSTAT & 0X400)==0); //WAIT FOR FEED SEQUENCE TO BE
INSERTED
PLLCON=0X03;

// PLL HAS BEEN ACTIVE AND BEING

VPBDIV=0X00;
PLLFEED=0XAA;
PLLFEED=0X55;

// SET PCLK SAME AS FCCLK

//FEED SEQUENCE
//FEED SEQUENCE

CONNECTRD

}
void timer0_ini()
{
T0TCR=0X0; // to stop timer
T0PR=PRESCALAR-1; //load the timer value
T0TCR=0X02;
//reset timer
}
void delay(unsigned long int ms)
{
T0TC=0x00000000; // t0 reset timer counting
T0TCR=0X02; // reset the timer
T0TCR=0X01; // start timer
while(T0TC<=ms); // check the condition
T0TCR=0X00; // stop timer
}

INTERFACING ADC WITH ARM7

#include<LPC21XX.H> // header file for lpc2148

#include<stdio.h>
#include <stdlib.h>
unsigned int temperature;
int i;
char conv_temp[8];
void adc(void);
void lcd(unsigned char data,int rs_status); //lcd subroutine
void delay(void);
int main(void)
{
PINSEL0=0;
IODIR0=0x00000fff;
VPBDIV=0x00;
PINSEL1=(1<<22);
//Specifying A/D pin function
lcd(0x38,0);
//lcd intialization
lcd(0x0c,0);
while(1)
{
lcd(0x80,0);
adc();
}
}
void adc(void)
{
ADCR|=(1<<0)|(1<<16)|(1<<8)|(1<<21)|(1<<24); //mode selection
while(!(ADDR&(0x80000000)));
//Checking conversion status
temperature=(ADDR>>6)&0x3ff;
//Reading A/D value
// temperature=temperature/3;
//Real temp conversion
sprintf(conv_temp,"%lu",temperature); //int to char conversion
for(i=0;i<=5;i++)
lcd(conv_temp[i],1);

}
void lcd(unsigned char data,int rs_status)
{
IOSET0=(data<<0);
IOSET0=(rs_status<<8);
IOSET0=(1<<9);
delay();
IOCLR0=(1<<9);
IOCLR0=(rs_status<<8);
IOCLR0=(data<<0);
}
void delay(void)
{
unsigned int j;
for(j=0;j<=10000;j++);
}

SPI WITH ARM7

www.firmcodes.com
DEVELOPED BY:- FIRMWARE DEVELOPER
WHAT PROGRAM DO:- Program Of Multiplex 8 Seven Segment Using
Max7221 And Controlled With ARM(LPC21XX) Using SPI Protocol

******************************************************/
#include<lpc21xx.h>
unsigned char spi_rec;
void spi_ini();
void spi_tr1(unsigned int x);
char spi_re();
void spi_tr(unsigned char cmd,unsigned char data);
void spi_str(unsigned char *str);
int ar[10]={ 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f };
int ar1[8]={0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08};
void pll();
void delay_ms(unsigned int x);
int main()
{
int i,a,b,c,d,e,f,g,h;
a=b=c=d=e=f=g=h=0;
PINSEL0=0X00000000;
IO0DIR=0XFFFFFFFF;
pll();
spi_ini();
spi_tr(0x0a,0xf);
spi_tr(0x0b,0xf);
for(i=0;i<9;i++)
{
spi_tr(ar1[i],ar[0]);
delay_ms(100);
}
spi_tr(0x0c,0x01);
while(1)
{
spi_tr(ar1[7],ar[a]);
spi_tr(ar1[6],ar[b]);
spi_tr(ar1[5],ar[c]);
spi_tr(ar1[4],ar[d]);
spi_tr(ar1[3],ar[e]);
spi_tr(ar1[2],ar[f]);
spi_tr(ar1[1],ar[g]);
spi_tr(ar1[0],ar[h]);
a++;
if(a==10)
{
a=0;
b++;
}
if(b==10)
{

a=b=0;
c++;
}
if(c==10)
{
a=b=c=0;
d++;
}
if(d==10)
{
a=b=c=d=0;
e++;
}
if(e==10)
{
a=b=c=d=e=0;
f++;
}
if(f==10)
{
a=b=c=d=e=f=0;
g++;
}
if(g==10)
{
a=b=c=d=e=f=g=0;
h++;
}
if(h==10)
{
a=b=c=d=e=f=g=h=0;
}
delay_ms(3000);
}
}
void pll()
{
/*PLL IS CONFIGURED TO GET 60HZ pCLK*/
PLLCFG=0X24;
// SET PSEL=2 AND MSEL=5
PLLCON=0X01;
//PLL IS ACTIVE BUT NOT YET
CONNECT
PLLFEED=0XAA;
//FEED SEQUENCE
PLLFEED=0X55;
//FEED SEQUENCE
while((PLLSTAT & 0X400)==0); //WAIT FOR FEED SEQUENCE
TO BE INSERTED
PLLCON=0X03;

// PLL HAS BEEN ACTIVE AND BEING

VPBDIV=0X00;
PLLFEED=0XAA;
PLLFEED=0X55;

// SET PCLK SAME AS FCCLK

//FEED SEQUENCE
//FEED SEQUENCE

CONNECTRD

}
void spi_ini()

{
PINSEL0 |=0x1500;
/* P0.4, P0.5, P0.6, P0.7 are set as SCK,
MISO, MOSI and GPIO */
//IODIR0 |= 0X80;
/* SSEL is output */
//IOSET0 |=0X80;
/* set SSEL to high */
S0SPCCR=8;
/* SPI clock
prescale register minimum value is 8. */
S0SPCR=0x0030;
/* Device select as
master, Set data to 8-bit, CPOL = 0, CPHA = 0*/
}
void spi_tr1(unsigned int x)
{
S0SPDR =x;
while ( !(S0SPSR & 0x80) );
trabsfer complete */
}

/* Wait until the SPIF bit is set to indicate

char spi_re()
{
while ( !(S0SPSR & 0x80) );
trabsfer complete */
spi_rec= S0SPDR;
return spi_rec;
}

/* Wait until the SPIF bit is set to indicate

void spi_str(unsigned char *str)

{
while(*str!='\0')
{
spi_tr1(*str);
str++;
}
}
void spi_tr(unsigned char cmd,unsigned char data)
{
IO0CLR=(1<<7); //enable transmission
spi_tr1(cmd);
spi_tr1(data);
IO0SET=(1<<7); // disable transmission
}
void delay_ms(unsigned int x)
{
int i;
while(x--)
{
for(i=0;i<100;i++);
}
}

RTC WITH ARM7:

#include<lpc21xx.h>
#define
#define
#define
#define

LCD (0xff<<16)
RS (1<<13)
RW (1<<14)
EN (1<<15)

void delay_fv(unsigned int x,int y);

void
void
void
void
void

lcd_display(unsigned int x);

cmd(unsigned char m);
lcd_pos(int line,int pos);
lcd_ini();
lcd_str(unsigned char *x);

unsigned char flag=0;

void init_rtc();
void main()
{
unsigned int i,j,k,l,m,n;
PINSEL0=0X00000000;
PINSEL1=0X00000000;
IO0DIR=0XFFFFFFFF;

lcd_ini();
init_rtc();
lcd_str("CLOCK:- 24");
cmd(0xc0);
lcd_str("00:00:00");
while(1)
{
if(flag)
{
flag=0;
lcd_pos(2,0);
lcd_display(HOUR/10 + '0');
lcd_display(HOUR%10 + '0');
lcd_display(':') ;
lcd_display(MIN/10 + '0');
lcd_display(MIN%10 + '0');
lcd_display(':') ;
lcd_display(SEC/10 + '0');
lcd_display(SEC%10 + '0');
}
}
}
void delay_fv(unsigned int x,int y)
{
unsigned int i,j;
for(i=0;i<x;i++)
for(j=0;j<y;j++);
}
void lcd_display(unsigned int x)
{
IO0CLR|=(RS|RW|EN|LCD);
IO0SET|=(x<<16);
IO0SET|=RS;
IO0CLR|=RW;
IO0SET|=EN;
delay_fv(100,10);
IO0CLR|=EN;
delay_fv(10,10);
}
void cmd(unsigned char m)
{
IO0CLR|=(RS|RW|EN|LCD);
IO0SET|=(m<<16);
IO0CLR|=RS;
IO0CLR|=RW;
IO0SET|=EN;
delay_fv(100,250);
IO0CLR|=EN;
delay_fv(10,10);
}

void lcd_pos(int line,int pos)

{
if(line==1)
cmd(0x80+pos);
else if(line==2)
cmd(0xc0+pos);
}
void lcd_ini()
{
cmd(0X38);
cmd(0X0e);
cmd(0X06);
cmd(0X01);
cmd(0X80);
}
void lcd_str(unsigned char *x)
{
while(*x!='\0')
{
lcd_display(*x);
x++;
}
}
void rtc_int(void)__irq
{
ILR = 0X01;
flag = 1;
VICVectAddr = 0X00000000;
}
void init_rtc()
{
ILR = 0X01;
CCR = 0X13;
CCR = 0X11;
CIIR = 0X01;
SEC = 0X00;
HOUR = 12;
MIN = 11;
VICIntEnable = 0x00002000;
VICVectCntl0 = 0x0000002D;
VICVectAddr0 = (unsigned)rtc_int;
}

INTERRUPTS ON ARM7:

#include <lpc21xx.h> // header file of arm controller

#include "delay.h" // delay header file
#include "lcd4bit.h" // header file of lcd
int ar[10]={ 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f };// common
cathode code
int count=0; // varible of type int
void interrupt_ini(); // interrupt intilization
int main()
{

// start of main program

PINSEL0=0X00000000;
PINSEL1=0X00000000;

// port0.0 to port0.15 used as gpio mode

// port0.16 to port0.31 used as gpio

PINSEL2=0X00000000;

// port1.16 to port1.32 used as gpio

mode
mode
IO0DIR=0X0fFFFFFF;
// direction of port0.0 to port0.31 worked
as output mode
IO1DIR=0XFFFFFFFF;
// direction of port1.0 to port1.31 worked
as output mode
lcd_ini();
// lcd initilization function
interrupt_ini();
// interrupt intilization function
while(1)
{

IO1SET|=(ar[count]<<16);
delay_fv(1000,1000);
IO1CLR|=(ar[count]<<16);
count++;
if(count==10)
count=0;
}
return 0;
}
void interrupt_0()__irq // interrupt 0
{
EXTINT=0X01;
IO0SET|=(0XFF<<16);
delay_fv(500,1000);
IO0CLR|=(0XFF<<16);
delay_fv(500,1000);
}
void interrupt_1()__irq // interrupt 1
{
EXTINT=0X02;
cmd(0x01);
lcd_str("WELCOME TO");
cmd(0xc0);
lcd_str("FIRMCODES.COM");
delay_fv(1000,1000);
}
void interrupt_ini()
{
/* intialize interrupt 0*/
PINSEL0|=0x0c;
VICVectAddr0=(unsigned)interrupt_0;
VICVectCntl0=0x20|14;
VICIntEnable=1<<14;
// delay_fv(1000,100);
/* intialize interrupt 1*/
PINSEL0|=0xc0;
VICVectAddr1=(unsigned)interrupt_1;
VICVectCntl1=0x20|15;
VICIntEnable=1<<15;
}
DELAY.H HEADER FILE
***********************************************************************/
void delay_ff()
{
unsigned int b,v;
for(b=0;b<600;b++)

for(v=0;v<100;v++);
}
void delay_pf(unsigned int x)
{
unsigned int i,j;
for(i=0;i<x;i++)
for(j=0;j<153;j++);
}
void delay_fv(unsigned int x,int y)
{
unsigned int i,j;
for(i=0;i<x;i++)
for(j=0;j<y;j++);
}
void delay_ms(int count)
{
int j=0,i=0;
for(j=0;j<count;j++)
{
/* At 60Mhz, the below loop introduces
delay of 10 us */
for(i=0;i<35;i++);
}
}
LCD4BIT.H HEADER FILE
*********************************************************************/
#define LCD (0xf<<11)
#define RS (1<<8)
#define RW (1<<9)
#define EN (1<<10)
void lcd_display(unsigned char x)
{
unsigned int temp;
delay_ms(1000);
IO0CLR|=(RS|RW|EN|LCD);
temp=(x>>4)&0x0f;
//delay_ms(10);
IO0SET|=RS;
IO0CLR|=RW;
IO0SET|=EN;
IO0CLR|=LCD;
IO0SET|=(temp<<11);
delay_ms(100);
IO0CLR|=EN;
delay_fv(10,10);
IO0CLR|=(RS|RW|EN|LCD);

temp=x&0x0f;
//delay_ms(1000);
IO0SET|=RS;
IO0CLR|=RW;
IO0SET|=EN;
IO0CLR|=LCD;
IO0SET|=(temp<<11);
delay_ms(100);
IO0CLR|=EN;
delay_ms(100);
}
void cmd(unsigned char x)
{
unsigned int temp;
delay_ms(100);
temp=(x>>4)&0x0f;
IO0CLR|=(RS|RW|EN);
IO0CLR|=RS;
IO0CLR|=RW;
IO0SET|=EN;
IO0CLR|=LCD;
IO0SET|=(temp<<11);
delay_ms(100);
IO0CLR|=EN;
delay_fv(100,10);
IO0CLR|=(RS|RW|EN);
temp=x&0x0f;
IO0SET|=(temp<<11);
IO0CLR|=RS;
IO0CLR|=RW;
IO0SET|=EN;
IO0CLR|=LCD;
IO0SET|=(temp<<11);
delay_ms(100);
IO0CLR|=EN;
delay_fv(100,100);
}
void lcd_ini()
{
PINSEL0|=(0XFF<<8);
IO0DIR|=(0XF<<8);
cmd(0X02);
cmd(0X28);
// cmd(0X02);
cmd(0x0e);
cmd(0X06);
cmd(0X01);
cmd(0X80);
}

void lcd_str(unsigned char *str)

{
while(*str!='\0')
{
lcd_display(*str);
str++;
}
}