Libraries Guide

ISE 6.3i

"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved.
CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are
registered trademarks of Xilinx, Inc.

The shadow X shown above is a trademark of Xilinx, Inc.

ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator,
CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and
Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia,
MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, SelectRAM+,
Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze,
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The Programmable Logic Company is a service mark of Xilinx, Inc.
All other trademarks are the property of their respective owners.
Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey
any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any
time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for
the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or
information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature,
application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are
responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with
respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation
is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices
and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown
or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to
correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability
for the accuracy or correctness of any engineering or software support or assistance provided to a user.
Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without
the written consent of the appropriate Xilinx officer is prohibited.
The contents of this manual are owned and copyrighted by Xilinx. Copyright 1994-2004 Xilinx, Inc. All Rights Reserved. Except as stated
herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form
or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent
of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and
publicity, and communications regulations and statutes.

Libraries Guide

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ISE 6.3i

About This Guide

The Libraries Guide is part of the ISE documentation collection.

Guide Contents
This guide contains the following:

Discussion of the Xilinx Unified Libraries

Slice Count information for FPGAs

Architecture-Specific Information sections

A listing of the various Functional Categories of design elements

Individual sections for each of the Design Elements

Additional Resources
For additional information, go to http://www.xilinx.com/support. The following
table lists some of the resources you can access from this website. You can also directly
access these resources using the provided URLs.
Resource
Tutorials

Description/URL
Tutorials covering Xilinx design flows, from design entry to verification
and debugging

http://www.xilinx.com/support/techsup/tutorials/index.htm
Answer Browser

Database of Xilinx solution records

http://www.xilinx.com/xlnx/xil_ans_browser.jsp

Application
Notes

Descriptions of device-specific design techniques and approaches

http://www.xilinx.com/apps/appsweb.htm

Data Sheets

Pages from The Programmable Logic Data Sheets, which contains devicespecific information on Xilinx device characteristics, including readback,
boundary scan, configuration, length count, and debugging http://
www.xilinx.com/xlnx/xweb/xil_publications_index.jsp

Problem Solvers

Interactive tools that allow you to troubleshoot your design issues

http://www.xilinx.com/support/troubleshoot/psolvers.htm
Tech Tips

Latest news, design tips, and patch information for the Xilinx design
environment

http://www.xilinx.com/xlnx/xil_tt_home.jsp

Libraries Guide
ISE 6.3i

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About This Guide

Conventions
This document uses the following conventions. An example illustrates each
convention.

Typographical
The following typographical conventions are used in this document:
Convention

Meaning or Use

Example

Courier font

Messages, prompts, and program

files that the system displays

Courier bold

Literal commands that you enter in ngdbuild design_name

a syntactical statement

Helvetica bold

Commands that you select from a

menu

File Open

Keyboard shortcuts

Ctrl+C

Italic font

speed grade: - 100

Variables in a syntax statement for ngdbuild design_name

which you must supply values
References to other manuals

See the Development System

Reference Guide for more
information.

Emphasis in text

If a wire is drawn so that it

overlaps the pin of a symbol,
the two nets are not connected.

Square brackets [ ]

An optional entry or parameter.

However, in bus specifications,
such as bus[7:0], they are
required.

ngdbuild [option_name]
design_name

Braces

A list of items from which you

must choose one or more

lowpwr ={on|off}

Vertical bar |

Separates items in a list of choices

lowpwr ={on|off}

Vertical ellipsis
.
.
.

Repetitive material that has been

omitted

IOB #1: Name = QOUT

IOB #2: Name = CLKIN
.
.
.

Horizontal ellipsis . . .

Repetitive material that has been

omitted

allow block block_name loc1

loc2 ... locn;

{ }

Online Document
The following conventions are used in this document:
Convention

Meaning or Use

Example

Blue text

Cross-reference link to a location See the section Additional

in the current document
Resources for details.

Red text

Cross-reference link to a location See Figure 2-5 in the Virtex-II

in another document
Handbook.

Blue, underlined text

Hyperlink to a website (URL)

www.xilinx.com
1-800-255-7778

Go to http://www.xilinx.com
for the latest speed files.

Libraries Guide
ISE 6.3i

Whats New

Whats New
The following design elements have been removed from the current release:

GT10_3GIO_n

IOBUFE

The following design elements have been added to the current release:

Libraries Guide
ISE 6.3i

IBUFDS_DIFF_OUT

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Libraries Guide
ISE 6.3i

Table of Contents
About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Whats New . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Xilinx Unified Libraries

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applicable Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Attributes and Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17
18
18
18
18
19
19

19
Spartan-II, Spartan-IIE, Virtex, and Virtex-E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3 . . . . . . . . . . . . . . . . . . . . . . . . . 20

Flip-Flop, Counter, and Register Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Unconnected Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Slice Count
About Configurable Logic Blocks (CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Slice Count for FPGA Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Architecture-Specific Information
Spartan-II and Spartan-IIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spartan-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtex and Virtex-E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtex-II, Virtex-II Pro, Virtex-II Pro X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC9500/XV/XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoolRunner XPLA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CoolRunner-II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

39
41
45
47
51
53
55

Functional Categories
Arithmetic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Edge Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Input Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Input/Output Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Input/Output Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Logic Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Map Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Memory Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Design Elements
ACC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACC4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADD4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADSU1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADSU4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AND2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AND12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BRLSHFT4, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BSCAN_SPARTAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BSCAN_SPARTAN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BSCAN_VIRTEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BSCAN_VIRTEX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUF4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFE, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFGCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFGCE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFGDLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFGMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFGMUX_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFGSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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107
111
119
121
127
131
137
143
147
149
151
153
155
157
159
161
163
167
169
171
173
175
177
179
181

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ISE 6.3i

BUFGTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFT, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAPTURE_SPARTAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAPTURE_SPARTAN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAPTURE_VIRTEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAPTURE_VIRTEX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CB2CE, CB4CE, CB8CE, CB16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CB2CLE, CB4CLE, CB8CLE, CB16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CB2CLED, CB4CLED, CB8CLED, CB16CLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CB2RE, CB4RE, CB8RE, CB16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CB2RLE, CB4RLE, CB8RLE, CB16RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CB2X1, CB4X1, CB8X1, CB16X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CB2X2, CB4X2, CB8X2, CB16X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBD2CE, CBD4CE, CBD8CE, CBD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED . . . . . . . . . . . . . . . . . . . . . . .
CBD2RE, CBD4RE, CBD8RE, CBD16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBD2X1, CBD4X1, CBD8X1, CBD16X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBD2X2, CBD4X2, CBD8X2, CBD16X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC8CE, CC16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC8CLE, CC16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC8CLED, CC16CLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC8RE, CC16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDD4CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDD4CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDD4RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDD4RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CJ4CE, CJ5CE, CJ8CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CJ4RE, CJ5RE, CJ8RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CJD4CE, CJD5CE, CJD8CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CJD4RE, CJD5RE, CJD8RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK_DIV2,4,6,8,10,12,14,16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK_DIV2,4,6,8,10,12,14,16R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK_DIV2,4,6,8,10,12,14,16RSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK_DIV2,4,6,8,10,12,14,16SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKDLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKDLLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Libraries Guide
ISE 6.3i

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1-800-255-7778

183
185
189
191
193
195
197
201
205
209
213
215
219
223
225
229
233
237
241
243
247
251
255
259
263
267
271
275
279
281
283
285
287
289
291
293
295
299
305
313
321
325

CLKDLLHF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMP2, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMPM2, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMPMC8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CR8CE, CR16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRD8CE, CRD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D2_4E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D3_8E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D4_16E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEC_CC4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DECODE4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DECODE32, 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD4CE, FD8CE, FD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD4RE, FD8RE, FD16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDC_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDCE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDCP_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDCPE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDD4,8,16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDD4CE, FDD8CE, FDD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDD4RE, FDD8RE, FDD16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDRCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDRRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10

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329
333
335
339
343
347
349
351
353
355
363
365
367
369
371
373
375
377
379
381
383
385
387
389
391
395
397
399
401
403
405
407
409
411
413
415
417
419
421
423
425
427

Libraries Guide
ISE 6.3i

FDDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDDSRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDP_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDPE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDR_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDRE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDRS_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDRSE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDS_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDSE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDSRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FJKC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FJKCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FJKCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FJKCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FJKP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FJKPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FJKRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FJKSRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FMAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTCLEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTCPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTDCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTDCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

429
431
433
435
437
439
441
445
447
451
453
455
457
461
463
467
469
473
475
477
479
483
485
487
489
491
493
495
497
499
501
503
505
507
511
515
517
519
521
523
525
527

11

FTDCLEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTDCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTDRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTDRSLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTRSLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTSRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTSRLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT_AURORA_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT_CUSTOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT_ETHERNET_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT_FIBRE_CHAN_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT_INFINIBAND_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT_XAUI_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT10_AURORA_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT10_AURORAX_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT10_CUSTOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT10_INFINIBAND_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT10_XAUI_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT10_10GE_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT10_10GFC_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT10_OC48_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT10_OC192_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GT10_PCI_EXPRESS_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IBUF, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IBUFDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IBUFDS_DIFF_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IBUFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IBUFGDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICAP_VIRTEX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFDDRCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFDDRRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFDI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFDX, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFDX_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12

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529
531
533
535
537
541
543
545
547
549
551
553
555
559
561
565
569
573
577
581
585
587
591
595
599
603
607
611
615
627
631
633
637
641
643
647
649
651
653
655
657
661

Libraries Guide
ISE 6.3i

IFDXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFDXI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ILD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ILD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ILDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ILDI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ILDX, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ILDX_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ILDXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ILDXI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INV, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOBUFDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOPAD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPAD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAGPPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
KEEPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDC_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDCE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD4CE, LD8CE, LD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDCP_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDCPE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDG4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDP_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDPE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LUT1, 2, 3, 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LUT1_D, LUT2_D, LUT3_D, LUT4_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LUT1_L, LUT2_L, LUT3_L, LUT4_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M2_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M2_1B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

663
665
667
671
673
675
677
681
683
685
687
689
693
695
697
699
701
703
707
709
711
713
715
717
719
721
723
725
727
729
731
733
735
737
739
741
743
745
751
757
763
765

13

M2_1B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M2_1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M4_1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8_1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M16_1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MULT_AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MULT18X18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MULT18X18S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXCY_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXCY_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXF5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXF5_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXF5_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXF6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXF6_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXF6_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXF7_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXF7_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXF8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXF8_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUXF8_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NAND2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NAND12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOR2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOR12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OBUF, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OBUFDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OBUFE, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OBUFT, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OBUFTDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFDDRCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFDDRRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFDDRTCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFDDRTRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFDE, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFDE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFDI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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767
769
771
773
775
777
779
781
783
785
787
789
791
793
795
797
799
801
803
805
807
809
811
813
817
821
825
829
835
837
841
847
849
855
857
859
861
865
867
871
873
875

Libraries Guide
ISE 6.3i

OFDT, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
OFDT_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
OFDX, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
OFDX_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
OFDXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
OFDXI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
OPAD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
OR2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
OR12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
ORCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
PPC405 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
PULLDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
PULLUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
RAM16X1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
RAM16X1D_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
RAM16X1S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
RAM16X1S_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
RAM16X2D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
RAM16X2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
RAM16X4D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
RAM16X4S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
RAM16X8D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
RAM16X8S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
RAM32X1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
RAM32X1D_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
RAM32X1S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
RAM32X1S_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
RAM32X2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
RAM32X4S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
RAM32X8S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
RAM64X1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
RAM64X1D_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
RAM64X1S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
RAM64X1S_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
RAM64X2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
RAM128X1S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
RAM128X1S_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
RAMB4_Sn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
RAMB4_Sm_Sn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
RAMB16_Sn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
RAMB16_Sm_Sn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
ROC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079

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ROCBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROM16X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROM32X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROM64X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROM128X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROM256X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOP3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR4CE, SR8CE, SR16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR4CLE, SR8CLE, SR16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR4CLED, SR8CLED, SR16CLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR4RE, SR8RE, SR16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR4RLE, SR8RLE, SR16RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR4RLED, SR8RLED, SR16RLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRD4CE, SRD8CE, SRD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRD4CLE, SRD8CLE, SRD16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRD4CLED, SRD8CLED, SRD16CLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRD4RE, SRD8RE, SRD16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRD4RLE, SRD8RLE, SRD16RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRD4RLED, SRD8RLED, SRD16RLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRL16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRL16_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRL16E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRL16E_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRLC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRLC16_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRLC16E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRLC16E_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STARTBUF_architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STARTUP_SPARTAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STARTUP_SPARTAN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STARTUP_VIRTEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STARTUP_VIRTEX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TOCBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UPAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XNOR2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XOR2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XORCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XORCY_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XORCY_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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1081
1083
1085
1087
1089
1091
1093
1095
1097
1099
1103
1105
1107
1111
1113
1115
1119
1121
1123
1127
1131
1133
1135
1137
1139
1141
1143
1145
1147
1149
1151
1153
1155
1157
1159
1161
1163
1169
1175
1177
1179

Libraries Guide
ISE 6.3i

Xilinx Unified Libraries

This chapter describes the Unified Libraries and the applicable device architectures
for each library. It also briefly discusses the contents of the other chapters, the general
naming conventions, and performance issues.
This chapter consists of the following major sections.

Overview

Applicable Architectures

Functional Categories

Design Elements

Schematic Examples

Naming Conventions

Attributes and Constraints

Carry Logic

Flip-Flop, Counter, and Register Performance

Unconnected Pins

Overview
Xilinx maintains software libraries with thousands of functional design elements
(primitives and macros) for different device architectures. New functional elements
are assembled with each release of development system software. The catalog of
design elements is known as the Unified Libraries. Elements in these libraries are
common to all Xilinx device architectures. This unified approach means that you
can use your circuit design created with unified library elements across all current
Xilinx device architectures that recognize the element you are using.
Elements that exist in multiple architectures look and function the same, but their
implementations might differ to make them more efficient for a particular
architecture. A separate library still exists for each architecture (or architectural
group) and common symbols are duplicated in each one, which is necessary for
simulation (especially board level) where timing depends on a particular architecture.
If you have active designs that were created with former Xilinx library primitives or
macros, you may need to change references to the design elements that you were
using to reflect the Unified Libraries elements.
The Libraries Guide describes the primitive and macro logic elements available in the
Unified Libraries for the Xilinx FPGA and CPLD devices. Common logic functions
can be implemented with these elements and more complex functions can be built by
combining macros and primitives. Several hundred design elements (primitives and

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macros) are available across multiple device architectures, providing a common base
for programmable logic designs.
This libraries guide provides a functional selection guide and describes the design
elements.

Applicable Architectures
Design elements for the Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,
Virtex -II, Virtex-II Pro, Virtex-II Pro X, XC9500/XV/XL, CoolRunner XPLA3, and
CoolRunner-II libraries are included in the Xilinx Unified Libraries. Each library
supports specific device architectures. For detailed information on the architectural
families referenced below and the devices in each, see the current version of The
Programmable Logic Data Sheets(an online version is available from the Xilinx web site,
http://support.xilinx.com).

Functional Categories
The functional categories list the available elements in each category along with a
brief description of each element and an applicability table identifying which libraries
(Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex -II, Virtex-II Pro, Virtex-II Pro X,
XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II) contain the element.

Design Elements
Design elements are organized in alphanumeric order, with all numeric suffixes in
ascending order. For example, FDR precedes FDRS, and ADD4 precedes ADD8,
which precedes ADD16.
The following information is provided for each library element, where applicable:

Graphic symbol

Applicability table (with primitive versus macro identification)

Functional description

Truth table

Schematic for macros

VHDL and Verilog instantiation and inference code

Commonly used constraints

Schematic Examples
Schematics are included for each library if the implementation differs.
Design elements with bussed or multiple I/O pins (2-, 4-, 8-, 16-bit versions) typically
include just one schematic -- generally the 8-bit version. When only one schematic is
included, implementation of the smaller and larger elements differs only in the
number of sections. In cases where an 8-bit version is very large, an appropriate
smaller element serves as the schematic example.

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Naming Conventions

Naming Conventions
Examples of the general naming conventions for the unified library elements are
shown in the following figures.
Example 1
FUNCTION

SIZE

Counter, Binary

4-Bit

CONTROL PINS
Clear (Asynchronous)
Load

Clock Enable
Bi-Directional

CB4CLED
Precedence of Control Pins

Example 2
FUNCTION

SIZE

Flip-Flop, D-type

16-Bit

CONTROL PINS
Reset (Synchronous)
Clock Enable

FD16RE
Precedence of Control Pins

X7764

Naming Conventions

AND3B2
Logic Function
Number of Inputs
Inverting (Bubble) Inputs
Number of Inverting Inputs

X4316

Combinatorial Naming Conventions

Attributes and Constraints

Attributes and constraints are instructions placed on components or nets to indicate
their placement, implementation, naming, directionality, and so forth. The Constraints
Guide provides information on all attributes and constraints.

Carry Logic
The Spartan-II, Spartan-IIE, Virtex, and Virtex-II architectures include dedicated carry
logic components.

Spartan-II, Spartan-IIE, Virtex, and Virtex-E

Carry Logic for Spartan-II, Spartan-IIE, Virtex, and Virtex-E is a simple structure
associated with each look-up table. The design entry library contains the following
dedicated carry logic primitives: MULT_AND, MUXCY, MUXCY_D, MUXCY_L,
XORCY, XORCY_D, and XORCY_L. The function performed is determined by their

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Xilinx Unified Libraries

connectivity and the contents of the look-up table. For an example of how to use carry
logic, see CC8CE, CC16CE.
For detailed information on Carry Logic in Virtex and Spartan-II, see The
Programmable Logic Data Sheets available on the Xilinx web site, http://
support.xilinx.com.

Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3

The dedicated carry logic primitives for Virtex-II, Virtex-II Pro, Virtex-II Pro X, and
Spartan-3 are MULT_AND, MUXCY, MUXCY_D, MUXCY_L, XORCY, XORCY_D,
and XORCY_L.
ORCY can only be used exclusively with Virtex-II, Virtex-II Pro, and Virtex-II Pro X.
For detailed information on Carry Logic in Virtex-II, Virtex-II Pro, Virtex-II Pro X, and
Spartan-3, see The Programmable Logic Data Sheets available on the Xilinx web site,
http://support.xilinx.com.

Flip-Flop, Counter, and Register Performance

All counter, register, and storage functions derived from the flip-flops are available in
the Configurable Logic Blocks (CLBs).
The D flip-flop is the basic building block for all architectures. Differences occur from
the availability of asynchronous Clear (CLR) and Preset (PRE) inputs, and the source
of the synchronous control signals, such as Clock Enable (CE), Clock (C), Load enable
(L), synchronous Reset (R), and synchronous Set (S). The basic flip-flop configuration
for each architecture follows.
The basic XC9000 flip-flops have both Clear and Preset inputs.
PRE

FDCP

Q
C

CLR
X4397

Virtex and Spartan-II have two basic flip-flop types. One has both Clear and Preset
inputs and one has both asynchronous and synchronous control functions.
PRE

FDCPE

CE

CLR
X4389

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Flip-Flop, Counter, and Register Performance

D
CE

FDRSE

X3732

The asynchronous and synchronous control functions, when used, have a priority that
is consistent across all devices and architectures. These inputs can be either activeHigh or active-Low as defined by the macro. The priority, from highest to lowest, is as
follows.

Asynchronous Clear (CLR)

Asynchronous Preset (PRE)

Synchronous Set (S)

Synchronous Reset (R)

Clock Enable (CE)

Note: The asynchronous CLR and PRE inputs, by definition, have priority over all the
synchronous control and clock inputs.
For FPGA families, the Clock Enable (CE) function is implemented using two
different methods in the Xilinx Unified Libraries; both are shown in the following
figure.

In method 1, CE is implemented by connecting the CE pin of the macro directly to

the dedicated Enable Clock (EC) pin of the internal Configurable Logic Block
(CLB) flip-flop. This allows one CE per CLB. CE takes precedence over the L, S,
and R inputs. All flip-flops with asynchronous clear or preset use this method.

In method 2, CE is implemented using function generator logic. This allows two

CEs per CLB. CE has the same priority as the L, S, and R inputs. All flip-flops with
synchronous set or reset use this method.

The method used in a particular macro is indicated by the inclusion of asynchronous

clear, asynchronous preset, synchronous set, or synchronous reset in the macro's
description.

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Xilinx Unified Libraries

CE

C1
C1
C2

D
Function
Generator

EC

Function
Generator

C2
CE

C
X=(CE * C2)+(CE * C1)

C1
C2

D
Function
Generator

EC

C1

CE

Function
Generator

C2

C
Y=(CE * C1)+(CE * C2)

Method 1

Method 2

CE implemented
using dedicated EC pin.

CE implemented as a
function generator input.
X4675

Clock Enable Implementation Methods

Unconnected Pins
Xilinx recommends that you always connect input pins in your designs. This ensures
that front end simulation functionally matches back end timing simulation. If an input
pin is left unconnected, mapper errors may result.
If an output pin is left unconnected in your design, the corresponding function is
trimmed. If the component has only one output, the entire component is trimmed. If
the component has multiple outputs, the portion that drives the output is trimmed.
As an example of the latter case, if the overflow pin (OFL) in an adder macro is
unconnected, the logic that generates that term is trimmed, but the rest of the adder is
retained (assuming all of the sum outputs are connected).

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Slice Count
This chapter contains the following sections.

About Configurable Logic Blocks (CLBs)

Slice Count for FPGA Components

About Configurable Logic Blocks (CLBs)

Configurable Logic Blocks (CLBs) implement most of the logic in an FPGA.
Each Virtex, Virtex-E and Spartan-II, Spartan-IIE CLB contains two slices. Each
Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X CLB contains four slices. In the
following table, the numbers for Spartan-II, Spartan-IIE, Virtex, Virtex-E, Spartan-3,
Virtex-II, Virtex-II Pro, and Virtex-II Pro X are the number of slices required to
implement the component.
The Slice Count table lists FPGA design elements in alphanumeric order with the
number of CLBs or slices needed for their implementation in each applicable library.
Note: This information is for reference only. The actual count could vary, depending upon the
switch settings of the implementation tools; for example, the effort level in PAR (Place and
Route) or usage of the components with other components.
The asterisk for the RAM16X1D and RAM16X1D_1 in the Spartan-3, Virtex-II, VirtexII Pro, and Virtex-II Pro X columns indicates that these design elements consume 1/2
of two slices.
The double asterisks for design elements indicate that these primitives cannot be used
by themselves. However, there is only one available per slice.

Slice Count for FPGA Components

Spartan-II, Spartan-IIE
Name
ACC4

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

5

ACC8

10

10

ACC16

17

18

17

18

ADD4

ADD8

ADD16

ADSU4

ADSU8

ADSU16

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Slice Count

Slice Count for FPGA Components

Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

AND2

AND3

AND4

AND5

AND6

AND7

AND8

AND9

AND12

AND16

BRLSHFT4

BRLSHFT8

12

12

12

12

BSCAN_SPARTAN2

BSCAN_VIRTEX

BSCAN_VIRTEX2

BUF

BUF4

BUF8

BUF16

BUFCF

BUFE

BUFE4

BUFE8

BUFE16

BUFG

BUFGCE

BUFGCE_1

BUFGDLL

BUFGMUX

BUFGMUX_1

BUFGP

BUFT

BUFT4

BUFT8

BUFT16

CAPTURE_SPARTAN2

CAPTURE_VIRTEX

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Slice Count for FPGA Components

Slice Count for FPGA Components

Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

CAPTURE_VIRTEX2

CB2CE

CB2CLE

CB2CLED

CB2RE

CB4CE

CB4CLE

CB4CLED

CB4RE

CB8CE

CB8CLE

10

10

CB8CLED

12

12

12

12

CB8RE

CB16CE

13

14

13

14

CB16CLE

18

19

18

19

CB16CLED

24

25

24

25

CB16RE

13

14

13

14

CC8CE

CC8CLE

CC8CLED

17

17

CC8RE

CC16CE

16

16

CC16CLE

17

17

17

17

CC16CLED

17

33

17

33

CC16RE

17

17

17

17

CD4CE

CD4CLE

CD4RE

CD4RLE

CJ4CE

CJ4RE

CJ5CE

CJ5RE

CJ8CE

CJ8RE

CLKDLL

CLKDLLE

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Slice Count

Slice Count for FPGA Components

Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

CLKDLLHF

COMP2

COMP4

COMP8

COMP16

COMPM2

COMPM4

COMPM8

11

13

11

13

COMPM16

24

32

24

32

COMPMC8

COMPMC16

16

16

16

16

CR8CE

CR16CE

16

16

16

16

D2_4E

D3_8E

D4_16E

16

16

16

16

DCM

DEC_CC4

DEC_CC8

DEC_CC16

DECODE4

DECODE8

DECODE16

DECODE32

DECODE64

FD

FD_1

FD4CE

FD4RE

FD8CE

FD8RE

FD16CE

FD16RE

FDC

FDC_1

FDCE

FDCE_1

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Slice Count for FPGA Components

Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

FDCP

FDCP_1

FDCPE

FDCPE_1

FDDRCPE

FDDRRSE

FDE

FDE_1

FDP

FDP_1

FDPE

FDPE_1

FDR

FDR_1

FDRE

FDRE_1

FDRS

FDRS_1

FDRSE

FDRSE_1

FDS

FDS_1

FDSE

FDSE_1

FJKC

FJKCE

FJKP

FJKPE

FJKRSE

FJKSRE

FMAP

FTC

FTCE

FTCLE

FTCLEX

FTP

FTPE

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Slice Count

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Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

FTPLE

FTRSE

FTRSLE

FTSRE

FTSRLE

GND

GT_AURORA_n

GT_CUSTOM_n

GT_ETHERNET_n

GT_FIBRE_CHAN_n

GT_INFINIBAND_n

GT_XAUI_n

GT10_AURORA_n

GT10_AURORAX_n

GT10_CUSTOM_n

GT10_INFINIBAND_n

GT10_XAUI_n

GT10_10GE_n

GT10_10GFC_n

GT10_OC48_n

GT10_OC192_n

IBUF

IBUF4

IBUF8

IBUF16

IBUFDS

IBUFG

IBUFGDS

ICAP_VIRTEX2

IFD

IFD_1

IFD4

IFD8

IFD16

IFDDRCPE

IFDDRRSE

IFDI

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Slice Count for FPGA Components

Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

IFDI_1

IFDX

IFDX4

IFDX8

IFDX16

IFDX_1

IFDXI

IFDXI_1

ILD

ILD_1

ILD4

ILD8

ILD16

ILDI

ILDI_1

ILDX

ILDX4

ILDX8

ILDX16

ILDX_1

ILDXI

ILDXI_1

INV

INV4

INV8

INV16

IOBUF

IOPAD

IOPAD4

IOPAD8

IOPAD16

IPAD

IPAD4

IPAD8

IPAD16

JTAGPPC

KEEPER

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Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

LD

LD_1

LD4

LD8

LD16

LD4CE

LD8CE

LD16CE

LDC

LDC_1

LDCE

LDCE_1

LDCP

LDCP_1

LDCPE

LDCPE_1

LDE

LDE_1

LDP

LDP_1

LDPE

LDPE_1

LUT1

LUT2

LUT3

LUT4

LUT1_D

LUT2_D

LUT3_D

LUT4_D

LUT1_L

LUT2_L

LUT3_L

LUT4_L

M2_1

M2_1B1

M2_1B2

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Slice Count for FPGA Components

Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

M2_1E

M4_1E

M8_1E

M16_1E

MULT_AND **

MULT18X18

MULT18X18S

MUXCY **

MUXCY_D **

MUXCY_L **

MUXF5 **

MUXF5_D **

MUXF5_L **

MUXF6 **

MUXF6_D **

MUXF6_L **

MUXF7 **

MUXF7_D **

MUXF7_L **

MUXF8 **

MUXF8_D **

MUXF8_L **

NAND2

NAND3

NAND4

NAND5

NAND6

NAND7

NAND8

NAND9

NAND12

NAND16

NOR2

NOR3

NOR4

NOR5

NOR6

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Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

NOR7

NOR8

NOR9

NOR12

NOR16

OBUF

OBUF4

OBUF8

OBUF16

OBUFDS

OBUFE

OBUFE4

OBUFE8

OBUFE16

OBUFT

OBUFT4

OBUFT8

OBUFT16

OBUFTDS

OFD

OFD_1

OFD4

OFD8

OFD16

OFDDRCPE

OFDDRRSE

OFDDRTCPE

OFDDRTRSE

OFDE

OFDE_1

OFDE4

OFDE8

OFDE16

OFDI

OFDI_I

OFDT

OFDT_1

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Slice Count for FPGA Components

Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

OFDT4

OFDT8

OFDT16

OFDX

OFDX4

OFDX8

OFDX16

OFDX_1

OFDXI

OFDXI_I

OPAD

OPAD4

OPAD8

OPAD16

OR2

OR3

OR4

OR5

OR6

OR7

OR8

OR9

OR12

OR16

ORCY **

PPC405

PULLDOWN

PULLUP

RAM16X1D

2*

2*

RAM16X1D_1

2*

2*

RAM16X1S

RAM16X1S_1

RAM16X2D

RAM16X2S

RAM16X4D

RAM16X4S

RAM16X8D

16

16

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Slice Count

Slice Count for FPGA Components

Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

RAM16X8S

RAM32X1D

RAM32X1D_1

RAM32X1S

RAM32X1S_1

RAM32X2S

RAM32X4S

RAM32X8S

RAM64X1D

RAM64X1D_1

RAM64X1S

RAM64X1S_1

RAM64X2S

RAM128X1S

RAM128X1S_1

RAMB4_Sn

RAMB4_Sm_Sn

RAMB16_Sn

RAMB16_Sm_Sn

ROM16X1

ROM32X1

ROM64X1

ROM128X1

ROM256X1

SOP3

SOP4

SR4CE

SR4CLE

SR4CLED

SR4RE

SR4RLE

SR4RLED

SR8CE

SR8CLE

SR8CLED

SR8RE

SR8RLE

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Slice Count for FPGA Components

Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

SR8RLED

SR16CE

SR16CLE

SR16CLED

17

17

17

17

SR16RE

SR16RLE

SR16RLED

17

17

17

17

SRL16

SRL16_1

SRL16E

SRL16E_1

SRLC16

SRLC16_1

SRLC16E

SRLC16E_1

STARTUP_SPARTAN2

STARTUP_VIRTEX

STARTUP_VIRTEX2

UPAD

VCC

XNOR2

XNOR3

XNOR4

XNOR5

XNOR6

XNOR7

XNOR8

XNOR9

XOR2

XOR3

XOR4

XOR5

XOR6

XOR7

XOR8

XOR9

XORCY **

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Slice Count

Slice Count for FPGA Components

Spartan-II, Spartan-IIE
Name

Spartan-3

Virtex, Virtex-E

Virtex-II, Virtex-II Pro,

Virtex-II Pro X

Number of Slices to Implement

XORCY_D **

XORCY_L **

* The RAM16X1D and RAM16X1D_1 consume 1/2 of two slices.

** These primitives cannot be used by themselves. However, there is only one
available per slice.

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Architecture-Specific Information
The following sections list the design elements that can be used with supported
architectures.

Spartan-II and Spartan-IIE

Spartan-3

Virtex and Virtex-E

Virtex-II, Virtex-II Pro, Virtex-II Pro X

XC9500/XV/XL

CoolRunner XPLA3

CoolRunner-II

To access lists of the constraints associated with each of these architectures, see
"Architecture Specific Constraints," in the Xilinx Constraints Guide.

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Spartan-II and Spartan-IIE

The following table indicates the supported design elements for Spartan-II and
Spartan-IIE. For a complete description of these architectures, see the Product Data
Sheets (http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp).
Spartan-II, Spartan-IIE Design Elements
ACC4, 8, 16

ADD4, 8, 16

ADSU4, 8, 16

AND2-9

AND12, 16

BRLSHFT4, 8

BSCAN_SPARTAN2

BUF

BUFCF

BUFE, 4, 8, 16

BUFG

BUFGDLL

BUFGP

BUFT, 4, 8, 16

CAPTURE_SPARTAN2

CB2CE, CB4CE, CB8CE, CB16CE

CB2CLE, CB4CLE, CB8CLE, CB16CLE

CB2CLED, CB4CLED, CB8CLED,

CB16CLED

CB2RE, CB4RE, CB8RE, CB16RE

CC8CE, CC16CE

CC8CLE, CC16CLE

CC8CLED, CC16CLED

CC8RE, CC16RE

CD4CE

CD4CLE

CD4RE

CD4RLE

CJ4CE, CJ5CE, CJ8CE

CJ4RE, CJ5RE, CJ8RE

CLKDLL, CLKDLLE (Spartan-IIE only)

CLKDLLHF

COMP2, 4, 8, 16

COMPM2, 4, 8, 16

COMPMC8, 16

CR8CE, CR16CE

D2_4E

D3_8E

D4_16E

DEC_CC4, 8, 16

DECODE4, 8, 16

DECODE32, 64

FD

FD_1

FD4CE, FD8CE, FD16CE

FD4RE, FD8RE, FD16RE

FDC

FDC_1

FDCE

FDCE_1

FDCP

FDCP_1

FDCPE

FDCPE_1

FDE

FDE_1

FDP

FDP_1

FDPE

FDPE_1

FDR

FDR_1

FDRE

FDRE_1

FDRS

FDRS_1

FDRSE

FDRSE_1

FDS

FDS_1

FDSE

FDSE_1

FJKC

FJKCE

FJKP

FJKPE

FJKRSE

FJKSRE

FMAP

FTC

FTCE

FTCLE

FTCLEX

FTP

FTPE

FTPLE

FTRSE

FTRSLE

FTSRE

FTSRLE

GND

IBUF, 4, 8, 16

IBUFG

IFD, 4, 8, 16

IFD_1

IFDI

IFDI_1

IFDX, 4, 8, 16

IFDX_1

IFDXI

IFDXI_1

ILD, 4, 8, 16

ILD_1

ILDI

ILDI_1

ILDX, 4, 8, 16

ILDX_1

ILDXI

Libraries Guide
ISE 6.3i

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1-800-255-7778

39

Spartan-II, Spartan-IIE Design Elements

ILDXI_1

INV, 4, 8, 16

IOBUF

IOPAD, 4, 8, 16

IPAD, 4, 8, 16

KEEPER

LD

LD_1

LD4, 8, 16

LDC

LDC_1

LDCE

LDCE_1

LD4CE, LD8CE, LD16CE

LDCP

LDCP_1

LDCPE

LDCPE_1

LDE

LDE_1

LDP

LDP_1

LDPE

LDPE_1

LUT1, 2, 3, 4

LUT1_D, LUT2_D, LUT3_D, LUT4_D

LUT1_L, LUT2_L, LUT3_L, LUT4_L

M2_1

M2_1B1

M2_1B2

M2_1E

M4_1E

M8_1E

M16_1E

MULT_AND

MUXCY

MUXCY_D

MUXCY_L

MUXF5

MUXF5_D

MUXF5_L

MUXF6

MUXF6_D

MUXF6_L

NAND2-9

NAND12, 16

NOR2-9

NOR12, 16

OBUF, 4, 8, 16

OBUFE, 4, 8, 16

OBUFT, 4, 8, 16

OFD, 4, 8, 16

OFD_1

OFDE, 4, 8, 16

OFDE_1

OFDI

OFDI_1

OFDT, 4, 8, 16

OFDT_1

OFDX, 4, 8, 16

OFDX_1

OFDXI

OFDXI_1

OPAD, 4, 8, 16

OR2-9

OR12, 16

PULLDOWN

PULLUP

RAM16X1D

RAM16X1D_1

RAM16X1S

RAM16X1S_1

RAM16X2D

RAM16X2S

RAM16X4D

RAM16X4S

RAM16X8D

RAM16X8S

RAM32X1S

RAM32X1S_1

RAM32X2S

RAM32X4S

RAM32X8S

RAMB4_Sn

RAMB4_Sm_Sn

ROC

ROCBUF

ROM16X1

ROM32X1

SOP3-4

SR4CE, SR8CE, SR16CE

SR4CLE, SR8CLE, SR16CLE

SR4CLED, SR8CLED, SR16CLED

SR4RE, SR8RE, SR16RE

SR4RLE, SR8RLE, SR16RLE

SR4RLED, SR8RLED, SR16RLED

SRL16

SRL16_1

SRL16E

SRL16E_1

STARTBUF_architecture

STARTUP_SPARTAN2

TOC

TOCBUF

UPAD

VCC

XNOR2-9

XOR2-9

XORCY

XORCY_D

XORCY_L

40

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1-800-255-7778

Libraries Guide
ISE 6.3i

Spartan-3
The table below indicates the supported design elements for Spartan-3.
Spartan-3 Design Elements
ACC4, 8, 16

ADD4, 8, 16

ADSU4, 8, 16

AND2-9

AND12, 16

BRLSHFT4, 8

BSCAN_SPARTAN3

BUF

BUFCF

BUFG

BUFGCE

BUFGCE_1

BUFGDLL

BUFGMUX

BUFGMUX_1

BUFGP

CAPTURE_SPARTAN3

CB2CE, CB4CE, CB8CE, CB16CE

CB2RE, CB4RE, CB8RE, CB16RE

CB2CLE, CB4CLE, CB8CLE, CB16CLE

CB2CLED, CB4CLED, CB8CLED,

CB16CLED

CC8CE, CC16CE

CC8CLE, CC16CLE

CC8CLED, CC16CLED

CC8RE, CC16RE

CD4CE

CD4CLE

CD4RE

CD4RLE

CJ4CE, CJ5CE, CJ8CE

CJ4RE, CJ5RE, CJ8RE

COMP2, 4, 8, 16

COMPM2, 4, 8, 16

COMPMC8, 16

CR8CE, CR16CE

D2_4E

D3_8E

D4_16E

DCM

DEC_CC4, 8, 16

DECODE4, 8, 16

DECODE32, 64

FD

FD_1

FD4CE, FD8CE, FD16CE

FD4RE, FD8RE, FD16RE

FDC

FDC_1

FDCE

FDCE_1

FDCP

FDCP_1

FDCPE

FDCPE_1

FDDRCPE

FDDRRSE

FDE

FDE_1

FDP

FDP_1

FDPE_1

FDR

FDR_1

FDRE

FDRE_1

FDRS

FDRS_1

FDRSE

FDRSE_1

FDS

FDS_1

FDSE

FDSE_1

FJKC

FJKCE

FJKP

FJKPE

FJKRSE

FJKSRE

FMAP

FTC

FTCE

FTCLE

FTCLEX

FTP

FTPE

FTPLE

FTRSE

FTRSLE

FTSRE

FTSRLE

GND

IBUF, 4, 8, 16

IBUFDS

IBUFG

IBUFGDS

IFD, 4, 8, 16

IFD_1

IFDDRCPE

IFDDRRSE

IFDI

IFDI_1

IFDX, 4, 8, 16

IFDX_1

IFDXI

IFDXI_1

ILD, 4, 8, 16

ILD_1

ILDI

ILDI_1

ILDX, 4, 8, 16

ILDX_1

ILDXI

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

41

Spartan-3 Design Elements

ILDXI_1

INV, 4, 8, 16

IOBUF

IOBUFDS

KEEPER

LD

LD_1

LD4, 8, 16

LDC

LDC_1

LDCE

LDCE_1

LD4CE, LD8CE, LD16CE

LDCP

LDCP_1

LDCPE

LDCPE_1

LDE

LDE_1

LDP

LDP_1

LDPE

LDPE_1

LUT1, 2, 3, 4

LUT1_D, LUT2_D, LUT3_D, LUT4_D

LUT1_L, LUT2_L, LUT3_L, LUT4_L

M2_1

M2_1B1

M2_1B2

M2_1E

M4_1E

M8_1E

M16_1E

MULT_AND

MULT18X18

MULT18X18S

MUXCY

MUXCY_D

MUXCY_L

MUXF5

MUXF5_D

MUXF5_L

MUXF6

MUXF6_D

MUXF6_L

MUXF7

MUXF7_D

MUXF7_L

MUXF8

NAND2-9

NAND12, 16

NOR2-9

NOR12, 16

OBUF, 4, 8, 16

OBUFDS

OBUFT, 4, 8, 16

OBUFTDS

OFD, 4, 8, 16

OFD_1

OFDDRCPE

OFDDRRSE

OFDDRTCPE

OFDDRTRSE

OFDE, 4, 8, 16

OFDE_1

OFDI

OFDI_1

OFDT, 4, 8, 16

OFDT_1

OFDX, 4, 8, 16

OFDX_1

OFDXI

OFDXI_1

OPAD, 4, 8, 16

OR2-9

OR12, 16

PULLDOWN

PULLUP

RAM16X1D

RAM16X1D_1

RAM16X1S

RAM16X1S_1

RAM16X2S

RAM16X4S

RAM16X8S

RAM32X1S

RAM32X1S_1

RAM32X2S

RAM64X1S

RAM64X1S_1

RAMB16_Sn

RAMB16_Sm_Sn

ROC

ROCBUF

ROM16X1

ROM32X1

ROM64X1

ROM128X1

ROM256X1

SOP3-4

SR4CE, SR8CE, SR16CE

SR4CLE, SR8CLE, SR16CLE

SR4CLED, SR8CLED, SR16CLED

SR4RE, SR8RE, SR16RE

SR4RLE, SR8RLE, SR16RLE

SR4RLED, SR8RLED, SR16RLED

SRL16

SRL16_1

SRL16E

SRL16E_1

SRLC16

SRLC16_1

SRLC16E

SRLC16E_1

STARTBUF_architecture

STARTUP_SPARTAN3

TOC

TOCBUF

VCC

XNOR2-9

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

42

Spartan-3 Design Elements

XOR2-9

XORCY

XORCY_D

XORCY_L

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

43

44

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Libraries Guide
ISE 6.3i

Virtex and Virtex-E

The table below indicates the supported design elements for Virtex and Virtex-E. For a
complete description, see the Product Data Sheets ((http://www.xilinx.com/xlnx/
xweb/xil_publications_index.jsp).
Virtex, Virtex-E Design Elements
ACC4, 8, 16

ADD4, 8, 16

ADSU4, 8, 16

AND2-9

AND12, 16

BRLSHFT4, 8

BSCAN_VIRTEX

BUF

BUFCF

BUFE, 4, 8, 16

BUFG

BUFGDLL

BUFGP

BUFT, 4, 8, 16

CAPTURE_VIRTEX

CB2CE, CB4CE, CB8CE, CB16CE

CB2CLE, CB4CLE, CB8CLE, CB16CLE

CB2CLED, CB4CLED, CB8CLED,

CB16CLED

CB2RE, CB4RE, CB8RE, CB16RE

CC8CE, CC16CE

CC8CLE, CC16CLE

CC8CLED, CC16CLED

CC8RE, CC16RE

CD4CE

CD4CLE

CD4RE

CD4RLE

CJ4CE, CJ5CE, CJ8CE

CJ4RE, CJ5RE, CJ8RE

CLKDLL

CLKDLLE

CLKDLLHF

COMP2, 4, 8, 16

COMPM2, 4, 8, 16

COMPMC8, 16

CR8CE, CR16CE

D2_4E

D3_8E

D4_16E

DEC_CC4, 8, 16

DECODE4, 8, 16

DECODE32, 64

FD

FD_1

FD4CE, FD8CE, FD16CE

FD4RE, FD8RE, FD16RE

FDC

FDC_1

FDCE

FDCE_1

FDCP

FDCP_1

FDCPE

FDCPE_1

FDE

FDE_1

FDP

FDP_1

FDPE

FDPE_1

FDR

FDR_1

FDRE

FDRE_1

FDRS

FDRS_1

FDRSE

FDRSE_1

FDS

FDS_1

FDSE

FDSE_1

FJKC

FJKCE

FJKP

FJKPE

FJKRSE

FJKSRE

FMAP

FTC

FTCE

FTCLE

FTCLEX

FTP

FTPE

FTPLE

FTRSE

FTRSLE

FTSRE

FTSRLE

GND

IBUF, 4, 8, 16

IBUFG

IFD, 4, 8, 16

IFD_1

IFDI

IFDI_1

IFDX, 4, 8, 16

IFDX_1

IFDXI

IFDXI_1

ILD, 4, 8, 16

ILD_1

ILDI

ILDI_1

ILDX, 4, 8, 16

ILDX_1

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

45

Virtex, Virtex-E Design Elements

ILDXI

ILDXI_1

INV, 4, 8, 16

IOBUF

IOPAD, 4, 8, 16

IPAD, 4, 8, 16

KEEPER

LD

LD_1

LD4, 8, 16

LDC

LDC_1

LDCE

LDCE_1

LD4CE, LD8CE, LD16CE

LDCP

LDCP_1

LDCPE

LDCPE_1

LDE

LDE_1

LDP

LDP_1

LDPE

LDPE_1

LUT1, 2, 3, 4

LUT1_D, LUT2_D, LUT3_D, LUT4_D

LUT1_L, LUT2_L, LUT3_L, LUT4_L

M2_1

M2_1B1

M2_1B2

M2_1E

M4_1E

M8_1E

M16_1E

MULT_AND

MUXCY

MUXCY_D

MUXCY_L

MUXF5

MUXF5_D

MUXF5_L

MUXF6

MUXF6_D

MUXF6_L

NAND2-9

NAND12, 16

NOR2-9

NOR12, 16

OBUF, 4, 8, 16

OBUFE, 4, 8, 16

OBUFT, 4, 8, 16

OFD, 4, 8, 16

OFD_1

OFDE, 4, 8, 16

OFDE_1

OFDI

OFDI_1

OFDT, 4, 8, 16

OFDT_1

OFDX, 4, 8, 16

OFDX_1

OFDXI

OFDXI_1

OPAD, 4, 8, 16

OR2-9

OR12, 16

PULLDOWN

PULLUP

RAM16X1D

RAM16X1D_1

RAM16X1S

RAM16X1S_1

RAM16X2D

RAM16X2S

RAM16X4D

RAM16X4S

RAM16X8D

RAM16X8S

RAM32X1S

RAM32X1S_1

RAM32X2S

RAM32X4S

RAM32X8S

RAMB4_Sn

RAMB4_Sm_Sn

ROC

ROCBUF

ROM16X1

ROM32X1

SOP3-4

SR4CE, SR8CE, SR16CE

SR4CLE, SR8CLE, SR16CLE

SR4CLED, SR8CLED, SR16CLED

SR4RE, SR8RE, SR16RE

SR4RLE, SR8RLE, SR16RLE

SR4RLED, SR8RLED, SR16RLED

SRL16

SRL16_1

SRL16E

SRL16E_1

STARTBUF_architecture

STARTUP_VIRTEX

TOC

TOCBUF

UPAD

VCC

XNOR2-9

XOR2-9

XORCY

XORCY_D

XORCY_L

46

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Libraries Guide
ISE 6.3i

Virtex-II, Virtex-II Pro, Virtex-II Pro X

The table below indicates the supported design elements for Virtex-II, Virtex-II Pro,
and Virtex-II Pro X. For a complete description of Virtex-II, see the Product Data
Sheets (http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp).
Virtex-II, Virtex-II Pro, Virtex-II Pro X Design Elements
ACC4, 8, 16

ADD4, 8, 16

ADSU4, 8, 16

AND2-9

AND12, 16

BRLSHFT4, 8

BSCAN_VIRTEX2

BUF

BUFCF

BUFE, 4, 8, 16

BUFG

BUFGCE

BUFGCE_1

BUFGDLL

BUFGMUX

BUFGMUX_1

BUFGP

BUFT, 4, 8, 16

CAPTURE_VIRTEX2

CB2CE, CB4CE, CB8CE, CB16CE

CB2CLE, CB4CLE, CB8CLE, CB16CLE

CB2CLED, CB4CLED, CB8CLED,

CB16CLED

CB2RE, CB4RE, CB8RE, CB16RE

CC8CE, CC16CE

CC8CLE, CC16CLE

CC8CLED, CC16CLED

CC8RE, CC16RE

CD4CE

CD4CLE

CD4RE

CD4RLE

CJ4CE, CJ5CE, CJ8CE

CJ4RE, CJ5RE, CJ8RE

COMP2, 4, 8, 16

COMPM2, 4, 8, 16

COMPMC8, 16

CR8CE, CR16CE

D2_4E

D3_8E

D4_16E

DCM

DEC_CC4, 8, 16

DECODE4, 8, 16

DECODE32, 64

FD

FD_1

FD4CE, FD8CE, FD16CE

FD4RE, FD8RE, FD16RE

FDC

FDC_1

FDCE

FDCE_1

FDCP

FDCP_1

FDCPE

FDCPE_1

FDDRCPE

FDDRRSE

FDE

FDE_1

FDP

FDP_1

FDPE

FDPE_1

FDR

FDR_1

FDRE

FDRE_1

FDRS

FDRS_1

FDRSE

FDRSE_1

FDS

FDS_1

FDSE

FDSE_1

FJKC

FJKCE

FJKP

FJKPE

FJKRSE

FJKSRE

FMAP

FTC

FTCE

FTCLE

FTCLEX

FTP

FTPE

FTPLE

FTRSE

FTRSLE

FTSRE

FTSRLE

GND

GT_AURORA_n (Virtex-II Pro only)

GT_CUSTOM (Virtex-II Pro only)

GT_ETHERNET_n (Virtex-II Pro only)

GT_FIBRE_CHAN_n (Virtex-II Pro only)

GT_INFINIBAND_n (Virtex-II Pro only) GT_XAUI_n (Virtex-II Pro only)

GT10_AURORA_n (Virtex-II Pro X only)

GT10_AURORAX_n (Virtex-II Pro X

only)

GT10_INFINIBAND_n (Virtex-II Pro X

only)

Libraries Guide
ISE 6.3i

GT10_CUSTOM (Virtex-II Pro X only)

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1-800-255-7778

47

Virtex-II, Virtex-II Pro, Virtex-II Pro X Design Elements

GT10_XAUI_n (Virtex-II Pro X only)

GT10_10GE_n (Virtex-II Pro X only)

GT10_10GFC_n (Virtex-II Pro X only)

GT10_OC48_n (Virtex-II Pro X only)

GT10_OC192_n (Virtex-II Pro X only)

IBUF, 4, 8, 16

IBUFDS

IBUFG

IBUFGDS

IBUFDS_DIFF_OUT

ICAP_VIRTEX2

IFD, 4, 8, 16

IFD_1

IFDDRCPE

IFDDRRSE

IFDI

IFDI_1

IFDX, 4, 8, 16

IFDX_1

IFDXI

IFDXI_1

ILD, 4, 8, 16

ILD_1

ILDI

ILDI_1

ILDX, 4, 8, 16

ILDX_1

ILDXI

ILDXI_1

INV, 4, 8, 16

IOBUF

IOBUFDS

IOPAD, 4, 8, 16

IPAD, 4, 8, 16

JTAGPPC (Virtex-II Pro only)

KEEPER

LD

LD_1

LD4, 8, 16

LDC

LDC_1

LDCE

LDCE_1

LD4CE, LD8CE, LD16CE

LDCP

LDCP_1

LDCPE

LDCPE_1

LDE

LDE_1

LDP

LDP_1

LDPE

LDPE_1

LUT1, 2, 3, 4

LUT1_D, LUT2_D, LUT3_D, LUT4_D

LUT1_L, LUT2_L, LUT3_L, LUT4_L

M2_1

M2_1B1

M2_1B2

M2_1E

M4_1E

M8_1E

M16_1E

MULT_AND

MULT18X18

MULT18X18S

MUXCY

MUXCY_D

MUXCY_L

MUXF5

MUXF5_D

MUXF5_L

MUXF6

MUXF6_D

MUXF6_L

MUXF7

MUXF7_D

MUXF7_L

MUXF8

NAND2-9

NAND12, 16

NOR2-9

NOR12, 16

OBUF, 4, 8, 16

OBUFDS

OBUFE, 4, 8, 16

OBUFT, 4, 8, 16

OBUFTDS

OFD, 4, 8, 16

OFD_1

OFDDRCPE

OFDDRRSE

OFDDRTCPE

OFDDRTRSE

OFDE, 4, 8, 16

OFDE_1

OFDI

OFDI_1

OFDT, 4, 8, 16

OFDT_1

OFDX, 4, 8, 16

OFDX_1

OFDXI

OFDXI_1

OPAD, 4, 8, 16

OR2-9

OR12, 16

ORCY

PPC405 (Virtex-II Pro only)

PULLDOWN

PULLUP

RAM16X1D

RAM16X1D_1

RAM16X1S

RAM16X1S_1

RAM16X2D

RAM16X2S

RAM16X4D

RAM16X4S

RAM16X8D

RAM16X8S

48

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Libraries Guide
ISE 6.3i

Virtex-II, Virtex-II Pro, Virtex-II Pro X Design Elements

RAM32X1D

RAM32X1D_1

RAM32X1S

RAM32X1S_1

RAM32X2S

RAM32X4S

RAM32X8S

RAM64X1D

RAM64X1D_1

RAM64X1S

RAM64X1S_1

RAM64X2S

RAM128X1S

RAM128X1S_1

RAMB16_Sn

RAMB16_Sm_Sn

ROC

ROCBUF

ROM16X1

ROM32X1

ROM64X1

ROM128X1

ROM256X1

SOP3-4

SR4CE, SR8CE, SR16CE

SR4CLE, SR8CLE, SR16CLE

SR4CLED, SR8CLED, SR16CLED

SR4RE, SR8RE, SR16RE

SR4RLE, SR8RLE, SR16RLE

SR4RLED, SR8RLED, SR16RLED

SRL16

SRL16_1

SRL16E

SRL16E_1

SRLC16

SRLC16_1

SRLC16E

SRLC16E_1

STARTBUF_architecture

STARTUP_VIRTEX2

TOC

TOCBUF

UPAD

VCC

XNOR2-9

XOR2-9

XORCY

XORCY_D

XORCY_L

Libraries Guide
ISE 6.3i

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1-800-255-7778

49

50

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Libraries Guide
ISE 6.3i

XC9500/XV/XL
The table below indicates the supported design elements for XC95000/XV/XL. For a
complete description, see the Product Data Sheets (http://www.xilinx.com/xlnx/
xweb/xil_publications_index.jsp).
XC9500/XV/XL Design Elements
ACC1

ACC4, 8, 16

ADD1

ADD4, 8, 16

ADSU1

ADSU4, 8, 16

AND2-9

BRLSHFT4, 8

BUF

BUF4, 8, 16

BUFE, 4, 8, 16

BUFG

BUFGSR

BUFGTS

BUFT, 4, 8, 16

CB2CE, CB4CE, CB8CE, CB16CE

CB2CLE, CB4CLE, CB8CLE, CB16CLE

CB2CLED, CB4CLED, CB8CLED,

CB16CLED

CB2RE, CB4RE, CB8RE, CB16RE

CB2RLE, CB4RLE, CB8RLE, CB16RLE

CB2X1, CB4X1, CB8X1, CB16X1

CB2X2, CB4X2, CB8X2, CB16X2

CD4CE

CD4CLE

CD4RE

CD4RLE

CJ4CE, CJ5CE, CJ8CE

CJ4RE, CJ5RE, CJ8RE

COMP2, 4, 8, 16

COMPM2, 4, 8, 16

CR8CE, CR16CE

D2_4E

D3_8E

D4_16E

FD

FD4, 8, 16

FD4CE, FD8CE, FD16CE

FD4RE, FD8RE, FD16RE

FDC

FDCE

FDCP

FDCPE

FDP

FDPE

FDR

FDRE

FDRS

FDRSE

FDS

FDSE

FDSR

FDSRE

FJKC

FJKCE

FJKCP

FJKCPE

FJKP

FJKPE

FJKRSE

FJKSRE

FTC

FTCE

FTCLE

FTCP

FTCPE

FTCPLE

FTDCP

FTP

FTPE

FTPLE

FTRSE

FTRSLE

FTSRE

FTSRLE

GND

IBUF, 4, 8, 16

INV, 4, 8, 16

IOPAD, 4, 8, 16

IPAD, 4, 8, 16

LD

LD4, 8, 16

LDC

LDCP

LDP

M2_1

M2_1B1

M2_1B2

M2_1E

M4_1E

M8_1E

M16_1E

NAND2-9

NOR2-9

OBUF, 4, 8, 16

OBUFE, 4, 8, 16

OBUFT, 4, 8, 16

OPAD, 4, 8, 16

OR2-9

SOP3-4

SR4CE, SR8CE, SR16CE

SR4CLE, SR8CLE, SR16CLE

SR4CLED, SR8CLED, SR16CLED

SR4RE, SR8RE, SR16RE

SR4RLE, SR8RLE, SR16RLE

SR4RLED, SR8RLED, SR16RLED

VCC

XNOR2-9

XOR2-9

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ISE 6.3i

CoolRunner XPLA3
The table below indicates the supported design elements for CoolRunner XPLA3. For
a complete description, see the Product Data Sheets (http://www.xilinx.com/xlnx/
xweb/xil_publications_index.jsp)
CoolRunner XPLA3 Design Elements
ACC1

ACC4, 8, 16

ADD1

ADD4, 8, 16

ADSU1

ADSU4, 8, 16

AND2-9

BRLSHFT4, 8

BUF

BUF4, 8, 16

BUFE, 4, 8, 16

BUFG

BUFT, 4, 8, 16

CB2CE, CB4CE, CB8CE, CB16CE

CB2CLE, CB4CLE, CB8CLE, CB16CLE

CB2CLED, CB4CLED, CB8CLED,

CB16CLED

CB2RE, CB4RE, CB8RE, CB16RE

CB2RLE, CB4RLE, CB8RLE, CB16RLE

CB2X1, CB4X1, CB8X1, CB16X1

CB2X2, CB4X2, CB8X2, CB16X2

CD4CE

CD4CLE

CD4RE

CD4RLE

CJ4CE, CJ5CE, CJ8CE

CJ4RE, CJ5RE, CJ8RE

COMP2, 4, 8, 16

COMPM2, 4, 8, 16

CR8CE, CR16CE

D2_4E

D3_8E

D4_16E

FD

FD4, 8, 16

FD4CE, FD8CE, FD16CE

FD4RE, FD8RE, FD16RE

FDC

FDCE

FDCP

FDCPE

FDP

FDPE

FDR

FDRE

FDRS

FDRSE

FDS

FDSE

FDSR

FDSRE

FJKC

FJKCE

FJKCP

FJKCPE

FJKP

FJKPE

FJKRSE

FJKSRE

FTC

FTCE

FTCLE

FTCP

FTCPE

FTCPLE

FTDCP

FTP

FTPE

FTPLE

FTRSE

FTRSLE

FTSRE

FTSRLE

GND

IBUF, 4, 8, 16

INV, 4, 8, 16

IOPAD, 4, 8, 16

IPAD, 4, 8, 16

LD

LD4, 8, 16

LDC

LDCP

LDP

M2_1

M2_1B1

M2_1B2

M2_1E

M4_1E

M8_1E

M16_1E

NAND2-9

NOR2-9

OBUF, 4, 8, 16

OBUFE, 4, 8, 16

OBUFT, 4, 8, 16

OPAD, 4, 8, 16

OR2-9

SOP3-4

SR4CE, SR8CE, SR16CE

SR4CLE, SR8CLE, SR16CLE

SR4CLED, SR8CLED, SR16CLED

SR4RE, SR8RE, SR16RE

SR4RLE, SR8RLE, SR16RLE

SR4RLED, SR8RLED, SR16RLED

VCC

XNOR2-9

XOR2-9

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ISE 6.3i

CoolRunner-II
The table below indicates the supported design elements for CoolRunner-II. For a
complete description of CoolRunner-II, see the Product Data Sheets (http://
www.xilinx.com/xlnx/xweb/xil_publications_index.jsp).
CoolRunner-II Design Elements
ACC1

ACC4, 8, 16

ADD1

ADD4, 8, 16

ADSU1

ADSU4, 8, 16

AND2-9

BRLSHFT4, 8

BUF

BUF4, 8, 16

BUFG

BUFGSR

BUFGTS

CB2CE, CB4CE, CB8CE, CB16CE

CB2CLE, CB4CLE, CB8CLE, CB16CLE

CB2CLED, CB4CLED, CB8CLED,

CB16CLED

CB2RE, CB4RE, CB8RE, CB16RE

CB2RLE, CB4RLE, CB8RLE, CB16RLE

CB2X1, CB4X1, CB8X1, CB16X1

CB2X2, CB4X2, CB8X2, CB16X2

CBD2CE, CBD4CE, CBD8CE, CBD16CE

CBD2CLE, CBD4CLE, CBD8CLE,

CBD16CLE

CBD2CLED, CBD4CLED, CBD8CLED,

CBD16CLED

CBD2RE, CBD4RE, CBD8RE, CBD16RE

CBD2RLE, CBD4RLE, CBD8RLE,

CBD16RLE

CBD2X1, CBD4X1, CBD8X1, CBD16X1

CBD2X2, CBD4X2, CBD8X2, CBD16X2

CD4CE

CD4CLE

CD4RE

CD4RLE

CDD4CE

CDD4CLE

CDD4RE

CDD4RLE

CJ4CE, CJ5CE, CJ8CE

CJ4RE, CJ5RE, CJ8RE

CJD4CE, CJD5CE, CJD8CE

CJD4RE, CJD5RE, CJD8RE

CLK_DIV2,4,6,8,10,12,14,16

CLK_DIV2,4,6,8,10,12,14,16R

CLK_DIV2,4,6,8,10,12,14,16RSD

CLK_DIV2,4,6,8,10,12,14,16SD

COMP2, 4, 8, 16

COMPM2, 4, 8, 16

CR8CE, CR16CE

CRD8CE, CRD16CE

D2_4E

D3_8E

D4_16E

FD

FD4, 8, 16

FD4CE, FD8CE, FD16CE

FD4RE, FD8RE, FD16RE

FDC

FDCE

FDCP

FDCPE

FDD

FDD4,8,16

FDD4CE, FDD8CE, FDD16CE

FDD4RE, FDD8RE, FDD16RE

FDDC

FDDCE

FDDCP

FDDCPE

FDDP

FDDPE

FDDR

FDDRE

FDDRS

FDDRSE

FDDS

FDDSE

FDDSR

FDDSRE

FDP

FDPE

FDR

FDRE

FDRS

FDRSE

FDS

FDSE

FDSR

FDSRE

FJKC

FJKCE

FJKCP

FJKCPE

FJKP

FJKPE

FJKRSE

FJKSRE

FTC

FTCE

FTCLE

FTCP

FTCPE

FTCPLE

FTDCE

FTDCLE

FTDCLEX

FTDCP

FTDRSE

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55

CoolRunner-II Design Elements

FTDRSLE

FTP

FTPE

FTPLE

FTRSE

FTRSLE

FTSRE

FTSRLE

GND

IBUF, 4, 8, 16

INV, 4, 8, 16

IOPAD, 4, 8, 16

IPAD, 4, 8, 16

KEEPER

LD

LD4, 8, 16

LDC

LDCP

LDG

LDG4, 8, 16

LDP

M2_1

M2_1B1

M2_1B2

M2_1E

M4_1E

M8_1E

M16_1E

NAND2-9

NOR2-9

OBUF, 4, 8, 16

OBUFE, 4, 8, 16

OBUFT, 4, 8, 16

OPAD, 4, 8, 16

OR2-9

PULLDOWN

PULLUP

SOP3-4

SR4CE, SR8CE, SR16CE

SR4CLE, SR8CLE, SR16CLE

SR4CLED, SR8CLED, SR16CLED

SR4RE, SR8RE, SR16RE

SR4RLE, SR8RLE, SR16RLE

SR4RLED, SR8RLED, SR16RLED

SRD4CE, SRD8CE, SRD16CE

SRD4CLE, SRD8CLE, SRD16CLE

SRD4CLED, SRD8CLED, SRD16CLED

SRD4RE, SRD8RE, SRD16RE

SRD4RLE, SRD8RLE, SRD16RLE

SRD4RLED, SRD8RLED, SRD16RLED

VCC

XNOR2-9

XOR2-9

56

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ISE 6.3i

Functional Categories
This section categories, by function, the logic elements that are described in detail in
the Design Elements sections. Each category is briefly described. Tables under each
category identify all the available elements for the function and indicate which
architectures are supported by each.
Arithmetic Functions

Flip-Flops

Logic Primitives

Buffers

General

Map Elements

Comparators

Input Latches

Memory Elements

Counters

Input/Output Flip-Flops

Multiplexers

Decoders

Input/Output Functions

Shifters

Edge Decoders

Latches

Shift Registers

Elements are listed in alphanumeric order under each category.

See the Xilinx Unified Libraries chapter for information on the specific device families
that use each library. "No" column means that the element does not apply.
The Xilinx libraries contain three types of elements.

Primitives are basic logical elements such as AND2 and OR2 gates.

Soft macros are schematics made by combining primitives and sometimes other
soft macros.

Relationally placed macros (RPMs) are soft macros that contain relative location
constraint (RLOC) information, carry logic symbols, and FMAP symbols, where
appropriate.

The last item mentioned above, RPMs, applies only to FPGA families.
The relationally placed macro (RPM) library uses RLOC constraints to define the
order and structure of the underlying design primitives. Because these macros are
built upon standard schematic parts, they do not have to be translated before
simulation. The components that are implemented as RPMs are listed in the Slice
Count section.
Designs created with RPMs can be functionally simulated. RPMs can, but need not,
include all the following elements.

Relative location (RLOC) constraints to provide placement structure. They allow

positioning of elements relative to each other.

Carry logic primitive symbols.

The RPM library offers the functionality and precision of the hard macro library with
added flexibility. You can optimize RPMs and merge other logic within them. The
elements in the RPM library allow you to access carry logic easily and to control
mapping and block placement. Because RPMs are a superset of ordinary macros, you

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57

Functional Categories

can design them in the normal design entry environment. They can include any
primitive logic. The macro logic is fully visible to you and can be easily backannotated with timing information.

58

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ISE 6.3i

Arithmetic Functions
There are three types of arithmetic functions: accumulators (ACC), adders (ADD), and
adder/subtracters (ADSU). With an ADSU, either unsigned binary or twoscomplement operations cause an overflow. If the result crosses the overflow
boundary, an overflow is generated. Similarly, when the result crosses the carry-out
boundary, a carry-out is generated. The following figure shows the ADSU carry-out
and overflow boundaries.

127

128

127

NS
U

-1

SI

255

E N T OR

ED BINAR
Y
IGN

AR

LEM

ED BIN

MP

MPL EMENT O
R

SIGN

CO

CO

UN

SIG

OS

NE

-127

TW

Overflow

ED

TW

Carry-Out
X4720

ADSU Carry-Out and Overflow Boundaries

Design
Element

Description

Spartan-II,
IIE

Spartan3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

ACC1

1-Bit Loadable Cascadable

Accumulator with Carry-In, CarryOut, and Synchronous Reset

No

No

No

No

Macro

Macro

Macro

ACC4

4-Bit Loadable Cascadable

Accumulator with Carry-In, CarryOut, and Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

ACC8

8-Bit Loadable Cascadable

Accumulator with Carry-In, CarryOut, and Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

ACC16

16-Bit Loadable Cascadable

Accumulator with Carry-In, CarryOut, and Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

ADD1

1-Bit Full Adder with Carry-In and

Carry-Out

No

No

No

No

Macro

Macro

Macro

ADD4

4-Bit Cascadable Full Adder with

Carry-In, Carry-Out, and Overflow

Macro

Macro

Macro

Macro

Macro

Macro

Macro

ADD8

8-Bit Cascadable Full Adder with

Carry-In, Carry-Out, and Overflow

Macro

Macro

Macro

Macro

Macro

Macro

Macro

ADD16

16-Bit Cascadable Full Adder with

Carry-In, Carry-Out, and Overflow

Macro

Macro

Macro

Macro

Macro

Macro

Macro

ADSU1

1-Bit Cascadable Adder/Subtracter

with Carry-In, Carry-Out

No

No

No

No

Macro

Macro

Macro

ADSU4

4-Bit Cascadable Adder/Subtracter

with Carry-In, Carry-Out, and
Overflow

Macro

Macro

Macro

Macro

Macro

Macro

Macro

ADSU8

8-Bit Cascadable Adder/Subtracter

with Carry-In, Carry-Out, and
Overflow

Macro

Macro

Macro

Macro

Macro

Macro

Macro

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59

Design
Element

60

Functional Categories

Description

Spartan-II,
IIE

Spartan3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

ADSU16

16-Bit Cascadable Adder/Subtracter

with Carry-In, Carry-Out, and
Overflow

Macro

Macro

Macro

Macro

Macro

Macro

Macro

MULT18X18

18 x 18 Signed Multiplier

No

Primitive

No

Primitive

No

No

No

MULT18X18S

18 x 18 Signed Multiplier -- Registered

Version

No

Primitive

No

Primitive

No

No

No

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ISE 6.3i

Buffers
The buffers in this section route high fanout signals, 3-state signals, and clocks inside
a PLD device. The Input/Output Functions section covers off-chip interfaces.
Design
Element

Description

Spartan-II,
IIE

Spartan3

Virtex, E

Virtex II,
Pro, Pro X

XC9500
/XV/XL

CR XPLA3

CR-II

BUF

General Purpose Buffer

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

BUF4

4-Bit General Purpose

Buffer

No

No

No

No

Macro

Macro

Macro

BUF8

8-Bit General Purpose

Buffer

No

No

No

No

Macro

Macro

Macro

BUF16

16-Bit General Purpose

Buffer

No

No

No

No

Macro

Macro

Macro

BUFCF

Fast Connect Buffer

Primitive

Primitive

Primitive

Primitive

No

No

No

BUFE

Internal 3-State Buffer

with Active High Enable

Primitive

No

Primitive

Primitive

Primitivea

No

No

BUFE4

Internal 3-State Buffer

with Active High Enable

Macro

No

Macro

Macro

Macrob

No

No

BUFE8

Internal 3-State Buffer

with Active High Enable

Macro

No

Macro

Macro

Macroc

No

No

BUFE16

Internal 3-State Buffer

with Active High Enable

Macro

No

Macro

Macro

Macrod

No

No

BUFG

Global Clock Buffer

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

BUFGCE

Global Clock MUX with

Clock Enable and Output
State 0

No

Primitive

No

Primitive

No

No

No

BUFGCE_1

Global Clock MUX Buffer

with Clock Enable and
Output State 1

No

Primitive

No

Primitive

No

No

No

BUFGDLL

Clock Delay Locked Loop

Buffer

Primitive

Primitive

Primitive

Primitive

No

No

No

BUFGMUX

Global Clock MUX Buffer

with Output State 0

No

Primitive

No

Primitive

No

No

No

BUFGMUX_1

Global Clock MUX with

Output State 1

No

Primitive

No

Primitive

No

No

No

BUFGP

Primary Global Buffer for

Driving Clocks or
Longlines (Four per PLD
Device)

Primitive

Primitive

Primitive

Primitive

No

No

No

BUFGSR

Global Set/Reset Input

Buffer

No

No

No

No

Primitive

Primitive

Primitive

BUFGTS

Global 3-State Input

Buffer

No

No

No

No

Primitive

Primitive

Primitive

BUFT

Internal 3-State Buffer

with Active-Low Enable

Primitive

No

Primitive

Primitive

Primitivee

No

No

BUFT4

Internal 3-State Buffer

with Active-Low Enable

Macro

No

Macro

Macro

Macrof

No

No

BUFT8

Internal 3-State Buffer

with Active-Low Enable

Macro

No

Macro

Macro

Macrog

No

No

BUFT16

Internal 3-State Buffer

with Active-Low Enable

Macro

No

Macro

Macro

Macroh

No

No

a.Not supported for XC9500XL and XC9500XV devices.

b.Not supported for XC9500XL and XC9500XV devices.
c.Not supported for XC9500XL and XC9500XV devices.
d.Not supported for XC9500XL and XC9500XV devices.
e.Not supported for XC9500XL and XC9500XV devices.
f.Not supported for XC9500XL and XC9500XV devices.

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Functional Categories

g.Not supported for XC9500XL and XC9500XV devices.

h.Not supported for XC9500XL and XC9500XV devices.

62

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ISE 6.3i

Comparators
Following is a list of comparators.
Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

COMP2

2-Bit Identity Comparator

Macro

Macro

Macro

Macro

Macro

Macro

Macro

COMP4

4-Bit Identity Comparator

Macro

Macro

Macro

Macro

Macro

Macro

Macro

COMP8

8-Bit Identity Comparator

Macro

Macro

Macro

Macro

Macro

Macro

Macro

COMP16

16-Bit Identity Comparator

Macro

Macro

Macro

Macro

Macro

Macro

Macro

COMPM2

2-Bit Magnitude Comparator

Macro

Macro

Macro

Macro

Macro

Macro

Macro

COMPM4

4-Bit Magnitude Comparator

Macro

Macro

Macro

Macro

Macro

Macro

Macro

COMPM8

8-Bit Magnitude Comparator

Macro

Macro

Macro

Macro

Macro

Macro

Macro

COMPM16

16-Bit Magnitude Comparator Macro

Macro

Macro

Macro

Macro

Macro

Macro

COMPMC8

8-Bit Magnitude Comparator

Macro

Macro

Macro

Macro

No

No

No

COMPMC16

16-Bit Magnitude Comparator Macro

Macro

Macro

Macro

No

No

No

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Counters
There are six types of counters with various synchronous and asynchronous inputs.
The name of the counter defines the modulo or bit size, the counter type, and which
control functions are included. The counter naming convention is shown in the
following figure.

CB16CLED
Counter
Binary (B)
BCD (D)
Binary, Carry Logic (C)
Johnson (J)
Ripple (R)
Modulo (Bit Size)
Synchronous Reset (R)
Asynchronous Clear (C)
Loadable
Clock Enable
Directional

X4577

Counter Naming Convention

A carry-lookahead design accommodates large counters without extra gating. On TTL
7400-type counters with trickle clock enable (ENT), parallel clock enable (ENP), and
ripple carry-out (RCO), both the ENT and ENP inputs must be High to count. ENT is
propagated forward to enable RCO, which produces a High output with the
approximate duration of the QA output. The following figure illustrates a carrylookahead design.
RCO
ENP
ENT

RCO
ENP
ENT

Vcc

RCO
ENP
ENT

Vcc
RCO
ENP
CE

ENT

X4719

Carry-Lookahead Design

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The RCO output of the first stage of the ripple carry is connected to the ENP input of
the second stage and all subsequent stages. The RCO output of the second stage and
all subsequent stages is connected to the ENT input of the next stage. The ENT of the
second stage is always enabled/tied to VCC. CE is always connected to the ENT input
of the first stage. This cascading method allows the first stage of the ripple carry to be
built as a prescaler. In other words, the first stage is built to count very fast.
Note: For counters, do not use TC (or any other gated signal) as a clock. Possible glitches
may not always allow for a proper setup time when using gated signals.
Design Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

CB2CE

2-Bit Cascadable Binary Counter

with Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CB4CE

4-Bit Cascadable Binary Counter

with Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CB8CE

8-Bit Cascadable Binary Counter

with Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CB16CE

16-Bit Cascadable Binary Counter

with Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CB2CLE

2-Bit Loadable Cascadable Binary

Counters with Clock Enable and
Asynchronous Clear

No

No

No

No

Macro

Macro

Macro

CB4CLE

4-Bit Loadable Cascadable Binary

Counters with Clock Enable and
Asynchronous Clear

No

No

No

No

Macro

Macro

Macro

CB8CLE

8-Bit Loadable Cascadable Binary

Counters with Clock Enable and
Asynchronous Clear

No

No

No

No

Macro

Macro

Macro

CB16CLE

16-Bit Loadable Cascadable

Binary Counters with Clock
Enable and Asynchronous Clear

No

No

No

No

Macro

Macro

Macro

CB2CLED

2-, 4-, 8-, 16-Bit Loadable

Cascadable Bidirectional Binary
Counters with Clock Enable and
Asynchronous Clear

No

No

No

No

Macro

Macro

Macro

CB4CLED

2-, 4-, 8-, 16-Bit Loadable

Cascadable Bidirectional Binary
Counters with Clock Enable and
Asynchronous Clear

No

No

No

No

Macro

Macro

Macro

CB8CLED

2-, 4-, 8-, 16-Bit Loadable

Cascadable Bidirectional Binary
Counters with Clock Enable and
Asynchronous Clear

No

No

No

No

Macro

Macro

Macro

CB16CLED

2-, 4-, 8-, 16-Bit Loadable

Cascadable Bidirectional Binary
Counters with Clock Enable and
Asynchronous Clear

No

No

No

No

Macro

Macro

Macro

CB2RE

2-Bit Cascadable Binary Counter

with Clock Enable and
Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CB4RE

4-Bit Cascadable Binary Counter

with Clock Enable and
Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CB8RE

8-Bit Cascadable Binary Counter

with Clock Enable and
Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CB16RE

16-Bit Cascadable Binary Counter

with Clock Enable and
Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

Libraries Guide
ISE 6.3i

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1-800-255-7778

65

Design Element

66

Functional Categories

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

CB2RLE

2-Bit Loadable Cascadable Binary

Counter with Clock Enable and
Synchronous Reset

No

No

No

Macro

Macro

Macro

Macro

CB4RLE

4-Bit Loadable Cascadable Binary

Counter with Clock Enable and
Synchronous Reset

No

No

No

Macro

Macro

Macro

Macro

CB8RLE

8-Bit Loadable Cascadable Binary

Counter with Clock Enable and
Synchronous Reset

No

No

No

Macro

Macro

Macro

Macro

CB16RLE

16-Bit Loadable Cascadable

Binary Counter with Clock
Enable and Synchronous Reset

No

No

No

Macro

Macro

Macro

Macro

CB2X1

2-Bit Loadable Cascadable

Bidirectional Binary Counter with
Clock Enable and Asyn-chronous
Clear

No

No

No

Macro

Macro

Macro

Macro

CB4X1

4-Bit Loadable Cascadable

Bidirectional Binary Counter with
Clock Enable and Asyn-chronous
Clear

No

No

No

Macro

Macro

Macro

Macro

CB8X1

8-Bit Loadable Cascadable

Bidirectional Binary Counter with
Clock Enable and Asyn-chronous
Clear

No

No

No

Macro

Macro

Macro

Macro

CB16X1

16-Bit Loadable Cascadable

Bidirectional Binary Counter with
Clock Enable and Asyn-chronous
Clear

No

No

No

Macro

Macro

Macro

Macro

CB2X2

2-Bit Loadable Cascadable

Bidirectional Binary Counter with
Clock Enable and Synchro-nous
Reset

No

No

No

Macro

Macro

Macro

Macro

CB4X2

4-Bit Loadable Cascadable

Bidirectional Binary Counter with
Clock Enable and Synchro-nous
Reset

No

No

No

Macro

Macro

Macro

Macro

CB8X2

8-Bit Loadable Cascadable

Bidirectional Binary Counter with
Clock Enable and Synchro-nous
Reset

No

No

No

Macro

Macro

Macro

Macro

CB16X2

16-Bit Loadable Cascadable

Bidirectional Binary Counter with
Clock Enable and Synchro-nous
Reset

No

No

No

Macro

Macro

Macro

Macro

CBD2CE

2-Bit Cascadable Dual Edge

Triggered Binary Counter with
Clock Enable and Asynchronous
Clear

No

No

No

No

No

No

Macro

CBD4CE

4-Bit Cascadable Dual Edge

Triggered Binary Counter with
Clock Enable and Asynchronous
Clear

No

No

No

No

No

No

Macro

CBD8CE

8-Bit Cascadable Dual Edge

Triggered Binary Counter with
Clock Enable and Asynchronous
Clear

No

No

No

No

No

No

Macro

CBD16CE

16-Bit Cascadable Dual Edge

Triggered Binary Counter with
Clock Enable and Asynchronous
Clear

No

No

No

No

No

No

Macro

CBD2CLE

2-Bit Loadable Cascadable Dual

Edge Triggered Binary Counter
with Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

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1-800-255-7778

Libraries Guide
ISE 6.3i

Design Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

CBD4CLE

4-Bit Loadable Cascadable Dual

Edge Triggered Binary Counter
with Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

CBD8CLE

8-Bit Loadable Cascadable Dual

Edge Triggered Binary Counter
with Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

CBD16CLE

16-Bit Loadable Cascadable Dual

Edge Triggered Binary Counter
with Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

CBD2CLED

2-Bit Loadable Cascadable

Bidirectional Dual Edge Triggered
Binary Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

CBD4CLED

4-Bit Loadable Cascadable

Bidirectional Dual Edge Triggered
Binary Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

CBD8CLED

8-Bit Loadable Cascadable

Bidirectional Dual Edge Triggered
Binary Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

CBD16CLED

16-Bit Loadable Cascadable

Bidirectional Dual Edge Triggered
Binary Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

CBD2RE

2-Bit Cascadable Dual Edge

Triggered Binary Counter with
Clock Enable and Synchronous
Reset

No

No

No

No

No

No

Macro

CBD4RE

4-Bit Cascadable Dual Edge

Triggered Binary Counter with
Clock Enable and Synchronous
Reset

No

No

No

No

No

No

Macro

CBD8RE

8-Bit Cascadable Dual Edge

Triggered Binary Counter with
Clock Enable and Synchronous
Reset

No

No

No

No

No

No

Macro

CBD16RE

16-Bit Cascadable Dual Edge

Triggered Binary Counter with
Clock Enable and Synchronous
Reset

No

No

No

No

No

No

Macro

CBD2RLE

2-Bit Loadable Cascadable Dual

Edge Triggered Binary Counter
with Clock Enable and
Synchronous Reset

No

No

No

No

No

No

Macro

CBD4RLE

4-Bit Loadable Cascadable Dual

Edge Triggered Binary Counter
with Clock Enable and
Synchronous Reset

No

No

No

No

No

No

Macro

CBD8RLE

8-Bit Loadable Cascadable Dual

Edge Triggered Binary Counter
with Clock Enable and
Synchronous Reset

No

No

No

No

No

No

Macro

CBD16RLE

16-Bit Loadable Cascadable Dual

Edge Triggered Binary Counter
with Clock Enable and
Synchronous Reset

No

No

No

No

No

No

Macro

CBD2X1

2-Bit Loadable Cascadable

Bidirectional Dual Edge Triggered
Binary Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

Libraries Guide
ISE 6.3i

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1-800-255-7778

67

Design Element

68

Functional Categories

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

CBD4X1

4-Bit Loadable Cascadable

Bidirectional Dual Edge Triggered
Binary Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

CBD8X1

8-Bit Loadable Cascadable

Bidirectional Dual Edge Triggered
Binary Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

CBD16X1

16-Bit Loadable Cascadable

Bidirectional Dual Edge Triggered
Binary Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

CBD2X2

2-Bit Loadable Cascadable

Bidirectional Dual Edge Triggered
Binary Counter with Clock
Enable and Synchronous Reset

No

No

No

No

No

No

Macro

CBD4X2

4-Bit Loadable Cascadable

Bidirectional Dual Edge Triggered
Binary Counter with Clock
Enable and Synchronous Reset

No

No

No

No

No

No

Macro

CBD8X2

8-Bit Loadable Cascadable

Bidirectional Dual Edge Triggered
Binary Counter with Clock
Enable and Synchronous Reset

No

No

No

No

No

No

Macro

CBD16X2

16-Bit Loadable Cascadable

Bidirectional Dual Edge Triggered
Binary Counter with Clock
Enable and Synchronous Reset

No

No

No

No

No

No

Macro

CC8CE

8-Bit Cascadable Binary Counter

with Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

No

No

No

CC16CE

16-Bit Cascadable Binary Counter

with Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

No

No

No

CC8CLE

8-Bit Loadable Cascadable Binary

Counter with Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

No

No

No

CC16CLE

16-Bit Loadable Cascadable

Binary Counter with Clock
Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

No

No

No

CC8CLED

8-Bit Loadable Cascadable

Bidirectional Binary Counter with
Clock Enable and Asynchronous
Clear

Macro

Macro

Macro

Macro

No

No

No

CC16CLED

16-Bit Loadable Cascadable

Bidirectional Binary Counter with
Clock Enable and Asynchronous
Clear

Macro

Macro

Macro

Macro

No

No

No

CC8RE

8-Bit Cascadable Binary Counter

with Clock Enable and
Synchronous Reset

Macro

Macro

Macro

Macro

No

No

No

CC16RE

16-Bit Cascadable Binary Counter

with Clock Enable and
Synchronous Reset

Macro

Macro

Macro

Macro

No

No

No

CD4CE

4-Bit Cascadable BCD Counter

with Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CD4CLE

4-Bit Loadable Cascadable BCD

Counter with Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CDD4CE

4-Bit Cascadable Dual Edge

Triggered BCD Counter with
Clock Enable and Asynchronous
Clear

No

No

No

No

No

No

Macro

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1-800-255-7778

Libraries Guide
ISE 6.3i

Design Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

CD4RE

4-Bit Cascadable BCD Counter

with Clock Enable and
Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CD4RLE

4-Bit Cascadable BCD Counter

with Clock Enable And
Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CDD4CLE

4-Bit Loadable Cascadable Dual

Edge Triggered BCD Counter
with Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

CDD4RE

4-Bit Cascadable Dual Edge

Triggered BCD Counter with
Clock Enable and Synchronous
Reset

No

No

No

No

No

No

Macro

CDD4RLE

4-Bit Loadable Cascadable Dual

Edge Triggered BCD Counter
with Clock Enable and
Synchronous Reset

No

No

No

No

No

No

Macro

CD4RE

4-Bit Cascadable BCD Counter

with Clock Enable and
Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CD4RLE

4-Bit Loadable Cascadable BCD

Counter with Clock Enable and
Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CJ4CE

4-Bit Johnson Counter with Clock

Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CJ5CE

5-Bit Johnson Counter with Clock

Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CJ8CE

8-Bit Johnson Counter with Clock

Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CJD4CE

4-Bit Dual Edge Triggered

Johnson Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

CJD5CE

5-Bit Dual Edge Triggered

Johnson Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

CJD8CE

8-Bit Dual Edge Triggered

Johnson Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

CJD4RE

4-Bit Dual Edge Triggered

Johnson Counter with Clock
Enable and Synchronous Reset

No

No

No

No

No

No

Macro

CJD5RE

5-Bit Dual Edge Triggered

Johnson Counter with Clock
Enable and Synchronous Reset

No

No

No

No

No

No

Macro

CJD8RE

8-Bit Dual Edge Triggered

Johnson Counter with Clock
Enable and Synchronous Reset

No

No

No

No

No

No

Macro

CJ4RE

4-Bit Johnson Counter with Clock

Enable and Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CJ5RE

5-Bit Johnson Counter with Clock

Enable and Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CJ8RE

8-Bit Johnson Counter with Clock

Enable and Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CR8CE

8-Bit Negative-Edge Binary

Ripple Counter with Clock
Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CR16CE

16-Bit Negative-Edge Binary

Ripple Counter with Clock
Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

69

Design Element

70

Functional Categories

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

CRD8CE

8-Bit Dual-Edge Triggered Binary

Ripple Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

CRD16CE

16-Bit Dual-Edge Triggered

Binary Ripple Counter with Clock
Enable and Asynchronous Clear

No

No

No

No

No

No

Macro

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1-800-255-7778

Libraries Guide
ISE 6.3i

Decoders
Decoder names, shown in the following figure, indicate the number of inputs and
outputs and whether or not an enable is available. Decoders with an enable can be
used as multiplexers.

D2_4E
Decoder
Number of Inputs
Number of Outputs
Output Enable

X4619

Decoder Naming Convention

Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

D2_4E

2- to 4-Line Decoder/
Demultiplexer with Enable

Macro

Macro

Macro

Macro

Macro

Macro

Macro

D3_8E

3- to 8-Line Decoder/
Demultiplexer with Enable

Macro

Macro

Macro

Macro

Macro

Macro

Macro

D4_16E

4- to 16-Line Decoder/
Demultiplexer with Enable

Macro

Macro

Macro

Macro

Macro

Macro

Macro

DEC_CC4

4-Bit Active Low Decoder

Macro

Macro

Macro

Macro

No

No

No

DEC_CC8

8-Bit Active Low Decoder

Macro

Macro

Macro

Macro

No

No

No

DEC_CC16

16-Bit Active Low Decoder

Macro

Macro

Macro

Macro

No

No

No

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ISE 6.3i

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71

Functional Categories

Edge Decoders
Edge decoders are open-drain wired AND gates that are available in different bit
sizes.
Design
Element

72

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

DECODE4

4-Bit Active-Low Decoder

Macro

Macro

Macro

Macro

No

No

No

DECODE8

8-Bit Active-Low Decoder

Macro

Macro

Macro

Macro

No

No

No

DECODE16

16-Bit Active-Low Decoder

Macro

Macro

Macro

Macro

No

No

No

DECODE32

32-Bit Active-Low Decoder

Macro

Macro

Macro

Macro

No

No

No

DECODE64

64-Bit Active-Low Decoder

Macro

Macro

Macro

Macro

No

No

No

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1-800-255-7778

Libraries Guide
ISE 6.3i

Flip-Flops
There are three types of flip-flops (D, J-K, toggle) with various synchronous and
asynchronous inputs. Some are available with inverted clock inputs and/or the ability
to set in response to global set/reset rather than reset. The naming convention shown
in the following figure provides a description for each flip-flop. D-type flip-flops are
available in multiples of up to 16 in one macro.

FDPE_1
Flip-Flop
D-Type (D)
JK-Type (JK)
Toggle-Type (T)
Asynchronous Preset (P)
Asynchronous Clear (C)
Synchronous Set (S)
Synchronous Reset (R)
Clock Enable
Inverted Clock

X4579

Flip-Flop Naming Convention

Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

FD

D Flip-Flop

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

FD_1

D Flip-Flop with Negative-Edge

Clock

Primitive

Primitive

Primitive

Primitive

No

No

No

FD4

Multiple D Flip-Flop

No

No

No

No

Macro

Macro

Macro

FD8

Multiple D Flip-Flop

No

No

No

No

Macro

Macro

Macro

FD16

Multiple D Flip-Flop

No

No

No

No

Macro

Macro

Macro

FD4CE

4-Bit Data Register with Clock

Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FD8CE

8-Bit Data Register with Clock

Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FD16CE

16-Bit Data Register with Clock

Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FD4RE

4-Bit Data Register with Clock

Enable and Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FD8RE

8-Bit Data Register with Clock

Enable and Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FD16RE

16-Bit Data Register with Clock

Enable and Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FDC

D Flip-Flop with Asynchronous

Clear

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

FDC_1

D Flip-Flop with Negative-Edge

Clock and Asynchronous Clear

Primitive

Primitive

Primitive

Primitive

No

No

No

FDCE

D Flip-Flop with Clock Enable

and Asynchronous Clear

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

FDCE_1

D Flip-Flop with Negative-Edge

Clock, Clock Enable, and
Asynchronous Clear

Primitive

Primitive

Primitive

Primitive

No

No

No

FDCP

D Flip-Flop with Asynchronous

Preset and Clear

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

FDCP_1

D Flip-Flop with Negative-Edge

Clock and Asynchronous Preset
and Clear

Primitive

Primitive

Primitive

Primitive

No

No

No

Libraries Guide
ISE 6.3i

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1-800-255-7778

73

Design
Element

74

Functional Categories

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

FDCPE

D Flip-Flop with Clock Enable

and Asynchronous Preset and
Clear

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Primitive

FDCPE_1

D Flip-Flop with Negative-Edge

Clock, Clock Enable, and
Asynchronous Preset and Clear

Primitive

Primitive

Primitive

Primitive

No

No

No

FDD

Dual Edge Triggered D Flip-Flop

No

No

No

No

No

No

Macro

FDD4

Multiple Dual Edge Triggered D

Flip-Flop

No

No

No

No

No

No

Macro

FDD8

Multiple Dual Edge Triggered D

Flip-Flop

No

No

No

No

No

No

Macro

FDD16

Multiple Dual Edge Triggered D

Flip-Flop

No

No

No

No

No

No

Macro

FDD4CE

4-Bit Dual Edge Triggered Data

Register with Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

FDD8CE

8-Bit Dual Edge Triggered Data

Register with Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

FDD16CE

16-Bit Dual Edge Triggered Data

Register with Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

FDD4RE

4-Bit Dual Edge Triggered Data

Register with Clock Enable and
Synchronous Reset

No

No

No

No

No

No

Macro

FDD8RE

8-Bit Dual Edge Triggered Data

Register with Clock Enable and
Synchronous Reset

No

No

No

No

No

No

Macro

FDD16RE

16-Bit Dual Edge Triggered Data

Register with Clock Enable and
Synchronous Reset

No

No

No

No

No

No

Macro

FDDC

D Dual Edge Triggered Flip-Flop

with Asynchronous Clear

No

No

No

No

No

No

Macro

FDDCE

Dual Edge Triggered D Flip-Flop

with Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Primitive

FDDCP

Dual Edge Triggered D Flip-Flop

Asynchronous Preset and Clear

No

No

No

No

No

No

Primitive

FDDCPE

Dual Edge Triggered D Flip-Flop

with Clock Enable and
Asynchronous Preset and Clear

No

No

No

No

No

No

Primitive

FDDP

Dual Edge Triggered D Flip-Flop

with Asynchronous Preset

No

No

No

No

No

No

Macro

FDDPE

Dual Edge Triggered D Flip-Flop

with Clock Enable and
Asynchronous Preset

No

No

No

No

No

No

Primitive

FDDR

Dual Edge Triggered D Flip-Flop

with Synchronous Reset

No

No

No

No

No

No

Macro

FDDRCPE

Dual Data Rate D Flip-Flop with

Clock Enable and Asynchronous
Preset and Clear

No

Primitive

No

Primitive

No

No

No

FDDRE

Dual Edge Triggered D Flip-Flop

with Clock Enable and
Synchronous Reset

No

No

No

No

No

No

Macro

FDDRSE

Dual Data Rate D Flip-Flop with

Clock Enable and Synchronous
Reset and Set

No

Primitive

No

Primitive

No

No

No

FDDRS

Dual Edge Triggered D Flip-Flop

with Synchronous Reset and Set

No

No

No

No

No

No

Macro

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Libraries Guide
ISE 6.3i

Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

FDDRSE

Dual Edge Triggered D Flip-Flop

with Synchronous Reset and Set
and Clock Enable

No

No

No

No

No

No

Macro

FDDS

Dual Edge Triggered D Flip-Flop

with Synchronous Set

No

No

No

No

No

No

Macro

FDDSE

D Flip-Flop with Clock Enable

and Synchronous Set

No

No

No

No

No

No

Macro

FDDSR

Dual Edge Triggered D Flip-Flop

with Synchronous Set and Reset

No

No

No

No

No

No

Macro

FDDSRE

Dual Edge Triggered D Flip-Flop

with Synchronous Set and Reset
and Clock Enable

No

No

No

No

No

No

Macro

FDE

D Flip-Flop with Clock Enable

Primitive

Primitive

Primitive

Primitive

No

No

No

FDE_1

D Flip-Flop with Negative-Edge

Clock and Clock Enable

Primitive

Primitive

Primitive

Primitive

No

No

No

FDP

D Flip-Flop with Asynchronous

Preset

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

FDP_1

D Flip-Flop with Negative-Edge

Clock and Asynchronous Preset

Primitive

Primitive

Primitive

Primitive

No

No

No

FDPE

D Flip-Flop with Clock Enable

and Asynchronous Preset

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

FDPE_1

D Flip-Flop with Negative-Edge

Clock, Clock Enable, and
Asynchronous Preset

Primitive

Primitive

Primitive

Primitive

No

No

No

FDR

D Flip-Flop with Synchronous

Reset

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

FDR_1

D Flip-Flop with Negative-Edge

Clock and Synchronous Reset

Primitive

Primitive

Primitive

Primitive

No

No

No

FDRE

D Flip-Flop with Clock Enable

and Synchronous Reset

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

FDRE_1

D Flip-Flop with Negative-Clock

Edge, Clock Enable, and
Synchronous Reset

Primitive

Primitive

Primitive

Primitive

No

No

No

FDRS

D Flip-Flop with Synchronous

Reset and Set

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

FDRS_1

D Flip-Flop with Negative-Clock

Edge and Synchronous Reset and
Set

Primitive

Primitive

Primitive

Primitive

No

No

No

FDRSE

D Flip-Flop with Synchronous

Reset and Set and Clock Enable

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

FDRSE_1

D Flip-Flop with Negative-Clock

Edge, Synchronous Reset and
Set, and Clock Enable

Primitive

Primitive

Primitive

Primitive

No

No

No

FDS

D Flip-Flop with Synchronous

Set

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

FDS_1

D Flip-Flop with Negative-Edge

Clock and Synchronous Set

Primitive

Primitive

Primitive

Primitive

No

No

No

FDSE

D Flip-Flop with Clock Enable

and Synchronous Set

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

FDSE_1

D Flip-Flop with Negative-Edge

Clock, Clock Enable, and
Synchronous Set

Primitive

Primitive

Primitive

No

No

No

No

FDSR

D Flip-Flop with Synchronous

Set and Reset

No

No

No

No

Macro

Macro

Macro

FDSRE

D Flip-Flop with Synchronous

Set and Reset and Clock Enable

No

No

No

No

Macro

Macro

Macro

FJKC

J-K Flip-Flop with Asynchronous

Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

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75

Design
Element

76

Functional Categories

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

FJKCE

J-K Flip-Flop with Clock Enable

and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FJKCP

J-K Flip-Flop with Asynchronous

Clear and Preset

No

No

No

No

Macro

Macro

Macro

FJKCPE

J-K Flip-Flop with Asynchronous

Clear and Preset and Clock
Enable

No

No

No

No

Macro

Macro

Macro

FJKP

J-K Flip-Flop with Asynchronous

Preset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FJKPE

J-K Flip-Flop with Clock Enable

and Asynchronous Preset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FJKRSE

J-K Flip-Flop with Clock Enable

and Synchronous Reset and Set

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FJKSRE

J-K Flip-Flop with Clock Enable

and Synchronous Set and Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTC

Toggle Flip-Flop with Toggle

Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTCE

Toggle Flip-Flop with Toggle and

Clock Enable and Asynchronous
Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTCLE

Toggle/Loadable Flip-Flop with

Toggle and Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTCLEX

Toggle/Loadable Flip-Flop with

Toggle and Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTCP

Toggle Flip-Flop with Toggle

Enable and Asynchronous Clear
and Preset

No

No

No

No

Primitive

Primitive

Primitive

FTCPE

Toggle Flip-Flop with Toggle and

Clock Enable and Asynchronous
Clear and Preset

No

No

No

No

Macro

Macro

Macro

FTCPLE

Loadable Toggle Flip-Flop with

Toggle and Clock Enable and
Asynchronous Clear and Preset

No

No

No

No

Macro

Macro

Macro

FTDCE

Dual Edge Triggered Toggle Flip- No

Flop with Toggle and Clock
Enable and Asynchronous Clear

No

No

No

No

No

Macro

FTDCLE

Dual Edge Triggered Toggle/

Loadable Flip-Flop with Toggle
and Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

FTDCLEX

Dual Edge Triggered Toggle/

Loadable Flip-Flop with Toggle
and Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

FTDCP

Toggle Flip-Flop with Toggle

Enable and Asynchronous Clear
and Preset

No

No

No

No

Primitive

Primitive

Primitive

FTDRSE

Dual Edge Triggered Toggle Flip- No

Flop with Toggle and Clock
Enable and Synchronous Reset
and Set

No

No

No

No

No

Macro

FTDRSLE

Dual Edge Triggered Toggle/

Loadable Flip-Flop with Toggle
and Clock Enable and
Synchronous Reset and Set

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTP

Toggle Flip-Flop with Toggle

Macro
Enable and Asynchronous Preset

Macro

Macro

Macro

Macro

Macro

Macro

FTPE

Toggle Flip-Flop with Toggle and

Clock Enable and Asynchronous
Preset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

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Libraries Guide
ISE 6.3i

Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

FTPLE

Toggle/Loadable Flip-Flop with

Toggle and Clock Enable and
Asynchronous Preset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTRSE

Toggle Flip-Flop with Toggle and

Clock Enable and Synchronous
Reset and Set

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTRSLE

Toggle/Loadable Flip-Flop with

Toggle and Clock Enable and
Synchronous Reset and Set

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTSRE

Toggle Flip-Flop with Toggle and

Clock Enable and Synchronous
Set and Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTSRLE

Toggle/Loadable Flip-Flop with

Toggle and Clock Enable and
Synchronous Set and Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

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ISE 6.3i

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77

Functional Categories

General
General elements include FPGA configuration functions, oscillators, boundary scan
logic, and other functions not classified in other sections.
Design Element

78

Description

Spartan-II,
IIE

Spartan3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

BSCAN_SPARTAN2

Spartan-II Boundary Scan

Logic Control Circuit

Primitivea

No

No

No

No

No

No

BSCAN_SPARTAN3

Spartan-3 Boundary Scan

Logic Control Circuit

No

Primitive

No

No

No

No

No

BSCAN_VIRTEX

Virtex Boundary Scan Logic

Control Circuit

Primitiveb

No

Primitive

No

No

No

No

BSCAN_VIRTEX2

Virtex2 Boundary Scan

Logic Control Circuit

No

No

No

Primitive

No

No

No

CAPTURE_SPARTA
N2

Spartan-II Register State

Capture for Bitstream
Readback

Primitive

No

No

No

No

No

No

CAPTURE_SPARTA
N3

Spartan-3 Register State

Capture for Bitstream
Readback

No

Primitive

No

No

No

No

No

CAPTURE_VIRTEX

Virtex Register State

Capture for Bitstream
Readback

No

No

Primitive

No

No

No

No

CAPTURE_VIRTEX2

Virtex-II Register State

Capture for Bitstream
Readback

No

No

No

Primitive

No

No

No

CLK_DIV2

Global Clock Divider

No

No

No

No

No

No

Primitive

CLK_DIV4

Global Clock Divider

No

No

No

No

No

No

Primitive

CLK_DIV6

Global Clock Divider

No

No

No

No

No

No

Primitive

CLK_DIV8

Global Clock Divider

No

No

No

No

No

No

Primitive

CLK_DIV10

Global Clock Divider

No

No

No

No

No

No

Primitive

CLK_DIV12

Global Clock Divider

No

No

No

No

No

No

Primitive

CLK_DIV14

Global Clock Divider

No

No

No

No

No

No

Primitive

CLK_DIV16

Global Clock Divider

No

No

No

No

No

No

Primitive

CLK_DIV2R

Global Clock Divider with

Synchronous Reset

No

No

No

No

No

No

Primitive

CLK_DIV4R

Global Clock Divider with

Synchronous Reset

No

No

No

No

No

No

Primitive

CLK_DIV6R

Global Clock Divider with

Synchronous Reset

No

No

No

No

No

No

Primitive

CLK_DIV8R

Global Clock Divider with

Synchronous Reset

No

No

No

No

No

No

Primitive

CLK_DIV10R

Global Clock Divider with

Synchronous Reset

No

No

No

No

No

No

Primitive

CLK_DIV12R

Global Clock Divider with

Synchronous Reset

No

No

No

No

No

No

Primitive

CLK_DIV14R

Global Clock Divider with

Synchronous Reset

No

No

No

No

No

No

Primitive

CLK_DIV16R

Global Clock Divider with

Synchronous Reset

No

No

No

No

No

No

Primitive

CLK_DIV2RSD

Global Clock Divider with

Synchronous Reset and Start
Delay

No

No

No

No

No

No

Primitive

CLK_DIV4RSD

Global Clock Divider with

Synchronous Reset and Start
Delay

No

No

No

No

No

No

Primitive

CLK_DIV6RSD

Global Clock Divider with

Synchronous Reset and Start
Delay

No

No

No

No

No

No

Primitive

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Libraries Guide
ISE 6.3i

Design Element

Description

Spartan-II,
IIE

Spartan3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

CLK_DIV8RSD

Global Clock Divider with

Synchronous Reset and Start
Delay

No

No

No

No

No

No

Primitive

CLK_DIV10RSD

Global Clock Divider with

Synchronous Reset and Start
Delay

No

No

No

No

No

No

Primitive

CLK_DIV12RSD

Global Clock Divider with

Synchronous Reset and Start
Delay

No

No

No

No

No

No

Primitive

CLK_DIV14RSD

Global Clock Divider with

Synchronous Reset and Start
Delay

No

No

No

No

No

No

Primitive

CLK_DIV16RSD

Global Clock Divider with

Synchronous Reset and Start
Delay

No

No

No

No

No

No

Primitive

CLK_DIV2SD

Global Clock Divider with

Start Delay

No

No

No

No

No

No

Primitive

CLK_DIV4SD

Global Clock Divider with

Start Delay

No

No

No

No

No

No

Primitive

CLK_DIV6SD

Global Clock Divider with

Start Delay

No

No

No

No

No

No

Primitive

CLK_DIV8SD

Global Clock Divider with

Start Delay

No

No

No

No

No

No

Primitive

CLK_DIV10SD

Global Clock Divider with

Start Delay

No

No

No

No

No

No

Primitive

CLK_DIV12SD

Global Clock Divider with

Start Delay

No

No

No

No

No

No

Primitive

CLK_DIV14SD

Global Clock Divider with

Start Delay

No

No

No

No

No

No

Primitive

CLK_DIV16SD

Global Clock Divider with

Start Delay

No

No

No

No

No

No

Primitive

CLKDLL

Clock Delay Locked Loop

Primitive

No

Primitive

No

No

No

No

CLKDLLE

Clock Delay Locked Loop

with Expanded Output

Primitivec

No

Primitived

No

No

No

No

CLKDLLHF

High Frequency Clock

Delay Locked Loop

Primitive

No

Primitivee

No

No

No

No

DCM

Digital Clock Manager

No

Primitive

No

Primitive

No

No

No

GND

Ground-Connection Signal
Tag

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

ICAP_VIRTEX2

User Interface to Virtex-II

Internal Configuration
Access Port

No

No

No

Primitive

No

No

No

JTAGPPC

JTAG Primitive for the

Power PC

No

No

No

Primitivef

No

No

No

KEEPER

KEEPER Symbol

Primitive

Primitive

Primitive

Primitive

Primitiveg

No

Primitive

LUT1

1-Bit Look-Up-Table with

General Output

Primitive

Primitive

Primitive

Primitive

No

No

No

LUT2

2-Bit Look-Up-Table with

General Output

Primitive

Primitive

Primitive

Primitive

No

No

No

LUT3

3-Bit Look-Up-Table with

General Output

Primitive

Primitive

Primitive

Primitive

No

No

No

LUT4

4-Bit Look-Up-Table with

General Output

Primitive

Primitive

Primitive

Primitive

No

No

No

LUT1_D

1-Bit Look-Up-Table with

Dual Output

Primitive

Primitive

Primitive

Primitive

No

No

No

LUT2_D

2-Bit Look-Up-Table with

Dual Output

Primitive

Primitive

Primitive

Primitive

No

No

No

LUT3_D

3-Bit Look-Up-Table with

Dual Output

Primitive

Primitive

Primitive

Primitive

No

No

No

Libraries Guide
ISE 6.3i

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1-800-255-7778

79

Design Element

Functional Categories

Description

Spartan-II,
IIE

Spartan3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

LUT4_D

4-Bit Look-Up-Table with

Dual Output

Primitive

Primitive

Primitive

Primitive

No

No

No

LUT1_L

1-Bit Look-Up-Table with

Local Output

Primitive

Primitive

Primitive

Primitive

No

No

No

LUT2_L

2-Bit Look-Up-Table with

Local Output

Primitive

Primitive

Primitive

Primitive

No

No

No

LUT3_L

3-Bit Look-Up-Table with

Local Output

Primitive

Primitive

Primitive

Primitive

No

No

No

LUT4_L

4-Bit Look-Up-Table with

Local Output

Primitive

Primitive

Primitive

Primitive

No

No

No

PPC405

Primitive for the Power PC

Core

No

No

No

Primitiveh

No

No

No

PULLDOWN

Resistor to GND for Input

Pads

Primitive

Primitive

Primitive

Primitive

No

No

No

PULLUP

Resistor to VCC for Input

PADs, Open-Drain, and 3State Outputs

Primitive

Primitive

Primitive

Primitive

No

Primitive

Primitive

ROC

Reset On Configuration

Primitive

Primitive

Primitive

Primitive

No

No

No

STARTBUF_architect
ure

VHDL Simulation of FPGA

Designs

Primitive

Primitive

Primitive

Primitive

No

No

No

STARTUP_SPARTA
N2

Spartan-II User Interface to

Global Clock, Reset, and 3State Controls

Primitivei

No

No

No

No

No

No

STARTUP_SPARTA
N3

Spartan-3 User Interface to

Global Clock, Reset, and 3State Controls

No

Primitive

No

No

No

No

No

STARTUP_VIRTEX

Virtex User Interface to

Global Clock, Reset, and 3State Controls

Primitivej

No

Primitive

No

No

No

No

STARTUP_VIRTEX2

Virtex-II User Interface to

Global Clock, Reset, and 3State Controls

No

No

No

Primitive

No

No

No

TOC

Three-State On
Configuration

Primitive

Primitive

Primitive

Primitive

No

No

No

TOCBUF

Three-State On
Configuration Buffer

Primitive

Primitive

Primitive

Primitive

No

No

No

VCC

VCC-Connection Signal Tag

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

a.Primitive is supported for Spartan-II, but not for Spartan-IIE, which is supported by BSCAN_VIRTEX
b.Primitive is supported for Spartan-IIE, but not for Spartan-II, which is supported by BSCAN_SPARTAN2.
c. Supported for Spartan-IIE and Virtex-E devices only.
d. Supported for Spartan-IIE and Virtex-E devices only.
e.For Virtex E, use CLKDLLHF in HF mode. In LF mode, both the separate CLKDLLE and CLKDLL primitive can be used.
f.Supported for Virtex-II Pro and Virtex-II Pro X only.
g.Supported for only XC9500XL and XC9500XV.
h.Not supported for Virtex-II. Supported for Virtex-II Pro and Virtex-II Pro X only.
i.The Primitive in the field marked Spartan IIE is supported only for Spartan-II but not for Spartan-IIE, the latter of which
is supported by STARTUP_VIRTEX.
j.The Primitive in the Spartan IIE field is supported for Spartan-IIE, but not for Spartan-II, which is supported by
STARTUP_SPARTAN2.

80

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Libraries Guide
ISE 6.3i

Input Latches
Single and multiple input latches can hold transient data entering a chip. Input latches
use the same naming convention as I/O flip-flops.
Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

ILD

Transparent Input Data

Latch

Macro

Macro

Macro

Macro

No

No

No

ILD4

Transparent Input Data

Latch

Macro

Macro

Macro

Macro

No

Nob

No

ILD8

Transparent Input Data

Latch

Macro

Macro

Macro

Macro

No

No

No

ILD16

Transparent Input Data

Latch

Macro

Macro

Macro

Macro

No

No

No

ILD_1

Transparent Input Data

Latch with Inverted Gate

Macro

Macro

Macro

Macro

No

No

No

ILDI

Transparent Input Data

Latch (Asynchronous
Preset)

Macro

Macro

Macro

Macro

No

No

No

ILDI_1

Transparent Input Data

Latch with Inverted Gate
(Asynchronous Preset)

Macro

Macro

Macro

Macro

No

No

No

ILDX

Transparent Input Data

Latch

Macro

Macro

Macro

Macro

No

No

No

ILDX4

Transparent Input Data

Latch

Macro

Macro

Macro

Macro

No

No

No

ILDX8

Transparent Input Data

Latch

Macro

Macro

Macro

Macro

No

No

No

ILDX16

Transparent Input Data

Latch

Macro

Macro

Macro

Macro

No

No

No

ILDX_1

Transparent Input Data

Latch with Inverted Gate

Macro

Macro

Macro

Macro

No

No

No

ILDXI

Transparent Input Data

Latch (Asynchronous
Preset)

Macro

Macro

Macro

Macro

No

No

No

ILDXI_1

Transparent Input Data

Latch with Inverted Gate
(Asynchronous Preset)

Macro

Macro

Macro

Macro

No

No

No

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81

Functional Categories

Input/Output Flip-Flops
Input/Output flip-flops are configured in IOBs. They include flip-flops whose
outputs are enabled by 3-state buffers, flip-flops that can be set upon global set/reset
rather than reset, and flip-flops with inverted clock inputs. The naming convention
specifies each flip-flop function and is illustrated in the following figure.

OFDEI_1
Output (O), Input (I)
Flip-Flop
D-Type
Active High Enable (E)
Active Low Enable (T)
Inverse of Normal Initial State
Inverted Clock

X4580

Input/Output Flip-Flop Naming Convention

Design
Element

82

Description

Spartan-II,
IIE

Spartan3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

IFD

Single- and Multiple-Input

D Flip-Flop

Macro

Macro

Macro

Macro

No

No

No

IFD_1

Input D Flip-Flop with

Inverted Clock

Macro

Macro

Macro

Macro

No

No

No

IFD4

Single- and Multiple-Input

D Flip-Flop

Macro

Macro

Macro

Macro

No

No

No

IFD8

Single- and Multiple-Input

D Flip-Flop

Macro

Macro

Macro

Macro

No

No

No

IFD16

Single- and Multiple-Input

D Flip-Flop

Macro

Macro

Macro

Macro

No

No

No

IFDDRCPE

Dual Data Rate Input D

Flip-Flop with Clock Enable
and Asynchronous Preset
and Clear

No

Primitive

No

Primitive

No

No

No

IFDDRRSE

Dual Data Rate Input D

Flip-Flop with Synchronous
Reset and Set and Clock
Enable

No

Primitive

No

Primitive

No

No

No

IFDI

Input D Flip-Flop
(Asynchronous Preset)

Macro

Macro

Macro

Macro

No

No

No

IFDI_1

Input D Flip-Flop with

Inverted Clock
(Asynchronous Preset)

Macro

Macro

Macro

Macro

No

No

No

IFDX

Single- and Multiple-Input

D Flip-Flop with Clock
Enable

Macro

Macro

Macro

Macro

No

No

No

IFDX_1

Input D Flip-Flop with

Inverted Clock and Clock
Enable

Macro

Macro

Macro

Macro

No

No

No

IFDX4

Single- and Multiple-Input

D Flip-Flop with Clock
Enable

Macro

Macro

Macro

Macro

No

No

No

IFDX8

Single- and Multiple-Input

D Flip-Flop with Clock
Enable

Macro

Macro

Macro

Macro

No

No

No

IFDX16

Single- and Multiple-Input

D Flip-Flops with Clock
Enable

Macro

Macro

Macro

Macro

No

No

No

IFDXI

Input D Flip-Flop with

Clock Enable
(Asynchronous Preset)

Macro

Macro

Macro

Macro

No

No

No

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Libraries Guide
ISE 6.3i

Design
Element

Description

Spartan-II,
IIE

Spartan3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

OFD

Single- and MultipleOutput D Flip-Flops

Macro

Macro

Macro

Macro

No

No

No

OFD4

Single- and MultipleOutput D Flip-Flops

Macro

Macro

Macro

Macro

No

No

No

OFD8

Single- and MultipleOutput D Flip-Flops

Macro

Macro

Macro

Macro

No

No

No

OFD16

Single- and MultipleOutput D Flip-Flops

Macro

Macro

Macro

Macro

No

No

No

OFD_1

Output D Flip-Flop with

Inverted Clock

Macro

Macro

Macro

Macro

No

No

No

OFDDRCPE

Dual Data Rate Output D

Flip-Flop with Clock Enable
and Asynchronous Preset
and Clear

No

Primitive

No

Primitive

No

No

No

OFDDRRSE

Dual Data Rate Output D

Flip-Flop with Synchronous
Reset and Set and Clock
Enable

No

Primitive

No

Primitive

No

No

No

OFDDRTCPE

Dual Data Rate D Flip-Flop

with Active-Low 3--State
Output Buffer, Clock
Enable, and Asynchro-nous
Preset and Clear

No

Primitive

No

Primitive

No

No

No

OFDDRTRSE

Dual Data Rate D Flip-Flop

with Active -Low 3-State
Output Buffer,
Synchronous Reset and Set,
and Clock Enable

No

Primitive

No

Primitive

No

No

No

OFDE

D Flip-Flop with ActiveMacro

High Enable Output Buffers

Macro

Macro

Macro

No

No

No

OFDE4

D Flip-Flop with ActiveMacro

High Enable Output Buffers

Macro

Macro

Macro

No

No

No

OFDE8

D Flip-Flop with ActiveMacro

High Enable Output Buffers

Macro

Macro

Macro

No

No

No

OFDE16

D Flip-Flop with ActiveMacro

High Enable Output Buffers

Macro

Macro

Macro

No

No

No

OFDE_1

D Flip-Flop with ActiveHigh Enable Output Buffer

and Inverted Clock

Macro

Macro

Macro

Macro

No

No

No

OFDI

Output D Flip-Flop
(Asynchronous Preset)

Macro

Macro

Macro

Macro

No

No

No

OFDI_1

Output D Flip-Flop with

Inverted Clock
(Asynchronous Preset)

Macro

Macro

Macro

Macro

No

No

No

OFDT

Single and Multiple D FlipFlop with Active-Low 3State Output Buffers

Macro

Macro

Macro

Macro

No

No

No

OFDT4

Single and Multiple D FlipFlop with Active-Low 3State Output Buffers

Macro

Macro

Macro

Macro

No

No

No

OFDT8

Single and Multiple D FlipFlop with Active-Low 3State Output Buffers

Macro

Macro

Macro

Macro

No

No

No

OFDT16

Single and Multiple D FlipFlop with Active-Low 3State Output Buffers

Macro

Macro

Macro

Macro

No

No

No

OFDT_1

D Flip-Flop with ActiveLow 3-State Output Buffer

and Inverted Clock

Macro

Macro

Macro

Macro

No

No

No

OFDX

Single- and MultipleOutput D Flip-Flop with

Clock Enable

Macro

Macro

Macro

Macro

No

No

No

Libraries Guide
ISE 6.3i

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1-800-255-7778

83

Design
Element

84

Functional Categories

Description

Spartan-II,
IIE

Spartan3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

OFDX4

Single- and MultipleOutput D Flip-Flop with

Clock Enable

Macro

Macro

Macro

Macro

No

No

No

OFDX8

Single- and MultipleOutput D Flip-Flop with

Clock Enable

Macro

Macro

Macro

Macro

No

No

No

OFDX16

Single- and MultipleOutput D Flip-Flop with

Clock Enable

Macro

Macro

Macro

Macro

No

No

No

OFDX_1

Output D Flip-Flop with

Inverted Clock and Clock
Enable

Macro

Macro

Macro

Macro

No

No

No

OFDXI

Output D Flip-Flop with

Clock Enable
(Asynchronous Preset)

Macro

Macro

Macro

Macro

No

No

No

OFDXI_1

Output D Flip-Flop with

Inverted Clock and Clock
Enable (Asynchronous
Preset)

Macro

Macro

Macro

Macro

No

No

No

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1-800-255-7778

Libraries Guide
ISE 6.3i

Input/Output Functions
Input/Output Block (IOB) resources are configured into various I/O primitives and
macros for convenience, such as output buffers (s) and output buffers with an enable
(OBUFEs). Pads used to connect the circuit to PLD device pins are also included.
Virtex, Virtex-E, Spartan-II, Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro, and VirtexII Pro X have multiple variants (Primitives) to choose from for each SelectIO buffer.
The I/O interface for each variant corresponds to a specific I/O standard.
Design Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

GT_AURORA_n

Gigabit Transceiver for

High-Speed I/O

No

No

No

Primitive

No

No

No

GT_CUSTOM

Gigabit Transceiver for

High-Speed I/O

No

No

No

Primitive

No

No

No

GT_ETHERNET_n

Gigabit Transceiver for

High-Speed I/O

No

No

No

Primitive

No

No

No

GT_FIBRE_CHAN_n

Gigabit Transceiver for

High-Speed I/O

No

No

No

Primitive

No

No

No

GT_INFINIBAND_n

10-Gigabit Transceiver
for High-Speed I/O

No

No

No

Primitive

No

No

No

GT_XAUI_n

10-Gigabit Transceiver
for High-Speed I/O

No

No

No

Primitive

No

No

No

GT10_10GE_n

10-Gigabit Transceiver
for High-Speed I/O

No

No

No

Primitive

No

No

No

GT10_10GFC_n

10-Gigabit Transceiver
for High-Speed I/O

No

No

No

Primitive

No

No

No

GT10_AURORA_n

10-Gigabit Transceiver
for High-Speed I/O

No

No

No

Primitive

No

No

No

GT10_AURORAX_n

10-Gigabit Transceiver
for High-Speed I/O

No

No

No

Primitive

No

No

No

GT10_CUSTOM

10-Gigabit Transceiver
for High-Speed I/O

No

No

No

Primitive

No

No

No

GT10_OC48_n

10-Gigabit Transceiver
for High-Speed I/O

No

No

No

Primitive

No

No

No

GT10_OC192_n

10-Gigabit Transceiver
for High-Speed I/O

No

No

No

Primitive

No

No

No

GT10_PCI_EXPRESS_n

10-Gigabit Transceiver
for High-Speed I/O

No

No

No

Primitive

No

No

No

IBUF

Single- and MultipleInput Buffer

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

IBUF4

Single- and MultipleInput Buffer

Macro

No

Macro

Macro

Macro

Macro

Macro

IBUF8

Single- and MultipleInput Buffer

Macro

No

Macro

Macro

Macro

Macro

Macro

IBUF16

Single- and MultipleInput Buffer

Macro

No

Macro

Macro

Macro

Macro

Macro

IBUFDS

Differential Signaling
Input Buffer with
Selectable I/O Interface

No

Primitive

No

Primitive

No

No

No

IBUFG

Dedicated Input Buffer

with Selectable I/O
Interface

Primitive

Primitive

Primitive

Primitive

No

No

No

IBUFGDS

Dedicated Differential
Signaling Input Buffer
with Selectable I/O
Interface

No

Primitive

No

Primitive

No

No

No

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

85

Design Element

86

Functional Categories

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

IOBUF

Bi-Directional Buffer
with Selectable I/0
Interface (multiple
primitives)

Primitive

Primitive

Primitive

Primitive

No

No

No

IOBUFDS

3-State Differential
Signaling I/O Buffer
with Active Low Output
Enable

No

Primitive

No

Primitive

No

No

No

IOPAD

Single- and MultipleInput/Output Pad

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

IOPAD4

Single- and MultipleInput/Output Pad

Macro

Macro

Macro

Macro

Macro

Macro

Macro

IOPAD8

Single- and MultipleInput/Output Pad

Macro

Macro

Macro

Macro

Macro

Macro

Macro

IOPAD16

Single- and MultipleInput/Output Pad

Macro

Macro

Macro

Macro

Macro

Macro

Macro

IPAD

Single- and MultipleInput Pad

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

IPAD4

Single- and MultipleInput Pad

Macro

Macro

Macro

Macro

Macro

Macro

Macro

IPAD8

Single- and MultipleInput Pad

Macro

Macro

Macro

Macro

Macro

Macro

Macro

IPAD16

Single- and MultipleInput Pad

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OBUF

Single- and MultipleOutput Buffer

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OBUF4

Single- and MultipleOutput Buffer

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OBUF8

Single- and MultipleOutput Buffer

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OBUF16

Single- and MultipleOutput Buffer

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OBUFDS

Differential Signaling
Output Buffer with
Selectable I/O Interface

No

Primitive

No

Primitive

No

No

No

OBUFE

3-State Output Buffers

with Active-High
Output Enable

Macro

No

Macro

Macro

Primitive

Primitive

Primitive

OBUFE4

3-State Output Buffers

with Active-High
Output Enable

Macro

No

Macro

Macro

Macro

Macro

Macro

OBUFE8

3-State Output Buffers

with Active-High
Output Enable

Macro

No

Macro

Macro

Macro

Macro

Macro

OBUFE16

3-State Output Buffers

with Active-High
Output Enable

Macro

No

Macro

Macro

Macro

Macro

Macro

OBUFT

Single and Multiple 3State Output Buffer with

Active Low Output
Enable

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OBUFT4

Single and Multiple 3State Output Buffer with

Active Low Output
Enable

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OBUFT8

Single and Multiple 3State Output Buffer with

Active Low Output
Enable

Macro

Macro

Macro

Macro

Macro

Macro

Macro

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Libraries Guide
ISE 6.3i

Design Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

OBUFT16

Single and Multiple 3State Output Buffer with

Active Low Output
Enable

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OBUFTDS

3-State Output Buffer

with Differential
Signaling, Active-Low
Output Enable, and
Selectable I/O Interface

No

Primitive

No

Primitive

No

No

No

OPAD

Single- and MultipleOutput Pad

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OPAD4

Multiple-Output Pad

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OPAD8

Multiple-Output Pad

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OPAD16

Multiple-Output Pad

Macro

Macro

Macro

Macro

Macro

Macro

Macro

UPAD

Connects the I/O Node

of an IOB to the Internal
PLD Circuit

Primitive

Primitive

Primitive

Primitive

No

No

No

Libraries Guide
ISE 6.3i

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1-800-255-7778

87

Functional Categories

Latches
Latches (LD) are available for all architectures.
Design
Element

88

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

LD

Transparent Data Latch

Primitive

Primitive

Primitive

Primitive

Macro

Primitive

Primitive

LD_1

Transparent Data Latch

with Inverted Gate

Primitive

Primitive

Primitive

Primitive

No

No

No

LD4

Multiple Transparent Data

Latch

Macro

Macro

Macro

Macro

Macro

Macro

Macro

LD8

Multiple Transparent Data

Latch

Macro

Macro

Macro

Macro

Macro

Macro

Macro

LD16

Multiple Transparent Data

Latch

Macro

Macro

Macro

Macro

Macro

Macro

Macro

LD4CE

Transparent Data Latch

with Asynchronous Clear
and Gate Enable

Macro

Macro

Macro

Macro

No

No

No

LD8CE

Transparent Data Latch

with Asynchronous Clear
and Gate Enable

Macro

Macro

Macro

Macro

No

No

No

LD16CE

Transparent Data Latch

with Asynchronous Clear
and Gate Enable

Macro

Macro

Macro

Macro

No

No

No

LDC

Transparent Data Latch

with Asynchronous Clear

Primitive

Primitive

Primitive

Primitive

Macro

Primitive

Primitive

LDC_1

Transparent Data Latch

with Asynchronous Clear
and Inverted Gate

Primitive

Primitive

Primitive

Primitive

No

No

No

LDCE

Transparent Data Latch

with Asynchronous Clear
and Gate Enable

Primitive

Primitive

Primitive

Primitive

No

No

No

LDCE_1

Transparent Data Latch

with Asynchronous Clear,
Gate Enable, and Inverted
Gate

Primitive

Primitive

Primitive

Primitive

No

No

No

LDCP

Transparent Data Latch

with Asynchronous Clear
and Preset

Primitive

Primitive

Primitive

Primitive

Macro

Primitive

Primitive

LDCP_1

Transparent Data Latch

with Asynchronous Clear
and Preset and Inverted
Gate

Primitive

Primitive

Primitive

Primitive

No

No

No

LDCPE

Transparent Data Latch

Primitive
with Asynchronous Clear
and Preset and Gate Enable

Primitive

Primitive

Primitive

No

No

No

LDCPE_1

Transparent Data Latch

with Asynchronous Clear
and Preset, Gate Enable,
and Inverted Gate

Primitive

Primitive

Primitive

Primitive

No

No

No

LDE

Transparent Data Latch

with Gate Enable

Primitive

Primitive

Primitive

Primitive

No

No

No

LDE_1

Transparent Data Latch

with Gate Enable and
Inverted Gate

Primitive

Primitive

Primitive

Primitive

No

No

No

LDG

Transparent Datagate Latch No

No

No

No

No

No

Primitive

LDG4

Multiple Transparent
Datagate Latch

No

No

No

No

No

No

Macro

LDG8

Multiple Transparent
Datagate Latch

No

No

No

No

No

No

Macro

LDG16

Multiple Transparent
Datagate Latch

No

No

No

No

No

No

Macro

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1-800-255-7778

Libraries Guide
ISE 6.3i

Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

LDP

Transparent Data Latch

with Asynchronous Preset

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

LDP_1

Transparent Data Latch

with Asynchronous Preset
and Inverted Gate

Primitive

Primitive

Primitive

Primitive

No

No

No

LDPE

Transparent Data Latch

with Asynchronous Preset
and Gate Enable

Primitive

Primitive

Primitive

Primitive

No

No

No

LDPE_1

Transparent Data Latch

with Asynchronous Preset,
Gate Enable, and Inverted
Gate

Primitive

Primitive

Primitive

Primitive

No

No

No

Libraries Guide
ISE 6.3i

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1-800-255-7778

89

Functional Categories

Logic Primitives
Combinatorial logic gates that implement the basic Boolean functions are available in
all architectures with up to five inputs in all combinations of inverted and noninverted inputs, and with six to nine inputs non-inverted.
Design
Element

90

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

AND2

2-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

AND2B1

2-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND2B2

2-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND3

3-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

AND3B1

3-Input AND Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

AND3B2

3-Input AND Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

AND3B3

3-Input AND Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

AND4

4-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

AND4B1

4-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND4B2

4-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND4B3

4-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND4B4

4-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND5

5-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

AND5B1

5-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND5B2

5-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND5B3

5-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND5B4

5-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND5B5

5-Input AND Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

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1-800-255-7778

Libraries Guide
ISE 6.3i

Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

AND6

6-Input AND Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Primitive

Primitive

Primitive

AND7

7-Input AND Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Primitive

Primitive

Primitive

AND8

8-Input AND Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Primitive

Primitive

Primitive

AND9

9-Input AND Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Primitive

Primitive

Primitive

AND12

12- Input AND Gate with

Non-Inverted Inputs

Macro

Macro

Macro

Macro

No

No

No

AND16

16- Input AND Gate with

Non-Inverted Inputs

Macro

Macro

Macro

Macro

No

No

No

INV

Single and Multiple Inverters Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

INV4

Single and Multiple Inverters Macro

Macro

Macro

Macro

Macro

Macro

Macro

INV8

Single and Multiple Inverters Macro

Macro

Macro

Macro

Macro

Macro

Macro

INV16

Single and Multiple Inverters Macro

Macro

Macro

Macro

Macro

Macro

Macro

MULT_AND

Fast Multiplier AND

Primitive

Primitive

Primitive

Primitive

No

No

No

NAND2

2-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

NAND2B1

2-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND2B2

2-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND3

3-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

NAND3B1

3-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND3B2

3-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND3B3

3-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND4

4-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

NAND4B1

4-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND4B2

4-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND4B3

4-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND4B4

4-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND5

5-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

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ISE 6.3i

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91

Design
Element

92

Functional Categories

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

NAND5B1

5-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND5B2

5-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND5B3

5-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND5B4

5-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND5B5

5-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND6

6-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NAND7

7-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NAND8

8-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NAND9

9-Input NAND Gate with

Inverted and Non-Inverted
Inputs.

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NAND12

12- Input NAND Gate with

Non-Inverted Inputs.

Macro

Macro

Macro

Macro

No

No

No

NAND16

16- Input NAND Gate with

Non-Inverted Inputs.

Macro

Macro

Macro

Macro

No

No

No

NOR2

2- Input NOR Gate with

Inverted and Non-Inverted
Inputs.

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

NOR2B1

2- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR2B2

2- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR3

3- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

NOR3B1

3- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR3B2

3- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR3B3

3- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR4

4- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

NOR4B1

4- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR4B2

4- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

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1-800-255-7778

Libraries Guide
ISE 6.3i

Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

NOR4B3

4- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR4B4

4- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR5

5- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

NOR5B1

5- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR5B2

5- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR5B3

5- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR5B4

5- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR5B5

5- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR6

6- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NOR7

7- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NOR8

8- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NOR9

9- Input NOR Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NOR12

12-Input NOR Gate with

Non-Inverted Inputs

Macro

Macro

Macro

Macro

No

No

No

NOR16

16-Input NOR Gate with

Non-Inverted Inputs

Macro

Macro

Macro

Macro

No

No

No

OR2

2-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR2B1

2-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR2B2

2-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR3

3-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR3B1

3-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR3B2

3-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR3B3

3Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

93

Design
Element

94

Functional Categories

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

OR4

4-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR4B1

4-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR4B2

4-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR4B3

4-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR5B1

5-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

OR5B2

12-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

OR5B3

5-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

OR5B4

5-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

OR5B5

5-Input OR Gate with

Inverted and Non-Inverted
Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

OR6

6-Input OR Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OR7

6-Input OR Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OR8

8-Input OR Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OR9

9-Input OR Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OR12

12-Input OR Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

No

No

No

OR16

16-Input OR Gate with

Inverted and Non-Inverted
Inputs

Macro

Macro

Macro

Macro

No

No

No

ORCY

OR with Carry Logic

No

No

No

Primitive

No

No

No

SOP3

Sum of Products

Macro

Macro

Macro

Macro

No

No

No

SOP3B1A

Sum of Products

Macro

Macro

Macro

Macro

No

No

No

SOP3B1B

Sum of Products

Macro

Macro

Macro

Macro

No

No

No

SOP3B2A

Sum of Products

Macro

Macro

Macro

Macro

No

No

No

SOP3B2B

Sum of Products

Macro

Macro

Macro

Macro

No

No

No

SOP3B3

Sum of Products

Macro

Macro

Macro

Macro

No

No

No

SOP4

Sum of Products

Macro

Macro

Macro

Macro

No

No

No

SOP4B3

Sum of Products

Macro

Macro

Macro

Macro

No

No

No

SOP4B4

Sum of Products

Macro

Macro

Macro

Macro

No

No

No

SOP4B1

Sum of Products

Macro

Macro

Macro

Macro

No

No

No

SOP4B2A

Sum of Products

Macro

Macro

Macro

Macro

No

No

No

SOP4B2B

Sum of Products

Macro

Macro

Macro

Macro

No

No

No

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

XNOR2

2-Input XNOR Gate with

Non-Inverted Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

XNOR3

3-Input XNOR Gate with

Non-Inverted Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

XNOR4

4-Input XNOR Gate with

Non-Inverted Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

XNOR5

5-Input XNOR Gate with

Non-Inverted Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

XNOR6

6-Input XNOR Gate with

Non-Inverted Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

XNOR7

7-Input XNOR Gate with

Non-Inverted Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

XNOR8

8-Input XNOR Gate with

Non-Inverted Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

XNOR9

9-Input XNOR Gate with

Non-Inverted Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

XOR2

2-Input XOR Gate with NonInverted Inputs

Macro

Macro

Macro

Macro

Primitive

Primitive

Primitive

XOR3

3-Input XOR Gate with NonInverted Inputs

Macro

Macro

Macro

Macro

Primitive

Primitive

Primitive

XOR4

4-Input XOR Gate with NonInverted Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

XOR5

5-Input XOR Gate with NonInverted Inputs

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

XOR6

6-Input XOR Gate with NonInverted Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

XOR7

7-Input XOR Gate with NonInverted Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

XOR8

8-Input XOR Gate with NonInverted Inputs

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

XOR9

9-Input XOR Gate with NonInverted Inputs

Macro

Macro

Macro

Macro

Macro

Macro

Macro

XORCY

XOR for Carry Logic with

General Output

Primitive

Primitive

Primitive

Primitive

No

No

No

XORCY_D

XOR for Carry Logic with

Dual Output

Primitive

Primitive

Primitive

Primitive

No

No

No

XORCY_L

XOR for Carry Logic with

Local Output

Primitive

Primitive

Primitive

Primitive

No

No

No

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

95

Functional Categories

Map Elements
Map elements are used in conjunction with logic symbols to constrain the logic to
particular CLBs or particular F function generators.
Design
Element
FMAP

96

Description
F Function Generator
Partitioning Control Symbol

Spartan-II,
IIE
Primitive

Spartan-3
Primitive

Virtex, E
Primitive

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1-800-255-7778

Virtex II,
Pro, Pro X
Primitive

XC9500/XV/
XL
No

CR XPLA3
No

CR-II
No

Libraries Guide
ISE 6.3i

Memory Elements
In the Virtex, Virtex-E, Spartan-II, and Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro,
and Virtex-II Pro X architectures, a number of static RAMs are defined as primitives.
These 16- or 32-word RAMs are 1, 2, 4, and 8 bits wide.
The Virtex, Virtex-E, Spartan-II, and Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro,
and Virtex-II Pro X architectures have dedicated blocks of on-chip 4096-bit single-port
and dual-port synchronous RAM. Each port is configured to a specific data width.
There are five single-port block RAM primitives and 30 dual-port block RAM
primitives.
Design Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

RAM16X1D

16-Deep by 1-Wide Static Dual

Port Synchronous RAM

Primitive

Primitive

Primitive

Primitive

No

No

No

RAM16X1D_1

16-Deep by 1-Wide Static Dual

Port Synchronous RAM with
Negative-Edge Clock

Primitive

Primitive

Primitive

Primitive

No

No

No

RAM16X1S

16-Deep by 1-Wide Static

Synchronous RAM

Primitive

Primitive

Primitive

Primitive

No

No

No

RAM16X1S_1

16-Deep by 1-Wide Static

Synchronous RAM with
Negative-Edge Clock

Primitive

Primitive

Primitive

Primitive

No

No

No

RAM16X2D

16-Deep by 2-Wide Static Dual

Port Synchronous RAM

Macro

No

Macro

Macro

No

No

No

RAM16X2S

16-Deep by 2-Wide Static

Synchronous RAM

Macro

Primitive

Macro

Primitive

No

No

No

RAM16X4D

16-Deep by 4-Wide Static Dual

Port Synchronous RAM

Macro

No

Macro

Macro

No

No

No

RAM16X4S

16-Deep by 4-Wide Static

Synchronous RAM

Macro

Primitive

Macro

Primitive

No

No

No

RAM16X8D

16-Deep by 8-Wide Static Dual

Port Synchronous RAM

Macro

No

Macro

Macro

No

No

No

RAM16X8S

16-Deep by 8-Wide Static

Synchronous RAM

Macro

No

Macro

Primitive

No

No

No

RAM32X1D

32-Deep by 1-Wide Static Dual

Static Port Synchronous RAM

No

No

No

Primitive

No

No

No

RAM32X1D_1

32-Deep by 1-Wide Static Dual

Port Synchronous RAM with
Negative-Edge Clock

No

No

No

Primitive

No

No

No

RAM32X1S

32-Deep by 1-Wide Static

Synchronous RAM

Primitive

Primitive

Primitive

Primitive

No

No

No

RAM32X1S_1

32-Deep by 1-Wide Static

Synchronous RAM with
Negative-Edge Clock

Primitive

Primitive

Primitive

Primitive

No

No

No

RAM32X2S

32-Deep by 2-Wide Static

Synchronous RAM

Macro

Primitive

Macro

Primitive

No

No

No

RAM32X4S

32-Deep by 4-Wide Static

Synchronous RAM

Macro

No

Macro

Primitive

No

No

No

RAM32X8S

32-Deep by 8-Wide Static

Synchronous RAM

Macro

No

Macro

Primitive

No

No

No

RAM64X1D

64-Deep by 1-Wide Dual Port

Static Synchronous RAM

No

No

No

Primitive

No

No

No

RAM64X1D_1

64-Deep by 1-Wide Dual Port

Static Synchronous RAM with
Negative-Edge Clock

No

No

No

Primitive

No

No

No

RAM64X1S

64-Deep by 1-Wide Static

Synchronous RAM

No

Primitive

No

Primitive

No

No

No

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

97

Design Element

98

Functional Categories

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

RAM64X1S_1

64-Deep by 1-Wide Static

Synchronous RAM with
Negative-Edge Clock

No

Primitive

No

Primitive

No

No

No

RAM64X2S

64-Deep by 2-Wide Static

Synchronous RAM

No

No

No

Primitive

No

No

No

RAM128X1S

128-Deep by 1-Wide Static

Synchronous RAM

No

No

No

Primitive

No

No

No

RAM128X1S_1

128-Deep by 1-Wide Static

Synchronous RAM with
Negative-Edge Clock

No

No

No

Primitive

No

No

No

RAMB4_Sm_Sn

4096-Bit Dual-Port
Synchronous Block RAM with
Port Width (m or n)
Configured to 1, 2, 4, 8, or 16
Bits

Primitive

No

Primitive

No

No

No

No

RAMB4_Sn

4096-Bit Single-Port
Synchronous Block RAM with
Port Width (n) Configured to
1, 2, 4, 8, or 16 Bits

Primitive

No

Primitive

No

No

No

No

RAMB16_Sm_Sn

16384-Bit Data Memory and

No
2048-Bit Parity Memory, DualPort Synchronous Block RAM
with Port Width (m or n)
Configured to 1, 2, 4, 9, 18, or
36 Bits

Primitive

No

Primitive

No

No

No

RAMB16_Sn

16384-Bit Data Memory and

2048-Bit Parity Memory,
Single-Port Synchronous
Block RAM with Port Width
(n) Configured to 1, 2, 4, 9, 18,
or 36 Bits

No

Primitive

No

Primitive

No

No

No

ROC

Reset On Configuration

Primitive

Primitive

Primitive

Primitive

No

No

No

ROCBUF

Reset On Configuration Buffer Primitive

Primitive

Primitive

Primitive

No

No

No

ROM16X1

16-Deep by 1-Wide ROM

Primitive

Primitive

Primitive

Primitive

No

No

No

ROM32X1

32-Deep by 1-Wide ROM

Primitive

Primitive

Primitive

Primitive

No

No

No

ROM64X1

64-Deep by 1-Wide ROM

No

Primitive

No

Primitive

No

No

No

ROM128X1

128-Deep by 1-Wide ROM

No

Primitive

No

Primitive

No

No

No

ROM256X1

256-Deep by 1-Wide ROM

No

Primitive

No

Primitive

No

No

No

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Libraries Guide
ISE 6.3i

Multiplexers
The multiplexer naming convention shown in the following figure indicates the
number of inputs and outputs and whether or not an enable is available.

M8_1E
Multiplexer
Number of Inputs
Number of Outputs
Output Enable
X4620

Multiplexer Naming Convention

Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

M2_1

2-to-1 Multiplexer

Macro

Macro

Macro

Macro

Macro

Macro

Macro

M2_1B1

2-to-1 Multiplexer with D0

Inverted

Macro

Macro

Macro

Macro

Macro

Macro

Macro

M2_1B2

2-to-1 Multiplexer with D0 and

D1 Inverted

Macro

Macro

Macro

Macro

Macro

Macro

Macro

M2_1E

2-to-1 Multiplexer with Enable

Macro

Macro

Macro

Macro

Macro

Macro

Macro

M4_1E

4-to-1 Multiplexer with Enable

Macro

Macro

Macro

Macro

Macro

Macro

Macro

M8_1E

8-to-1 Multiplexer with Enable

Macro

Macro

Macro

Macro

Macro

Macro

Macro

M16_1E

16-to-1 Multiplexer with

Enable

Macro

Macro

Macro

Macro

Macro

Macro

Macro

MUXCY

2-to-1 Multiplexer for Carry

Logic with General Output

Primitive

Primitive

Primitive

Primitive

No

No

No

MUXCY_D

2-to-1 Multiplexer for Carry

Logic with Dual Output

Primitive

Primitive

Primitive

Primitive

No

No

No

MUXCY_L

2-to-1 Multiplexer for Carry

Logic with Local Output

Primitive

Primitive

Primitive

Primitive

No

No

No

MUXF5

2-to-1 Lookup Table

Multiplexer with General
Output

Primitive

Primitive

Primitive

Primitive

No

No

No

MUXF5_D

2-to-1 Lookup Table

Multiplexer with Dual Output

Primitive

Primitive

Primitive

Primitive

No

No

No

MUXF5_L

2-to-1 Lookup Table

Multiplexer with Local Output

Primitive

Primitive

Primitive

Primitive

No

No

No

MUXF6

2-to-1 Lookup Table

Multiplexer with General
Output

Primitive

Primitive

Primitive

Primitive

No

No

No

MUXF6_D

2-to-1 Lookup Table

Multiplexer with Dual Output

Primitive

Primitive

Primitive

Primitive

No

No

No

MUXF6_L

2-to-1 Lookup Table

Multiplexer with Local Output

Primitive

Primitive

Primitive

Primitive

No

No

No

MUXF7

2-to-1 Lookup Table

Multiplexer with General
Output

No

Primitive

No

Primitive

No

No

No

MUXF7_D

2-to-1 Lookup Table

Multiplexer with Dual Output

No

Primitive

No

Primitive

No

No

No

MUXF7_L

2-to-1 Lookup Table

Multiplexer with Local Output

No

Primitive

No

Primitive

No

No

No

MUXF8

2-to-1 Lookup Table

Multiplexer with General
Output

No

Primitive

No

Primitive

No

No

No

MUXF8_D

2-to-1 Lookup Table

Multiplexer with Dual Output

No

Primitive

No

Primitive

No

No

No

MUXF8_L

2-to-1 Lookup Table

Multiplexer with Local Output

No

Primitive

No

Primitive

No

No

No

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ISE 6.3i

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99

100

Functional Categories

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Libraries Guide
ISE 6.3i

Shifters
Shifters are barrel shifters (BRLSHFT) of four and eight bits.
Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

BRLSHFT4

4-Bit Barrel Shifter

Macro

Macro

Macro

Macro

Macro

Macro

Macro

BRLSHFT8

8-Bit Barrel Shifter

Macro

Macro

Macro

Macro

Macro

Macro

Macro

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ISE 6.3i

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101

Functional Categories

Shift Registers
Shift registers are available in a variety of sizes and capabilities. The naming
convention shown in the following figure illustrates available features.

SR8RLED
Shift Register
Bit Size
Synchronous Reset (R)
Asynchronous Clear (C)
Loadable
Clock Enable
Directional

X4578

Shift Register Naming Convention

Design
Element

102

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

SR4CE

4-Bit Serial-In Parallel-Out Shift

Register with Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR8CE

8-Bit Serial-In Parallel-Out Shift

Register with Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR16CE

16-Bit Serial-In Parallel-Out Shift

Register with Clock Enable and
Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR4CLE

4-Bit Loadable Serial/Parallel-In

Parallel-Out Shift Register with
Clock Enable and Asynchronous
Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR8CLE

8-Bit Loadable Serial/Parallel-In

Parallel-Out Shift Register with
Clock Enable and Asynchronous
Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR16CLE

16-Bit Loadable Serial/Parallel-In

Parallel-Out Shift Register with
Clock Enable and Asynchronous
Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR4CLED

4-Bit Shift Register with Clock

Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR8CLED

8-Bit Shift Register with Clock

Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR16CLED

16-Bit Shift Register with Clock

Enable and Asynchronous Clear

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR4RE

4-Bit Serial-In Parallel-Out Shift

Register with Clock Enable and
Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR8RE

8-Bit Serial-In Parallel-Out Shift

Register with Clock Enable and
Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR16RE

16-Bit Serial-In Parallel-Out Shift

Register with Clock Enable and
Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR4RLE

4-Bit Loadable Serial/Parallel-In

Parallel-Out Shift Register with
Clock Enable and Synchronous
Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR8RLE

8-Bit Loadable Serial/Parallel-In

Parallel-Out Shift Register with
Clock Enable and Synchronous
Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

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Libraries Guide
ISE 6.3i

Design
Element

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

SR16RLE

16-Bit Loadable Serial/Parallel-In

Parallel-Out Shift Register with
Clock Enable and Synchronous
Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR4RLED

4-Bit Shift Register with Clock

Enable and Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR8RLED

8-Bit Shift Register with Clock

Enable and Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR16RLED

16-Bit Shift Register with Clock

Enable and Synchronous Reset

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SRD4CE

4-Bit Serial-In Parallel-Out Dual

Edge Triggered Shift Register with
Clock Enable and Asynchronous
Clear

No

No

No

No

No

No

Macro

SRD8CE

8-Bit Serial-In Parallel-Out Dual

Edge Triggered Shift Register with
Clock Enable and Asynchronous
Clear

No

No

No

No

No

No

Macro

SRD16CE

16-Bit Serial-In Parallel-Out Dual

Edge Triggered Shift Register with
Clock Enable and Asynchronous
Clear

No

No

No

No

No

No

Macro

SRD4CLE

4-Bit Loadable Serial/Parallel-In

Parallel-Out Dual Edge Triggered
Shift Register with Clock Enable
and Asynchronous Clear

No

No

No

No

No

No

Macro

SRD8CLE

8-Bit Loadable Serial/Parallel-In

Parallel-Out Dual Edge Triggered
Shift Register with Clock Enable
and Asynchronous Clear

No

No

No

No

No

No

Macro

SRD16CLE

16-Bit Loadable Serial/Parallel-In

Parallel-Out Dual Edge Triggered
Shift Register with Clock Enable
and Asynchronous Clear

No

No

No

No

No

No

Macro

SRD4CLED

4-Bit Dual Edge Triggered Shift

Register with Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

SRD8CLED

8-Bit Dual Edge Triggered Shift

Register with Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

SRD16CLED

16-Bit Dual Edge Triggered Shift

Register with Clock Enable and
Asynchronous Clear

No

No

No

No

No

No

Macro

SRD4RE

4-Bit Serial-In Parallel-Out Dual

Edge Triggered Shift Register with
Clock Enable and Synchronous
Reset

No

No

No

No

No

No

Macro

SRD8RE

8-Bit Serial-In Parallel-Out Dual

Edge Triggered Shift Register with
Clock Enable and Synchronous
Reset

No

No

No

No

No

No

Macro

SRD16RE

16-Bit Serial-In Parallel-Out Dual

Edge Triggered Shift Register with
Clock Enable and Synchronous
Reset

No

No

No

No

No

No

Macro

SRD4RLE

4-Bit Loadable Serial/Parallel-In

Parallel-Out Dual Edge Triggered
Shift Register with Clock Enable
and Synchronous Reset

No

No

No

No

No

No

Macro

SRD8RLE

8-Bit Loadable Serial/Parallel-In

Parallel-Out Dual Edge Triggered
Shift Register with Clock Enable
and Synchronous Reset

No

No

No

No

No

No

Macro

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ISE 6.3i

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103

Design
Element

104

Functional Categories

Description

Spartan-II,
IIE

Spartan-3

Virtex, E

Virtex II,
Pro, Pro X

XC9500/XV/
XL

CR XPLA3

CR-II

SRD16RLE

16-Bit Loadable Serial/Parallel-In

Parallel-Out Dual Edge Triggered
Shift Register with Clock Enable
and Synchronous Reset

No

No

No

No

No

No

Macro

SRD4RLED

4-Bit Dual Edge Triggered Shift

Register with Clock Enable and
Synchronous Reset

No

No

No

No

No

No

Macro

SRD8RLED

8-Bit Dual Edge Triggered Shift

Register with Clock Enable and
Synchronous Reset

No

No

No

No

No

No

Macro

SRD16RLED

16-Bit Dual Edge Triggered Shift

Register with Clock Enable and
Synchronous Reset

No

No

No

No

No

No

Macro

SRL16

16-Bit Shift Register Look-UpTable (LUT)

Primitive

Primitive

Primitive

Primitive

No

No

No

SRL16_1

16-Bit Shift Register Look-UpTable (LUT) with Negative-Edge

Clock

Primitive

Primitive

Primitive

Primitive

No

No

No

SRL16E

16-Bit Shift Register Look-UpTable (LUT) with Clock Enable

Primitive

Primitive

Primitive

Primitive

No

No

No

SRL16E_1

16-Bit Shift Register Look-UpTable (LUT) with Negative-Edge

Clock and Clock Enable

Primitive

Primitive

Primitive

Primitive

No

No

No

SRLC16

16-Bit Shift Register Look-UpTable (LUT) with Carry

No

Primitive

No

Primitive

No

No

No

SRLC16_1

16-Bit Shift Register Look-UpTable (LUT) with Carry and

Negative-Edge Clock

No

Primitive

No

Primitive

No

No

No

SRLC16E

16-Bit Shift Register Look-UpTable (LUT) with Carry and Clock

Enable

No

Primitive

No

Primitive

No

No

No

SRLC16E_1

16-Bit Shift Register Look-UpNo

Table (LUT) with Carry, NegativeEdge Clock, and Clock Enable

Primitive

No

Primitive

No

No

No

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Libraries Guide
ISE 6.3i

Design Elements
The remaining sections in this book describe each design element that can be used
with the supported architectures.
Design elements are organized in alphanumeric order, with all numeric suffixes in
ascending order. For example, FDR precedes FDRS, and ADD4 precedes ADD8,
which precedes ADD16.
The following information is provided for each library element, where applicable

Libraries Guide
ISE 6.3i

Graphic symbol

Applicability table (with primitive versus macro identification)

Functional description

Truth table

Schematic for macros

VHDL and Verilog instantiation and inference code

Commonly used constraints

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105

106

Design Elements

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Libraries Guide
ISE 6.3i

ACC1

ACC1
1-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and
Synchronous Reset
Architectures Supported
ACC1
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

CI
B0

ACC1

Q0
CO

D0
L
ADD
CE
C

X3862

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

ACC1 can add or subtract a 1-bit unsigned-binary word to or from the contents of a 1bit data register and store the results in the register. The register can be loaded with a
1-bit word. The synchronous reset (R) has priority over all other inputs and, when
High, causes the output to go to logic level zero during the Low-to-High clock (C)
transition. Clock (C) transitions are ignored when clock enable (CE) is Low. The
accumulator is asynchronously cleared, outputs Low, when power is applied. For
XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition
can be simulated by applying a High-level pulse on the PRLD global net.

Load
When the load input (L) is High, CE is ignored and the data on the input D0 is loaded
into the 1-bit register during the Low-to-High clock (C) transition.

Add
When control inputs ADD and CE are both High, the accumulator adds a 1-bit word
(B0) and carry-in (CI) to the contents of the 1-bit register. The result is stored in the
register and appears on output Q0 during the Low-to-High clock transition. The
carry-out (CO) is not registered synchronously with the data output. CO always
reflects the accumulation of input B0 and the contents of the register, which allows
cascading of ACC1s by connecting CO of one stage to CI of the next stage. In add
mode, CO acts as a carry-out, and CO and CI are active-High.

Subtract
When ADD is Low and CE is High, the 1-bit word B0 and CI are subtracted from the
contents of the register. The result is stored in the register and appears on output Q0
during the Low-to-High clock transition. The carry-out (CO) is not registered
synchronously with the data output. CO always reflects the accumulation of input B0
and the contents of the register, which allows cascading of ACC1s by connecting CO
of one stage to CI of the next stage. In subtract mode, CO acts as a borrow, and CO
and CI are active-Low.

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ISE 6.3i

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107

ACC1

VCC

CE
AND2

CI
ADD
L

OR2
GND

INV
INV

B0

INV
AND6

INV
INV
INV
INV
INV

AND6

OR4

INV
INV
INV

AND6

INV
INV
INV

AND6

D0
FD
D

AND3B1
OR2

XOR2

Q0

Q0

AND3B2

AND3

AND3

CO
AND3B2
OR5

AND3B2

AND2

X7688

ACC1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

108

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Libraries Guide
ISE 6.3i

ACC1

Usage
ACC is schematic and inference only-- not instantiated.

VHDL Inference Code

Following is some "basic" code for inference of the ACC modules.
architecture Behavioral of acc1 is
begin
process(C, R)
begin
if (R = '1') then
Q <= (others => '0');
elsif (C'event and C = '1') then
if (L = '1') then
Q <= D;
elsif (CE = '1') then
if (ADD = '1') then
Q <= Q + B;
else
Q <= Q - B;
end if;
end if;
end if;
end process;
end Behavioral;

Verilog Inference Code

always @ (posedge C)
begin
if (R)
Q <= 0;
else if (L)
Q <= D;
else if (CE)
end
if (ADD)
Q <= Q + B;
else
Q <= Q - B;
end

Libraries Guide
ISE 6.3i

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109

110

ACC1

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Libraries Guide
ISE 6.3i

ACC4, 8, 16

ACC4, 8, 16
4-, 8-, 16-Bit Loadable Cascadable Accumulators with Carry-In, CarryOut, and Synchronous Reset
Architectures Supported
ACC4, ACC8, ACC16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CI

ACC4

B0

Q0
Q1

B1
B2

Q2

B3

Q3

D0

CO

D1

OFL

D2
D3
L
ADD

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

ACC4, ACC8, ACC16 can add or subtract a 4-, 8-, 16-bit unsigned-binary, respectively
or twos-complement word to or from the contents of a 4-, 8-, 16-bit data register and
store the results in the register. The register can be loaded with the 4-, 8-, 16-bit word.
The synchronous reset (R) has priority over all other inputs, and when High, causes
all outputs to go to logic level zero during the Low-to-High clock (C) transition. Clock
(C) transitions are ignored when clock enable (CE) is Low.
The accumulator is asynchronously cleared, outputs Low, when power is applied.

CE
C

CI

X3863

ACC8

Q[7:0]

B[7:0]

CO

D[7:0]

OFL

L
ADD

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

CE

Load

X4374

CI

ACC16

Q[15:0]

B[15:0]

CO

D[15:0]

OFL

When the load input (L) is High, CE is ignored and the data on the D inputs is loaded
into the register during the Low-to-High clock (C) transition. ACC4 loads the data on
inputs D3 D0 into the 4-bit register. ACC8 loads the data on D7 D0 into the 8-bit
register. ACC16 loads the data on inputs D15 D0 into the 16-bit register.

Unsigned Binary Versus Twos Complement

L
ADD
CE
C

X4375

Libraries Guide
ISE 6.3i

ACC4, ACC8, ACC16 can operate, respectively, on either 4-, 8-, 16-bit unsigned binary
numbers or 4-, 8-, 16-bit twos-complement numbers. If the inputs are interpreted as
unsigned binary, the result can be interpreted as unsigned binary. If the inputs are
interpreted as twos complement, the output can be interpreted as twos complement.
The only functional difference between an unsigned binary operation and a twoscomplement operation is how they determine when overflow occurs. Unsigned

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111

ACC4, 8, 16

binary uses CO, while twos complement uses OFL to determine when overflow
occurs.

Unsigned Binary Operation

For unsigned binary operation, ACC4 can represent numbers between 0 and 15,
inclusive; ACC8 between 0 and 255, inclusive; and ACC16 between 0 and 65535,
inclusive. In add mode, CO is active (High) when the sum exceeds the bounds of the
adder/subtracter. In subtract mode, CO is an active-Low borrow-out and goes Low
when the difference exceeds the bounds. The carry-out (CO) is not registered
synchronously with the data outputs. CO always reflects the accumulation of the B
inputs (B3 B0 for ACC4, B7 B0 for ACC8, B15 B0 for ACC16) and the contents of
the register. This allows cascading of ACC4s, ACC8s, or ACC16s by connecting CO of
one stage to CI of the next stage. An unsigned binary overflow that is always activeHigh can be generated by gating the ADD signal and CO as follows.
unsigned overflow = CO XOR ADD

Ignore OFL in unsigned binary operation.

Twos-Complement Operation
For twos-complement operation, ACC4 can represent numbers between -8 and +7,
inclusive; ACC8 between -128 and +127, inclusive; ACC16 between -32768 and
+32767, inclusive. If an addition or subtraction operation result exceeds this range, the
OFL output goes High. The overflow (OFL) is not registered synchronously with the
data outputs. OFL always reflects the accumulation of the B inputs (B3 B0 for ACC4,
B7 B0 for ACC8, B15 B0 for ACC16) and the contents of the register, which allows
cascading of ACC4s, ACC8s, or ACC16s by connecting OFL of one stage to CI of the
next stage.
Ignore CO in twos-complement operation.

112

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Libraries Guide
ISE 6.3i

ACC4, 8, 16

Q[7:0]
CI

ADSU8
CI
A[7:0]

S[7:0]
S[7:0]

B[7:0]
B[7:0]
ADD CO

OFL
OFL
CO

ADD
RLOC=R0C0
M2_1

D[7:0]

S0
D0

D0
D1
S0

FDCE

O SD0

R_SD0
D
Q
CE
C
CLR

SD0
AND2B1

Q0

Q0

RLOC=R3C0.S0
FMAP

FMAP
M2_1

R
S3
D3
L

I4
I3
I2
I1

R_SD3

S1
D1

D0
D1
S0

FDCE

O SD1

R_SD1
D
Q
CE
C
CLR

SD1
AND2B1

Q1

R
S7
D7
L

I4
I3
I2
I1

R_SD7

Q1

RLOC=R2C0.S0

RLOC=R0C0.S0
RLOC=R3C0.S0
M2_1
S2
D2

FMAP
R
S2
D2
L

D0
D1
S0

FDCE
O SD2

R_SD2

D
Q
CE
C
CLR

SD2
AND2B1

I4
I3
I2
I1

RLOC=R2C0.S0
M2_1
S3
D3

D0
D1
S0

I4
I3
I2
I1

R_SD3

D
Q
CE
C CLR

SD3

FMAP
M2_1
R_SD1

S4
D4

D0
D1
S0

R_SD6

RLOC=R0C0.S0

Q3

Q3
FMAP

RLOC=R2C0.S0

FDCE

O SD3

AND2B1

I4
I3
I2
I1

FMAP
R
S6
D6
L

Q2

R_SD2

RLOC=R2C0.S0

R
S1
D1
L

Q2

FDCE

O SD4

R_SD4

D
Q
CE
C
CLR

SD4
AND2B1

RLOC=R3C0.S0

Q4

R
S5
D5
L

I4
I3
I2
I1

R_SD5

RLOC=R1C0.S0

Q4

RLOC=R1C0.S0
M2_1
S5
D5

FMAP
R
S0
D0
L

I4
I3
I2
I1

D0
D1
S0

FDCE
O SD5

R_SD5

D
Q
CE
C
CLR

SD5
AND2B1

R_SD0

RLOC=R3C0.S0

Q5
FMAP
R
S4
D4
L

Q5

RLOC=R1C0.S0
M2_1
S6
D6

D0
D1
S0

R_SD6

D
Q
CE
C
CLR

SD6
AND2B1

R_SD4

RLOC=R1C0.S0

FDCE

O SD6

I4
I3
I2
I1

Q6

Q6

RLOC=R0C0.S0
M2_1
S7
D7

D0
D1
S0

FDCE

O SD7

R_SD7

D
Q
CE
C
CLR

SD7
AND2B1

L
CE
R
C

Q7

Q7

R_L_CE
RLOC=R0C0.S0
OR3

X8689
GND

ACC8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

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113

ACC4, 8, 16

Q [7:0]

ADSU8

CI

CI
A [7:0]

S [7:0]
S [7:0]

B [7:0]

B [7:0]
OFL
CO
ADD

OFL

ADD

CO
RLOC=X1Y0

D [7:0]

M2_1
S0

D0

D0

D1
S0

FDCE
SD0

R_SD0

SD0

Q0

CE

AND2B1

CLR
Q0

RLOC=X0Y0

M2_1
FMAP
R

S1

D0

D1

D1

I4

S3

I3

D3

I2

S0
O

FDCE
SD1

R_SD1

SD1
AND2B1

R_SD3

CLR

I1
D0

D2

D1

FMAP
I4

S2

I3

D2

I2

S0

SD2

R_SD2

SD2

D0
D1
S0

R_SD3

SD3

S1

I3

D1

I2

I1

D0

D4

D1
S0

R_SD4

SD4

I4

S0

I3

D0

I2

I1

Q4

I4

S5

I3

D5

I2

I1

S5

D0

D5

D1
S0

R_SD5

SD5

Q5

CE

AND2B1

I1

D1
S0

S4

I3

D4

I2

R_SD4

I1

CLR
RLOC=X0Y2

Q5

D6

I4

RLOC=X0Y2

M2_1
D0

RLOC=X0Y0
S6

R_SD5

FMAP

FDCE
SD5

CLR

RLOC=X0Y2

M2_1
R_SD0

R_SD6

RLOC=X0Y3

Q4

RLOC=X0Y2

FMAP
R

I2

CE

AND2B1

RLOC=X0Y0

I3

D6

FMAP

FDCE
SD4

S6

CLR

RLOC=X0Y1

M2_1
S4

I4

Q3

Q3
R_SD1

L
Q

I1

CE

AND2B1
I4

CLR

FDCE
SD3

FMAP
R

R_SD7

FMAP

RLOC=X0Y1

M2_1
D3

Q2

Q2
S3

I2

RLOC=X0Y3
Q

R_SD2

I1

I3

D7

CE
C

RLOC=X0Y1

S7

FDCE

AND2B1
O

I4

Q1
S2

FMAP
R

RLOC=X0Y0

M2_1
RLOC=X0Y1

Q1

CE

FDCE
SD6

R_SD6

SD6

Q6

CE

AND2B1

CLR
Q6

RLOC=X0Y3

M2_1
S7

D0

D7

D1
S0

FDCE
SD7

R_SD7

SD7

R_L_CE

CE

Q7

CLR
Q7

R
C

CE

AND2B1

RLOC=X0Y3

OR3

X9301

GND

ACC8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

114

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Libraries Guide
ISE 6.3i

ACC4, 8, 16

OFL_POS_ADD

AND4B2
OFL_NEG_ADD
CI

CI_0
AND4B1

AND2

OFL_OUT
OFL
OR4

R_0

AND4B2
Q3

OR2

OFL_POS_SUB

S3
B3
ADD_1

AND4B3

L_0

OFL_NEG_SUB

OR2
GND
VCC
CE

AND2
CE_1

FD

S0

Q0

ADD

ADD_1
NOR2
AND2

AND3B2

AND2

Q0

FD

S1

AND3

Q1

AND3B2

D0

AND3
AND3B1

OR2

NOR2

Q1

KEEP
X0

AND4B2

OR4

NOR2

AND3

B0

FD

S2

BX0

Q2

XNOR2
AND4

OR3

NOR2

Q2

AND4
AND3B2

D1

AND3B1

KEEP
X1

AND4B2

OR4

NOR2
AND3

B1

FD

S3

AND4
BX1

Q3

XNOR2
OR4

NOR2

Q3
AND5
AND3B2

D2

AND3B1

AND5

KEEP
X2

AND4B2

B2

OR4

NOR2
AND3

BX2

AND4

XNOR2
CO
AND5

OR5

AND3B2

D3

AND6
AND3B1

KEEP
X3

AND4B2

OR4

NOR2

AND6
B3
C

BX3
XNOR2

X7607

ACC4 Implementation XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II

Libraries Guide
ISE 6.3i

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115

ACC4, 8, 16

ACC4X2
CI
B0
B1
B2
B[7:0]

B3
D0
D1
D2
D3

CI
B0

QO

B1
B2
B3

Q1

QO
Q1
Q2
Q3

Q2
Q3
CO

D0

Q3_0

D1
D2
D3
L
ADD
CE
C

C3
Q[7:0]

ACC4
B4
B5
B6
B7
D4
D[7:0]

D5
D6
D7

L
ADD
CE
C

CI
B0

QO

B1
B2
B3

Q1
Q2
Q3
CO

D0
D1
D2

Q4
Q5
Q6
Q7
CO
OFL

Q7_4 OFL

D3
L
ADD
CE
C
R

X7766

ACC8 Implementation XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II

Usage
ACC is schematic and inference only -- not instantiated.

VHDL Inference Code (ACC4)

Following is some "basic" code for inference of the ACC modules.
architecture Behavioral of acc4 is
begin
process(C)
begin
if (R = '1') then
Q <= (others => '0');
elsif (C'event and C = '1') then
if (L = '1') then
Q <= D;
elsif (CE = '1') then
if (ADD = '1') then
Q <= Q + B;
else
Q <= Q - B;
end if;
end if;
end if;

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Libraries Guide
ISE 6.3i

ACC4, 8, 16

end process;
end Behavioral;

Verilog Inference Code

always @ (posedge C)
begin
if (R)
Q <= 0;
else if (L)
Q <= D;
else if (CE)
end
if (ADD)
Q <= Q + B;
else
Q <= Q - B;
end

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ISE 6.3i

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118

ACC4, 8, 16

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Libraries Guide
ISE 6.3i

ADD1

ADD1
1-Bit Full Adder with Carry-In and Carry-Out
Architectures Supported
ADD1
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

CI
A0
S0

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

ADD1 is a cascadable 1-bit full adder with carry-in and carry-out. It adds two 1-bit
words (A and B) and a carry-in (CI), producing a binary sum (S0) output and a carryout (CO).

B0
CO
X4034

Inputs

Libraries Guide
ISE 6.3i

Outputs

A0

B0

CI

S0

CO

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119

ADD1

A0

S0

B0
CI

XOR2
AND2B1
OR2
AND2B1

AND2
CO
AND2

OR3

AND2

X7689

ADD1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element is schematic or inference only -- no instantiation.

VHDL Inference Code

architecture Behavioral of ADD is
signal sum: std_logic_vector(WIDTH downto 0);
signal zeros: std_logic_vector(WIDTH-1 downto 0) := (others => '0');
begin
process (CI, A, B, sum)
begin
sum <= ('0' & A) + ('0' & B) + (zeros & CI);
S <= sum(WIDTH-1 downto 0);
CO <= sum(WIDTH);
end process;
end Behavioral;

Verilog Inference Code

always @ (A or B or CI)
begin
{CO,S} <= A + B + CI;
end

120

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Libraries Guide
ISE 6.3i

ADD4, 8, 16

ADD4, 8, 16
4-, 8-, 16-Bit Cascadable Full Adders with Carry-In, Carry-Out, and
Overflow
Architectures Supported
ADD4, ADD8, ADD16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

CI
A0
A1
A2
A3

ADD4
S0
S1
S2
S3

B0
B1
B2
B3

OFL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

ADD4, ADD8, and ADD16 add two words and a carry-in (CI), producing a sum
output and carry-out (CO) or overflow (OFL). ADD4 adds A3 A0, B3 B0, and CI
producing the sum output S3 S0 and CO (or OFL). ADD8 adds A7 A0, B7 B0, and
CI, producing the sum output S7 S0 and CO (or OFL). ADD16 adds A15 A0, B15
B0 and CI, producing the sum output S15 S0 and CO (or OFL).

Unsigned Binary Versus Twos Complement

CO
X4376

CI
A[7:0]
ADD8

S[7:0]

B[7:0]
OFL
CO
X4377

ADD4, ADD8, ADD16 can operate on either 4-, 8-, 16-bit unsigned binary numbers or
4-, 8-, 16-bit twos-complement numbers, respectively. If the inputs are interpreted as
unsigned binary, the result can be interpreted as unsigned binary. If the inputs are
interpreted as twos complement, the output can be interpreted as twos complement.
The only functional difference between an unsigned binary operation and a twoscomplement operation is how they determine when overflow occurs. Unsigned
binary uses CO, while twos-complement uses OFL to determine when overflow
occurs. To interpret the inputs as unsigned binary, follow the CO output. To interpret
the inputs as twos complement, follow the OFL output.

Unsigned Binary Operation

CI
A[15:0]
ADD16
S[15:0]
B[15:0]
OFL
CO

For unsigned binary operation, ADD4 can represent numbers between 0 and 15,
inclusive; ADD8 between 0 and 255, inclusive; ADD16 between 0 and 65535,
inclusive. CO is active (High) when the sum exceeds the bounds of the adder.
OFL is ignored in unsigned binary operation.

X4378

Twos-Complement Operation
For twos-complement operation, ADD4 can represent numbers between -8 and +7,
inclusive; ADD8 between -128 and +127, inclusive; ADD16 between -32768 and
+32767, inclusive. OFL is active (High) when the sum exceeds the bounds of the
adder. CO is ignored in twos-complement operation.

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ISE 6.3i

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121

ADD4, 8, 16

CO
OFL
XOR2
O

B7
A7

I7
XOR2

RLOC=R0C0.S1

S MUXCY
0
1
CI
DI

FMAP
I4
LI

CI

LO

I6

DI

RLOC=R0C0.S1

I4

CI

LO

I5

DI

RLOC=R1C0.S1

XOR2

I4

B4
A4
O

XOR2

I4

I1

S4
RLOC=R1C0.S1

FMAP

RLOC=R2C0.S1

LO

I3
I2

XORCY

C3

I4

MUXCY_L
0
DI

I5

I1

FMAP

RLOC=R1C0.S1

S MUXCY_L
0
1
CI
DI

I2

RLOC=R1C0.S1

LI

I3

S5

I3

XORCY

CI

B3
A3

I6

FMAP
B5
A5

CI

LO

I1

I4

C4

I4

I3
I2

RLOC=R0C0.S1

1
CI
LI

B4
A4

B6
A6

MUXCY_L
0

XOR2

S6

XORCY

C5

I7

I1

FMAP

1
CI
LI

B5
A5

I2

RLOC=R0C0.S1

MUXCY_D

0
XOR2

B7
A7

XORCY

C6

B6
A6

S7

I3

1
CI

B3
A3
LI

CI

S3

I3

I3

I2
I1

RLOC=R2C0.S1

XORCY

C2

FMAP
LO

B2
A2

I2

0
DI

XOR2

RLOC=R2C0.S1

I4

MUXCY_L

B2
A2

1
CI
LI

CI

I3

I2

I2
I1

RLOC=R2C0.S1

S2

XORCY

C1

FMAP
LO

B1
A1

I1

0
DI

XOR2

I4

RLOC=R3C0.S1

MUXCY_L

B1
A1

1
CI
LI

CI

I3

I1

I2
I1

RLOC=R3C0.S1

S1

XORCY

C0

FMAP
B0
A0

I0
XOR2

A[7:0]

LO
MUXCY_L
0
DI

B0
A0

1
CI

I3

I0

I2
I1

RLOC=R3C0.S1

LI

CI

B[7:0]

I4

RLOC=R3C0.S1

S0

XORCY

S[7:0]
CI

X8687

ADD8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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ISE 6.3i

ADD4, 8, 16

CO

OFL
O

XOR2
RLOC=X0Y3

B7
I7

A7

MUXCY
0
1
DI

XOR2

FMAP

CI
I4
LI
O

C6

B7
A7

XORCY

C6O

I3

S7

CI

I7

I2
I1
RLOC=X0Y3

LO

O
RLOC=X0Y3

B6
I6

A6
XOR2

FMAP

MUXCY_D
0
1
DI

I4

CI

I3

LI
O

S6

CI

B6
A6

I6

I2
I1

XORCY
RLOC=X0Y3

C5
LO
RLOC=X0Y2

B5
I5

A5
XOR2

FMAP

MUXCY_L
0
1
DI

I4

CI

I3
B5

LI
O

S5

CI

A5

XORCY

I5

I2
I1
RLOC=X0Y2

C4
LO

FMAP

RLOC=X0Y2

B4
I4

A4

MUXCY_L
0
1
DI

XOR2

I4
I3

CI
B4

LI
O

S4

A4

CI

I4

I2
I1
RLOC=X0Y2

XORCY
C3
LO

FMAP
RLOC=X0Y1

B3
I3

A3

MUXCY_L
0
1
DI

XOR2

I4
I3

CI

B3
LI
O

S3

A3

I3

I2
I1

CI
RLOC=X0Y1
XORCY
C2

FMAP

LO
RLOC=X0Y1

B2
I2

A2

DI

XOR2

I4

MUXCY_L
0
1

I3
B2

CI

A2

LI
O

S2

CI

I2

I2
I1
RLOC=X0Y1

XORCY
C1

FMAP

LO
I4

RLOC=X0Y0

B1
I1

A1

MUXCY_L
0
1
DI

XOR2

I3
B1

CI

A1
LI
O

I1

I2
I1

S1
RLOC=X0Y0

CI
XORCY
C0

FMAP

LO

I0
A0
A [7:0]

I4

RLOC=X0Y0

B0

XOR2

I3

MUXCY_L
0
1

B0

DI

A0

CI

I0

I2
I1

LI
O
B [7:0]

CI

S0

RLOC=X0Y0

XORCY
S [7:0]
CI

X9302

ADD8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide
ISE 6.3i

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123

ADD4, 8, 16

S3
A3
B3
OFL

AND3B2
OR2

AND3B1

S0
XOR2

S1
AND2

OR2

XOR2

OR3

XOR2

AND2

AND2

S2
AND3

CI

CI_ORO
OR2
AND3
GND

A0
AND2

KEEP
X0
B0

S3

XOR2
AND3
XOR2
OR4

A1
AND4

KEEP
X1
B1

XOR2
AND4

A2
AND2

KEEP
X2
XOR2

AND3

B2

CO
AND4

OR5

A3
KEEP
X3

AND5

XOR2

B3

AND5

X7613

ADD4 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

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ISE 6.3i

ADD4, 8, 16

S3_0
CI

ADD4X2
CI

A[7:0]

B[7:0]

A0
A1
A2
A3
B0
B1
B2
B3

A0
A1
A2
A3
B0
B1
B2
B3

S[7:0]
S0
S1
S2
S3

S0
S1
S2
S3

CO

C3

ADD4
CI

A4
A5
A6
A7
B4
B5
B6
B7

X7771

A0
A1
A2
A3
B0
B1
B2
B3

S4
S5
S6
S7

S0
S1
S2
S3

CO

CO

OFL
CO

S7_4

ADD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element is schematic or inference only -- no instantiation.

VHDL Inference Code (ADD4)

architecture Behavioral of ADD is
signal sum: std_logic_vector(WIDTH-1 downto 0);
signal zeros: std_logic_vector(WIDTH-1 downto 0) := (others => '0');
begin
process (CI, A, B, sum)
begin
sum <= ('0' & A) + ('0' & B) + (zeros & CI);
S <= sum(WIDTH-1 downto 0);
CO <= sum(WIDTH);
end process;
end Behavioral;

Verilog Inference Code (ADD4)

always @ (A or B or CI)
begin
{CO,sum} <= A + B + CI;
end

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ISE 6.3i

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126

ADD4, 8, 16

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Libraries Guide
ISE 6.3i

ADSU1

ADSU1
1-Bit Cascadable Adder/Subtracter with Carry-In and Carry-Out
Architectures Supported
ADSU1
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

CI
A0
S0
B0

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

When the ADD input is High, two 1-bit words (A0 and B0) are added with a carry-in
(CI), producing a 1-bit output (S0) and a carry-out (CO). When the ADD input is Low,
B0 is subtracted from A0, producing a result (S0) and borrow (CO). In add mode, CO
represents a carry-out, and CO and CI are active-High. In subtract mode, CO
represents a borrow, and CO and CI are active-Low.

CO

ADD

X4035

Add Function, ADD=1

Inputs

Outputs

A0

B0

CI

S0

CO

Subtract Function, ADD=0

Inputs

Libraries Guide
ISE 6.3i

Outputs

A0

B0

CI

S0

CO

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127

ADSU1

Subtract Function, ADD=0

Inputs

Outputs

A0

B0

CI

S0

CO

A0
B0
ADD
AND3
CI

AND3

CO
AND3B2
OR5

AND3B2

AND2
SO
XOR2

AND3B3

AND3B1

OR4
AND3B1

AND3B1

X8144

ADSU1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Instantiation Template

-- Component Declaration for ADSU1 should be placed
-- after architecture statement but before begin keyword

128

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ISE 6.3i

ADSU1

component ADSU1
port (CO : out STD_ULOGIC;
S0 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
ADD: in STD_ULOGIC;
B0 : in STD_ULOGIC;
CI : in STD_ULOGIC);
end component;
-- Component Attribute specification for ADSU1
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for ADSU1 should be placed

-- in architecture after the begin keyword
ADSU1_INSTANCE_NAME : ADSU1
-- synthesis translate_off
generic map (CDS_ACTION => "string_value")
-- synthesis translate_on
port map (CO =>user_CO,
S0 => user_SO,
A0 => user_A0,
ADD => user_ADD,
B0 => user_B0,
CI => user_CI);

Verilog Instantiation Template

ADSU1 instance_name (.CO (user_CO),
.S0 (user_SO),
.A0 (user_A0),
.ADD(user_ADD),
.B0 (user_B0),
.CI (user_CI));

Libraries Guide
ISE 6.3i

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129

130

ADSU1

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Libraries Guide
ISE 6.3i

ADSU4, 8, 16

ADSU4, 8, 16
4-, 8-, 16-Bit Cascadable Adders/Subtracters with Carry-In, Carry-Out,
and Overflow
Architectures Supported
ADSU4, ADSU8, ADSU16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

CI
A0
A1

ADSU4

A2

S0

A3

S1
S2
S3

B0
B1
B2
B3

OFL

ADD

CO
X4379

CI
A[7:0]

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

When the ADD input is High, ADSU4, ADSU8, and ADSU16 add two words and a
carry-in (CI), producing a sum output and carry-out (CO) or overflow (OFL). ADSU4
adds two 4-bit words (A3 A0 and B3 B0) and a CI, producing a 4-bit sum output
(S3 S0) and CO or OFL. ADSU8 adds two 8-bit words (A7 A0 and B7 B0) and a CI
producing, an 8-bit sum output (S7 S0) and CO or OFL. ADSU16 adds two 16-bit
words (A15 A0 and B15 B0) and a CI, producing a 16-bit sum output (S15 S0) and
CO or OFL.
When the ADD input is Low, ADSU4, ADSU8, and ADSU16 subtract Bz B0 from
Az A0, producing a difference output and CO or OFL. ADSU4 subtracts B3 B0 from
A3 A0, producing a 4-bit difference (S3 S0) and CO or OFL. ADSU8 subtracts B7
B0 from A7 A0, producing an 8-bit difference (S7 S0) and CO or OFL. ADSU16
subtracts B15 B0 from A15 A0, producing a 16-bit difference (S15 S0) and CO or
OFL.

ADSU8
S[7:0]

B[7:0]

In add mode, CO and CI are active-High. In subtract mode, CO and CI are active-Low.
OFL is active-High in add and subtract modes.

OFL

ADD

CO
X4380

CI
A[15:0]
ADSU16

S[15:0]

B[15:0]
OFL
ADD

CO
X4381

ADSU4, ADSU8, and ADSU16 CI and CO pins do not use the CPLD carry chain.

Unsigned Binary Versus Twos Complement

ADSU4, ADSU8, ADSU16 can operate, respectively, on either 4-, 8-, 16-bit unsigned
binary numbers or 4-, 8-, 16-bit twos-complement numbers. If the inputs are
interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the
inputs are interpreted as twos complement, the output can be interpreted as twos
complement. The only functional difference between an unsigned binary operation
and a twos-complement operation is how they determine when overflow occurs.
Unsigned binary uses CO, while twos complement uses OFL to determine when
overflow occurs.
With adder/subtracters, either unsigned binary or twos-complement operations
cause an overflow. If the result crosses the overflow boundary, an overflow is
generated. Similarly, when the result crosses the carry-out boundary, a carry-out is
generated. The following figure shows the ADSU carry-out and overflow boundaries.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

131

ADSU4, 8, 16

-127

127

128

127

OS

AR

LEM

ED BIN

MPL EMENT O
R

SIGN

MP

CO

UN

ED

-1

255

SI

CO

TW

E N T OR
SIG
NE
D
ED BINAR
N
G
Y
SI

Overflow

TW

Carry-Out
X4720

ADSU Carry-Out and Overflow Boundaries

Unsigned Binary Operation

For unsigned binary operation, ADSU4 can represent numbers between 0 and 15,
inclusive; ADSU8 between 0 and 255, inclusive; ADSU16 between 0 and 65535,
inclusive. In add mode, CO is active (High) when the sum exceeds the bounds of the
adder/subtracter. In subtract mode, CO is an active-Low borrow-out and goes Low
when the difference exceeds the bounds.
An unsigned binary overflow that is always active-High can be generated by gating
the ADD signal and CO as follows.
unsigned overflow = CO XOR ADD

OFL is ignored in unsigned binary operation.

Twos-Complement Operation
For twos-complement operation, ADSU4 can represent numbers between -8 and +7,
inclusive; ADSU8 between -128 and +127, inclusive; ADSU16 between -32768 and
+32767, inclusive. If an addition or subtraction operation result exceeds this range, the
OFL output goes High.
CO is ignored in twos-complement operation.

132

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Libraries Guide
ISE 6.3i

ADSU4, 8, 16

CO
OFL
XOR2
O

SUB7

B7
A7

I7

INV
XOR3

RLOC=R0C0.S1

S MUXCY_L
0
1
DI
CI

FMAP

LI
CI

C6

LO

SUB6

B6
A6

I6

INV

XORCY

C5

LO

SUB5

I5

INV

RLOC=R0C0.S1

XOR3

I4
XOR3

S5

I6

I2
I1

I4
I3

I5

I2
I1

FMAP
ADD
B4
A4

I4
I3

I4

I2
I1

S4
RLOC=R1C0.S1

XORCY

FMAP

MUXCY_L
0
DI

XOR3

I3

RLOC=R1C0.S1

RLOC=R2C0.S1

LO

SUB3

I3

S MUXCY_L
0
1
CI
DI

C3

INV

I4

XORCY

LI
CI

B3
A3

I7

I1

FMAP
ADD
B5
A5

RLOC=R1C0.S1

LO

SUB4

I2

RLOC=R0C0.S1

RLOC=R1C0.S1

C4

INV

S6

1
CI

CI

B4
A4

XORCY

LI

I3

FMAP
ADD
B6
A6

MUXCY_L
0
DI

I4

RLOC=R0C0.S1

1
CI
LI
CI

B5
A5

S7

MUXCY_D

0
DI

XOR3

ADD
B7
A7

ADD
B3
A3

1
CI
LI
CI

S3

I4
I3

I3

I2
I1

RLOC=R2C0.S1

XORCY

C2

FMAP
LO

SUB2

B2
A2

I2

INV

0
DI

XOR3

RLOC=R2C0.S1

MUXCY_L

ADD
B2
A2

1
CI
LI
CI

C1

I4
I3

I2

I2
I1

RLOC=R2C0.S1

S2

XORCY

FMAP
LO

SUB1

B1
A1

I1

INV

0
DI

XOR3

RLOC=R3C0.S1

ADD
B1
A1

MUXCY_L
1
CI
LI
CI

C0

I4
I3

I1

I2
I1

RLOC=R3C0.S1

S1

XORCY

FMAP
SUB0

B0
A0

I0

INV

LO
MUXCY_L
0

XOR3

DI

RLOC=R3C0.S1

ADD
B0
A0

1
CI

I4
I3

I0

I2
I1

RLOC=R3C0.S1
A[7:0]

LI
CI

B[7:0]

S0

XORCY

S[7:0]
ADD
CI

X8686

ADSU8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

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1-800-255-7778

133

ADSU4, 8, 16

CO

OFL
XOR2
O
SUB7
B7

RLOC=X1Y3

INV

I7

A7

MUXCY
0
1
DI

XOR3

FMAP

CI
I4
LI
O

S7

CI

B7

I3

I7

I2

A7

XORCY
C6

ADD

I1

C6O
RLOC=X1Y3

LO

SUB6
B6

RLOC=X1Y3

INV

I6

A6

MUXCY_D
0
1
DI

XOR3

FMAP

CI

I4
ADD

LI
O

S6

CI

B6

I3

I6

I2

A6

I1

XORCY
C5

RLOC=X1Y3

LO
SUB5
B5

RLOC=X1Y2

INV

I5

A5

MUXCY_L
0
1
DI

XOR3

FMAP
I4

CI
ADD
LI
O

S5

CI

B5

I3

I5

I2

A5

I1

XORCY
RLOC=X1Y2

C4

LO
SUB4
B4

RLOC=X1Y2

INV

I4

A4
XOR3

FMAP

MUXCY_L
0
1
DI

I4

CI

ADD
B4

LI
O

S4

CI

I3

I4

I2

A4

I1

XORCY

RLOC=X1Y2

C3

LO
SUB3
B3

FMAP

RLOC=X1Y1

INV

I3

A3

MUXCY_L
0
1
DI

XOR3

I4
ADD

CI

B3
LI
O

S3

I3

I3

I2

A3

I1

CI

RLOC=X1Y1

XORCY
C2

LO

FMAP

SUB2
B2

RLOC=X1Y1

INV

I2

A2

MUXCY_L
0
1
DI

XOR3

I4
ADD

CI

B2
O

I2

I2

A2

LI

I3

I1

S2

CI

RLOC=X1Y1
XORCY

C1

FMAP

LO
SUB1
B1

RLOC=X1Y0

INV

I1

A1

DI

XOR3

I4

MUXCY_L
0
1

ADD
B1

CI

I1

I2

A1

I1

LI
O

I3

S1

RLOC=X1Y0

CI
XORCY
C0

FMAP
LO
SUB0
B0

I4

RLOC=X1Y0

INV

I0

A0
XOR3

ADD

MUXCY_L
0
1
DI

B0

CI

I0

I1

LI
O

I3
I2

A0

A [7:0]

RLOC=X1Y0

S0

CI

B [7:0]

XORCY
ADD

S [7:0]

X9303

CI

ADSU8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

134

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Libraries Guide
ISE 6.3i

ADSU4, 8, 16

CI
A0
B0

ADSU1
CI
A0

S0

S0
B0
ADD CO

S0

ADSU1
A1
B1

CI
A0

S1

S0
B0
ADD CO

S1

ADSU1
A2
B2

CI
A0

S2

S0

OFL_POS_ADD

B0
ADD CO

S2
AND4B2

OFL_NEG_ADD

ADSU1
A3
B3

CI
A0

OFL_OUT

S3

S0

AND4B1

B0
ADD CO

S3

OFL
OR4

CO
AND4B2

OFL_POS_SUB
ADD
AND4B3

OFL_NEG_SUB
X7615

ADSU4 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

S3_0
CI

ADSU4X2
CI

A[7:0]

B[7:0]

A0
A1
A2
A3
B0
B1
B2
B3

A0
A1
A2
A3
B0
B1
B2
B3
CO
ADD

S[7:0]
S0
S1
S2
S3

S0
S1
S2
S3

C3

ADSU4
CI

A4
A5
A6
A7
B4
B5
B6
B7
ADD

A0
A1
A2
A3
B0
B1
B2

S0
S1
S2
S3

OFL
B3
CO
ADD

S4
S5
S6
S7

OFL
CO

S7_4
X7774

ADSU8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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135

136

ADSU4, 8, 16

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Libraries Guide
ISE 6.3i

AND2-9

AND2-9
2- to 9-Input AND Gates with Inverted and Non-Inverted Inputs
Architectures Supported
AND2, AND3, AND4, AND5
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

AND2B1, AND2B2, AND4B1, AND4B2, AND4B3, AND4B4,

AND5B1, AND5B2, AND5B3, AND5B4, AND5B5
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro
AND3B1, AND3B2, AND3B3,

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro
AND6, AND7, AND8, AND9

Libraries Guide
ISE 6.3i

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Macro

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

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137

AND2-9

I1

I0

I2
I1
I0

AND2

I4

I3

I2
I1
I0

AND3

I5

I4

I3
O

I2

I1

I0
AND5

AND6
I6
I5

I4
I1
I0

I2
I1
I0

I3
O

I3

I2
I1
I0

I2

I2
I1

I0

AND4

I3

I4
O

I3

I1

I2

I0

I1
I0

AND2B1

I1
I0

AND3B1

I2
I1
I0

AND4B1

AND7

I4

I3
O

AND5B1

I3

I2
I1
I0

I2

I1

I7

I0

I6
I5

AND2B2

AND3B2

I2
I1
I0

AND4B2

AND3B3

I2
I1

I2

I3

I2
I1
I0

I4
I3

I4

I3
O

AND5B2

I1
I0

I0
AND4B3

AND5B3

AND8

I4

I3

I3

I2
I1
I0

I2
I1

O
I8
I7

I0
AND4B4

AND5B4

I6
I5
I4
I2

I3
I2
I1

I3

I4
O

I1
I0

I0
AND5B5

AND9
X9461

AND Gate Representations

AND functions of up to five inputs are available in any combination of inverting and
non-inverting inputs. AND functions of six to nine inputs are available with only noninverting inputs. To make some or all inputs inverting, use external inverters. Because
each input uses a CLB resource in Spartan-II, Spartan-3, Spartan-IIE, Virtex, Virtex-E,
Virtex-II, Virtex-II Pro, and Virtex-II Pro X replace functions with unused inputs with
functions having the appropriate number of inputs.
See AND12, 16 for information on additional AND functions for Virtex, Virtex-E,
Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3.

138

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Libraries Guide
ISE 6.3i

AND2-9

FMAP
I4
I3
S1
S0
I7
I6

I1
RLOC=R0C0.S0

S1

I5
I4

I2

FMAP

AND4
I7
O
AND2

I6
I5
I4

I3

I4
I3

S1

I2
I1

RLOC=R0C0.S1

I2

S0

I1
I0

FMAP
I3

AND4

I2
I1
I0
X8702

I4
I3

S0

I2
I1

RLOC=R0C0.S1

AND8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I4
I7
I6

S1

S1

S0

I5

I3
I2

I1

I4
RLOC=X0Y1

AND4
O

FMAP
AND2

I7
I6

I3

I5

I2

S0

I4

I1
I0

I4
I3
I2

S1

I1
RLOC=X0Y0

AND4

FMAP
I3
I2
I1
I0

I4
I3
I2

S0

I1
RLOC=X0Y0

X9304

AND8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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ISE 6.3i

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139

AND2-9

Usage
If possible, it is recommended that these design elements be inferred rather than
instantiated.

VHDL Instantiation Template for AND2, AND2B1, or AND2B2

-- Component Declaration for AND2, AND2B1, or AND2B2 should
-- be placed after architecture statement but before begin
-- keyword
component {AND2|AND2B1|AND2B2}
port (O : out STD_ULOGIC;
I1 : in STD_ULOGIC;
I0 : in STD_ULOGIC);
end component;
-- Component Attribute specification for AND2, AND2B1, or
-- AND2B2 should be placed after architecture declaration
-- but before the begin keyword
-- Enter attributes here

-- Component Instantiation for AND2, AND2B1, or AND2B2

-- should be placed in architecture after the begin
-- keyword
INSTANCE_NAME : {AND2|AND2B1|AND2B2}
port map (O => user_O,
I0 => user_I0,
I1 => user_I1);

Verilog Instantiation Template for AND2, AND2B1, or AND2B2

ANDn instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1));

VHDL Instantiation Template for AND3 Through AND3B3

-- Component Declaration for AND3 through AND3B3 should
-- be placed after architecture statement but before begin
-- keyword
component {AND3|AND3B1|AND3B2|AND3B3}
port (O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC);
end component;
-- Component Attribute specification for AND3 through AND3B3
-- should be placed after architecture declaration
-- but before the begin keyword
-- Enter attributes here

140

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Libraries Guide
ISE 6.3i

AND2-9

-- Component Instantiation for AND3 through AND3B3

-- should be placed in architecture after the begin
-- keyword
INSTANCE_NAME : {AND3|AND3B1|AND3B2|AND3B3}
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2);

Verilog Instantiation Template for AND3 Through AND3B3

ANDn instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.I2 (user_I2));

VHDL Instantiation Template for AND4 Through AND4B4

-- Component Declaration for AND4 through AND4B4 should
-- be placed after architecture statement but before begin
-- keyword
component {AND4|AND4B1|AND4B2|AND4B3|AND4B4}
port (O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC;
I3 : in STD_ULOGIC);
end component;
-- Component Attribute specification for AND4 through AND4B4
-- should be placed after architecture declaration
-- but before the begin keyword
-- Enter attributes here
-- Component Instantiation for AND4 through AND4B4
-- should be placed in architecture after the begin
-- keyword
INSTANCE_NAME : AND4_thru_AND4B4
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2,
I3 => user_I3);

Verilog Instantiation Template for AND4 through AND4B4

ANDn instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.I2 (user_I2),
.I3 (user_I3));

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ISE 6.3i

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141

AND2-9

VHDL Instantiation Template for AND5 Through AND5B5

-- Component Declaration for AND5 through AND5B5 should
-- be placed after architecture statement but before begin
-- keyword
component {AND5|AND5B1|AND5B2|AND5B3|AND5B4|AND5B5}
port (O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC;
I3 : in STD_ULOGIC;
I4 : in STD_ULOGIC);
end component;
-- Component Attribute specification for AND5 through AND5B5
-- should be placed after architecture declaration
-- but before the begin keyword
-- Enter attributes here
-- Component Instantiation for AND5 through AND5B5
-- should be placed in architecture after the begin
-- keyword
INSTANCE_NAME : AND5_thru_AND5B5
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2,
I3 => user_I3,
I4 => user_I4);

Verilog Instantiation Template for AND5 through AND5B5

ANDn instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.I2 (user_I2),
.I3 (user_I3),
.I4 (user_I4));

142

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Libraries Guide
ISE 6.3i

AND12, 16

AND12, 16
12- and 16-Input AND Gates with Non-Inverted Inputs
Architectures Supported
AND12, AND16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

AND12 and AND16 functions are performed in the Configurable Logic Block (CLB)
function generator.

I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0

The 12- and 16-input AND functions are available only with non-inverting inputs. To
invert all of some inputs, use external inverters.
See AND2-9 for information on more AND functions.
FMAP

AND12
S2

X9459

S1
S0

I4
I3
I2

I1
RLOC=R0C0.S0

I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0

I11

FMAP

I10

S2

I9
I8

I11
I10
I9
I8

AND4

I7
I6
I5
I4

I7
I6

I3
I2

I5
I4

S0

I1
I0

I2

S2

I1

FMAP

AND3

AND4

I3

RLOC=R0C0.S0

S1

I4

I4
I3
I2

S1

I1
RLOC=R0C0.S1

AND4

AND16
X9460

FMAP
I3
I2
I1
I0
X8705

I4
I3
I2

S0

I1
RLOC=R0C0.S1

AND12 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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143

AND12, 16

FMAP
I11

I4

S2

I10

I3

S1

S2

I9

I2

S0

I1

I8
AND4

RLOC=X0Y1

FMAP
I11
I7

I4

I10

I6

S1

I3

I9

I5
I4

I1

AND3

AND4

S2

I2

I8

RLOC=X0Y1

FMAP
I7

I4

I6

I3

I3

I5

I2

S0

S1

I2

I4

I1

I1

I0

RLOC=X0Y0

AND4

FMAP
I3

I4

I2

I3

I1

S0

I2

I0

I1
RLOC=X0Y0
X9305

AND12 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

O

FMAP
I15

I15

MUXCY

I14

I14
S3

I13

RLOC=R0C0.S1

S
0
DI

I12

I13

1
I12

CI

I4
I3
O

S3

I2
I1

AND4
RLOC=R0C0.S1
C2
FMAP
I11

LO

I11

MUXCY_L

I10

S2

I9

I10
RLOC=R0C0.S1

S
0

DI

I8

I9
I8

CI

I4
I3
O

S2

I2
I1

AND4
RLOC=R0C0.S1
C1
FMAP
I7

LO

I7

MUXCY_L

I6

S1

I5

I6
RLOC=R1C0.S1

S
0

I4

I5

DI

I4

CI

I4
I3
O

S1

I2
I1

AND4
RLOC=R1C0.S1

C0

FMAP
LO

I3

I3

MUXCY_L

I2

S0

I1

RLOC=R1C0.S1

S
0
DI

I0

I2
I1

1
CI

AND4

I0

I4
I3
O

S0

I2
I1
RLOC=R1C0.S1

CIN
GND
VCC

X8708

AND16 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

144

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ISE 6.3i

AND12, 16

FMAP
I15

I14

S3

I13

I12

MUXCY
0
1
DI
CI

RLOC=X0Y1

I15

I4

I14

I3

I13

I2

I12

I1

S3

AND4
RLOC=X0Y1

C2

I11

FMAP

LO

I10

S MUXCY_L
0
1
DI
CI

S2

I9
I8

RLOC=X0Y1

I11

I4

I10

I3

I9

I2

I8

AND4
C1

I7
S1

I5

I4

S2

I1
RLOC=X0Y1

FMAP

LO

I6

MUXCY_L
0
1
DI
CI

RLOC=X0Y0

AND4

I7

I4

I6

I3

I5

I2

I4

S1

I1

C0
RLOC=X0Y0
I3

LO

I2

S0

I1

I0

MUXCY_L
0
1
DI
CI

FMAP

RLOC=X0Y0

AND4

I3

I4

I2

I3

I1

I2

I0

S0

I1

CIN
RLOC=X0Y0

GND
VCC

X9306

AND16 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, it is recommended that these design elements be inferred rather than
instantiated.

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146

AND12, 16

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Libraries Guide
ISE 6.3i

BRLSHFT4, 8

BRLSHFT4, 8
4-, 8-Bit Barrel Shifters
Architectures Supported
BRLSHFT4, BRLSHFT8
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

I0
I1

BRLSHFT4

O0
O1

I2

O2

I3

O3

S0
S1

X3856

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

BRLSHFT4, a 4-bit barrel shifter, can rotate four inputs (I3 I0) up to four places. The
control inputs (S1 and S0) determine the number of positions, from one to four, that
the data is rotated. The four outputs (O3 O0) reflect the shifted data inputs.
BRLSHFT8, an 8-bit barrel shifter, can rotate the eight inputs (I7 I0) up to eight
places. The control inputs (S2 S0) determine the number of positions, from one to
eight, that the data is rotated. The eight outputs (O7 O0) reflect the shifted data
inputs.
BRLSHFT4 Truth Table

I0
I1

Inputs

BRLSHFT8 O0
O1

I2

O2

I3

O3

I4
I5

O4

I6

O6

I7

O7

O5

Outputs

S1

S0

I0

I1

I2

I3

O0

O1

O2

O3

S0
S1
S2

BRLSHFT8 Truth Table

X3857

Inputs
S2 S1 S0

Libraries Guide
ISE 6.3i

I0

I1

I2

Outputs
I3

I4

I5

I6

I7

O0 O1 O2 O3 O4 O5 O6 O7

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147

I0

BRLSHFT4, 8

D0
D1
S0

I1

D0
D1
S0

I2

D0
D1
S0

I3

D0
D1
S0

I4

I5

D0
D1

D0
D1
S0

I7

D0
D1

S0

M01

D0
S0

M2_1
O

M12

D0
S0

M2_1
M23

D0
S0

M2_1
M34

M34

D0
D1
S0

S0

M45

M45

D0
D1
S0

M2_1
O

M56

M56

D0
D1
S0

M2_1
O

M67

M67

D0
D1
S0

M2_1
O

M70

M70

S1

D0
D1
S0

MO0

D0

S0

MO1

D0
S0

M2_1
MO2

D0
S0

M2_1
MO3

MO3

D0
D1
S0

M2_1
O

MO4

MO4

D0
D1
S0

M2_1
O

MO5

MO5

D0
D1
S0

M2_1
O

MO6

MO6

D0
D1
S0

M2_1
O

MO7

MO7

D0
D1
S0

O0

M2_1
O

O1

O1

M2_1
O

D1

MO2

O
O0

D1

MO1

M2_1

D1

M2_1

D1

M23

O
MO0

D1

M12

M2_1

D1

M01

M2_1
D0
D1
S0

S0

I6

M2_1

O2

O2

M2_1
O

O3

O3

M2_1
O

O4

O4

M2_1
O

O5

O5

M2_1
O

O6

O6

M2_1
O

O7

O7

S2

X8143

BRLSHFT8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II,

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro,
Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

148

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Libraries Guide
ISE 6.3i

BSCAN_SPARTAN2

BSCAN_SPARTAN2
Spartan-II Boundary Scan Logic Control Circuit
Architectures Supported
BSCAN_SPARTAN2
Spartan-II, Spartan-IIE

Primitive*

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

* Supported for Spartan-II, but not for SpartanIIE, which is supported by BSCAN_VIRTEX.

BSCAN_SPARTAN2
UPDATE
SHIFT
RESET
TDI
SEL1

The BSCAN_SPARTAN2 symbol creates internal boundary scan chains in a Spartan-II

device. The 4-pin JTAG interface (TDI, TDO, TCK, and TMS) are dedicated pins in
Spartan-II. To use normal JTAG for boundary scan purposes, just hook up the JTAG
pins to the port and go. The pins on the BSCAN_SPARTAN2 symbol do not need to be
connected, unless those special functions are needed to drive an internal scan chain.

DRCK1
SEL2

TDO1
TDO2

DRCK2

X8894

A signal on the TDO1 input is passed to the external TDO output when the USER1
instruction is executed; the SEL1 output goes High to indicate that the USER1
instruction is active.The DRCK1 output provides USER1 access to the data register
clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar
function for the USER2 instruction and the DRCK2 output provides USER2 access to
the data register clock (generated by the TAP controller). The RESET, UPDATE, and
SHIFT pins represent the decoding of the corresponding state of the boundary scan
internal state machine. The TDI pin provides access to the TDI signal of the JTAG port
in order to shift data into an internal scan chain.
Note: For specific information on boundary scan for an architecture, see The Programmable
Logic Data Sheets.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- Component Declaration for BSCAN_SPARTAN2 should be placed
-- after architecture statement but before begin keyword
-- <Cut code below this line and paste into the architecture body>
-- BSCAN_SPARTAN2: Boundary Scan primitve for connecting internal
-logic to. JTAG interface. Spartan-II
-- Xilinx HDL Libraries Guide version 7.1i

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149

BSCAN_SPARTAN2

BSCAN_SPARTAN2_inst : BSCAN_SPARTAN2
port map (
DRCK1 => DRCK1,
-- Data register output for USER1 functions
DRCK2 => DRCK2,
-- Data register output for USER2 functions
RESET => RESET,
-- Reset output from TAP controller
SEL1 => SEL1,
-- USER1 active output
SEL2 => SEL2,
-- USER2 active output
SHIFT => SHIFT,
-- SHIFT output from TAP controller
TDI => TDI,
-- TDI output from TAP controller
UPDATE => UPDATE,
-- UPDATE output from TAP controller
TDO1 => TDO1,
-- Data input for USER1 function
TDO2 => TDO2
-- Data input for USER2 function
);

Verilog Instantiation Template

// BSCAN_SPARTAN2:Boundary Scan primitve for connecting internal logic
//
JTAG interface. Spartan-II
// Xilinx HDL Libraries Guide version 7.1i
BSCAN_SPARTAN2 BSCAN_SPARTAN2_inst (
.DRCK1(DRCK1),
// Data register output - USER1 functions
.DRCK2(DRCK2),
// Data register output - USER2 functions
.RESET(RESET),
// Reset output from TAP controller
.SEL1(SEL1),
// USER1 active output
.SEL2(SEL2),
// USER2 active output
.SHIFT(SHIFT),
// SHIFT output from TAP controller
.TDI(TDI),
// TDI output from TAP controller
.UPDATE(UPDATE),
// UPDATE output from TAP controller
.TDO1(TDO1),
// Data input for USER1 function
.TDO2(TDO2)
// Data input for USER2 function
);

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ISE 6.3i

BSCAN_SPARTAN3

BSCAN_SPARTAN3
Spartan-3 Boundary Scan Logic Control Circuit
Architectures Supported
BSCAN_SPARTAN3
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

BSCAN_SPARTAN3
UPDATE
SHIFT
RESET
TDI
SEL1

No

CoolRunner XPLA3

No

CoolRunner-II

No

BSCAN_SPARTAN3 provides access to the BSCAN sites on a Spartan-3 device. It is

used to create internal boundary scan chains. The 4-pin JTAG interface (TDI, TDO,
TCK, and TMS) are dedicated pins in Spartan-3. To use normal JTAG for boundary
scan purposes, just hook up the JTAG pins to the port and go. The pins on the
BSCAN_SPARTAN3 symbol do not need to be connected, unless those special
functions are needed to drive an internal scan chain.

DRCK1
TDO1

SEL2

TDO2

DRCK2
CAPTURE

X10183

A signal on the TDO1 input is passed to the external TDO output when the USER1
instruction is executed; the SEL1 output goes High to indicate that the USER1
instruction is active.The DRCK1 output provides USER1 access to the data register
clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar
function for the USER2 instruction and the DRCK2 output provides USER2 access to
the data register clock (generated by the TAP controller). The RESET, UPDATE,
SHIFT, and CAPTURE pins represent the decoding of the corresponding state of the
boundary scan internal state machine. The TDI pin provides access to the TDI signal
of the JTAG port in order to shift data into an internal scan chain.

Usage
This design element is instantiated rather than inferred.

VHDL Instantiation Template

-- Component Declaration for BSCAN_SPARTAN3 should be placed
-- after architecture statement but before begin keyword
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TD01 : in STD_ULOGIC;

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BSCAN_SPARTAN3

TD02 : in STD_ULOGIC);
end component;
-- Component Attribute specification for BSCAN_SPARTAN3
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for BSCAN_SPARTAN3 should be

-- placed in architecture after the begin keyword
BSCAN_SPARTAN3_INSTANCE_NAME : BSCAN_SPARTAN3
port map (CAPTURE => user_CAPTURE,
DRCK1 => user_DRCK1,
DRCK2 => user_DRCK2,
RESET => user_RESET,
SEL1 => user_SEL1,
SEL2 => user_SEL2,
SHIFT => user_SHIFT,
TDI => user_TDI,
UPDATE => user_UPDATE,
TD01 => user_TD01,
TD02 => user_TD02);

Verilog Instantiation Template

// BSCAN_SPARTAN3:Boundary Scan primitve for connecting internal logic
//
JTAG interface. Spartan-II
// Xilinx HDL Libraries Guide version 7.1i
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst (
.CAPTURE(CAPTURE), // CAPTURE output from TAP controller
.DRCK1(DRCK1),
// Data register output - USER1 functions
.DRCK2(DRCK2),
// Data register output - USER2 functions
.RESET(RESET),
// Reset output from TAP controller
.SEL1(SEL1),
// USER1 active output
.SEL2(SEL2),
// USER2 active output
.SHIFT(SHIFT),
// SHIFT output from TAP controller
.TDI(TDI),
// TDI output from TAP controller
.UPDATE(UPDATE),
// UPDATE output from TAP controller
.TDO1(TDO1),
// Data input for USER1 function
.TDO2(TDO2)
// Data input for USER2 function
);

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Libraries Guide
ISE 6.3i

BSCAN_VIRTEX

BSCAN_VIRTEX
Virtex Boundary Scan Logic Control Circuit
Architectures Supported
BSCAN_VIRTEX
Spartan-II, Spartan-IIE

Primitive*

Spartan-3

No

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

* Supported for Spartan-IIE, but not for Spartan-II,

which is supported by BSCAN_SPARTAN2.

BSCAN_VIRTEX
UPDATE
SHIFT
RESET
TDI
SEL1
DRCK1
TDO1
TDO2

SEL2
DRCK2

X8679

The BSCAN_VIRTEX symbol is used to create internal boundary scan chains in a

Virtex or Virtex- E device. The 4-pin JTAG interface (TDI, TDO, TCK, and TMS) are
dedicated pins in Virtex and Virtex-E. To use normal JTAG for boundary scan
purposes, just hook up the JTAG pins to the port and go. The pins on the
BSCAN_VIRTEX symbol do not need to be connected, unless those special functions
are needed to drive an internal scan chain.
Note: For Virtex-II, Virtex-II Pro, and Virtex-II Pro X, see BSCAN_VIRTEX2.
A signal on the TDO1 input is passed to the external TDO output when the USER1
instruction is executed; the SEL1 output goes High to indicate that the USER1
instruction is active.The DRCK1 output provides USER1 access to the data register
clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar
function for the USER2 instruction and the DRCK2 output provides USER2 access to
the data register clock (generated by the TAP controller). The RESET, UPDATE, and
SHIFT pins represent the decoding of the corresponding state of the boundary scan
internal state machine. The TDI pin provides access to the TDI signal of the JTAG port
in order to shift data into an internal scan chain.
Note: For specific information on boundary scan for an architecture, see The Programmable
Logic Data Sheets.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- BSCAN_VIRTEX: Boundary Scan primitve for connecting internal logic
to
-JTAG interface. Virtex/E, Spartan-IIE
-- Xilinx HDL Libraries Guide version 7.1i
BSCAN_VIRTEX_inst : BSCAN_VIRTEX

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BSCAN_VIRTEX

port map (
DRCK1 => DRCK1,
DRCK2 => DRCK2,
RESET => RESET,
SEL1 => SEL1,
SEL2 => SEL2,
SHIFT => SHIFT,
TDI => TDI,
UPDATE => UPDATE,
TDO1 => TDO1,
TDO2 => TDO2
);

-----------

Data register output for USER1 functions

Data register output for USER2 functions
Reset output from TAP controller
USER1 active output
USER2 active output
SHIFT output from TAP controller
TDI output from TAP controller
UPDATE output from TAP controller
Data input for USER1 function
Data input for USER2 function

Verilog Instantiation Template

// BSCAN_VIRTEX: Boundary Scan primitve for connecting internal logic
//
JTAG interface. Virtex/E, Spartan-IIE
// Xilinx HDL Libraries Guide version 7.1i
BSCAN_VIRTEX BSCAN_VIRTEX_inst (
.DRCK1(DRCK1),
// Data register output for USER1 functions
.DRCK2(DRCK2),
// Data register output for USER2 functions
.RESET(RESET),
// Reset output from TAP controller
.SEL1(SEL1),
// USER1 active output
.SEL2(SEL2),
// USER2 active output
.SHIFT(SHIFT),
// SHIFT output from TAP controller
.TDI(TDI),
// TDI output from TAP controller
.UPDATE(UPDATE),
// UPDATE output from TAP controller
.TDO1(TDO1),
// Data input for USER1 function
.TDO2(TDO2)
// Data input for USER2 function
);

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ISE 6.3i

BSCAN_VIRTEX2

BSCAN_VIRTEX2
Virtex-II Boundary Scan Logic Control Circuit
Architectures Supported
BSCAN_VIRTEX2
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

BSCAN_VIRTEX2
UPDATE
SHIFT
RESET
TDI
SEL1
DRCK1
TD01

SEL2

TD02

DRCK2
CAPTURE

X9402

No

CoolRunner XPLA3

No

CoolRunner-II

No

BSCAN_VIRTEX2 provides access to the BSCAN sites on a Virtex-II, Virtex-II Pro, or

Virtex-II Pro X device. It is used to create internal boundary scan chains. The 4-pin
JTAG interface (TDI, TDO, TCK, and TMS) are dedicated pins in Virtex-II, Virtex-II
Pro, and Virtex-II Pro X. To use normal JTAG for boundary scan purposes, just hook
up the JTAG pins to the port and go. The pins on the BSCAN_VIRTEX2 symbol do not
need to be connected, unless those special functions are needed to drive an internal
scan chain.
Note: For Virtex and Virtex-E, see BSCAN_VIRTEX.
A signal on the TDO1 input is passed to the external TDO output when the USER1
instruction is executed; the SEL1 output goes High to indicate that the USER1
instruction is active.The DRCK1 output provides USER1 access to the data register
clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar
function for the USER2 instruction and the DRCK2 output provides USER2 access to
the data register clock (generated by the TAP controller). The RESET, UPDATE,
SHIFT, and CAPTURE pins represent the decoding of the corresponding state of the
boundary scan internal state machine. The TDI pin provides access to the TDI signal
of the JTAG port in order to shift data into an internal scan chain.
Note: For specific information on boundary scan for an architecture, see The Programmable
Logic Data Sheets.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- BSCAN_VIRTEX2: Boundary Scan primitve for connecting internal
-logic to. JTAG interface. Virtex-II/II-Pro
-- Xilinx HDL Libraries Guide version 7.1i
BSCAN_VIRTEX2_inst : BSCAN_VIRTEX2
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK1 => DRCK1,
-- Data register output for USER1 functions

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BSCAN_VIRTEX2

DRCK2 => DRCK2,

RESET => RESET,
SEL1 => SEL1,
SEL2 => SEL2,
SHIFT => SHIFT,
TDI => TDI,
UPDATE => UPDATE,
TDO1 => TDO1,
TDO2 => TDO2

----------

Data register output for USER2 functions

Reset output from TAP controller
USER1 active output
USER2 active output
SHIFT output from TAP controller
TDI output from TAP controller
UPDATE output from TAP controller
Data input for USER1 function
Data input for USER2 function

);

Verilog Instantiation Template

// BSCAN_VIRTEX2: Boundary Scan primitve for connecting internal logic
//
JTAG interface. Virtex-II/II-Pro
// Xilinx HDL Libraries Guide version 7.1i
BSCAN_VIRTEX2 BSCAN_VIRTEX2_inst (
.CAPTURE(CAPTURE), // CAPTURE output from TAP controller
.DRCK1(DRCK1),
// Data register output - USER1 functions
.DRCK2(DRCK2),
// Data register output - USER2 functions
.RESET(RESET),
// Reset output from TAP controller
.SEL1(SEL1),
// USER1 active output
.SEL2(SEL2),
// USER2 active output
.SHIFT(SHIFT),
// SHIFT output from TAP controller
.TDI(TDI),
// TDI output from TAP controller
.UPDATE(UPDATE),
// UPDATE output from TAP controller
.TDO1(TDO1),
// Data input for USER1 function
.TDO2(TDO2)
// Data input for USER2 function
);

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BUF

BUF
General-Purpose Buffer
Architectures Supported
BUF
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

BUF is a general purpose, non-inverting buffer.

O
X9444

In Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and

Virtex-II Pro X, BUF is usually not necessary and is removed by the partitioning
software (MAP).
In XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, BUF is usually removed,
unless you inhibit optimization by applying the OPT=OFF attribute to the BUF
symbol.

Usage
This design is supported in schematics and instantiation but not for inference.

VHDL Instantiation Template

-- Component Declaration for BUF should be placed
-- after architecture statement but before begin keyword
component BUF
port (O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for BUF
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for BUF should be placed

-- in architecture after the begin keyword
BUF_INSTANCE_NAME : BUF
port map (O => user_O,
I => user_I);

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BUF

Verilog Instantiation Template

BUF instance_name (.O (user_O),
.I (user_I));

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BUF4, 8, 16

BUF4, 8, 16
General-Purpose Buffers
Architectures Supported
BUF4, BUF8, BUF16
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

BUF4

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

BUF4, 8, 16 are general purpose, non-inverting buffers.

In XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, BUF4, BUF8, and BUF16
are usually removed, unless you inhibit optimization by applying the OPT=OFF
attribute to the BUF4, BUF8, or BUF16 symbol or by using the LOGIC_OPT=OFF
global attribute.
O [7:0]
X4614
I0

O1

I1

BUF
1

O1

I2

BUF
2

O2

I3

BUF
3

O3

I4

BUF
4

O4

I5

BUF
5

O5

I6

BUF
6

O6

I7

BUF
7

O7

BUF8

X4615

BUF16

X4616

I[7:0]

BUF
X 7776

BUF8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
These design elements are schematic only.

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160

BUF4, 8, 16

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ISE 6.3i

BUFCF

BUFCF
Fast Connect Buffer
Architectures Supported
BUFCF
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

O
X9444

No

CoolRunner XPLA3

No

CoolRunner-II

No

BUFCF is a single fast connect buffer used to connect the outputs of the LUTs and
some dedicated logic directly to the input of another LUT. Using this buffer implies
CLB packing. No more than four LUTs may be connected together as a group.

Usage
This design element is supported for schematics and instantiation but not for
inferrence.

VHDL Instantiation Template

-- Component Declaration for BUFCF should be placed
-- after architecture statement but before begin keyword
component BUFCF
port (O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for BUFCF
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here
-- Component Instantiation for BUFCF should be placed
-- in architecture after the begin keyword
BUFCF_INSTANCE_NAME : BUFCF
port map (O => user_O,
I => user_I);

Verilog Instantiation Template

BUFCF instance_name (.O (user_O),
.I (user_I));

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162

BUFCF

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BUFE, 4, 8, 16

BUFE, 4, 8, 16
Internal 3-State Buffers with Active High Enable
Architectures Supported
BUFE
Spartan-II, Spartan-IIE

Primitive

Spartan-3

No

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

No

CoolRunner-II

No

BUFE4, BUFE8, BUFE16

Spartan-II, Spartan-IIE

Macro

Spartan-3

No

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

Macro*

CoolRunner XPLA3

No

CoolRunner-II

No

*Not supported for XC9500XL and XC9500XV

devices

BUFE
E

X3790

BUFE4
E

BUFE, BUFE4, BUFE8, and BUFE16 are single or multiple 3-state buffers with inputs I,
I3 I0, I7 I0, and I15 I0, respectively; outputs O, O3 O0, O7 O0, and O15 O0,
respectively; and active-High output enable (E). When E is High, data on the inputs of
the buffers is transferred to the corresponding outputs. When E is Low, the output is
high impedance (Z state or Off). The outputs of the buffers are connected to horizontal
longlines in FPGA architectures.
The outputs of separate BUFE symbols can be tied together to form a bus or a
multiplexer. Make sure that only one E is High at any one time. If none of the E inputs
is active-High, a weak-keeper circuit (Spartan-II, Spartan-IIE, Virtex, Virtex-E,
Virtex-II, Virtex-II Pro, and Virtex-II Pro X) keeps the output bus from floating but
does not guarantee that the bus remains at the last value driven onto it.

X3797

For XC9500 devices, BUFE output nets assume the High logic level when all
connected BUFE/BUFT buffers are disabled.

BUFE16
BUFE8

For Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro
X, BUFE elements need a PULLUP element connected to their output. NGDBuild
inserts a PULLUP element if one is not connected.

EE

X3809

X3821

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BUFE, 4, 8, 16

Inputs

Outputs

O[7:0]
E
O0

I0
E

BUFE

BUFE

BUFE

BUFE

BUFE

BUFE

BUFE

O1

I1

O2

I2

O3

I3

O4

I4

O5

I5

O6

I6

O7

I7
BUFE
I[7:0]

X8119

BUFE8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II,

Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
These design elements are supported for schematic, inference, and instantiation.

VHDL Instantiation Template

-- Component Declaration for BUFE should be placed
-- after architecture statement but before begin keyword
component BUFE
port (O : out STD_ULOGIC;
E : in STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for BUFE
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for BUFE should be placed

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BUFE, 4, 8, 16

-- in architecture after the begin keyword

BUFE_INSTANCE_NAME :
port map (O =>
E =>
I =>

BUFE
user_O,
user_E,
user_I);

Verilog Instantiation Template

BUFE instance_name (.O (user_O),
.E (user_E),
.I (user_I));

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166

BUFE, 4, 8, 16

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ISE 6.3i

BUFG

BUFG
Global Clock Buffer
Architectures Supported
BUFG
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

O
X9428

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

BUFG, an architecture-independent global buffer, distributes high fan-out clock

signals throughout a PLD device. The Xilinx implementation software converts each
BUFG to an appropriate type of global buffer for the target PLD device. To use a
specific type of buffer, instantiate it manually.
To use a BUFG in a schematic, connect the input of the BUFG symbol to the clock
source. Depending on the target PLD family, the clock source can be an external PAD
symbol, an IBUF symbol, or internal logic. For a negative-edge clock input, insert an
INV (inverter) symbol between the BUFG output and the clock input. The inversion is
implemented at the Configurable Logic Block (CLB) or Input Output Block (IOB)
clock pin.

XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II

Consult the device data sheet for the number of available global pins. For these
architectures BUFG is always implemented using an IOB. Connect the input of BUFG
to an IPAD or an IOPAD that represents an external signal source. Each BUFG can
drive any number of register clocks in a design. The output of a BUFG may also be
used as an ordinary input signal to other logic elsewhere in the design.

Virtex, Virtex-E, Spartan-II, Spartan-IIE

In Virtex, Virtex-E, Spartan-II, and Spartan-IIE, the BUFG cannot be driven directly
from a pad. It can be driven from an IBUFG to indicate to use the dedicated pin
(GCLKIOB pin) or from an internal driver to create an internal clock. BUFG can also
be driven with an IBUF to represent an externally driven clock that does not use the
dedicated pin.

Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, clock buffers are multiplexed
clock buffers. In Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, a BUFG is
implemented using a BUFGMUX with the S_B input tied high, basically meaning the
S input is tied low. I1 is unused. I0 is used.

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167

BUFG

Usage
This design element is supported for schematic and instantiation. Synthesis tools
usually infer a BUFGP on any clock net. If there are more clock nets than BUFGPs, the
synthesis tool usually instantiates BUFGPs for the clocks that are most utilized. The
BUFGP contains both a BUFG and an IBUFG.

VHDL Instantiation Template

-- Component Declaration for BUFG should be placed
-- after architecture statement but before begin keyword
component BUFG
port (O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for BUFG
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for BUFG should be placed

-- in architecture after the begin keyword
BUFG_INSTANCE_NAME : BUFG
port map (O => user_O,
I => user_I);

Verilog Instantiation Template

BUFG instance_name (.O (user_O),
.I (user_I));

Commonly Used Constraints

LOC

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BUFGCE

BUFGCE
Global Clock MUX Buffer with Clock Enable and Output State 0
Architectures Supported
BUFGCE
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

CE
I

No

CoolRunner XPLA3

No

CoolRunner-II

No

BUFGCE is a global clock buffer with a single gated input. Its O output is "0" when
clock enable (CE) is Low (inactive). When clock enable (CE) is High, the I input is
transferred to the O output.
Inputs

BUFGCE
X9384

Outputs

CE

I
BUFGMUX

I0

CE

XGND

I1

CE_IN

INV
X9307

GND

BUFGCE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This design element is supported for schematics and instantiations but not for
inference.

VHDL Instantiation Template

-- Component Declaration for BUFGCE should be placed
-- after architecture statement but before begin keyword
component BUFGCE
port (O : out STD_ULOGIC;
CE : in STD_ULOGIC;
I : in STD_ULOGIC);
end component;

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BUFGCE

-- Component Attribute specification for BUFGCE

-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for BUFGCE should be placed

-- in architecture after the begin keyword
BUFGCE_INSTANCE_NAME : BUFGCE
port map (O => user_O,
CE => user_CE,
I => user_I);

Verilog Instantiation Template

BUFGCE instance_name (.O (user_O),
.CE (user_CE),
.I (user_I));

Commonly Used Constraints

LOC

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BUFGCE_1

BUFGCE_1
Global Clock MUX Buffer with Clock Enable and Output State 1
Architectures Supported
BUFGCE_1
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

CE
I

No

CoolRunner XPLA3

No

CoolRunner-II

No

BUFGCE_1 is a multiplexed global clock buffer with a single gated input. Its O output
is High (1) when clock enable (CE) is Low (inactive). When clock enable (CE) is High,
the I input is transferred to the O output.

BUFGCE_1

Inputs

Outputs

X9385

CE

I
BUFGMUX_1

I0

CE

XVCC

I1

CE_IN

INV
X9308

VCC

BUFGCE_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This design element is supported for schematics and instantiations but not for
inference.

VHDL Instantiation Template

-- Component Declaration for BUFGCE_1 should be placed
-- after architecture statement but before begin keyword
component BUFGCE_1
port (O : out STD_ULOGIC;
CE : in STD_ULOGIC;
I: in STD_ULOGIC);
end component;
-- Component Attribute specification for BUFGCE_1

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BUFGCE_1

-- should be placed after architecture declaration but

-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for BUFGCE_1 should be placed

-- in architecture after the begin keyword
BUFGCE_1_INSTANCE_NAME : BUFGCE_1
port map (O => user_O,
CE => user_CE,
I => user_I);

Verilog Instantiation Template

BUGCE_1 instance_name (.O (user_O),
.CE (user_CE),
.I (user_I));

Commonly Used Constraints

LOC

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BUFGDLL

BUFGDLL
Clock Delay Locked Loop Buffer
Architectures Supported
BUFGDLL
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL
CoolRunner XPLA3

No

CoolRunner-II

No

BUFGDLL is a special purpose clock delay locked loop buffer for clock skew
management. It is provided as a user convenience for the most frequently used
configuration of elements for clock skew management. Internally, it consists of an
IBUFG driving the CLKIN pin of a CLKDLL followed by a BUFG that is driven by the
CLK0 pin of the CLKDLL. Because BUFGDLL already contains an input buffer
(IBUFG), it can only be driven by a top-level port (IPAD).

BUFGDLL

No

X10092

Any DUTY_CYCLE_CORRECTION attribute on a BUFGDLL applies to the

underlying CLKDLL symbol.

Usage
This design element is supported for schematics and instantiations but not for
inference.

VHDL Instantiation Template

-- Component Declaration for BUFGDLL should be placed
-- after architecture statement but before begin keyword
component BUFGDLL
port (O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for BUFGDLL
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

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BUFGDLL

-- Component Instantiation for BUFGDLL should be placed

-- in architecture after the begin keyword
BUFGDLL_INSTANCE_NAME : BUFGDLL
port map (O => user_O,
I => user_I);

Verilog Instantiation Template

BUFGDLL instance_name (.O (user_O),
.I (user_I));

Commonly Used Constraints

STARTUP_WAIT

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BUFGMUX

BUFGMUX
Global Clock MUX Buffer with Output State 0
Architectures Supported
BUFGMUX
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

BUFGMUX
I0

I1
S

X9251

No

CoolRunner XPLA3

No

CoolRunner-II

No

BUFGMUX is a multiplexed global clock buffer that can select between two input
clocks I0 and I1. When the select input (S) is Low, the signal on I0 is selected for
output (O). When the select input (S) is High, the signal on I1 is selected for output.
BUFGMUX and BUFGMUX_1 are distinguished by which state the output assumes
when it switches between clocks in response to a change in its select input.
BUGFMUX assumes output state 0 and BUFGMUX_1 assumes output state 1.
Using a BUFGMUX element in your design may cause inaccurate simulation if all the
following conditions occur: both clock inputs (I0 and I1) are used, GSR is activated
during simulation (after simulation time `0'), and the secondary clock input (I1) is
selected before or while GSR is active. In this case, the primary clock input (I0) is
incorrectly selected. This occurs because there is a cross-coupled register pair that
ensures the BUFGMUX output does not inadvertently generate a clock edge. When
GSR is asserted, these registers initialize to the default state of I0. To select the
secondary clock, you must send a clock pulse to both the primary and secondary
clock inputs while GSR is inactive.
Note: BUFGMUX guarantees that when S is toggled, the state of the output will remain in the
inactive state until the next active clock edge (either I0 or I1) occurs.
Inputs

Outputs

I0

I1

I0

I0

I1

I1

Usage
This design element is supported for schematics and instantiations but not for
inference.

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175

BUFGMUX

VHDL Instantiation Template

-- Component Declaration for BUFGMUX should be placed
-- after architecture statement but before begin keyword
component BUFGMUX
port (O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for BUFGMUX
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for BUFGMUX should be placed

-- in architecture after the begin keyword
BUFGMUX_INSTANCE_NAME : BUFGMUX
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
S => user_S);

Verilog Instantiation Template

BUFGMUX instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

Commonly Used Constraints

LOC

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BUFGMUX_1

BUFGMUX_1
Global Clock MUX Buffer with Output State 1
Architectures Supported
BUFGMUX_1
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

BUFGMUX_1 is a multiplexed global clock buffer that can select between two input
clocks I0 and I1. When the select input (S) is Low, the signal on I0 is selected for
output (O). When the select input (S) is High, the signal on I1 is selected for output.

X9252

BUFGMUX and BUFGMUX_1 are distinguished by which state the output assumes
when it switches between clocks in response to a change in its select input.
BUFGMUX assumes output state 0 and BUFGMUX_1 assumes output state 1.

BUFGMUX_1
I0
I1
S

Using a BUFGMUX_1 element in your design may cause inaccurate simulation if all
the following conditions occur: both clock inputs (I0 and I1) are used, GSR is activated
during simulation (after simulation time `0'), and the secondary clock input (I1) is
selected before or while GSR is active. In this case, the primary clock input (I0) is
incorrectly selected. This occurs because there is a cross-coupled register pair that
ensures the BUFGMUX_1 output does not inadvertently generate a clock edge. When
GSR is asserted, these registers initialize to the default state of I0. To select the
secondary clock, you must send a clock pulse to both the primary and secondary
clock inputs while GSR is inactive.
Inputs

Outputs

I0

I1

I0

I0

I1

I1

Usage
This design element is supported for schematics and instantiations but not for
inference.

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BUFGMUX_1

VHDL Instantiation Template

-- Component Declaration for BUFGMUX_1 should be placed
-- after architecture statement but before begin keyword
component BUFGMUX_1
port (O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for BUFGMUX_1
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for BUFGMUX should be placed

-- in architecture after the begin keyword
BUFGMUX_1_INSTANCE_NAME : BUFGMUX_1
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
S => user_S);

Verilog Instantiation Template

BUFGMUX_1 instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

Commonly Used Constraints

LOC

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BUFGP

BUFGP
Primary Global Buffer for Driving Clocks or Longlines (Four per PLD
Device)
BUFGP
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

BUFGP, a primary global buffer, is used to distribute high fan-out clock or control
signals throughout PLD devices.
In Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, BUFGP is equivalent to an IBUFG driving a BUFG.

X3902

In XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, BUFGP is treated like

BUFG.
A BUFGP provides direct access to Configurable Logic Block (CLB) and Input Output
Block (IOB) clock pins and limited access to other CLB inputs. The input to a BUFGP
comes only from a dedicated IOB.
Because of its structure, a BUFGP can always access a clock pin directly. However, it
can access only one of the F3, G1, C3, or C1 pins, depending on the corner in which
the BUFGP is placed. When the required pin cannot be accessed directly from the
vertical line, PAR feeds the signal through another CLB and uses general purpose
routing to access the load pin.
To use a BUFGP in a schematic, connect the input of the BUFGP element directly to
the PAD symbol. Do not use any IBUFs, because the signal comes directly from a
dedicated IOB. The output of the BUFGP is then used throughout the schematic. For a
negative-edge clock, insert an INV (inverter) element between the output of the
BUFGP and the clock input. This inversion is performed inside each CLB or IOB.
A Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, or
Spartan-3 BUFGP must be sourced by an external signal.

Usage
This design element is supported for schematic and instantiation. Synthesis tools
usually infer a BUFGP on any clock net. If there are more clock nets than BUFGPs, the
synthesis tool usually instantiates BUFGPs for the clocks that are most utilized.

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BUFGP

VHDL Instantiation Template

-- Component Declaration for BUFGP should be placed
-- after architecture statement but before begin keyword
component BUFGP
port (O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for BUFGP
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for BUFGP should be placed

-- in architecture after the begin keyword
BUFGP_INSTANCE_NAME : BUFGP
port map (O => user_O,
I => user_I);

Verilog Instantiation Template

BUFGP instance_name (.O (user_O),
.I (user_I));

Commonly Used Constraints

HBLKNM

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ISE 6.3i

BUFGSR

BUFGSR
Global Set/Reset Input Buffer
Architectures Supported
BUFGSR
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

O
X9428

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

BUFGSR distributes global set/reset signals throughout selected flip-flops of an

XC9500/XV/XL, CoolRunner XPLA3, or CoolRunner-II device. Global Set/Reset
(GSR) control pins are available on these CPLD devices. Consult device data sheets for
availability.
BUFGSR always acts as an input buffer. To use it in a schematic, connect the input of
the BUFGSR symbol to an IPAD or an IOPAD representing the GSR signal source.
GSR signals generated on-chip must be passed through an OBUF-type buffer before
they are connected to BUFGSR.
For global set/reset control, the output of BUFGSR normally connects to the CLR or
PRE input of a flip-flop symbol, like FDCP, or any registered symbol with
asynchronous clear or preset. The global set/reset control signal may pass through an
inverter to perform an active-low set/reset. The output of BUFGSR may also be used
as an ordinary input signal to other logic elsewhere in the design. Each BUFGSR can
control any number of flip-flops in a design.

Usage
This design element is supported for schematics and instantiations but not for
inference.

VHDL Instantiation Template

-- Component Declaration for BUFGSR should be placed
-- after architecture statement but before begin keyword
component BUFGSR
port (O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for BUFGSR
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

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BUFGSR

-- Component Instantiation for BUFGSR should be placed

-- in architecture after the begin keyword
BUFGSR_INSTANCE_NAME : BUFGSR
port map (O => user_O,
I => user_I);

Verilog Instantiation Template

BUFGSR instance_name (.O (user_O),
.I (user_I));

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BUFGTS

BUFGTS
Global 3-State Input Buffer
Architectures Supported
BUFGTS
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

O
X9428

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

BUFGTS distributes global output-enable signals throughout the output pad drivers
of an XC9500/XV/XL, CoolRunner XPLA3, or CoolRunner-II device. Global ThreeState (GTS) control pins are available on these CPLD devices. Consult device data
sheets for availability.
BUFGTS always acts as an input buffer. To use it in a schematic, connect the input of
the BUFGTS symbol to an IPAD or an IOPAD representing the GTS signal source. GTS
signals generated on-chip must be passed through an OBUF-type buffer before they
are connected to BUFGTS.
For global 3-state control, the output of BUFGTS normally connects to the E input of a
3-state output buffer symbol, OBUFE. The global 3-state control signal may pass
through an inverter or control an OBUFT symbol to perform an active-low outputenable. The same 3-state control signal may even be used both inverted and noninverted to enable alternate groups of device outputs. The output of BUFGTS may
also be used as an ordinary input signal to other logic elsewhere in the design. Each
BUFGTS can control any number of output buffers in a design.

Usage
This design element is supported for schematics and instantiations but not for
inference.

VHDL Instantiation Template

-- Component Declaration for BUFGTS should be placed
-- after architecture statement but before begin keyword
component BUFGTS
port (O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for BUFGTS
-- should be placed after architecture declaration but
-- before the begin keyword

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BUFGTS

-- Enter attributes here

-- Component Instantiation for BUFGTS should be placed
-- in architecture after the begin keyword
BUFGTS_INSTANCE_NAME : BUFGTS
port map (O => user_O,
I => user_I);

Verilog Instantiation Template

BUFGTS instance_name (.O (user_O),
.I (user_I));

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BUFT, 4, 8, 16

BUFT, 4, 8, 16
Internal 3-State Buffers with Active-Low Enable
Architectures Supported
BUFT
Spartan-II, Spartan-IIE

Primitive

Spartan-3

No

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive*

CoolRunner XPLA3

No

CoolRunner-II

No

BUFT4, BUFT8, BUFT16

Spartan-II, Spartan-IIE

Macro

Spartan-3

No

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

Macro*

CoolRunner XPLA3

No

CoolRunner-II

No

*Not supported for XC9500XL and XC9500XV

devices.

BUFT
T

X3789

BUFT4
T

BUFT, BUFT4, BUFT8, and BUFT16 are single or multiple 3-state buffers with inputs I,
I3 I0, I7 I0, and I15 10, respectively; outputs O, O3 O0, O7 O0, and O15 O0,
respectively; and active-Low output enable (T). When T is Low, data on the inputs of
the buffers is transferred to the corresponding outputs. When T is High, the output is
high impedance (Z state or off). The outputs of the buffers are connected to horizontal
longlines in FPGA architectures.
The outputs of separate BUFT symbols can be tied together to form a bus or a
multiplexer. Make sure that only one T is Low at one time.
For XC9500 devices, BUFT output nets assume the High logic level when all
connected BUFE/BUFT buffers are disabled.

X3796

For Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro
X, when all BUFTs on a net are disabled, the net is High. For correct simulation of this
effect, a PULLUP element must be connected to the net. NGDBuild inserts a PULLUP
element if one is not connected so that back-annotation simulation reflects the true
state of the device.

BUFT8
T

X3808

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BUFT, 4, 8, 16

BUFT16
T

X3820

Inputs

Outputs

O[7:0]
T
O0

I0
T

BUFT

BUFT

BUFT

BUFT

BUFT

BUFT

BUFT

O1

I1

O2

I2

O3

I3

O4

I4

O5

I5

O6

I6

O7

I7
BUFT
I[7:0]

X8118

BUFT8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II,

Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
These design elements are supported for schematics, instantiations, or inferences.

VHDL Instantiation Template

-- Component Declaration for BUFT should be placed
-- after architecture statement but before begin keyword
component BUFT
port (O : out STD_ULOGIC;
I : in STD_ULOGIC;
T : in STD_ULOGIC);
end component;
-- Component Attribute specification for BUFT
-- should be placed after architecture declaration but
-- before the begin keyword

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BUFT, 4, 8, 16

-- Enter attributes here

-- Component Instantiation for BUFT should be placed

-- in architecture after the begin keyword
BUFT_INSTANCE_NAME :
port map (O =>
I =>
T =>

BUFT
user_O,
user_I,
user_T);

Verilog Instantiation Template

BUFT instance_name (.O (user_O),
.I (user_I),
.T (user_T));

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, LOC, U_SET

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188

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Libraries Guide
ISE 6.3i

CAPTURE_SPARTAN2

CAPTURE_SPARTAN2
Spartan-II Register State Capture for Bitstream Readback
Architectures Supported
CAPTURE_SPARTAN2
Spartan-II, Spartan-IIE

Primitive

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

CAPTURE_SPARTAN2
CAP

CLK

X8895

No

CoolRunner XPLA3

No

CoolRunner-II

No

CAPTURE_SPARTAN2 provides user control over when to capture register (flip-flop

and latch) information for readback. Spartan-II and Spartan-IIE devices provide the
readback function through dedicated configuration port instructions. The
CAPTURE_SPARTAN2 symbol is optional. Without it readback is still performed, but
the asynchronous capture function it provides for register states is not available.
Note: Spartan-II and Spartan-IIE devices only allow for capturing register (flip-flop and latch)
states. Although LUT RAM, SRL, and block RAM states are read back, they cannot be
captured.

An asserted High CAP signal indicates that the registers in the device are to be
captured at the next Low-to-High clock transition. By default, data is captured after
every trigger (transition on CLK while CAP is asserted). To limit the readback
operation to a single data capture, add the ONESHOT attribute to
CAPTURE_SPARTAN2. See the Constraints Guide for information on the ONESHOT
attribute.
Note: For details on the Spartan-II and Spartan-IIE readback functions, see The
Programmable Logic Data Sheets.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- CAPTURE_SPARTAN2: Register State Capture for Bitstream Readback
-Spartan-II/IIE
-- Xilinx HDL Libraries Guide version 7.1i
CAPTURE_SPARTAN2_inst : CAPTURE_SPARTAN2
port map (
CAP => CAP,
-- Capture input
CLK => CLK
-- Clock input
);

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CAPTURE_SPARTAN2

Verilog Instantiation Template

// CAPTURE_SPARTAN2: Register State Capture for Bitstream Readback
//
Spartan-II/IIE
// Xilinx HDL Libraries Guide version 7.1i
CAPTURE_SPARTAN2 CAPTURE_SPARTAN2_inst (
.CAP(CAP),
// Capture input
.CLK(CLK)
// Clock input
);

Commonly Used Constraints

ONESHOT

190

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ISE 6.3i

CAPTURE_SPARTAN3

CAPTURE_SPARTAN3
Spartan-3 Register State Capture for Bitstream Readback
Architectures Supported
CAPTURE_SPARTAN3
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

CAPTURE_SPARTAN3
CAP

No

CoolRunner XPLA3

No

CoolRunner-II

No

CAPTURE_SPARTAN3 provides user control over when to capture register (flip-flop

and latch) information for readback. Spartan-3 devices provide the readback function
through dedicated configuration port instructions.
The CAPTURE_SPARTAN3 symbol is optional. Without it readback is still performed,
but the asynchronous capture function it provides for register states is not available.

CLK

X9931

Spartan-3 allows for capturing register (flip-flop and latch) states only. Although LUT
RAM, SRL, and block RAM states are read back, they cannot be captured. An asserted
high CAP signal indicates that the registers in the device are to be captured at the next
Low-to-High clock transition.
By default, data is captured after every trigger (transition on CLK while CAP is
asserted). To limit the readback operation to a single data capture, add the ONESHOT
attribute to CAPTURE_SPARTAN3. See the Constraints Guide for information on the
ONESHOT attribute.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- CAPTURE_SPARTAN3: Register State Capture for Bitstream Readback
-Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
CAPTURE_SPARTAN3_inst : CAPTURE_SPARTAN3
port map (
CAP => CAP,
-- Capture input
CLK => CLK
-- Clock input
);

Verilog Instantiation Template

// CAPTURE_SPARTAN3: Register State Capture for Bitstream Readback
//
Spartan-3

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CAPTURE_SPARTAN3

// Xilinx HDL Libraries Guide version 7.1i

CAPTURE_SPARTAN3 CAPTURE_SPARTAN3_inst (
.CAP(CAP),
// Capture input
.CLK(CLK)
// Clock input
);

Commonly Used Constraints

ONESHOT

192

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Libraries Guide
ISE 6.3i

CAPTURE_VIRTEX

CAPTURE_VIRTEX
Virtex Register State Capture for Bitstream Readback
Architectures Supported
CAPTURE_VIRTEX
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

CAPTURE_VIRTEX
CAP

No

CoolRunner XPLA3

No

CoolRunner-II

No

CAPTURE_VIRTEX provides user control over when to capture register (flip-flop and
latch) information for readback. Virtex and Virtex-E devices provide the readback
function through dedicated configuration port instructions.
The CAPTURE_VIRTEX symbol is optional. Without it readback is still performed,
but the asynchronous capture function it provides for register states is not available.

CLK

X8681

Note: Virtex and Virtex-E allow for capturing register (flip-flop and latch) states only. Although
LUT RAM, SRL, and block RAM states are read back, they cannot be captured.
An asserted High CAP signal indicates that the registers in the device are to be
captured at the next Low-to-High clock transition. By default, data is captured after
every trigger (transition on CLK while CAP is asserted). To limit the readback
operation to a single data capture, add the ONESHOT attribute to
CAPTURE_VIRTEX. See the Constraints Guide for information on the ONESHOT
attribute.
For details on the Virtex and Virtex-E readback functions, see the Virtex datasheets on
the Xilinx web site, http://support.xilinx.com.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- CAPTURE_VIRTEX: Register State Capture for Bitstream Readback
-Virtex/E
-- Xilinx HDL Libraries Guide version 7.1i
CAPTURE_VIRTEX_inst : CAPTURE_VIRTEX
port map (
CAP => CAP,
-- Capture input
CLK => CLK
-- Clock input
);

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CAPTURE_VIRTEX

Verilog Instantiation Template

// CAPTURE_VIRTEX: Register State Capture for Bitstream Readback
//
Virtex/E
// Xilinx HDL Libraries Guide version 7.1i
CAPTURE_VIRTEX CAPTURE_VIRTEX_inst (
.CAP(CAP),
// Capture input
.CLK(CLK)
// Clock input
);

Commonly Used Constraints

ONESHOT

194

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ISE 6.3i

CAPTURE_VIRTEX2

CAPTURE_VIRTEX2
Virtex-II Register State Capture for Bitstream Readback
Architectures Supported
CAPTURE_VIRTEX2
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

CAPTURE_VIRTEX2
CAP

CLK

X9397

No

CoolRunner XPLA3

No

CoolRunner-II

No

CAPTURE_VIRTEX2 provides user control over when to capture register (flip-flop

and latch) information for readback. Virtex-II, Virtex-II Pro, and Virtex-II Pro X
devices provide the readback function through dedicated configuration port
instructions.
The CAPTURE_VIRTEX2 symbol is optional. Without it readback is still performed,
but the asynchronous capture function it provides for register states is not available.
Virtex-II, Virtex-II Pro, and Virtex-II Pro X allow for capturing register (flip-flop and
latch) states only. Although LUT RAM, SRL, and block RAM states are read back, they
cannot be captured.
An asserted high CAP signal indicates that the registers in the device are to be
captured at the next Low-to-High clock transition. By default, data is captured after
every trigger (transition on CLK while CAP is asserted). To limit the readback
operation to a single data capture, add the ONESHOT attribute to
CAPTURE_VIRTEX2. See the Constraints Guide for information on the ONESHOT
attribute.
The GRDBK (internal capture signal) is asserted at the rising edge of the Capture
clock when the Capture signal is high. The capture memory cell is continuously
updated if the value of the FF is continuously changing. The final value of the capture
memory cell occurs at the rising edge of the Capture clock when the Capture signal is
low.
For details on the Virtex-II, Virtex-II Pro, and Virtex-II Pro X readback functions, see
The Programmable Logic Data Sheets.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- CAPTURE_VIRTEX2: Register State Capture for Bitstream Readback
-Virtex-II/II-Pro
-- Xilinx HDL Libraries Guide version 7.1i

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CAPTURE_VIRTEX2

CAPTURE_VIRTEX2_inst : CAPTURE_VIRTEX2
port map (
CAP => CAP,
-- Capture input
CLK => CLK
-- Clock input
);

Verilog Instantiation Template

// CAPTURE_VIRTEX2: Register State Capture for Bitstream Readback
//
Virtex-II/II-Pro
// Xilinx HDL Libraries Guide version 7.1i
CAPTURE_VIRTEX2 CAPTURE_VIRTEX2_inst (
.CAP(CAP),
// Capture input
.CLK(CLK)
// Clock input
);

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Libraries Guide
ISE 6.3i

CB2CE, CB4CE, CB8CE, CB16CE

CB2CE, CB4CE, CB8CE, CB16CE

2-, 4-, 8-,16-Bit Cascadable Binary Counters with Clock Enable and
Asynchronous Clear
Architectures Supported
CB2CE, CB4CE, CB8CE, CB16CE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

CB2CE

Q0
Q1

CE

CEO

TC

CLR

X4353

CB4CE

Q0
Q1
Q2
Q3

CE

CEO

TC

CLR
X4357

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CB2CE, CB4CE, CB8CE, and CB16CE are, respectively, 2-, 4-, 8-, and 16-bit (stage),
asynchronous, clearable, cascadable binary counters. The asynchronous clear (CLR) is
the highest priority input. When CLR is High, all other inputs are ignored; the Q
outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero,
independent of clock transitions. The Q outputs increment when the clock enable
input (CE) is High during the Low-to-High clock (C) transition. The counter ignores
clock transitions when CE is Low. The TC output is High when all Q outputs are
High.
Larger counters are created by connecting the CEO output of the first stage to the CE
input of the next stage and connecting the C and CLR inputs in parallel. CEO is active
(High) when TC and CE are High. The maximum length of the counter is determined
by the accumulated CE-to-TC propagation delays versus the clock period. The clock
period must be greater than n(tCE-TC), where n is the number of stages and the time
tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use
the CEO output if the counter uses the CE input; use the TC output if it does not.
The counter is asynchronously cleared, outputs Low, when power is applied.

Q[7:0]

CB8CE
CE

CEO

TC

CLR

X4361

CB16CE

Q[15:0]

CE

CEO

TC

CLR

Libraries Guide
ISE 6.3i

X4365

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

CE

No Chg

No Chg

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Qz-Q0

TC

CEO

197

CB2CE, CB4CE, CB8CE, CB16CE

Inputs

Outputs

CLR

CE

Qz-Q0

TC

CEO

Inc

TC

CEO

z= 1 for CB2CE; z = 3 for CB4CE; z = 7 for CB8CE; z = 15 for CB16CE

TC = QzQ(z-1)Q(z-2)...Q0
CEO = TCCE

Q[7:0]

VCC

FTCE
T
CE
C

Q0

CLR

Q0

FTCE
T
CE
C

Q1

T2
CLR

Q1

AND2

FTCE
T
CE
C

Q2

T3
CLR

Q2

AND3

FTCE
T
CE
C

Q3

T4

CLR

Q3
AND4

FTCE
T
CE
C

Q4

T5
CLR

Q4

AND2

FTCE
T
CE
C

Q5

T6
CLR

Q5

AND3

FTCE
T
CE
C

Q6

T7

CLR

Q6
AND4

FTCE
CE
C

T
CE
C

CLR

Q7

CLR

TC
Q7
AND5

CEO
X8136
AND2

CB8CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

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ISE 6.3i

CB2CE, CB4CE, CB8CE, CB16CE

VCC

CE
Q0

AND2

Q1

FDC
D

Q
CEO

XOR2

C
CLR

AND3

Q0

TC
AND2

FDC
D
AND2

XOR2
C

CLR
Q1

CLR

X7779

CB2CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

CB2CE
Q0

Q0
CE
C

Q1

Q1
CE
C

CEO
TC
CLR
CB0

CLR

CB2CE
Q2

Q0

Q3

Q1
CE
C

CEO
TC
CLR
CB2

CB2CE
Q4

Q0

Q5

Q1
CE
C

CEO
TC
CLR
CB4

CB2CE
Q6

Q0

Q7

Q1
CE
C

CEO

CEO
TC
CLR
CB6

TC

AND4

X7783

CB8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

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CB2CE, CB4CE, CB8CE, CB16CE

Usage
For HDL, these design elements are inferred rather than instantiated.

200

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Libraries Guide
ISE 6.3i

CB2CLE, CB4CLE, CB8CLE, CB16CLE

CB2CLE, CB4CLE, CB8CLE, CB16CLE

2-, 4-, 8-, 16-Bit Loadable Cascadable Binary Counters with Clock
Enable and Asynchronous Clear
Architectures Supported
CB2CLE, CB4CLE, CB8CLE, CB16CLE
Spartan-II, Spartan-IIE

D0

CB2CLE

Q0
Q1

D1
L

CEO
TC

CE
C

CLR
X4354

D0

CB4CLE

Q0

D1

Q1

D2

Q2
Q3

D3
L
CE

CEO

TC

CLR

D[7:0]

X4358

CB8CLE

Q[7:0]

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CB2CLE, CB4CLE, CB8CLE, and CB16CLE are, respectively, 2-, 4-, 8-, and 16-bit
(stage) synchronously loadable, asynchronously clearable, cascadable binary
counters. The asynchronous clear (CLR) is the highest priority input. When CLR is
High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock
enable out (CEO) go to logic level zero, independent of clock transitions. The data on
the D inputs is loaded into the counter when the load enable input (L) is High during
the Low-to-High clock transition, independent of the state of clock enable (CE). The Q
outputs increment when CE is High during the Low-to-High clock transition. The
counter ignores clock transitions when CE is Low. The TC output is High when all Q
outputs are High.
Larger counters are created by connecting the CEO output of the first stage to the CE
input of the next stage and connecting the C, L, and CLR inputs in parallel. CEO is
active (High) when TC and CE are High. The maximum length of the counter is
determined by the accumulated CE-to-TC propagation delays versus the clock period.
The clock period must be greater than n(tCE-TC), where n is the number of stages and
the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading
counters, use the CEO output if the counter uses the CE input; use the TC output if it
does not.
The counter is asynchronously cleared, output Low, when power is applied.

L
CE

CEO

TC

CLR

D[15:0]

X4362

CB16CLE

Q[15:0]

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

L
CE

CEO

TC

CLR

Libraries Guide
ISE 6.3i

X4366

www.xilinx.com
1-800-255-7778

201

CB2CLE, CB4CLE, CB8CLE, CB16CLE

Inputs

Outputs

CLR

CE

Dz D0

Qz Q0

TC

CEO

Dn

Dn

TC

CEO

No Chg

No Chg

Inc

TC

CEO

z= 1 for CB2CLE; z = 3 for CB4CLE; z = 7 for CB8CLE; z = 15 for CB16CLE

TC = QzQ(z-1)Q(z-2)...Q0
CEO = TCCE

VCC

FTCLEX
D0

Q[7:0]

D
L
T
CE
C

Q0

CLR

Q0
FTCLEX
D1

D
L
T
CE
C

Q1

T2
CLR

Q1

AND2

FTCLEX
D2

D
L
T
CE
C

Q2

T3
CLR

Q2

AND3

FTCLEX
D3

D
L
T
CE
C

Q3

T4

CLR

Q3
AND4

FTCLEX
D4

D
L
T
CE
C

Q4

T5
CLR

Q4

AND2

FTCLEX
D5

D
L
T
CE
C

Q5

T6
CLR

Q5

AND3

FTCLEX
D6

D
L
T
CE
C

Q6

T7

CLR

Q6
AND4

D[7:0]

FTCLEX
D7

L
T
CE
C

CE
C
CLR

Q7

CLR

TC
Q7
AND5

OR_CE_L

CEO

OR2
AND2

X8135

CB8CLE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

202

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Libraries Guide
ISE 6.3i

CB2CLE, CB4CLE, CB8CLE, CB16CLE

VCC

CE
Q0

AND2

Q1
CEO

FDC
AND2B1

OR2

AND3
D

GND

TC

XOR2

AND2B1

AND2

C
CLR
OR2

Q0

D0
AND2

FDC

AND2B1
D

XOR2
AND3B1

C
CLR
OR2

Q1

D1
AND2

C
CLR

X7780

CB2CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

CB2CLE
D0
D1
L

D0

Q0

D1

Q1

Q0
Q1

CE

CE

CEO
TC
CLR
CB0

CLR

CB2CLE
D2
D3

D0

Q0

D1

Q1

Q2
Q3

L
CE
C

CEO
TC
CLR

D[7:0]

Q[7:0]

CB2

CB2CLE
D4
D5

D0

Q0

D1

Q1

Q4
Q5

L
CE
C

CEO
TC
CLR
CB4

CB2CLE
D6
D7

D0

Q0

D1

Q1

Q6
Q7

L
CE
C

CEO

CEO
TC
CLR
CB6

TC

AND4

X8130

CB8CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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1-800-255-7778

203

204

CB2CLE, CB4CLE, CB8CLE, CB16CLE

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CB2CLED, CB4CLED, CB8CLED, CB16CLED

CB2CLED, CB4CLED, CB8CLED, CB16CLED

2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters
with Clock Enable and Asynchronous Clear
Architectures Supported
CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED
Spartan-II, Spartan-IIE

D0

CB2CLED Q0

D1

Q1

UP
L
CE

CEO

TC

CLR

X4355

D0

CB4CLED Q0

D1

Q1

D2

Q2

D3

Q3

UP
L
CE

CEO

TC

CLR

D[7:0]

X4359

CB8CLED

Q[7:0]

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CB2CLED, CB4CLED, CB8CLED, and CB16CLED are, respectively, 2-, 4-, 8- and 16-bit
(stage), synchronously loadable, asynchronously clearable, cascadable, bidirectional
binary counters. The asynchronous clear (CLR) is the highest priority input. When
CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and
clock enable out (CEO) go to logic level zero, independent of clock transitions. The
data on the D inputs is loaded into the counter when the load enable input (L) is High
during the Low-to-High clock (C) transition, independent of the state of clock enable
(CE). The Q outputs decrement when CE is High and UP is Low during the Low-toHigh clock transition. The Q outputs increment when CE and UP are High. The
counter ignores clock transitions when CE is Low.
For counting up, the TC output is High when all Q outputs and UP are High. For
counting down, the TC output is High when all Q outputs and UP are Low. To
cascade counters, the CEO output of each counter is connected to the CE pin of the
next stage. The clock, UP, L, and CLR inputs are connected in parallel. CEO is active
(High) when TC and CE are High. The maximum length of the counter is determined
by the accumulated CE-to-TC propagation delays versus the clock period. The clock
period must be greater than n(tCE-TC), where n is the number of stages and the time
tCE-TC is the CE-to-TC propagation delay of each stage.
When cascading counters, use the CEO output if the counter uses the CE input; use
the TC output if it does not. For XC9500/XV/XL, CoolRunner XPLA3, and
CoolRunner-II, see CB2X1, CB4X1, CB8X1, CB16X1 for high-performance
cascadable, bidirectional counters.

UP

The counter is asynchronously cleared, output Low, when power is applied.

L
CE

CEO

TC

CLR

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.

X4363

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted with an inverter in front of the GSR
input of STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or
STARTUP_VIRTEX2.

Libraries Guide
ISE 6.3i

www.xilinx.com
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205

CB2CLED, CB4CLED, CB8CLED, CB16CLED

D[15:0] CB16CLED Q[15:0]

Inputs

UP
L
CE

CEO

TC

CLR

X4367

Outputs

CLR

CE

UP

Dz D0

Qz Q0

TC

CEO

*CE

Dn

Dn

TC

CEO

No Chg

No Chg

Inc

TC

CEO

Dec

TC

CEO

z = 1 for CB2CLED; z = 3 for CB4CLED; z = 7 for CB8CLED; z = 15 for CB16CLED

TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP)
CEO = TCCE

D[7:0]
D0

VCC

FTCLEX
D
L
T
Q
CE
C
CLR
Q0

Q0
D0
D1
S0

M2_1B1
O

T1

T1

FTCLEX

D1

D
L
T
Q
CE
C
CLR
Q1

Q1
T2_DN
M2_1
AND2B2
T2_UP

D0
D1
S0

O T2
T2

AND2
FTCLEX

D2

D
L
Q
T
CE
C
CLR
Q2

Q2
T3_DN
M2_1
AND3B3

D0
D1
S0

T3_UP

O T3
T3

AND3
FTCLEX

D3

D
L
T
Q
CE
C
CLR
Q3

Q3
T4_DN
M2_1
AND4B4

D0
D1
S0

O T4
T4

T4_UP
AND4
FTCLEX

D4

D
L
T
Q
CE
C
CLR
Q4

Q4
T5_DN
M2_1
AND2B1
T5_UP

D0
D1
S0

O T5
T5

AND2
FTCLEX

D5

D
L
T
Q
CE
C
CLR
Q5

Q5
T6_DN
M2_1
AND3B2

D0
D1
S0

T6_UP

O T6
T6

AND3
FTCLEX

D6

D
L
Q
T
CE
C
CLR
Q6

Q6
T7_DN
M2_1
AND4B3
T7_UP

D0
D1
S0

T7

T7

AND4
FTCLEX

D7

D
L
Q
T
CE
C
CLR
Q7

L
CE
C
CLR

Q7
Q[7:0]
TC_DN

AND5B4
OR_CE_L
OR2

TC_UP

M2_1
D0
O
D1
S0
TC

TC
CEO
AND2

AND5
UP
X4046

CB8CLED Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

206

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Libraries Guide
ISE 6.3i

CB2CLED, CB4CLED, CB8CLED, CB16CLED

VCC

CE
AND2

UP
OR2

AND3B2

FDC

GND

D
AND3B1

OR3

OR2

XOR2

Q0

C
CLR

GND

Q0

D0
AND2

AND2B1

AND4B3

FDC
D
AND4B1

OR3

XOR2

Q1

C
CLR

D1

Q1
AND2

AND2B1

AND5B4

FDC
D
OR3
AND5B1

XOR2

Q2

C
CLR

Q2

D2
AND2

AND2B1

INV
INV
INV
INV
INV

AND6

FDC
INV

D
OR3

XOR2

AND6

Q3

C
CLR

Q3
D3
AND2

AND2B1

TC

AND5
OR2

AND5B5

INV
INV
INV
INV
INV

AND6

CEO
OR2

AND6

C
CLR

X7625

CB4CLED Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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1-800-255-7778

207

208

CB2CLED, CB4CLED, CB8CLED, CB16CLED

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CB2RE, CB4RE, CB8RE, CB16RE

CB2RE, CB4RE, CB8RE, CB16RE

2-, 4-, 8-, 16-Bit Cascadable Binary Counters with Clock Enable and
Synchronous Reset
Architectures Supported
CB2RE, CB4RE, CB8RE, CB16RE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

CB2RE

Q0
Q1

CE

CEO

TC

X4356

CB4RE

Q0
Q1
Q2
Q3

CE

CEO

TC

X4360

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CB2RE, CB4RE, CB8RE, and CB16RE are, respectively, 2-, 4-, 8-, and 16-bit (stage),
synchronous, resettable, cascadable binary counters. The synchronous reset (R) is the
highest priority input. When R is High, all other inputs are ignored; the Q outputs,
terminal count (TC), and clock enable out (CEO) go to logic level zero during the
Low-to-High clock transition. The Q outputs increment when the clock enable input
(CE) is High during the Low-to-High clock (C) transition. The counter ignores clock
transitions when CE is Low. The TC output is High when both Q outputs are High.
Larger counters are created by connecting the CEO output of the first stage to the CE
input of the next stage and connecting the C and R inputs in parallel. CEO is active
(High) when TC and CE are High. The maximum length of the counter is determined
by the accumulated CE-to-TC propagation delays versus the clock period. The clock
period must be greater than n(tCE-TC), where n is the number of stages and the time
tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use
the CEO output if the counter uses the CE input; use the TC output if it does not.
The counter is asynchronously cleared, output Low, when power is applied.

CB8RE

Q[7:0]

CE

CEO

TC

X4364

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

CB16RE
CE

CEO

TC

Libraries Guide
ISE 6.3i

Outputs

Q[15:0]

CE

Qz Q0

TC

CEO

No Chg

No Chg

X4368

www.xilinx.com
1-800-255-7778

209

CB2RE, CB4RE, CB8RE, CB16RE

Inputs

Outputs

CE

Qz Q0

TC

CEO

Inc

TC

CEO

z = 1 for CB2RE; z = 3 for CB4RE; z = 7 for CB8RE; z = 15 for CB16RE

TC = QzQ(z-1)Q(z-2)...Q0)
CEO = TCCE

Q[7:0]

FTRSE

VCC

T
CE
C

Q0

Q0

FTRSE
T
CE
C

Q1

T2
R

Q1

AND2

FTRSE
T
CE
C

Q2

T3
R

Q2

AND3

FTRSE
T
CE
C

Q3

T4

Q3
AND4

FTRSE
T
CE
C

Q4

T5
R

Q4

AND2

FTRSE
T
CE
C

Q5

T6
R

Q5

AND3

FTRSE
T
CE
C

Q6

T7

Q6
AND4

FTRSE
T
CE
C

CE
C
R

Q7

TC
Q7
AND5

GND

CEO
X8137
AND2

CB8RE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, VirtexII, Virtex-II Pro, Virtex-II Pro X

210

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Libraries Guide
ISE 6.3i

CB2RE, CB4RE, CB8RE, CB16RE

VCC

CE
AND2
R
CEO
AND3

FD
D
AND2B1

TC

XOR2

AND2

C
Q0
AND2B1

FD
D
AND3B1

Q0
Q1

XOR2
C
Q1

AND2B1

X7781

CB2RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

CB2RE
Q0

Q0
CE
C

Q1

Q1
CE

CEO
TC

C
R

CB0

CB2RE
Q2

Q0

Q3

Q1
CE

CEO
TC

C
R

CB2

CB2RE
Q4

Q0

Q5

Q1
CE

CEO
TC

C
R

CB4

CB2RE
Q6

Q0
CE

CEO

CEO
TC

Q[7:0]

Q7

Q1

R
CB6

TC
X8129
AND4

CB8RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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1-800-255-7778

211

212

CB2RE, CB4RE, CB8RE, CB16RE

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CB2RLE, CB4RLE, CB8RLE, CB16RLE

CB2RLE, CB4RLE, CB8RLE, CB16RLE

2-, 4-, 8-, 16-Bit Loadable Cascadable Binary Counters with Clock
Enable and Synchronous Reset
Architectures Supported
CB2RLE, CB4RLE, CB8RLE, CB16RLE
Spartan-II, Spartan-IIE

D0

CB2RLE

Q0
Q1

D1

L
CE

CEO

TC

X4513

D0

CB4RLE

Q0

D1

Q1

D2

Q2
Q3

D3
L
CE

CEO

TC

D[7:0]

X4514

CB8RLE

Q[7:0]

L
CE

CEO

TC

D[15:0]

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CB2RLE, CB4RLE, CB8RLE, and CB16RLE are, respectively, 2-, 4-, 8-, and 16-bit
(stage), synchronous, loadable, resettable, cascadable binary counters. The
synchronous reset (R) is the highest priority input. The synchronous R, when High,
overrides all other inputs and resets the Q outputs, terminal count (TC), and clock
enable out (CEO) outputs to Low on the Low-to-High clock (C) transition.
The data on the D inputs is loaded into the counter when the load enable input (L) is
High during the Low-to-High clock (C) transition, independent of the state of CE. The
Q outputs increment when CE is High during the Low-to-High clock transition. The
counter ignores clock transitions when CE is Low. The TC output is High when all Q
outputs are High. The CEO output is High when all Q outputs and CE are High to
allow direct cascading of counters.
Larger counters are created by connecting the CEO output of the first stage to the CE
input of the next stage and by connecting the C, L, and R inputs in parallel. The
maximum length of the counter is determined by the accumulated CE-to-CEO
propagation delays versus the clock period. When cascading counters, use the CEO
output if the counter uses the CE input; use the TC output if it does not.
The counter is asynchronously cleared, output Low, when power is applied. For
XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition
can be simulated by applying a High-level pulse on the PRLD global net.
Inputs

X4515

CB16RLE Q[15:0]

No

Outputs

CE

Dz D0

Qz Q0

TC

CEO

Dn

Dn

TC

CEO

No Chg

No Chg

Inc

TC

CEO

L
CE

CEO

TC

X4516

z = 1 for CB2RLE; z = 3 for CB4RLE; z = 7 for CB8RLE; z = 15 for CB16RLE

TC = QzQ(z-1)Q(z-2)...Q0
CEO = TCCE

Libraries Guide
ISE 6.3i

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213

CB2RLE, CB4RLE, CB8RLE, CB16RLE

VCC

CE
AND2
L
OR2

CEO

GND

AND3

Q1
Q0

AND3B2
D0

FD

OR2

TC

AND3B1

Q
AND2

XOR2
C
Q0
AND3B2

AND4B2
D1

FD

OR2
AND3B1

XOR2
C
Q1
AND3B2
C

X7782

CB2RLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

CB2RLE
D0
D1
L
CE
C

Q0
Q1

D0
Q0
Q1
D1
L
CE CEO
TC
C
R
CB0

CB2RLE
D2
D3

Q2
Q3

D0
Q0
D1
Q1
L
CE CEO
C
TC
R
CB2

CB2RLE
D4
D5

Q4
Q5

D0
Q0
Q1
D1
L
CE CEO
TC
C
R
CB4

CB2RLE
D6
D7

Q6
Q7

D0
Q0
D1
Q1
L
CE CEO
C
TC
R

D[7:0]

CEO

CB6

Q[7:0]
TC
AND4

X7621

CB8RLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

214

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Libraries Guide
ISE 6.3i

CB2X1, CB4X1, CB8X1, CB16X1

CB2X1, CB4X1, CB8X1, CB16X1

2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters
with Clock Enable and Asynchronous Clear
Architectures Supported
CB2X1, CB4X1
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CB8X1, CB16X1
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D0

CB2X1

D1

QO
Q1
TCU

TCD

CEU

CEOU

CED

CEOD

CLR

D0

X4194

CB4X1

Q0

D1

Q1

D2

Q2

D3

Q3
TCU

CEU
CED

TCD

CEOU
CEOD

CLR

Libraries Guide
ISE 6.3i

X4196

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CB2X1, CB4X1, CB8X1, and CB16X1 are, respectively, 2-, 4-, 8-, and 16-bit (stage),
synchronously loadable, asynchronously clearable, bidirectional binary counters.
These counters have separate count-enable inputs and synchronous terminal-count
outputs for up and down directions to support high-speed cascading in
XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II.
The asynchronous clear (CLR) is the highest priority input. When CLR is High, all
other inputs are ignored; data outputs (Q) go to logic level zero, terminal count
outputs TCU and TCD go to zero and one, respectively, clock enable outputs CEOU
and CEOD go to Low and High, respectively, independent of clock transitions. The
data on the D inputs loads into the counter on the Low-to-High clock (C) transition
when the load enable input (L) is High, independent of the CE inputs.
The Q outputs increment when CEU is High, provided CLR and L are Low, during the
Low-to-High clock transition. The Q outputs decrement when CED is High, provided
CLR and L are Low. The counter ignores clock transitions when CEU and CED are
Low. Both CEU and CED should not be High during the same clock transition; the
CEOU and CEOD outputs might not function properly for cascading when CEU and
CED are both High.
For counting up, the CEOU output is High when all Q outputs and CEU are High. For
counting down, the CEOD output is High when all Q outputs are Low and CED is
High. To cascade counters, the CEOU and CEOD outputs of each counter are

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215

D[7:0]

CB2X1, CB4X1, CB8X1, CB16X1

CB8X1

Q[7:0]
TCU

L
CEU

TCD
CEOU

CED

CEOD

CLR

X4198

D[15:0]

CB16X1

Q[15:0]
TCU

The maximum clocking frequency of these counter components is unaffected by the

number of cascaded stages for all counting and loading functions. The TCU terminal
count output is High when all Q outputs are High, regardless of CEU. The TCD
output is High when all Q outputs are Low, regardless of CED.
When cascading counters, the final terminal count signals can be produced by AND
wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the
down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable
AND gates within the component. This results in zero propagation from the CEU and
CED inputs and from the Q outputs, provided all connections from each such output
remain on-chip. Otherwise, a macrocell buffer delay is introduced.

TCD

CEU

CEOU

CED

CEOD

CLR

connected directly to the CEU and CED inputs, respectively, of the next stage. The
clock, L, and CLR inputs are connected in parallel.

The counter is initialized to zero (TCU Low and TCD High) when power is applied.
The power-on condition can be simulated by applying a High-level pulse on the
PRLD global net.

X4200

Inputs

Outputs

CLR

CEU

CED

DzD0

QzQ0

TCU

TCD

CEOU

CEOD

CEOD

Dn

Dn

TCU

TCD

CEOU

CEOD

No Chg

No Chg

No Chg

Inc

TCU

TCD

CEOU

Dec

TCU

TCD

CEOD

Inc

TCU

TCD

Invalid

Invalid

z = 1 for CB2X1; z = 3 for CB4X1; z = 7 for CB8X1; z = 15 for CB16X1

TCU = QzQ(z-1)Q(z-2)...Q0
TCD = QzQ(z-1)Q(z-2)...Q0
CEOU = TCUCEU
CEOD = TCDCED

216

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Libraries Guide
ISE 6.3i

CB2X1, CB4X1, CB8X1, CB16X1

L
OR2

CEU
OR2

AND2B1

FDC
D

CED

AND3B2

Q0

OR3
XOR2

OR2

CLR

Q0

AND2B1
GND

D0
AND2

AND4B3

FDC
D
AND3B1

OR3

XOR2

Q1

C
CLR

Q1

AND2B1

D1
AND2

AND5B4

FDC
D
AND4B1

OR3

XOR2

Q2

C
CLR

Q2
AND2B1

D2
AND2

INV
INV
INV
INV
INV

AND6

FDC
D
OR3
AND5B1

XOR2

Q3

C
CLR

Q3
AND2B1

D3
AND2

TCU
AND4
INV
INV
INV
INV
INV
INV
INV

AND7

INV
INV
INV

FDC

INV
INV

AND7

D
NOR4

TCDINV

C
CLR

TCDINV
AND5B4

AND3B1

CEQU
AND2

CEQD
AND3B1

TCD
INV

C
CLR

X7624

CB4X1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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217

218

CB2X1, CB4X1, CB8X1, CB16X1

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Libraries Guide
ISE 6.3i

CB2X2, CB4X2, CB8X2, CB16X2

CB2X2, CB4X2, CB8X2, CB16X2

2-, 4-, 8-, and 16-Bit Loadable Cascadable Bidirectional Binary
Counters with Clock Enable and Synchronous Reset
Architectures Supported
CB2X2
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CB4X2, CB8X2, CB16X2

Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

CB2X2

D0
D1

QO
Q1
TCU

TCD

CEU

CEOU

CED

CEOD

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CB2X2, CB4X2, CB8X2, and CB16X2 are, respectively, 2-, 4-, 8-, and 16-bit (stage),
synchronous, loadable, resettable, bidirectional binary counters. These counters have
separate count-enable inputs and synchronous terminal-count outputs for up and
down directions to support high-speed cascading in CPLD architectures.

X4195

D0

CB4X2

Q0

D1

Q1

D2

Q2

D3

Q3
TCU
TCD

L
CEU

CEOU

CED

CEOD

X4197

D[7:0]

CB8X2

Q[7:0]
TCU

TCD

CEU

CEOU

CED

CEOD

Libraries Guide
ISE 6.3i

X4199

The synchronous reset (R) is the highest priority input. When R is High, all other
inputs are ignored; the data outputs (Q) go to logic level zero, terminal count outputs
TCU and TCD go to zero and one, respectively, and clock enable outputs CEOU and
CEOD go to Low and High, respectively, on the Low-to-High clock (C) transition. The
data on the D inputs loads into the counter on the Low-to-High clock (C) transition
when the load enable input (L) is High, independent of the CE inputs.
All Q outputs increment when CEU is High, provided R and L are Low during the
Low-to-High clock transition. All Q outputs decrement when CED is High, provided
R and L are Low. The counter ignores clock transitions when CEU and CED are Low.
Both CEU and CED should not be High during the same clock transition; the CEOU
and CEOD outputs might not function properly for cascading when CEU and CED
are both High.
For counting up, the CEOU output is High when all Q outputs and CEU are High. For
counting down, the CEOD output is High when all Q outputs are Low and CED is
High. To cascade counters, the CEOU and CEOD outputs of each counter are,
respectively, connected directly to the CEU and CED inputs of the next stage. The C,
L, and R inputs are connected in parallel.

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219

D[15:0]

CB16X2

CB2X2, CB4X2, CB8X2, CB16X2

Q[15:0]
TCU

TCD

CEU

CEOU

CED

CEOD

The maximum clocking frequency of these counter components is unaffected by the

number of cascaded stages for all counting and loading functions. The TCU terminal
count output is High when all Q outputs are High, regardless of CEU. The TCD
output is High when all Q outputs are Low, regardless of CED.

X4201

When cascading counters, the final terminal count signals can be produced by AND
wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the
down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable
AND gates within the component. This results in zero propagation from the CEU and
CED inputs and from the Q outputs, provided all connections from each such output
remain on-chip. Otherwise, a macrocell buffer delay is introduced.
The counter is initialized to zero (TCU Low and TCD High) when power is applied.
The power-on condition can be simulated by applying a High-level pulse on the
PRLD global net.

Inputs

Outputs

CEU

CED

Dz D0

Qz Q0

TCU

TCD

CEOU

CEOD

CEOD

Dn

Dn

TCU

TCD

CEOU

CEOD

No Chg

No Chg

No Chg

Inc

TCU

TCD

CEOU

Dec

TCU

TCD

CEOD

Inc

TCU

TCD

Invalid

Invalid

z = 1 for CB2X2; z = 3 for CB4X2; z = 7 for CB8X2; z = 15 for CB16X2

TCU = QzQ(z-1)Q(z-2)...Q0
TCD = QzQ(z-1)Q(z-2)...Q0
CEOU = TCUCEU
CEOD = TCDCED

220

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Libraries Guide
ISE 6.3i

CB2X2, CB4X2, CB8X2, CB16X2

Q3
Q2
Q1
Q0

L
OR2

CED
TCU

OR2

R
AND4B3

AND4

TCD
INV

FD
AND3B2

OR3

CEQD
Q
AND3B1

XOR2
C

CEQU

AND3B2

Q0

D0

AND2

AND3B1

CEU
OR2

AND5B4

GND

FD
AND4B2

OR3
D
XOR2

Q1

AND3B2

D1

AND3B1

INV
INV
INV
INV
INV

AND6

FDC

OR3
D

AND5B2
XOR2

Q2

AND3B2

D2

AND3B1

INV
INV
INV
INV
INV
INV

AND7

INV
INV

FDC

OR3
D

AND6
XOR2

Q3

AND3B2

D3

AND3B1
INV
INV
INV
INV
INV
INV
INV

AND7

INV
INV
INV
INV
INV

FDC

AND7
D

NOR5
INV

TCDINV

AND6

AND5B4

X7623

CB4X2 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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1-800-255-7778

221

222

CB2X2, CB4X2, CB8X2, CB16X2

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Libraries Guide
ISE 6.3i

CBD2CE, CBD4CE, CBD8CE, CBD16CE

CBD2CE, CBD4CE, CBD8CE, CBD16CE

2-, 4-, 8-,16-Bit Cascadable Dual Edge Triggered Binary Counters with
Clock Enable and Asynchronous Clear
Architectures Supported
CBD2CE, CBD4CE, CBD8CE, CBD16CE
Spartan-II, Spartan-IIE

CBD2CE

Q0
Q1

CE

CEO

TC

CLR
X9621

CBD4CE

Q2
Q3
CE

CEO

TC

CLR
X9622

Q[7:0]

CE

CEO

TC

CLR

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CBD2CE, CBD4CE, CBD8CE, and CBD16CE are, respectively, 2-, 4-, 8-, and 16-bit
(stage), asynchronous, clearable, cascadable dual edge triggered binary counters. The
asynchronous clear (CLR) is the highest priority input. When CLR is High, all other
inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go
to logic level zero, independent of clock transitions. The Q outputs increment when
the clock enable input (CE) is High during the Low-to-High and High-to-Low clock
(C) transition. The counter ignores clock transitions when CE is Low. The TC output is
High when all Q outputs are High.

Q0
Q1

CBD8CE

No

Larger counters are created by connecting the CEO output of the first stage to the CE
input of the next stage and connecting the C and CLR inputs in parallel. CEO is active
(High) when TC and CE are High. The maximum length of the counter is determined
by the accumulated CE-to-TC propagation delays versus the clock period. The clock
period must be greater than n(tCE-TC), where n is the number of stages and the time
tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use
the CEO output if the counter uses the CE input; use the TC output if it does not.
The counter is asynchronously cleared, outputs Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

X9623

CBD16CE

Q[15:0]

CE

CEO

TC

CLR
X9624

Libraries Guide
ISE 6.3i

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223

CBD2CE, CBD4CE, CBD8CE, CBD16CE

VCC

CE
Q0

AND2

Q1

FDDC
D

Q
CEO

XOR2
C
CLR

AND3

Q0

TC
AND2

FDDC
D

XOR2

AND2

CLR
Q1

CLR

X9625

CBD2CE Implementation CoolRunner-II

CBD2CE
Q0

Q0
CE
C

Q1

Q1
CE
C

CEO
TC
CLR
CB0

CLR

CBD2CE
Q2

Q0

Q3

Q1
CE
C

CEO
TC
CLR
CB2

CBD2CE
Q4

Q0

Q5

Q1
CE
C

CEO
TC
CLR
CB4

CBD2CE
Q6

Q0

Q7

Q1
CE
C

CEO

CEO
TC
CLR
CB6

TC

AND4

X9626

CBD8CE Implementation CoolRunner-II

Usage
For HDL, these design elements are supported for inference but not instantiation.

224

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Libraries Guide
ISE 6.3i

CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE

CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE

2-, 4-, 8-, 16-Bit Loadable Cascadable Dual Edge Triggered Binary
Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE
Spartan-II, Spartan-IIE

D0

CBD2CLE

Q0
Q1

D1
L
CE

CEO

TC

CLR
X9627

CBD4CLE

D0
D1
D2

Q0
Q1
Q2
Q3

D3
L

CEO

CE
C

TC

CLR
D[7:0]

X9628

CBD8CLE

Q[7:0]

L
CE

CEO

TC

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CBD2CLE, CBD4CLE, CBD8CLE, and CBD16CLE are, respectively, 2-, 4-, 8-, and 16bit (stage) synchronously loadable, asynchronously clearable, cascadable dual edge
triggered binary counters. The asynchronous clear (CLR) is the highest priority input.
When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC),
and clock enable out (CEO) go to logic level zero, independent of clock transitions.
The data on the D inputs is loaded into the counter when the load enable input (L) is
High during the Low-to-High clock transition, independent of the state of clock
enable (CE). The Q outputs increment when CE is High during the Low-to-High and
High-to-Low clock transition. The counter ignores clock transitions when CE is Low.
The TC output is High when all Q outputs are High.
Larger counters are created by connecting the CEO output of the first stage to the CE
input of the next stage and connecting the C, L, and CLR inputs in parallel. CEO is
active (High) when TC and CE are High. The maximum length of the counter is
determined by the accumulated CE-to-TC propagation delays versus the clock period.
The clock period must be greater than n(tCE-TC), where n is the number of stages and
the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading
counters, use the CEO output if the counter uses the CE input; use the TC output if it
does not.
The counter is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

CLR
X9629

D[15:0]

CBD16CLE

Outputs

CLR

CE

Dz D0

Qz Q0

TC

CEO

Dn

Dn

TC

CEO

Dn

Dn

TC

CEO

No Chg

No Chg

Q[15:0]

L
CE

CEO

TC

CLR
X9630

Libraries Guide
ISE 6.3i

Inputs

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225

CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE

Inputs

Outputs

CLR

CE

Dz D0

Qz Q0

TC

CEO

Inc

TC

CEO

Inc

TC

CEO

z= 1 for CBD2CLE; z = 3 for CBD4CLE; z = 7 for CBD8CLE; z = 15 for CBD16CLE

TC = QzQ(z-1)Q(z-2)...Q0
CEO = TCCE
VCC

CE
Q0

AND2

Q1
CEO

FDDC
AND2B1

OR2
GND

AND3
D

XOR2

AND2B1

TC
AND2

C
CLR
OR2

Q0

D0
AND2

FDDC

AND2B1
D

XOR2
AND3B1

C
CLR
OR2

Q1

D1
C

AND2

CLR
X9631

CBD2CLE Implementation CoolRunner-II

226

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Libraries Guide
ISE 6.3i

CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE

CBD2CLE
D0
D1
L

D0

Q0

D1

Q1

Q0
Q1

CE

CE

CEO
TC
CLR
CB0

CLR

CBD2CLE
D2
D3

D0

Q0

D1

Q1

L
CE
C

Q2
Q3

CEO
TC
CLR

D[7:0]

Q[7:0]

CB2

CBD2CLE
D4
D5

D0

Q0

D1

Q1

L
CE
C

Q4
Q5

CEO
TC
CLR
CB4

CBD2CLE
D6
D7

D0

Q0

D1

Q1

L
CE
C

Q6
Q7
CEO

CEO
TC
CLR
CB6

TC

AND4

X9632

CBD8CLE Implementation CoolRunner-II

Usage
For HDL, these design elements are supported for inference but not instantiation.

Libraries Guide
ISE 6.3i

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227

228

CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE

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Libraries Guide
ISE 6.3i

CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED

CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED

2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Dual Edge
Triggered Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED
Spartan-II, Spartan-IIE

D0

CBD2CLED Q0

D1

Q1

UP
L
CE

CEO

TC

CLR

X9633

D0

CBD4CLED Q0

D1

Q1
Q2
Q3

D2
D3
UP
L
CE

CEO

TC

CLR

D[7:0]

X9634

CBD8CLED

Q[7:0]

UP
L
CE

CEO

TC

CLR

X9635

D[15:0] CBD16CLED Q[15:0]

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CBD2CLED, CBD4CLED, CBD8CLED, and CBD16CLED are, respectively, 2-, 4-, 8and 16-bit (stage), synchronously loadable, asynchronously clearable, cascadable,
bidirectional dual edge triggered binary counters. The asynchronous clear (CLR) is
the highest priority input. When CLR is High, all other inputs are ignored; the Q
outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero,
independent of clock transitions. The data on the D inputs is loaded into the counter
when the load enable input (L) is High during the Low-to-High clock (C) transition,
independent of the state of clock enable (CE). The Q outputs decrement when CE is
High and UP is Low during the Low-to-High and High-to-Low clock transition. The
Q outputs increment when CE and UP are High. The counter ignores clock transitions
when CE is Low.
For counting up, the TC output is High when all Q outputs and UP are High. For
counting down, the TC output is High when all Q outputs and UP are Low. To
cascade counters, the CEO output of each counter is connected to the CE pin of the
next stage. The clock, UP, L, and CLR inputs are connected in parallel. CEO is active
(High) when TC and CE are High. The maximum length of the counter is determined
by the accumulated CE-to-TC propagation delays versus the clock period. The clock
period must be greater than n(tCE-TC), where n is the number of stages and the time
tCE-TC is the CE-to-TC propagation delay of each stage.
When cascading counters, use the CEO output if the counter uses the CE input; use
the TC output if it does not. For CoolRunner-II, see CB2X1, CB4X1, CB8X1, CB16X1
for high-performance cascadable, bidirectional counters.
The counter is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

UP
L
CE

CEO

TC

CLR

X9636

Libraries Guide
ISE 6.3i

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229

CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED

Inputs

Outputs

CLR

CE

UP

Dz D0

Qz Q0

TC

CEO

Dn

Dn

TC

CEO

Dn

Dn

TC

CEO

No Chg

No Chg

Inc

TC

CEO

Inc

TC

CEO

Dec

TC

CEO

Dec

TC

CEO

z = 1 for CBD2CLED; z = 3 for CBD4CLED; z = 7 for CBD8CLED; z = 15 for CBD16CLED

TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP)
CEO = TCCE

230

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Libraries Guide
ISE 6.3i

CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED

VCC

CE
AND2

UP
OR2

AND3B2

FDDC

GND

D
AND3B1

OR3

OR2

XOR2

Q0

C
CLR

GND

Q0

D0
AND2

AND2B1

AND4B3

FDDC
D
AND4B1

OR3

XOR2

Q1

C
CLR

D1

Q1
AND2

AND2B1

AND5B4

FDDC
D
OR3
AND5B1

XOR2

Q2

C
CLR
Q2

D2
AND2

AND2B1

INV
INV
INV
INV
INV

AND6

FDDC
INV

D
OR3

XOR2

AND6

Q3

C
CLR
Q3

D3
AND2

AND2B1

TC

AND5
OR2

AND5B5

INV
INV
INV
INV
INV

AND6

CEO
OR2

AND6

C
CLR

X9637

CBD4CLED Implementation CoolRunner-II

Libraries Guide
ISE 6.3i

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1-800-255-7778

231

CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED

Usage
For HDL, these design elements are supported for inference but not instantiation.

232

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Libraries Guide
ISE 6.3i

CBD2RE, CBD4RE, CBD8RE, CBD16RE

CBD2RE, CBD4RE, CBD8RE, CBD16RE

2-, 4-, 8-, 16-Bit Cascadable Dual Edge Triggered Binary Counters with
Clock Enable and Synchronous Reset
Architectures Supported
CBD2RE, CBD4RE, CBD8RE, CBD16RE
Spartan-II, Spartan-IIE

CBD2RE

Q0
Q1

CE

CEO

TC

X9638

CBD4RE

Q0
Q1
Q2
Q3

CE

CEO

TC

R
X9639

CBD8RE

Q[7:0]

CE

CEO

TC

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CBD2RE, CBD4RE, CBD8RE, and CBD16RE are, respectively, 2-, 4-, 8-, and 16-bit
(stage), synchronous, resettable, cascadable dual edge triggered binary counters. The
synchronous reset (R) is the highest priority input. When R is High, all other inputs
are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to
logic level zero during the Low-to-High or High-to-Low clock transition. The Q
outputs increment when the clock enable input (CE) is High during the Low-to-High
and High-to-Low clock (C) transition. The counter ignores clock transitions when CE
is Low. The TC output is High when both Q outputs are High.
Larger counters are created by connecting the CEO output of the first stage to the CE
input of the next stage and connecting the C and R inputs in parallel. CEO is active
(High) when TC and CE are High. The maximum length of the counter is determined
by the accumulated CE-to-TC propagation delays versus the clock period. The clock
period must be greater than n(tCE-TC), where n is the number of stages and the time
tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use
the CEO output if the counter uses the CE input; use the TC output if it does not.
The counter is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

R
X9640

Inputs

Outputs

Q[15:0]

CE

Qz Q0

TC

CEO

CE

CEO

TC

No Chg

No Chg

Inc

TC

CEO

CBD16RE

X9641

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

233

CBD2RE, CBD4RE, CBD8RE, CBD16RE

Inputs

Outputs

CE

Qz Q0

TC

CEO

Inc

TC

CEO

z = 1 for CBD2RE; z = 3 for CBD4RE; z = 7 for CBD8RE; z = 15 for CBD16RE

TC = QzQ(z-1)Q(z-2)...Q0)
CEO = TCCE
VCC

CE
AND2
R
CEO
AND3

FDD
D
AND2B1

XOR2

TC
AND2

C
Q0
AND2B1

FDD
D
AND3B1

Q0
Q

Q1

XOR2
C
Q1

AND2B1
X9642

CBD2RE Implementation CoolRunner-II

234

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Libraries Guide
ISE 6.3i

CBD2RE, CBD4RE, CBD8RE, CBD16RE

CBD2RE
Q0

Q0
CE
C

Q1

Q1
CE

CEO
TC

C
R

CB0

CBD2RE
Q2

Q0

Q3

Q1
CE

CEO
TC

C
R

CB2

CBD2RE
Q4

Q0

Q5

Q1
CE

CEO
TC

C
R

CB4

CBD2RE
Q6

Q0
CE

CEO

CEO
TC

Q[7:0]

Q7

Q1

R
CB6

TC

AND4
X9643

CBD8RE Implementation CoolRunner-II

Usage
For HDL, these design elements are supported for inference but not instantiation.

Libraries Guide
ISE 6.3i

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1-800-255-7778

235

236

CBD2RE, CBD4RE, CBD8RE, CBD16RE

www.xilinx.com
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Libraries Guide
ISE 6.3i

CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE

CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE

2-, 4-, 8-, 16-Bit Loadable Cascadable Dual Edge Triggered Binary
Counters with Clock Enable and Synchronous Reset
Architectures Supported
CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE
Spartan-II, Spartan-IIE

D0

CBD2RLE

L
CE

CEO

TC

X9644

D0

CBD4RLE

Q1

D2

Q2
Q3

L
CE

CEO

TC

D[7:0]

X9645

CBD8RLE

L
CEO

TC

D[15:0]

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CBD2RLE, CBD4RLE, CBD8RLE, and CBD16RLE are, respectively, 2-, 4-, 8-, and 16bit (stage), synchronous, loadable, resettable, cascadable dual edge triggered binary
counters. The synchronous reset (R) is the highest priority input. The synchronous R,
when High, overrides all other inputs and resets the Q outputs, terminal count (TC),
and clock enable out (CEO) outputs to Low on the Low-to-High or High-to-Low clock
(C) transition.

Larger counters are created by connecting the CEO output of the first stage to the CE
input of the next stage and by connecting the C, L, and R inputs in parallel. The
maximum length of the counter is determined by the accumulated CE-to-CEO
propagation delays versus the clock period. When cascading counters, use the CEO
output if the counter uses the CE input; use the TC output if it does not.

Q[7:0]

CE

No

Virtex, Virtex-E

The data on the D inputs is loaded into the counter when the load enable input (L) is
High during the Low-to-High and High-to-Low clock (C) transition, independent of
the state of CE. The Q outputs increment when CE is High during the Low-to-High
and High-to-Low clock transition. The counter ignores clock transitions when CE is
Low. The TC output is High when all Q outputs are High. The CEO output is High
when all Q outputs and CE are High to allow direct cascading of counters.

Q0

D1
D3

Spartan-3

Q0
Q1

D1

No

The counter is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

X9646

CBD16RLE

Q[15:0]

L
CE

CEO

TC

Libraries Guide
ISE 6.3i

X9647

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1-800-255-7778

237

CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE

Inputs

Outputs

CE

Dz D0

Qz Q0

TC

CEO

Dn

Dn

TC

CEO

Dn

Dn

TC

CEO

No Chg

No Chg

Inc

TC

CEO

Inc

TC

CEO

z = 1 for CBD2RLE; z = 3 for CBD4RLE; z = 7 for CBD8RLE; z = 15 for CBD16RLE

TC = QzQ(z-1)Q(z-2)...Q0
CEO = TCCE
VCC

CE
AND2
L
OR2

CEO

GND

AND3

Q1
Q0

AND3B2
D0

FDD

OR2

TC

AND3B1

Q
AND2

XOR2
C
Q0
AND3B2

AND4B2
D1

FDD

OR2
AND3B1

XOR2
C
Q1
AND3B2
C
X9648

CBD2RLE Implementation CoolRunner-II

238

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Libraries Guide
ISE 6.3i

CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE

CBD2RLE
D0
D1
L
CE
C

Q0
Q1

Q0
D0
Q1
D1
L
CE CEO
TC
C
R

CB0

CBD2RLE
D2
D3

Q2
Q3

D0
Q0
D1
Q1
L
CE CEO
C
TC
R
CB2

CBD2RLE
D4
D5

Q4
Q5

Q0
D0
Q1
D1
L
CE CEO
TC
C
R
CB4

CBD2RLE
D6
D7

Q6
Q7

D0
Q0
D1
Q1
L
CE CEO
C
TC
R
D[7:0]

CEO

CB6

Q[7:0]
TC

AND4
X9649

CBD8RLE Implementation CoolRunner-II

Usage
For HDL, these design elements are supported for inference but not instantiation.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

239

240

CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CBD2X1, CBD4X1, CBD8X1, CBD16X1

CBD2X1, CBD4X1, CBD8X1, CBD16X1

2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Dual Edge
Triggered Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CBD2X1, CBD4X1, CBD8X1, CBD16X1
Spartan-II, Spartan-IIE

D0

CBD2X1

D1

QO
Q1
TCU

TCD

CEU

CEOU

CED

CEOD

CLR

D0

X9650

CBD4X1

Q0

D1

Q1

D2

Q2

D3

Q3
TCU

CEU

TCD

CED

CEOU
CEOD

L
C

CLR
X9651

D[7:0]

CBD8X1

Q[7:0]
TCU

L
CEU

TCD
CEOU

CED

CEOD

CLR

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CBD2X1, CBD4X1, CBD8X1, and CBD16X1 are, respectively, 2-, 4-, 8-, and 16-bit
(stage), synchronously loadable, asynchronously clearable, bidirectional dual edge
triggered binary counters. These counters have separate count-enable inputs and
synchronous terminal-count outputs for up and down directions to support highspeed cascading in the CoolRunner-II architecture.
The asynchronous clear (CLR) is the highest priority input. When CLR is High, all
other inputs are ignored; data outputs (Q) go to logic level zero, terminal count
outputs TCU and TCD go to zero and one, respectively, clock enable outputs CEOU
and CEOD go to Low and High, respectively, independent of clock transitions. The
data on the D inputs loads into the counter on the Low-to-High and High-to-Low
clock (C) transition when the load enable input (L) is High, independent of the CE
inputs.
The Q outputs increment when CEU is High, provided CLR and L are Low, during the
Low-to-High and High-to-Low clock transition. The Q outputs decrement when CED
is High, provided CLR and L are Low. The counter ignores clock transitions when
CEU and CED are Low. Both CEU and CED should not be High during the same clock
transition; the CEOU and CEOD outputs might not function properly for cascading
when CEU and CED are both High.
For counting up, the CEOU output is High when all Q outputs and CEU are High. For
counting down, the CEOD output is High when all Q outputs are Low and CED is
High. To cascade counters, the CEOU and CEOD outputs of each counter are
connected directly to the CEU and CED inputs, respectively, of the next stage. The
clock, L, and CLR inputs are connected in parallel.
In CoolRunner-II, the maximum clocking frequency of these counter components is
unaffected by the number of cascaded stages for all counting and loading functions.
The TCU terminal count output is High when all Q outputs are High, regardless of
CEU. The TCD output is High when all Q outputs are Low, regardless of CED.

X9652

When cascading counters, the final terminal count signals can be produced by AND
wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the
down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable

Libraries Guide
ISE 6.3i

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1-800-255-7778

241

D[15:0]

CBD16X1

CBD2X1, CBD4X1, CBD8X1, CBD16X1

Q[15:0]
TCU

TCD

CEU

CEOU

CED

CEOD

AND gates within the component. This results in zero propagation from the CEU and
CED inputs and from the Q outputs, provided all connections from each such output
remain on-chip. Otherwise, a macrocell buffer delay is introduced.
The counter is initialized to zero (TCU Low and TCD High) when power is applied.
The power-on condition can be simulated by applying a High-level pulse on the
PRLD global net.

CLR
X9653

Inputs

Outputs

CLR

CEU

CED

DzD0

QzQ0

TCU

TCD

CEOU

CEOD

CEOD

Dn

Dn

TCU

TCD

CEOU

CEOD

Dn

Dn

TCU

TCD

CEOU

CEOD

No Chg

No Chg

No Chg

Inc

TCU

TCD

CEOU

Inc

TCU

TCD

CEOU

Dec

TCU

TCD

CEOD

Dec

TCU

TCD

CEOD

Inc

TCU

TCD

Invalid

Invalid

Inc

TCU

TCD

Invalid

Invalid

z = 1 for CBD2X1; z = 3 for CBD4X1; z = 7 for CBD8X1; z = 15 for CBD16X1

TCU = QzQ(z-1)Q(z-2)...Q0
TCD = QzQ(z-1)Q(z-2)...Q0
CEOU = TCUCEU
CEOD = TCDCED

CBD4X1 Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

242

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Libraries Guide
ISE 6.3i

CBD2X2, CBD4X2, CBD8X2, CBD16X2

CBD2X2, CBD4X2, CBD8X2, CBD16X2

2-, 4-, 8-, and 16-Bit Loadable Cascadable Bidirectional Dual Edge
Triggered Binary Counters with Clock Enable and Synchronous Reset
Architectures Supported
CBD2X2, CBD4X2, CBD8X2, CBD16X2
Spartan-II, Spartan-IIE

D0

CBD2X2

D1

QO
Q1
TCU

TCD

CEU

CEOU

CED

CEOD

D0

X9655

CBD4X2

Q0

D1

Q1

D2

Q2

D3

Q3
TCU
TCD

L
CEU

CEOU

CED

CEOD

R
X9656

D[7:0]

CBD8X2

Q[7:0]
TCU

TCD

CEU

CEOU

CED

CEOD

D[15:0]

X9657

CBD16X2

Q[15:0]
TCU

TCD

CEU

CEOU

CED

CEOD

Libraries Guide
ISE 6.3i

X9658

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CBD2X2, CBD4X2, CBD8X2, and CBD16X2 are, respectively, 2-, 4-, 8-, and 16-bit
(stage), synchronous, loadable, resettable, bidirectional dual edge triggered binary
counters. These counters have separate count-enable inputs and synchronous
terminal-count outputs for up and down directions to support high-speed cascading
in the CoolRunner-II architecture.
The synchronous reset (R) is the highest priority input. When R is High, all other
inputs are ignored; the data outputs (Q) go to logic level zero, terminal count outputs
TCU and TCD go to zero and one, respectively, and clock enable outputs CEOU and
CEOD go to Low and High, respectively, on the Low-to-High and High-to-Low clock
(C) transition. The data on the D inputs loads into the counter on the Low-to-High
and High-to-Low clock (C) transition when the load enable input (L) is High,
independent of the CE inputs.
All Q outputs increment when CEU is High, provided R and L are Low during the
Low-to-High and High-to-Low clock transition. All Q outputs decrement when CED
is High, provided R and L are Low. The counter ignores clock transitions when CEU
and CED are Low. Both CEU and CED should not be High during the same clock
transition; the CEOU and CEOD outputs might not function properly for cascading
when CEU and CED are both High.
For counting up, the CEOU output is High when all Q outputs and CEU are High. For
counting down, the CEOD output is High when all Q outputs are Low and CED is
High. To cascade counters, the CEOU and CEOD outputs of each counter are,
respectively, connected directly to the CEU and CED inputs of the next stage. The C,
L, and R inputs are connected in parallel.
In CoolRunner-II, the maximum clocking frequency of these counter components is
unaffected by the number of cascaded stages for all counting and loading functions.
The TCU terminal count output is High when all Q outputs are High, regardless of
CEU. The TCD output is High when all Q outputs are Low, regardless of CED.
When cascading counters, the final terminal count signals can be produced by AND
wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the
down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable

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243

CBD2X2, CBD4X2, CBD8X2, CBD16X2

AND gates within the component. This results in zero propagation from the CEU and
CED inputs and from the Q outputs, provided all connections from each such output
remain on-chip. Otherwise, a macrocell buffer delay is introduced.
The counter is initialized to zero (TCU Low and TCD High) when power is applied.
The power-on condition can be simulated by applying a High-level pulse on the
PRLD global net.

Inputs

Outputs

CEU

CED

Dz D0

Qz Q0

TCU

TCD

CEOU

CEOD

CEOD

CEOD

Dn

Dn

TCU

TCD

CEOU

CEOD

Dn

Dn

TCU

TCD

CEOU

CEOD

No Chg

No Chg

No Chg

Inc

TCU

TCD

CEOU

Inc

TCU

TCD

CEOU

Dec

TCU

TCD

CEOD

Dec

TCU

TCD

CEOD

Inc

TCU

TCD

Invalid

Invalid

Inc

TCU

TCD

Invalid

Invalid

z = 1 for CBD2X2; z = 3 for CBD4X2; z = 7 for CBD8X2; z = 15 for CBD16X2

TCU = QzQ(z-1)Q(z-2)...Q0
TCD = QzQ(z-1)Q(z-2)...Q0
CEOU = TCUCEU
CEOD = TCDCED

244

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Libraries Guide
ISE 6.3i

CBD2X2, CBD4X2, CBD8X2, CBD16X2

Q3
Q2

Q1
Q0

OR2

CED
TCU

OR2
R
AND4B3

AND4
TCD
INV

FDD
AND3B2

CEQD

OR3

Q
AND3B1

XOR2
C

CEQU

AND3B2

Q0

D0

AND2

AND3B1
CEU
OR2

AND5B4

GND

FDD
AND4B2

OR3
D
XOR2

AND3B2

Q1

D1

AND3B1

INV
INV
INV
INV
INV

AND6

FDDC

OR3
D

AND5B2
XOR2

C
Q2

AND3B2
D2

AND3B1

INV
INV
INV
INV
INV
INV

AND7

INV
INV

FDDC

OR3
D

AND6
XOR2

C
Q3

AND3B2
D3

AND3B1
INV
INV
INV
INV
INV
INV
INV

AND7

INV
INV
INV
INV
INV

FDDC

AND7
D

NOR5
INV

C
TCDINV

AND6

AND5B4
C
X9659

CBD4X2 Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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1-800-255-7778

245

246

CBD2X2, CBD4X2, CBD8X2, CBD16X2

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Libraries Guide
ISE 6.3i

CC8CE, CC16CE

CC8CE, CC16CE
8-, 16-Bit Cascadable Binary Counters with Clock Enable and
Asynchronous Clear
Architectures Supported
CC8CE, CC16CE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

CC8CE

Q[7:0]

CE

CEO

TC

CLR

X4290

CC16CE

Q[15:0]

CE

CEO

TC

CLR
X4286

No

CoolRunner XPLA3

No

CoolRunner-II

No

CC8CE and CC16CE are, respectively, 8- and 16-bit (stage), asynchronous clearable,
cascadable binary counters. These counters are implemented using carry logic with
relative location constraints to ensure efficient placement of logic. The asynchronous
clear (CLR) is the highest priority input. When CLR is High, all other inputs are
ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic
level zero, independent of clock transitions. The Q outputs increment when the clock
enable input (CE) is High during the Low-to-High clock (C) transition. The counter
ignores clock transitions when CE is Low. The TC output is High when all Q outputs
are High.
Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the C and CLR inputs in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, with Low outputs, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

CE

No Chg

No Chg

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Qz Q0

TC

CEO

247

CC8CE, CC16CE

Inputs

Outputs

CLR

CE

Qz Q0

TC

CEO

Inc

TC

CEO

z = 7 for CC8CE; z = 15 for CC16CE

TC = QzQ(z-1)Q(z-2)...Q0
CEO = TCCE

TC
CEO
Q[7:0]

AND2

Q7

MUXCY O
RLOC=R0C0.S1
S
0 1
CI
DI
LI
CI
C7

Q6

C4
Q3

C3
Q2

Q1

C1
Q0

GND
VCC

C0

Q6

C6
Q6

D
Q
CE
C
CLR

I4
I3
I2
I1

TQ6

FMAP
Q5

C5
Q5

I4
I3
I2
I1

TQ5

RLOC=R1C0.S0
FMAP

FDCE
O TQ4

TQ7

RLOC=R0C0.S0

RLOC=R1C0.S0
Q4

C4
Q4

I4
I3
I2
I1

TQ4

RLOC=R1C0.S0
RLOC=R1C0.S0
FMAP
FDCE
O TQ3

D
Q
CE
C
CLR

Q3

C3
Q3

D
Q
CE
C
CLR

Q2

C2
Q2

Q1

C1
Q1

D
Q
CE
C
CLR

TQ2

I4
I3
I2
I1

TQ1

FMAP

FDCE

XORCY

RLOC=R3C0.S0

RLOC=R3C0.S0
O TQ0

I4
I3
I2
I1

FMAP

FDCE
D
Q
CE
C
CLR

TQ3

RLOC=R2C0.S0

RLOC=R2C0.S0

O TQ1

FMAP

FDCE
O TQ2

I4
I3
I2
I1

RLOC=R2C0.S0

RLOC=R2C0.S0

XORCY

MUXCY_L LO
S
RLOC=R3C0.S1
0 1
CI
DI
LI
CI

D
Q
CE
C
CLR

FMAP

FDCE
O TQ5

XORCY

MUXCY_L LO
S
RLOC=R3C0.S1
0 1
CI
DI
LI
CI

D
Q
CE
C
CLR

I4
I3
I2
I1

RLOC=R0C0.S0

RLOC=R0C0.S0

XORCY

MUXCY_L LO
S
RLOC=R2C0.S1
0 1
DI
CI
LI
CI
C2

O TQ6

XORCY

MUXCY_L LO
RLOC=R2C0.S1
S
0 1
CI
DI
LI
CI

C7
Q7

FDCE

XORCY

MUXCY_L LO
S
RLOC=R1C0.S1
0 1
CI
DI
LI
CI

D
Q
CE
C
CLR

Q7

RLOC=R0C0.S0

XORCY

MUXCY_L LO
RLOC=R1C0.S1
S
0 1
CI
DI
LI
CI
C5

Q4

XORCY

MUXCY_L LO
S
RLOC=R0C0.S1
0 1
DI
CI
LI
CI
C6

Q5

FMAP
FDCE
O TQ7

Q0

C0
Q0

I4
I3
I2
I1

TQ0

RLOC=R3C0.S0
RLOC=R3C0.S0

CE
C
CLR

X8890

CC8CE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

248

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1-800-255-7778

Libraries Guide
ISE 6.3i

CC8CE, CC16CE

TC

CEO
AND2
Q[7:0]

O
Q7

MUXCY
0
DI

RLOC=X0Y3

1
CI

FDCE

LI
O

TQ7

CI

XORCY
C7

C
CLR

LO
S

Q6

MUXCY_L
0
DI

Q7

CE

RLOC=X0Y3
RLOC=X0Y3

1
CI

FDCE

LI
O

TQ6

CI

Q6

CE

XORCY

C6

CLR

LO
S

Q5

MUXCY_L
0
1
DI

RLOC=X0Y3

RLOC=X0Y2

CI

FDCE

LI
O

TQ5

CI

C
CLR

LO
S

Q4

MUXCY_L
0
DI

Q5

CE

XORCY
C5

RLOC=X0Y2
RLOC=X0Y2

1
CI

FDCE

LI
O

TQ4

CI

Q4

CE

XORCY

C4

CLR

LO
S

Q3

MUXCY_L
0
DI

RLOC=X0Y1

RLOC=X0Y2

1
CI

FDCE

LI
O

TQ3

CI

XORCY
C3

C
CLR

LO
S

Q2

MUXCY_L
0
1
DI

Q3

CE

RLOC=X0Y1
RLOC=X0Y1

CI

FDCE

LI
O

TQ2

CI

Q2

CE

XORCY

C2

CLR

LO
S

Q1

MUXCY_L
0
1
DI

RLOC=X0Y0

RLOC=X0Y1

CI

FDCE

LI
O

TQ1

CI

C1

CLR

LO
S

Q0

MUXCY_L
0
DI

RLOC=X0Y0
RLOC=X0Y0

1
CI

FDCE

LI
O
CI
XORCY

TQ0

Q0

CE
C

GND
VCC

Q1

CE

XORCY

C0

CLR

RLOC=X0Y0
CE
C
CLR

X9309

CC8CE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

249

250

CC8CE, CC16CE

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CC8CLE, CC16CLE

CC8CLE, CC16CLE
8-, 16-Bit Loadable Cascadable Binary Counters with Clock Enable and
Asynchronous Clear
Architectures Supported
CC8CLE, CC16CLE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D[7:0]

Q[7:0]

CC8CLE

CEO
L
CE

TC

No

CoolRunner XPLA3

No

CoolRunner-II

No

CC8CLE and CC16CLE are, respectively, 8- and 16-bit (stage), synchronously

loadable, asynchronously clearable, cascadable binary counters. These counters are
implemented using carry logic with relative location constraints to ensure efficient
placement of logic.

CLR

D[15:0]

X4289

CC16CLE Q[15:0]
CEO

L
CE

TC

CLR

X4284

The asynchronous clear (CLR) is the highest priority input. When CLR is High, all
other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out
(CEO) go to logic level zero, independent of clock transitions. The data on the D
inputs is loaded into the counter when the load enable input (L) is High during the
Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q
outputs increment when CE is High during the Low-to-High clock transition. The
counter ignores clock transitions when CE is Low. The TC output is High when all Q
outputs are High.
Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the C, L, and CLR inputs in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, with Low output, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

251

CC8CLE, CC16CLE

GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

CE

Dz D0

Qz Q0

TC

CEO

Dn

Dn

TC

CEO

No Chg

No Chg

Inc

TC

CEO

z = 7 for CC8CLE; z = 15 for CC16CLE

TC = QzQ(z-1)Q(z-2)...Q0
CEO = TCCE

252

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1-800-255-7778

Libraries Guide
ISE 6.3i

CC8CLE, CC16CLE

TC
CEO
Q[7:0]

AND2
MUXCY
S 0

Q7

O
RLOC=R0C0.S1

DI

CI

C7
Q6

MUXCY_L
S
0

O TQ7
D7
XORCY

M2_1

Q3

O TQ5
D5
XORCY

Q6

TQ6

O TQ4
D4
XORCY

D0
D1
S0

I2

MD6

D
Q
CE
C CLR

Q5

D5
TQ5

I4
I3
I2

MD5

I1
RLOC=R1C0.S0

LI
CI

D
Q
CE
C CLR

FMAP
Q4

L
D4
TQ4

RLOC=R1C0.S0

O TQ3
D3
XORCY

D0
D1
S0

O MD3

D
Q
CE
C CLR

D2
XORCY

D0
D1
S0

L
D3
TQ3

CI

M2_1
O TQ1
D1
XORCY

D0
D1
S0

D
Q
CE
C CLR

O MD1
D
Q
CE
C CLR

L
D2
TQ2

M2_1
D0
XORCY

MD3

Q1

C0
VCC

I3
I2

MD2

FMAP
L
D1
TQ1

I4
I3
I2

MD1

I1

FDCE
O MD0

I4

I1

RLOC=R3C0.S0

GND

I2

RLOC=R2C0.S0

RLOC=R3C0.S1

D0
D1
S0

I3

FMAP

Q2

FDCE

LO

O TQ0

I4

I1

RLOC=R2C0.S0

LI
CI

MD4

FDCE
O MD2

RLOC=R3C0.S1

CI

RLOC=R2C0.S0

M2_1
O TQ2

LO

I2

FMAP
Q3

RLOC=R2C0.S0

C1

I3

RLOC=R1C0.S0

FDCE

LO

LI
CI

I4

I1

M2_1

LI
CI

DI

I3
I1

FDCE
O MD4

RLOC=R2C0.S1

DI

I4

FMAP

M2_1

LI
CI

C2

MD7

RLOC=R0C0.S0

FDCE
O MD5

LO

CI

MUXCY_L

FMAP
D6

RLOC=R1C0.S0
CI

DI

MUXCY_L
S
0

I2

RLOC=R0C0.S0
L

RLOC=R2C0.S1

Q0

D0
D1
S0

I3

RLOC=R1C0.S1

C3

Q1

D
Q
CE
C CLR

I4

I1

RLOC=R0C0.S0

LO

CI

MUXCY_L

O MD6

DI

Q2

Q7

FDCE

M2_1

LI
CI

C4
MUXCY_L

D0
D1
S0

RLOC=R1C0.S1
CI

MUXCY_L
S
0
DI

D6
XORCY

C5
Q4

O TQ6

LO
1

DI

D
Q
CE
C CLR
RLOC=R0C0.S0

C6
MUXCY_L

O MD7

D7
TQ7

RLOC=R0C0.S1
CI
LI
CI

D0
D1
S0

FDCE

LO
1

DI

Q5

FMAP
L
M2_1

LI
CI

RLOC=R3C0.S0

Q0
D
Q
CE
C CLR
RLOC=R3C0.S0

FMAP
L
D0
TQ0

I4
I3
I2

MD0

I1
D[7:0]

RLOC=R3C0.S0

L
CE

L_CE

C
CLR

OR2
X8891

CC8CLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

253

CC8CLE, CC16CLE

TC

CEO
AND2
Q[7:0]

O
Q7

MUXCY
0
1
DI

RLOC=X0Y3

FMAP

CI

M2_1

LI
O

FDCE

D0

TQ7

CI

O
D7

MD7

D1

S0

CE

XORCY
C7

LO
Q6

MUXCY_L
0
1
DI

D7
Q

Q7

TQ7

CLR

FMAP
L

M2_1
O

FDCE

D6

D0

TQ6

O
D6

MD6

D1

S0

CE

XORCY
C6

Q6

TQ6

RLOC=X0Y2

CLR

FDCE
O

D5

MD5

D1

S0

CE

C5

LO

DI

D5

D0

TQ5

Q5

TQ5

CLR

M2_1
O

FMAP

FDCE

D4

D0

TQ4

O
D4

MD4

D1

S0

CE

C4

Q4

TQ4

RLOC=X0Y1

CLR

M2_1
O

FDCE

D3

D0

TQ3

O
D3

MD3

D1

S0

CE

XORCY
C3

LO

Q3

TQ3

CLR

FMAP

FDCE

D2

D0

TQ2

O
D2

MD2

D1

S0

CE

C2

Q2

TQ2

RLOC=X0Y0

CLR

FDCE
O

D1

MD1

D1

S0

CE

XORCY

LO

Q1

TQ1

I4
I3
O

MD1

I2
I1

CLR

RLOC=X1Y0

RLOC=X0Y0

FMAP

RLOC=X1Y0

CI

M2_1

LI
O

FDCE
O

D0

MD0

D1

S0

CE

XORCY
GND

D0

D0

TQ0

CI

VCC

D1

D0

TQ1

CI

MD2

FMAP
L

M2_1

C1

DI

O
I2

RLOC=X1Y1

CI

MUXCY_L
0
1

I3

RLOC=X1Y1

LI

I4

I1

LO

Q0

MD3

RLOC=X1Y1

M2_1

XORCY

DI

O
I2
I1

CI

MUXCY_L
0
1

I3

RLOC=X1Y1

CI

I4

RLOC=X0Y1

LI

Q1

MD4

FMAP
L

LI

DI

O
I2

RLOC=X1Y2

CI

MUXCY_L
0
1

I3

RLOC=X1Y2

CI

I4

I1

LO

Q2

MD5

RLOC=X1Y2

XORCY

DI

O
I2
I1

CI

MUXCY_L
0
1

I3

RLOC=X1Y2

LI

I4

RLOC=X0Y2

CI

Q3

MD6

FMAP
L

M2_1

XORCY

MUXCY_L
0
1

O
I2

RLOC=X1Y3

CI
LI

I3

RLOC=X1Y3

CI

Q4

I4

I1

LO

DI

MD7

RLOC=X1Y3

RLOC=X1Y3

LI

O
I2

RLOC=X0Y3

CI

Q5

I3

I1

CI

MUXCY_L
0
1

I4

C
C0

Q0

TQ0

I4
I3
O

MD0

I2
I1

CLR

RLOC=X1Y0

RLOC=X1Y0
D[7:0]
L
L_CE
CE
C

OR2

CLR

X9310

CC8CLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

254

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CC8CLED, CC16CLED

CC8CLED, CC16CLED
8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with
Clock Enable and Asynchronous Clear
Architectures Supported
CC8CLED, CC16CLED
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D[7:0]

CC8CLED Q[7:0]
CEO

UP

TC

L
CE
C

CLR

X4287

D[15:0] CC16CLED Q[15:0]

CEO
UP

TC

L
CE
C

CLR

X4285

No

CoolRunner XPLA3

No

CoolRunner-II

No

CC8CLED and CC16CLED are, respectively, 8- and 16-bit (stage), synchronously

loadable, asynchronously clearable, cascadable, bidirectional binary counters. These
counters are implemented using carry logic with relative location constraints, which
assures most efficient logic placement.
The asynchronous clear (CLR) is the highest priority input. When CLR is High, all
other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out
(CEO) go to logic level zero, independent of clock transitions. The data on the D
inputs is loaded into the counter when the load enable input (L) is High during the
Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q
outputs decrement when CE is High and UP is Low during the Low-to-High clock
transition. The Q outputs increment when CE and UP are High. The counter ignores
clock transitions when CE is Low.
For counting up, the TC output is High when all Q outputs and UP are High. For
counting down, the TC output is High when all Q outputs and UP are Low. To
cascade counters, the count enable out (CEO) output of each counter is connected to
the CE pin of the next stage. The clock, UP, L, and CLR inputs are connected in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, outputs Low, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

255

CC8CLED, CC16CLED

Inputs

Outputs

CLR

CE

UP

Dz D0

Qz Q0

TC

CEO

Dn

Dn

TC

CEO

No Chg

No Chg

Inc

TC

CEO

Dec

TC

CEO

z = 7 for CC8CLED; z = 15 for CC16CLED

TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP)
CEO = TCCE

TC
CEO

AND2
Q[7:0]

INV DN7

SQ7

Q7

XOR2

RLOC=R0C0.S1

MUXCY

0
DI

1
CI

FMAP

UP
Q7

I4
I3
I2
I1

LI
CI

D7

D0
D1
S0

FDCE
O

MD7

INV DN6

SQ6

XOR2

D
Q
CE
C
CLR

FMAP
Q7

L
D7
TQ7

I4
I3
I2
I1

MD7

RLOC=R0C0.S0

LO

Q6

FMAP

UP
Q6

M2_1

TQ7

C7

RLOC=R0C0.S1

I4
I3
I2
I1

O
XORCY

SQ7

RLOC=R0C0.S0

RLOC=R0C0.S1

MUXCY_L

0
DI

1
CI

FMAP
M2_1

LI
CI

SQ6

TQ6
D6

XORCY

D0
D1
S0

FDCE
O

MD6

C6
RLOC=R0C0.S1

D
Q
CE
C
CLR

Q6

L
D6
TQ6

I4
I3
I2
I1

MD6

RLOC=R0C0.S0

RLOC=R0C0.S0

UP
Q5

I4
I3
I2
I1

LO

INV DN5

FMAP

SQ5

Q5

XOR2
O

RLOC=R1C0.S1

MUXCY_L

0
DI

FMAP

1
CI

SQ5

M2_1

LI
CI

TQ5
D5

XORCY

RLOC=R1C0.S1

D0
D1
S0

FDCE
O

MD5

C5

FMAP

UP
Q4

I4
I3
I2
I1

SQ4

SQ4

XOR2

L
D4
TQ4

M2_1

TQ4
D4

XORCY

INV DN3

SQ3

SQ3

Q3

XOR2

0
DI

M2_1

TQ3
D3

XORCY

D0
D1
S0

MD3

SQ2
SQ2

XOR2

1
CI

M2_1
O

TQ2
D2

D0
D1
S0

MD2

D
Q
CE
C
CLR

Q1

XOR2

L
D1
TQ1

M2_1

LI
CI

TQ1
D1

XORCY

D0
D1
S0

MD1

SQ0
XOR2

MD1

Q1

L
D0
TQ0

I4
I3
I2
I1

MD0

RLOC=R3C0.S0

RLOC=R3C0.S1

MUXCY_L

0
DI

1
CI

M2_1

LI
CI

TQ0
D0

XORCY
GND

D
Q
CE
C
CLR
RLOC=R3C0.S0

LO

INV DN0

FMAP

FDCE
O

C1

Q0

I4
I3
I2
I1

1
CI

SQ0

RLOC=R3C0.S1

MD2

RLOC=R3C0.S0

FMAP
O

RLOC=R3C0.S1

MUXCY_L

0
DI

I4
I3
I2
I1

FMAP

Q2

RLOC=R2C0.S0
LO
SQ1

MD3

FDCE
O

C2

INV DN1

RLOC=R2C0.S0

XORCY
SQ1

I4
I3
I2
I1

FMAP
L
D2
TQ2

MUXCY_L

0
DI

MD4

Q3

RLOC=R2C0.S1

LI
CI

D
Q
CE
C
CLR

RLOC=R2C0.S0

RLOC=R2C0.S0
LO

INV DN2

RLOC=R3C0.S1

UP
Q0

I4
I3
I2
I1

FMAP
L
D3
TQ3

FDCE

C3

MD5

RLOC=R1C0.S0

1
CI

FMAP

I4
I3
I2
I1

Q4

MUXCY_L

LI
CI

Q2

UP
Q1

D
Q
CE
C CLR
RLOC=R1C0.S0

RLOC=R2C0.S1

I4
I3
I2
I1

MD4

RLOC=R2C0.S1

FMAP

UP
Q2

FDCE
O

C4
LO

RLOC=R2C0.S1

I4
I3
I2
I1

D0
D1
S0

FMAP

RLOC=R1C0.S1

LI
CI

I4
I3
I2
I1

RLOC=R1C0.S0

1
CI

FMAP

UP
Q3

Q5

MUXCY_L

0
DI

RLOC=R1C0.S1

I4
I3
I2
I1

D
Q
CE
C
CLR
RLOC=R1C0.S0

LO

INV DN4
Q4
O

L
D5
TQ5

D0
D1
S0

FDCE
O

MD0

C0

D
Q
CE
C
CLR

Q0

RLOC=R3C0.S0

VCC
UP

D[7:0]
L
CE
C
CLR

L_CE
OR2
X8892

CC8CLED Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

256

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CC8CLED, CC16CLED

TC

CEO
AND2
Q[7:0]

FMAP
O

I4
DN7

I3
O

UP

I2

Q7

I1

SQ7
Q7

SQ7

INV

XOR2

MUXCY
0
1
DI
CI

RLOC=X0Y3

FMAP
L

M2_1

LI
O

RLOC=X0Y3

TQ7

O
D7

I4

I1

S0

CE

LO
O

I2

SQ6
Q6

SQ6

INV

XOR2

M2_1
O

TQ6

Q5

D1

S0

CE

SQ5

INV

XOR2

I1

TQ5

MD5

D1

S0

CE

Q4

SQ4

INV

XOR2

M2_1
O

TQ4

XORCY

MD4

D1

S0

CE

LO

Q3

Q3

SQ3

INV

XOR2

I1

M2_1

LI
O

CI

TQ3

D0
D3

XORCY

C3

I4
O

SQ2

Q2

SQ2

INV

I2

XOR2

MD3

S0

CE

TQ2

RLOC=X0Y1

D2
XORCY

Q1

Q1

SQ1

INV

XOR2

D1

S0

CE

Q0

D1
MD1

D1

SQ0
XOR2

S0

CE

Q1
TQ1

I4
I3
O

MD1

I2
I1

CLR

MUXCY_L
0
1
DI
CI

RLOC=X1Y0

RLOC=X0Y0
RLOC=X1Y0

M2_1

LI

I1

TQ0

FDCE

D0
O

D0

RLOC=X0Y0

FMAP
L

D0

CI
XORCY

MD0

D1

S0

CE

Q0
TQ0

I4
I3
O

MD0

I2
I1

C0
VCC

DN0
INV

FDCE
O

D1

Q0

MD2

RLOC=X1Y1

D0

XORCY

C1

SQ0

O
I2

FMAP
M2_1
TQ1

LO

I3

I1

CI

I2

TQ2

I4

RLOC=X1Y1

LI

I3

MD3

RLOC=X0Y0

I1

I4

Q2

CLR

MUXCY_L
0
1
DI
CI

UP

O
I2

RLOC=X0Y0

FMAP

I3

FMAP
D2

MD2

LO
DN1
SQ1

I4

RLOC=X1Y1

FDCE
O

C2

D3
TQ3

D0

CI

I2

Q3

I1

M2_1

LI

I3

FMAP
L

FDCE
O

D1

RLOC=X1Y1

I1

I4

RLOC=X1Y2

RLOC=X0Y1

UP

MD4

I1

CLR

MUXCY_L
0
1
DI
CI

FMAP

O
I2

DN2

I3

TQ4

I3

RLOC=X1Y2

LO

UP

Q4

I4

RLOC=X0Y1

RLOC=X0Y1

Q2

CLR

MUXCY_L
0
1
DI
CI

FMAP

D4

DN3
SQ3

FMAP

FDCE
O

D4

MD5

RLOC=X1Y2

D0

CI

I2

O
I2
I1

C4

I3

I3

RLOC=X1Y2

LI

I4

I4

RLOC=X0Y2

RLOC=X0Y2

UP

TQ5

CLR

MUXCY_L
0
1
DI
CI

FMAP

D5
Q5

LO
SQ4

MD6

FMAP

FDCE
O

XORCY

DN4
O

I1

O
I2

RLOC=X1Y3

D0
D5

I2

I3

I1

M2_1
O

C5

I3

I4

RLOC=X1Y3

CI

I4

TQ6

RLOC=X0Y2

LI

UP

Q6

CLR

MUXCY_L
0
1
DI
CI

FMAP

D6
Q

LO
Q5

RLOC=X0Y2

Q4

MD6

DN5
SQ5

FMAP

FDCE
O

D6

MD7

RLOC=X1Y3

D0

XORCY

I2

O
I2
I1

C6

I3

TQ7

I3

RLOC=X1Y3

LI

I4

Q7

I4

RLOC=X0Y3

CI

FMAP

CLR

MUXCY_L
0
1
DI
CI

RLOC=X0Y3

UP

MD7

D1

DN6

I3
UP
Q6

XORCY

C7

D7

D0

CI

FMAP

FDCE

CLR

RLOC=X1Y0

GND
RLOC=X1Y0

UP
D[7:0]
L
L_CE
CE
C

OR2
X9311

CLR

CC8CLED Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

257

258

CC8CLED, CC16CLED

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CC8RE, CC16RE

CC8RE, CC16RE
8-, 16-Bit Cascadable Binary Counters with Clock Enable and
Synchronous Reset
Architectures Supported
CC8RE, CC16RE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

CC8RE

Q[7:0]

CE

CEO

TC

X4288

CC16RE

Q[15:0]

CE

CEO

TC

X4283

No

CoolRunner XPLA3

No

CoolRunner-II

No

CC8RE and CC16RE are, respectively, 8- and 16-bit (stage), synchronous resettable,
cascadable binary counters. These counters are implemented using carry logic with
relative location constraints to ensure efficient placement of logic. The synchronous
reset (R) is the highest priority input. When R is High, all other inputs are ignored; the
Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on
the Low-to-High clock (C) transition. The Q outputs increment when the clock enable
input (CE) is High during the Low-to-High clock transition. The counter ignores clock
transitions when CE is Low. The TC output is High when all Q outputs and CE are
High.
Larger counters are created by connecting the CEO output of the first stage to the CE
input of the next stage and connecting the C and R inputs in parallel. CEO is active
(High) when TC and CE are High. The maximum length of the counter is determined
by the accumulated CE-to-TC propagation delays versus the clock period. The clock
period must be greater than n(tCE-TC), where n is the number of stages and the time
tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use
the CEO output if the counter uses the CE input; use the TC output if it does not.
The counter is asynchronously cleared, with Low outputs, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

No Chg

www.xilinx.com
1-800-255-7778

Qz Q0

TC

CEO

259

CC8RE, CC16RE

Inputs

Outputs

CE

Qz Q0

TC

CEO

Inc

TC

CEO

z = 7 for CC8RE; z = 15 for CC16RE

TC = QzQ(z-1)Q(z-2)...Q0CE
CEO = TCCE

TC
CEO
AND2

Q[7:0]

O
MUXCY
Q7

VCC

FMAP

RLOC=R0C0.S1

S
0
DI

1
CI
O

CI

MUXCY_L
Q6

TQ7

D0
Q7

XORCY

C7
LO

CE
Q7

M2_1

LI

R_TQ7

0
DI

D0

TQ6
Q6

XORCY

FDCE

O CE_M6

D1

R_TQ6

S0

0
DI

RLOC=R0C0.S0
O

TQ5

D0
Q5

XORCY

FDCE
R_TQ5

TQ4
Q4

XORCY

D0
D1

FDCE
R_TQ4

S0

TQ4
Q

Q4

RLOC=R1C0.S0
LI

TQ3

D0
Q3

XORCY

FDCE

O CE_M3

R_TQ3

D1

S0

LO

TQ3
Q

Q3

LI

D0

TQ2
Q2

XORCY

Q2

FDCE

O CE_M2

D1

R_TQ2

S0

TQ2
Q

Q2

R_TQ2

I3

I2
I1

FMAP

1
CI

RLOC=R2C0.S0

M2_1

LI

CI

TQ1
Q1

XORCY

C1

D0
D1

R_TQ1

Q1

Q0

M2_1
TQ0
Q0

XORCY

D0
D1

FDCE

O CE_M0

R_TQ0

S0
INV

CEB0

I2
I1

FMAP
CE

RLOC=R3C0.S0

CI

R_TQ1

I3

RLOC=R3C0.S0
CLR

1
CI
LI

RLOC=R3C0.S1

C0

TQ1
Q

I4

CE

AND2B1

CEB1

INV

CE
Q1

FDCE

O CE_M1

S0

LO

S
DI

I4

CLR
RLOC=R3C0.S1

I1

RLOC=R2C0.S0

MUXCY_L

MUXCY_L

I2

CE

AND2B1

CEB2

INV

LO

R_TQ3

I3

FMAP
CE

RLOC=R2C0.S0

M2_1

CI

I4

RLOC=R2C0.S0
CLR

1
CI

C2

RLOC=R2C0.S1

I1

CE

AND2B1

CEB3

INV

MUXCY_L

CE
Q3

M2_1

CI

DI

I2

FMAP

1
CI

C3

DI

R_TQ4

I3

CLR
RLOC=R2C0.S1

I4

RLOC=R1C0.S0

MUXCY_L

DI

I1

CE

AND2B1

CEB4

INV

LO

I2

FMAP
Q4

O CE_M4

R_TQ5

I3

RLOC=R1C0.S0

CE

M2_1

CI

GND
VCC

CLR
RLOC=R1C0.S0

C4

Q0

Q5

1
CI
LI

Q1

TQ5
Q

I4

CE

AND2B1

CEB5

RLOC=R1C0.S1

CE
Q5

O CE_M5

D1
S0

INV

MUXCY_L

R_TQ6

I1
RLOC=R0C0.S0

M2_1

CI

DI

I2

FMAP

1
CI

C5
LO

I3

CLR

LI

Q2

RLOC=R1C0.S1

Q3

Q6

MUXCY_L

Q4

TQ6
Q

I4

CE

AND2B1

CEB6

INV

LO

I1

FMAP
CE
Q6

M2_1

CI

R_TQ7
O

I2

RLOC=R0C0.S0

RLOC=R0C0.S0

C6

CLR

1
CI
LI

Q5

Q7

RLOC=R0C0.S1

TQ7
Q

I3

CE

AND2B1

CEB7

INV

FDCE

O CE_M7

D1
S0

I4

TQ0
Q

Q0

I4
R_TQ0

I3

I2
I1

CE

AND2B1

RLOC=R3C0.S0

C
CLR
RLOC=R3C0.S0

CE
R

X8893

C
GND

CC8RE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

260

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CC8RE, CC16RE

TC

CEO
AND2
Q[7:0]

O
Q7

MUXCY
0
1
DI

VCC
RLOC=X1Y3

FMAP

CI

CE

M2_1

LI
O

D0

TQ7

CI
Q7

CE_M7

D1

TQ7
R_TQ7

S0
INV

LO
S

Q6

MUXCY_L
0
1
DI
CI

AND2B1
CEB7

D0

TQ6

O
Q6

CE_M6

D1

C6

INV

D0

TQ5

O
Q5

CE_M5

D1

INV

D0

TQ4

O
Q4

C4

INV

TQ4
R_TQ4

R_TQ4

I2
I1
RLOC=X0Y2

CLR

FMAP
CE

D0

TQ3

O
Q3

TQ3
R_TQ3

INV

S0

LO

Q3

FDCE

CE_M3

D1

XORCY

Q3
R

I4
I3
O

I1
RLOC=X0Y1

CLR

FMAP

RLOC=X0Y1
CE

M2_1

LI
O

D0

TQ2

CI
Q2

TQ2
R_TQ2

S0
INV

XORCY
C2

Q2

FDCE

CE_M2

D1

R_TQ3

I2

CE

AND2B1
CEB3

RLOC=X1Y1

CI

Q2
R

I4
I3
O

R_TQ2

I2
I1

CE

AND2B1
CEB2

LO

RLOC=X0Y1

CLR

RLOC=X1Y0

FMAP

RLOC=X0Y1

CI

CE

M2_1

LI
O

D0

TQ1

CI
Q1

TQ1
R_TQ1

INV

S0

LO

Q1

FDCE

CE_M1

D1

XORCY
C1

MUXCY_L
0
1
DI
CI

I3

RLOC=X0Y2

CI

Q1
R

I4
I3
O
I1

RLOC=X0Y0

CLR

FMAP

RLOC=X0Y0
CE

M2_1

LI
O

TQ0

D0
O
Q0

TQ0
R_TQ0

S0

Q0
R

I4
I3
O

R_TQ0

I2
I1

CE

AND2B1
INV

XORCY
GND

Q0

FDCE

CE_M0

D1

R_TQ1

I2

CE

AND2B1
CEB1

RLOC=X1Y0

CI

VCC

CE

AND2B1
CEB4

M2_1

C3

Q4

I4

RLOC=X1Y1

LI

Q0

LO

DI

R_TQ5

I1

FMAP
Q4

FDCE

CE_M4

D1
S0

MUXCY_L
0
1

O
I2

RLOC=X0Y2

CLR

CE

XORCY

I3

RLOC=X0Y2

M2_1

CI

Q1

Q5

I4

CE

AND2B1
CEB5

RLOC=X1Y2

LI

DI

CI

MUXCY_L
0
1

Q5
TQ5

R_TQ5

S0

LO

FMAP
CE

Q2

R_TQ6

I1
RLOC=X0Y3

CLR

FDCE

XORCY

MUXCY_L
0
1
DI
CI

O
I2

RLOC=X0Y3

CI

I3

CE

AND2B1
CEB6

M2_1

C5

Q3

Q6

I4

RLOC=X1Y2

LI

DI

LO

MUXCY_L
0
1

Q6
TQ6

R_TQ6

S0

R_TQ7

I1

FMAP
CE
O

Q4

O
I2

RLOC=X0Y3

CLR

FDCE

XORCY

MUXCY_L
0
1
DI
CI

I3

RLOC=X0Y3

M2_1

CI

Q7

I4

CE

RLOC=X1Y3

LI

Q5

XORCY
C7

Q7

FDCE

CEB0

C0

CLR

RLOC=X0Y0

RLOC=X0Y0
CE
R
C

GND

X9312

CC8RE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

261

262

CC8RE, CC16RE

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CD4CE

CD4CE
4-Bit Cascadable BCD Counter with Clock Enable and Asynchronous
Clear
Architectures Supported
CD4CE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

CD4CE

Q0
Q1
Q2
Q3

CE

CEO

TC

CLR

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CD4CE is a 4-bit (stage), asynchronous clearable, cascadable binary-coded-decimal

(BCD) counter. The asynchronous clear input (CLR) is the highest priority input.
When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC),
and clock enable out (CEO) go to logic level zero, independent of clock transitions.
The Q outputs increment when clock enable (CE) is High during the Low-to-High
clock (C) transition. The counter ignores clock transitions when CE is Low. The TC
output is High when Q3 and Q0 are High and Q2 and Q1 are Low.

X4369

The counter recovers from any of six possible illegal states and returns to a normal
count sequence within two clock cycles for Spartan-II, Spartan-IIE, Spartan-3, Virtex,
Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X as shown in the following state
diagram. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the counter
resets to zero or recovers within the first clock cycle.

X2355

Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the CLR and clock inputs
in parallel. CEO is active (High) when TC and CE are High. The maximum length of
the counter is determined by the accumulated CE-to-TC propagation delays versus
the clock period. The clock period must be greater than n(tCE-TC), where n is the
number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

263

CD4CE

When cascading counters, use the CEO output if the counter uses the CE input; use
the TC output if it does not.
The counter is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse to the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

CE

Q3

Q2

Q1

Q0

TC

CEO

Inc

Inc

Inc

Inc

TC

CEO

No Chg

No Chg

No Chg

No Chg

TC

TC = Q3!Q2!Q1Q0
CEO = TCCE

FDCE
D0
INV

D
CE
C

Q0

CLR
Q0

FDCE

AX1
AND2B1

D1
XOR2

D
CE
C

Q1

CLR
Q1

FDCE

AX2
AND2

D2
XOR2

AO3B

D
CE
C

Q2

CLR
AND3

Q2

AND2

FDCE

OX3

AO3A
OR2

D3
XOR2

D
CE
C

Q3

CLR
Q3

TC

C
CLR
AND4B2

CEO

CE
AND2
X7784

CD4CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

264

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CD4CE

VCC

CE
AND2

CLR
C
Q0
Q1
Q2
Q3

AND3B2

FDC
D

Q0

AND5B2

OR3
AND4B3

FDC

CLR

Q0

AND4B2

AND2B1
OR4

Q2
CEO

CLR
AND5B2

Q2

AND4B2
AND4B2

FDC
D

Q1

TC

AND2B1

OR3
AND4B2

AND4B2

CLR

Q1
AND2B1

AND5B1

FDC
D

Q3

OR3
AND5B3

CLR

Q3
AND2B1
X7629

CD4CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element can be inferred.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

265

266

CD4CE

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CD4CLE

CD4CLE
4-Bit Loadable Cascadable BCD Counter with Clock Enable and
Asynchronous Clear
Architectures Supported
CD4CLE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D0

CD4CLE

D1
D2
D3

Q0
Q1
Q2
Q3

L
CE

CEO

TC

CLR

X4370

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CD4CLE is a 4-bit (stage), synchronously loadable, asynchronously clearable, binarycoded-decimal (BCD) counter. The asynchronous clear input (CLR) is the highest
priority input. When CLR is High, all other inputs are ignored; the Q outputs,
terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of
clock transitions. The data on the D inputs is loaded into the counter when the load
enable input (L) is High during the Low-to-High clock (C) transition. The Q outputs
increment when clock enable input (CE) is High during the Low- to-High clock
transition. The counter ignores clock transitions when CE is Low. The TC output is
High when Q3 and Q0 are High and Q2 and Q1 are Low.
The counter recovers from any of six possible illegal states and returns to a normal
count sequence within two clock cycles for Spartan-II, Spartan-IIE, Spartan-3, Virtex,
Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X as shown in the following state
diagram.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the counter resets to
zero or recovers within the first clock cycle.

X2355

Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the CLR, L, and C inputs in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the

Libraries Guide
ISE 6.3i

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267

CD4CLE

clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs
CLR

0
0

CE

Outputs

D3 D0

Q3

Q2

Q1

Q0

TC

CEO

D3 D0

D3

D2

D1

D0

TC

CEO

Inc

Inc

Inc

Inc

TC

CEO

No Chg

No Chg

No Chg

No Chg

TC

TC = Q3!Q2!Q1Q0
CEO = TCCE

FTCLEX
D0
L

D
L
Q
T
CE
C
CLR
Q0

C
CLR

Q0

FTCLEX
D1

D
L
Q
T
CE
C
CLR

T1
AND2B1

Q1

OR_CE_L

Q1

FTCLEX

OR2
D2

D
L
Q
T
CE
C
CLR
Q2

Q2

FTCLEX
D3
TQ2

T2
AND2

AND2

D
L
Q
T
CE
C
CLR
Q3

T3
OR2

TQ03
AND2

Q3
TC

AND4B2
CEO

CE
AND2

X7785

CD4CLE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

268

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Libraries Guide
ISE 6.3i

CD4CLE

Q0
Q1
Q2
Q3

INV
INV
INV

AND5B4

AND6

CEO

FDC
AND4B3

Q
AND5B2

OR4

AND5B3

CLR
AND3B2

Q0

D0

TC

FDC
D

Q
AND4B2

AND2
AND5B3

OR5

CLR
Q2

AND3B2
AND5B3

D2
AND2

FDC
D

AND5B3
OR4

INV
Q

INV AND6

CLR
Q1

AND3B2

INV

D1

INV
INV

AND2

VCC

FDC

INV
AND6

CE

D
OR4

L
AND3B2

CLR
Q3

D3

GRD

AND2

C
CLR
X7628

CD4CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are supported for inference and instantiation.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

269

270

CD4CLE

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CD4RE

CD4RE
4-Bit Cascadable BCD Counter with Clock Enable and Synchronous
Reset
Architectures Supported
CD4RE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

CD4RE

Q0
Q1
Q2
Q3

CE

CEO

TC

X4371

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CD4RE is a 4-bit (stage), synchronous resettable, cascadable binary-coded-decimal

(BCD) counter. The synchronous reset input (R) is the highest priority input. When R
is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock
enable out (CEO) go to logic level zero on the Low-to-High clock (C) transition. The Q
outputs increment when the clock enable input (CE) is High during the Low-to-High
clock transition. The counter ignores clock transitions when CE is Low. The TC output
is High when Q3 and Q0 are High and Q2 and Q1 are Low.
The counter recovers from any of six possible illegal states and returns to a normal
count sequence within two clock cycles for Spartan-II, Spartan-IIE, Spartan-3, Virtex,
Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X as shown in the following state
diagram. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the counter
resets to zero or recovers within the first clock cycle.

X2355

Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the R and clock inputs in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

271

CD4RE

cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CE

Q3

Q2

Q1

Q0

TC

CEO

Inc

Inc

Inc

Inc

TC

CEO

No Chg

No Chg

No Chg

No Chg

TC

TC = Q3!Q2!Q1Q0
CEO = TCCE

FDRE
D0
INV

Q0

CE
C

R
Q0

FDRE

AX1
AND2B1

D1

Q1

CE

XOR2

R
Q1

FDRE

AX2
AND2

D2

A03B

R
Q2

AND3

FDRE

OX3

AO3A
OR2
AND2

Q2

CE

XOR2

D3
XOR2

Q3

CE
C

R
Q3

TC

R
CE

CEO

AND4B2
AND2

X9315

CD4RE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

272

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Libraries Guide
ISE 6.3i

CD4RE

R
Q0
Q1
Q2
Q3

INV

INV
INV

AND5B4

FD
D

AND6

OR3
AND4B3

CEO

FD
Q0

AND5B3

Q
AND5B2

AND3B2
OR4

Q2
TC

AND5B3

AND5B3

AND4B2

FD
D

AND3B2
Q

OR3

INV
C

AND5B3

Q1
INV

AND6

AND3B2

FD

INV
INV

INV
INV
AND6

VCC

OR3

Q3
CE
AND2

AND3B2
X7627

CD4RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element can be inferred.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

273

274

CD4RE

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

CD4RLE

CD4RLE
4-Bit Loadable Cascadable BCD Counter with Clock Enable and
Synchronous Reset
Architectures Supported
CD4RLE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D0

CD4RLE

D1

Q0

D2

Q1
Q2

D3

Q3

L
CE

CEO

TC

R
X4372

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CD4RLE is a 4-bit (stage), synchronous loadable, resettable, binary-coded-decimal

(BCD) counter. The synchronous reset input (R) is the highest priority input. When R
is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock
enable out (CEO) go to logic level zero on the Low-to-High clock transitions. The data
on the D inputs is loaded into the counter when the load enable input (L) is High
during the Low-to-High clock (C) transition. The Q outputs increment when the clock
enable input (CE) is High during the Low-to-High clock transition. The counter
ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are
High and Q2 and Q1 are Low.
The counter recovers from any of six possible illegal states and returns to a normal
count sequence within two clock cycles for Spartan-II, Spartan-IIE, Spartan-3, Virtex,
Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X as shown in the following state
diagram. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the counter
resets to zero or recovers within the first clock cycle.
0

X2355

Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the R, L, and C inputs in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

275

CD4RLE

cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs
R

CE

Outputs

D3 D0

Q3

Q2

Q1

Q0

TC

CEO

D3 D0

D3

D0

TC

CEO

Inc

Inc

Inc

Inc

TC

CEO

No Chg

No Chg

No Chg

No Chg

TC

TC = Q3!Q2!Q1Q0
CEO = TCCE

FTRSLE
D0
L

D S
L
T
CE
C
R

C
R

Q0

Q0

FTRSLE
D1

D S
L
T
CE
C
R

T1
AND2B1

Q1

Q1

FTRSLE
D2

D S
L
T
CE
C
R

Q2

Q2

FTRSLE
D3
TQ2

T2
AND2

AND2

D S
L
T
CE
C
R

T3
OR2

TQ03

Q3

AND2

Q3
TC

AND4B2
CEO

CE
AND2

GND

X7787

CD4RLE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

276

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Libraries Guide
ISE 6.3i

CD4RLE

C
Q0
Q1
Q2
Q3

VCC

CE
AND2

R
L

CEO

INV
INV
INV
OR2

INV
INV

AND5B2
AND6

TC

GND
AND4B2

FD
D

AND5B4

OR4
C

Q0
AND4B3

D0
AND3B1

INV
INV
INV
INV

AND6

INV
INV
INV
INV

FD
D

AND6

OR4
C

Q1
AND4B3

D1
AND3B1

INV
INV

INV
INV

AND7

INV
INV
INV
INV

AND6

FD
INV
INV
INV

OR5
C

INV

AND6

Q2

AND4B3

D2
AND3B1

INV
INV

INV

AND7

INV
INV
INV

FD

INV
INV

AND7

OR4
C

Q3
AND4B3

D3
AND3B1

X7626

CD4RLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

277

CD4RLE

Usage
For HDL, this design element is supported for inference and instantiation.

278

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Libraries Guide
ISE 6.3i

CDD4CE

CDD4CE
4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable
and Asynchronous Clear
Architectures Supported
CDD4CE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

CDD4CE

Q0
Q1
Q2
Q3

CE

CEO

TC

CLR
X9734

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CDD4CE is a 4-bit (stage), asynchronous clearable, cascadable dual edge triggered

Binary-coded-decimal (BCD) counter. The asynchronous clear input (CLR) is the
highest priority input. When CLR is High, all other inputs are ignored; the Q outputs,
terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of
clock transitions. The Q outputs increment when clock enable (CE) is High during the
Low-to-High and High-to-Low clock (C) transition. The counter ignores clock
transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2
and Q1 are Low. The counter recovers to zero from any illegal state within the first
clock cycle.
Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the CLR and clock inputs
in parallel. CEO is active (High) when TC and CE are High. The maximum length of
the counter is determined by the accumulated CE-to-TC propagation delays versus
the clock period. The clock period must be greater than n(tCE-TC), where n is the
number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage.
When cascading counters, use the CEO output if the counter uses the CE input; use
the TC output if it does not.
The counter is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse to the PRLD
global net.

Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

CE

Q3

Q2

Q1

Q0

TC

CEO

Inc

Inc

Inc

Inc

TC

CEO

Inc

Inc

Inc

Inc

TC

CEO

No Chg

No Chg

No Chg

No Chg

TC

www.xilinx.com
1-800-255-7778

279

CDD4CE

Inputs

Outputs

CLR

CE

Q3

Q2

Q1

Q0

TC

CEO

TC = Q3!Q2!Q1Q0
CEO = TCCE

VCC

CE
AND2
CLR
C
Q0
Q1
Q2
Q3

AND3B2

FDDC
D

Q0

AND5B2

OR3
AND4B3

CLR

FDDC
Q0

AND4B2

AND2B1
OR4

Q2
CEO

CLR
AND5B2

Q2

AND4B2
AND4B2

FDDC
D

Q1

TC

AND2B1

OR3
AND4B2

AND4B2
C

CLR
Q1

AND2B1

AND5B1

FDDC
D

Q3

OR3
AND5B3

CLR
Q3

AND2B1
X9735

CDD4CE Implementation CoolRunner-II

Usage
For HDL, this design element is supported for inference and instantiation.

280

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1-800-255-7778

Libraries Guide
ISE 6.3i

CDD4CLE

CDD4CLE
4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with
Clock Enable and Asynchronous Clear
Architectures Supported
CDD4CLE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

D0

CDD4CLE

D2

Q0
Q1
Q2

D3

Q3

D1

L
CE

CEO

TC

CLR

X9736

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CDD4CLE is a 4-bit (stage), synchronously loadable, asynchronously clearable, dual

edge triggered Binary-coded-decimal (BCD) counter. The asynchronous clear input
(CLR) is the highest priority input. When CLR is High, all other inputs are ignored;
the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero,
independent of clock transitions. The data on the D inputs is loaded into the counter
when the load enable input (L) is High during the Low-to-High and High-to-Low
clock (C) transitions. The Q outputs increment when clock enable input (CE) is High
during the Low- to-High clock transition. The counter ignores clock transitions when
CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low.
The counter recovers to zero from any illegal state within the first clock cycle.
Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the CLR, L, and C inputs in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

CE

D3 D0

Q3

Q2

Q1

Q0

TC

CEO

D3 D0

D3

D2

D1

D0

TC

CEO

D3 D0

D3

D2

D1

D0

TC

CEO

Inc

Inc

Inc

Inc

TC

CEO

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281

CDD4CLE

Inputs

Outputs

CLR

CE

D3 D0

Q3

Q2

Q1

Q0

TC

CEO

Inc

Inc

Inc

Inc

TC

CEO

No Chg

No Chg

No Chg

No Chg

TC

TC = Q3!Q2!Q1Q0
CEO = TCCE

Q0
Q1
Q2
Q3

INV
INV
INV

AND5B4

AND6
CEO

FDDC
AND4B3

Q
AND5B2

OR4

AND5B3

C
CLR

AND3B2

TC

FDDC

Q0

D0

Q
AND4B2

AND2
AND5B3

OR5

C
CLR
Q2

AND3B2
AND5B3
D2
AND2

FDDC
D

AND5B3
OR4

INV
Q

INV AND6

CLR
Q1

AND3B2

INV

D1

INV
INV

AND2
VCC

FDDC

INV
AND6

CE

D
OR4

L
AND3B2

CLR
Q3

D3

GRD

AND2
C
CLR

X9737

CDD4CLE Implementation CoolRunner-II

Usage
For HDL, this design element is supported for inference and instantiation.

282

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Libraries Guide
ISE 6.3i

CDD4RE

CDD4RE
4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable
and Synchronous Reset
Architectures Supported
CDD4RE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

CDD4RE

Q0
Q1
Q2
Q3

CE

CEO

TC

X9738

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CDD4RE is a 4-bit (stage), synchronous resettable, cascadable dual edge triggered

binary-coded-decimal (BCD) counter. The synchronous reset input (R) is the highest
priority input. When R is High, all other inputs are ignored; the Q outputs, terminal
count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High or
High-to-Low clock (C) transition. The Q outputs increment when the clock enable
input (CE) is High during the Low-to-High and High-to-Low clock transition. The
counter ignores clock transitions when CE is Low. The TC output is High when Q3
and Q0 are High and Q2 and Q1 are Low. The counter recovers to zero from any
illegal state within the first clock cycle.
Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the R and clock inputs in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

Q3

Q2

Q1

Q0

TC

CEO

Inc

Inc

Inc

Inc

TC

CEO

Inc

Inc

Inc

Inc

TC

CEO

No Chg

No Chg

No Chg

No Chg

TC

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283

CDD4RE

Inputs

Outputs

CE

Q3

Q2

Q1

Q0

TC

CEO

TC = Q3!Q2!Q1Q0
CEO = TCCE

R
Q0
Q1
Q2
Q3

INV

INV
INV

AND5B4

FDD
D

AND6

OR3
AND4B3

CEO

FDD
Q0

AND5B3

Q
AND5B2

AND3B2
OR4

C
Q2
TC

AND5B3
AND5B3

AND4B2

FDD
D

AND3B2
Q

OR3

INV
C

AND5B3

Q1
INV

AND6

AND3B2

FDD

INV
INV

INV
INV
AND6

VCC

OR3
C
Q3

CE
AND2

AND3B2
X9739

CDD4RE Implementation CoolRunner-II

Usage
For HDL, this design element can be inferred but not instantiated.

284

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Libraries Guide
ISE 6.3i

CDD4RLE

CDD4RLE
4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with
Clock Enable and Synchronous Reset
Architectures Supported
CDD4RLE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

D0
D1
D2
D3

CDD4RLE

Q0
Q1
Q2
Q3

L
CE

CEO

TC

R
X9740

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CDD4RLE is a 4-bit (stage), synchronous loadable, resettable, dual edge triggered

binary-coded-decimal (BCD) counter. The synchronous reset input (R) is the highest
priority input. When R is High, all other inputs are ignored; the Q outputs, terminal
count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High or
High-to-Low clock transitions. The data on the D inputs is loaded into the counter
when the load enable input (L) is High during the Low-to-High and High-to-Low
clock (C) transition. The Q outputs increment when the clock enable input (CE) is
High during the Low-to-High and High-to-Low clock transition. The counter ignores
clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High
and Q2 and Q1 are Low. The counter recovers to zero from any illegal state within the
first clock cycle.
Larger counters are created by connecting the count enable out (CEO) output of the
first stage to the CE input of the next stage and connecting the R, L, and C inputs in
parallel. CEO is active (High) when TC and CE are High. The maximum length of the
counter is determined by the accumulated CE-to-TC propagation delays versus the
clock period. The clock period must be greater than n(tCE-TC), where n is the number
of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
cascading counters, use the CEO output if the counter uses the CE input; use the TC
output if it does not.
The counter is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

D3 D0

Q3

Q2

Q1

Q0

TC

CEO

D3 D0

D3

D2

D1

D0

TC

CEO

D3 D0

D3

D2

D1

D0

TC

CEO

Inc

Inc

Inc

Inc

TC

CEO

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CDD4RLE

Inputs

Outputs

CE

D3 D0

Q3

Q2

Q1

Q0

TC

CEO

Inc

Inc

Inc

Inc

TC

CEO

No Chg

No Chg

No Chg

No Chg

TC

TC = Q3!Q2!Q1Q0
CEO = TCCE
C
Q0
Q1

VCC

Q2
Q3

CE
AND2

CEO

INV
INV
INV

R
L
OR2

INV
INV

AND5B2
AND6
TC

GND
AND4B2

FDD
D

AND5B4

OR4
C
Q0
AND4B3
D0
AND3B1

INV
INV
INV
INV

AND6

INV
INV
INV
INV

FDD
D

AND6

OR4
C
Q1
AND4B3
D1
AND3B1

INV
INV

INV
INV

AND7

INV
INV
INV
INV

AND6

FDD
INV
INV
INV

OR5
C

INV

AND6
Q2

AND4B3
D2
AND3B1

INV
INV

INV

AND7

INV
INV
INV

FDD

INV
INV

AND7

OR4
C
Q3
AND4B3
D3
AND3B1
X9741

CDD4RLE Implementation CoolRunner-II

Usage
For HDL, this design element can be inferred but not instantiated.

286

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Libraries Guide
ISE 6.3i

CJ4CE, CJ5CE, CJ8CE

CJ4CE, CJ5CE, CJ8CE

4-, 5-, 8-Bit Johnson Counters with Clock Enable and Asynchronous
Clear
Architectures Supported
CJ4CE, CJ5CE, CJ8CE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

CJ4CE

Q0
Q1

CE

Q2
Q3

CLR

X4112

CJ5CE

Q0
Q1
Q2

CE

Q3

Q4

CLR

X4114

CJ8CE

Q[7:0]

CE
C

CLR

X4118

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CJ4CE, CJ5CE, and CJ8CE are clearable Johnson/shift counters. The asynchronous
clear (CLR) input, when High, overrides all other inputs and causes the data (Q)
outputs to go to logic level zero, independent of clock (C) transitions. The counter
increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the clock enable input (CE)
is High during the Low-to-High clock transition. Clock transitions are ignored when
CE is Low.
For CJ4CE, the Q3 output is inverted and fed back to input Q0 to provide continuous
counting operation. For CJ5CE, the Q4 output is inverted and fed back to input Q0.
For CJ8CE, the Q7 output is inverted and fed back to input Q0.
The counter is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
CJ4CE Truth Table
Inputs

Outputs

CLR

CE

Q0

Q1

Q2

Q3

No Chg

No Chg

No Chg

No Chg

q3

q0

q1

q2

q = state of referenced output one setup time prior to active clock transition

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ISE 6.3i

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287

CJ4CE, CJ5CE, CJ8CE

CJ5CE Truth Table

Inputs

Outputs

CLR

CE

Q0

Q1

Q2

Q3

Q4

No Chg

No Chg

No Chg

No Chg

No Chg

q4

q0

q1

q2

q3

q = state of referenced output one setup time prior to active clock transition

CJ8CE Truth Table

Inputs

Outputs

CLR

CE

Q0

Q1 Q7

No Chg

No Chg

q7

q0 q6

q = state of referenced output one setup time prior to active clock transition

Q[7:0]
Q7

FDCE
FDCE
Q7B
INV

D
CE
C

Q3
Q

Q0

D
CE
C

Q4

CLR
CLR

Q4
Q0

FDCE
FDCE
D
CE
C

Q1

D
CE
C

Q5

CLR

CLR

Q5
Q1

FDCE
FDCE
D
CE
C

Q2

D
CE
C

Q6

CLR

CLR

Q6
Q2

FDCE
FDCE
D
CE
C

Q3

D
CE
C

CLR

Q7

CLR
Q7

Q3
CE
C
CLR

X7789

CJ8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element can be inferred but not instantiated.

288

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Libraries Guide
ISE 6.3i

CJ4RE, CJ5RE, CJ8RE

CJ4RE, CJ5RE, CJ8RE

4-, 5-, 8-Bit Johnson Counters with Clock Enable and Synchronous
Reset
Architectures Supported
CJ4RE, CJ5RE, CJ8RE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

CJ4RE

Q0
Q1

CE

Q2

Q3

X4113

CJ5RE

Q0
Q1
Q2

CE

Q3

Q4

X4115

CJ8RE

Q[7:0]

CE
C

X4119

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CJ4RE, CJ5RE, and CJ8RE are resettable Johnson/shift counters. The synchronous
reset (R) input, when High, overrides all other inputs and causes the data (Q) outputs
to go to logic level zero during the Low-to-High clock (C) transition. The counter
increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE)
is High during the Low-to-High clock transition. Clock transitions are ignored when
CE is Low.
For CJ4RE, the Q3 output is inverted and fed back to input Q0 to provide continuous
counting operations. For CJ5RE, the Q4 output is inverted and fed back to input Q0.
For CJ8RE, the Q7 output is inverted and fed back to input Q0.
The counter is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
CJ4RE Truth Table
Inputs

Outputs

CE

Q0

Q1

Q2

Q3

No Chg

No Chg

No Chg

No Chg

q3

q0

q1

q2

q = state of referenced output one setup time prior to active clock transition

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289

CJ4RE, CJ5RE, CJ8RE

CJ5RE Truth Table

Inputs

Outputs

CE

Q0

Q1

Q2

Q3

Q4

No Chg

No Chg

No Chg

No Chg

No Chg

q4

q0

q1

q2

q3

q = state of referenced output one setup time prior to active clock transition

CJ8RE Truth Table

Inputs

Outputs

CE

Q0

Q1 Q7

No Chg

No Chg

q7

q0 q6

q = state of referenced output one setup time prior to active clock transition

Q[7:0]
Q7

FDRE
FDRE
Q7B
INV

D
CE
C

Q3
Q

Q0

D
CE
C

Q4

R
R

Q4
Q0

FDRE
FDRE
D
CE
C

Q1

D
CE
C

Q5

Q5
Q1

FDRE
FDRE
D
CE
C

Q2

D
CE
C

Q6

Q6
Q2

FDRE
FDRE
D
CE
C

Q3

D
CE
C

Q7

Q7
Q3

CE
C
R

X7790

CJ8RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element can be inferred but not instantiated.

290

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Libraries Guide
ISE 6.3i

CJD4CE, CJD5CE, CJD8CE

CJD4CE, CJD5CE, CJD8CE

4-, 5-, 8-Bit Dual Edge Triggered Johnson Counters with Clock Enable
and Asynchronous Clear
Architectures Supported
CJD4CE, CJD5CE, CJD8CE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

CJD4CE
Q0
Q1
CE

Q2
Q3

CLR
X9742

CJD5CE

Q0
Q1
Q2

CE

Q3

Q4

CLR

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CJD4CE, CJD5CE, and CJD8CE are dual edge triggered clearable Johnson/shift
counters. The asynchronous clear (CLR) input, when High, overrides all other inputs
and causes the data (Q) outputs to go to logic level zero, independent of clock (C)
transitions. The counter increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the
clock enable input (CE) is High during the Low-to-High and High-to-Low clock
transition. Clock transitions are ignored when CE is Low.
For CJD4CE, the Q3 output is inverted and fed back to input Q0 to provide
continuous counting operations. For CJD5CE, the Q4 output is inverted and fed back
to input Q0. For CJD8CE, the Q7 output is inverted and fed back to input Q0.
The counter is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

X9743

CJD4CE Truth Table

CJD8CE

Q[7:0]

Inputs

CE
C

CLR

X9744

Outputs

CLR

CE

Q0

Q1

Q2

Q3

No Chg

No Chg

No Chg

No Chg

!q3

q0

q1

q2

!q3

q0

q1

q2

q = state of referenced output one setup time prior to active clock transition

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ISE 6.3i

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291

CJD4CE, CJD5CE, CJD8CE

CJD5CE Truth Table

Inputs

Outputs

CLR

CE

Q0

Q1

Q2

Q3

Q4

No Chg

No Chg

No Chg

No Chg

No Chg

!q4

q0

q1

q2

q3

!q4

q0

q1

q2

q3

q = state of referenced output one setup time prior to active clock transition

CJD8CE Truth Table

Inputs

Outputs

CLR

CE

Q0

Q1 Q7

No Chg

No Chg

!q7

q0 q6

!q7

q0 q6

q = state of referenced output one setup time prior to active clock transition

Usage
For HDL, this design element can be inferred but not instantiated.

292

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Libraries Guide
ISE 6.3i

CJD4RE, CJD5RE, CJD8RE

CJD4RE, CJD5RE, CJD8RE

4-, 5-, 8-Bit Dual Edge Triggered Johnson Counters with Clock Enable
and Synchronous Reset
Architectures Supported
CJD4RE, CJD5RE, CJD8RE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

CJD4RE

Q0
Q1

CE

Q2

Q3

X9745

CJD5RE

Q1
Q2
Q3

Q4

CoolRunner XPLA3

No

CoolRunner-II

Macro

CJD4RE, CJD5RE, and CJD8RE are resettable dual edge triggered Johnson/shift
counters. The synchronous reset (R) input, when High, overrides all other inputs and
causes the data (Q) outputs to go to logic level zero during the Low-to-High and
High-to-Low clock (C) transition. The counter increments (shifts Q0 to Q1, Q1 to Q2,
and so forth) when the clock enable input (CE) is High during the Low-to-High and
High-to-Low clock transition. Clock transitions are ignored when CE is Low.
For CJD4RE, the Q3 output is inverted and fed back to input Q0 to provide
continuous counting operations. For CJD5RE, the Q4 output is inverted and fed back
to input Q0. For CJD8RE, the Q7 output is inverted and fed back to input Q0.

Q0

CE

No

The counter is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

X9746

CJD4RE Truth Table

CJD8RE
CE
C

Inputs

Q[7:0]

X9747

Outputs

CE

Q0

Q1

Q2

Q3

No Chg

No Chg

No Chg

No Chg

q3

q0

q1

q2

q3

q0

q1

q2

q = state of referenced output one setup time prior to active clock transition

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ISE 6.3i

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CJD4RE, CJD5RE, CJD8RE

CJD5RE Truth Table

Inputs

Outputs

CE

Q0

Q1

Q2

Q3

Q4

No Chg

No Chg

No Chg

No Chg

No Chg

q4

q0

q1

q2

q3

q4

q0

q1

q2

q3

q = state of referenced output one setup time prior to active clock transition

CJD8RE Truth Table

Inputs

Outputs

CE

Q0

Q1 Q7

No Chg

No Chg

q7

q0 q6

q7

q0 q6

q = state of referenced output one setup time prior to active clock transition

Usage
For HDL, this design element can be inferred but not instantiated.

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Libraries Guide
ISE 6.3i

CLK_DIV2,4,6,8,10,12,14,16

CLK_DIV2,4,6,8,10,12,14,16
Global Clock Divider
Architectures Supported
CLK_DIV2
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

CLK_DIV4, CLK_DIV6, CLK_DIV8, CLK_DIV10,

CLK_DIV12, CLK_DIV14, CLK_DIV16

CLKIN

CLKDV

X10147

Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

The CLK_DIV2,4,6,8,10,12,14,16 Global Clock Dividers divide a user-provided

external clock signal gclk<2> by 2, 4, 6, 8, 10, 12, 14, and 16, respectively. Only one
clock divider may be used per design. The global clock divider is available on the
XC2C128, XC2C256, XC2C384, and XC2C512 CoolRunner-II devices, but not the
XC2C32 orXC2C64. The CLKIN input can only be connected to the device gclk<2>
pin. The duty cycle of the CLKDV output is 50-50.
The CLKDV output is reset low by power-on reset circuitry.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Templates

CLK_DIV2
-- CLK_DIV2: Simple clock Divide by 2
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV2_inst : CLK_DIV2
port map (
CLKDV => CLKDV,
-- Divided clock output

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295

CLK_DIV2,4,6,8,10,12,14,16

CLKIN => CLKIN

-- Clock input

);
CLK_DIV4
-- CLK_DIV4: Simple clock Divide by 4
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV4_inst : CLK_DIV4
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);
CLK_DIV6
-- CLK_DIV6: Simple clock Divide by 6
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV6_inst : CLK_DIV6
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);
CLK_DIV8
-- CLK_DIV8: Simple clock Divide by 8
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV8_inst : CLK_DIV8
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);
CLK_DIV10
-- CLK_DIV10: Simple clock Divide by 10
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV10_inst : CLK_DIV10
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);
CLK_DIV12
-- CLK_DIV12: Simple clock Divide by 12
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV12_inst : CLK_DIV12

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296

CLK_DIV2,4,6,8,10,12,14,16

port map (
CLKDV => CLKDV,
CLKIN => CLKIN
);

-- Divided clock output

-- Clock input

CLK_DIV14
-- CLK_DIV14: Simple clock Divide by 14
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV14_inst : CLK_DIV14
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);
CLK_DIV16
-- CLK_DIV16: Simple clock Divide by 16
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV16_inst : CLK_DIV16
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);

Verilog Instantiation Templates

CLK_DIV2
// CLK_DIV2: Simple clock Divide by 2
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV2 CLK_DIV2_inst (
.CLKDV(CLKDV),
// Divided clock output
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV4
// CLK_DIV4: Simple clock Divide by 4
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV4 CLK_DIV4_inst (
.CLKDV(CLKDV),
// Divided clock output
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV6
// CLK_DIV6: Simple clock Divide by 6
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i

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297

CLK_DIV2,4,6,8,10,12,14,16

CLK_DIV6 CLK_DIV6_inst (
.CLKDV(CLKDV),
// Divided clock output
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV8
// CLK_DIV8: Simple clock Divide by 8
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV8 CLK_DIV8_inst (
.CLKDV(CLKDV),
// Divided clock output
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV10
// CLK_DIV10: Simple clock Divide by 10
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV10 CLK_DIV10_inst (
.CLKDV(CLKDV),
// Divided clock output
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV12
// CLK_DIV12: Simple clock Divide by 12
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV12 CLK_DIV12_inst (
.CLKDV(CLKDV),
// Divided clock output
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV14
// CLK_DIV14: Simple clock Divide by 14
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV14 CLK_DIV14_inst (
.CLKDV(CLKDV),
// Divided clock output
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV16
// CLK_DIV16: Simple clock Divide by 16
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV16 CLK_DIV16_inst (
.CLKDV(CLKDV),
// Divided clock output
.CLKIN(CLKIN)
// Clock input
);

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ISE 6.3i

CLK_DIV2,4,6,8,10,12,14,16R

CLK_DIV2,4,6,8,10,12,14,16R
Global Clock Divider with Synchronous Reset
Architectures Supported
CLK_DIV2R
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

CLK_DIV4R, CLK_DIV6R, CLK_DIV8R, CLK_DIV10R,

CLK_DIV12R, CLK_DIV14R, CLK_DIV16R

CLKIN

CLKDV

X10147

Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

The CLK_DIV2,4,6,8,10,12,14,16R Global Clock Dividers with Synchronous Reset

divide a user-provided external clock signal gclk<2> by 2, 4, 6, 8, 10, 12, 14, and 16,
respectively. Only one clock divider may be used per design. The global clock divider
is available on the XC2C128, XC2C256, XC2C384, and XC2C512 CoolRunner-II
devices, but not the XC2C32 or XC2C64. The CLKIN and CDRST inputs can only be
connected to the device gclk<2> and CDRST pins. The duty cycle of the CLKDV
output is 50-50.
The CDRST input is an active High synchronous reset. If CDRST is input High when
the CLKDV output is High, the CLKDV output remains High to complete the last
clock pulse, and then goes Low.
The CLKDV output is reset low by power-on reset circuitry.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

CLK_DIV2R
-- CLK_DIV2R: Clock Divide by 2 with synchronous reset
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i

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CLK_DIV2,4,6,8,10,12,14,16R

CLK_DIV2R_inst : CLK_DIV2R
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);
CLK_DIV4R
-- CLK_DIV4R: Clock Divide by 4 with synchronous reset
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV4R_inst : CLK_DIV4R
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);
CLK_DIV6R
-- CLK_DIV6R: Clock Divide by 6 with synchronous reset
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV6R_inst : CLK_DIV6R
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);
CLK_DIV8R
-- CLK_DIV8R: Clock Divide by 8 with synchronous reset
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV8R_inst : CLK_DIV8R
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);
CLK_DIV10R
-- CLK_DIV10R: Clock Divide by 10 with synchronous reset
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV10R_inst : CLK_DIV10R
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input

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CLK_DIV2,4,6,8,10,12,14,16R

);
CLK_DIV12R
-- CLK_DIV12R: Clock Divide by 12 with synchronous reset
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV12R_inst : CLK_DIV12R
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);
CLK_DIV14R
-- CLK_DIV14R: Clock Divide by 14 with synchronous reset
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV14R_inst : CLK_DIV14R
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);
CLK_DIV16R
-- CLK_DIV16R: Clock Divide by 16 with synchronous reset
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV16R_inst : CLK_DIV16R
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);

Verilog Instantiation Template

CLK_DIV2R
// CLK_DIV2R: Clock Divide by 2 with synchronous reset
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV2R CLK_DIV2R_inst (
.CLKDV(CLKDV),
// Divided clock output
.CDRST(CDRST),
// Synchronous reset input
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV4R
// CLK_DIV4R: Clock Divide by 4 with synchronous reset

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CLK_DIV2,4,6,8,10,12,14,16R

//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV4R CLK_DIV4R_inst (
.CLKDV(CLKDV),
// Divided clock output
.CDRST(CDRST),
// Synchronous reset input
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV6R
// CLK_DIV6R: Clock Divide by 6 with synchronous reset
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV6R CLK_DIV6R_inst (
.CLKDV(CLKDV),
// Divided clock output
.CDRST(CDRST),
// Synchronous reset input
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV8R
// CLK_DIV8R: Clock Divide by 8 with synchronous reset
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV8R CLK_DIV8R_inst (
.CLKDV(CLKDV),
// Divided clock output
.CDRST(CDRST),
// Synchronous reset input
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV10R
// CLK_DIV10R: Clock Divide by 10 with synchronous reset
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV10R CLK_DIV10R_inst (
.CLKDV(CLKDV),
// Divided clock output
.CDRST(CDRST),
// Synchronous reset input
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV12R
// CLK_DIV12R: Clock Divide by 12 with synchronous reset
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV12R CLK_DIV12R_inst (
.CLKDV(CLKDV),
// Divided clock output
.CDRST(CDRST),
// Synchronous reset input
.CLKIN(CLKIN)
// Clock input
);

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ISE 6.3i

CLK_DIV2,4,6,8,10,12,14,16R

CLK_DIV14R
// CLK_DIV14R: Clock Divide by 14 with synchronous reset
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV14R CLK_DIV14R_inst (
.CLKDV(CLKDV),
// Divided clock output
.CDRST(CDRST),
// Synchronous reset input
.CLKIN(CLKIN)
// Clock input
);
CLK_DIV16R
// CLK_DIV16R: Clock Divide by 16 with synchronous reset
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV16R CLK_DIV16R_inst (
.CLKDV(CLKDV),
// Divided clock output
.CDRST(CDRST),
// Synchronous reset input
.CLKIN(CLKIN)
// Clock input
);

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ISE 6.3i

CLK_DIV2,4,6,8,10,12,14,16RSD

CLK_DIV2,4,6,8,10,12,14,16RSD
Global Clock Divider with Synchronous Reset and Start Delay
Architectures Supported
CLK_DIV2RSD
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

CLK_DIV4RSD, CLK_DIV6RSD, CLK_DIV8RSD, CLK_DIV10RSD,

CLK_DIV12RSD, CLK_DIV14RSD, CLK_DIV16RSD

CLKIN
CLKDV
CDRST

X10146

Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

The CLK_DIV2,4,6,8,10,12,14,16 Global Clock Dividers with Synchronous Reset and

Start Delay divide a user-provided external clock signal gclk<2> by 2, 4, 6, 8, 10, 12,
14, and 16, respectively. Only one clock divider may be used per design. The global
clock divider is available on the XC2C128, XC2C256, XC2C384, and XC2C512
CoolRunner-II devices, but not the XC2C32 or XC2C64. The CLKIN and CDRST
inputs can only be connected to the device gclk<2> and CDRST pins. The duty cycle
of the CLKDV output is 50-50.
The CDRST input is an active High synchronous reset. If CDRST is input High when
the CLKDV output is High, the CLKDV output remains High to complete the last
clock pulse, and then goes Low.
The start delay function delays the start of the CLKDV output by (n + 1) clocks, where
n is the divisor for the clock divider.
The CLKDV output is reset low by power-on reset circuitry.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

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CLK_DIV2,4,6,8,10,12,14,16RSD

VHDL Instantiation Template

CLK_DIV2RSD
-- CLK_DIV2RSD: Clock Divide by 2 with synchronous reset and start
-- delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV2RSD_inst : CLK_DIV2RSD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);
CLK_DIV4RSD
-- CLK_DIV4RSD: Clock Divide by 4 with synchronous reset and start
-- delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV4RSD_inst : CLK_DIV4RSD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);
CLK_DIV6RSD
-- CLK_DIV6RSD: Clock Divide by 6 with synchronous reset and start
-- delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV6RSD_inst : CLK_DIV6RSD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);

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ISE 6.3i

CLK_DIV2,4,6,8,10,12,14,16RSD

CLK_DIV8RSD
-- CLK_DIV8RSD: Clock Divide by 8 with synchronous reset and start
-- delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV8RSD_inst : CLK_DIV8RSD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);
CLK_DIV10RSD
-- CLK_DIV10RSD: Clock Divide by 10 with synchronous reset and start
-- delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV10RSD_inst : CLK_DIV10RSD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);
CLK_DIV12RSD
-- CLK_DIV12RSD: Clock Divide by 12 with synchronous reset and start
-- delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV12RSD_inst : CLK_DIV12RSD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);
CLK_DIV14RSD
-- CLK_DIV14RSD: Clock Divide by 14 with synchronous reset and start
-- delay

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CLK_DIV2,4,6,8,10,12,14,16RSD

-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV14RSD_inst : CLK_DIV14RSD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);
CLK_DIV16RSD
-- CLK_DIV16RSD: Clock Divide by 16 with synchronous reset and start
-- delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV16RSD_inst : CLK_DIV16RSD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CDRST => CDRST,
-- Synchronous reset input
CLKIN => CLKIN
-- Clock input
);

Verilog Instantiation Template

CLK_DIV2RSD
// CLK_DIV2RSD: Clock Divide by 2 with synchronous reset and start
// delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV2RSD CLK_DIV2RSD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV2RSD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV2RSD_inst instantiation

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CLK_DIV2,4,6,8,10,12,14,16RSD

CLK_DIV4RSD
// CLK_DIV4RSD: Clock Divide by 4 with synchronous reset and start
// delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV4RSD CLK_DIV4RSD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV4RSD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV4RSD_inst instantiation

CLK_DIV6RSD
// CLK_DIV6RSD: Clock Divide by 6 with synchronous reset and start
// delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV6RSD CLK_DIV6RSD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV6RSD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV6RSD_inst instantiation

CLK_DIV8RSD
// CLK_DIV8RSD: Clock Divide by 8 with synchronous reset and start
// delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV8RSD CLK_DIV8RSD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
// Edit the following defparam to specify the number of clock

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CLK_DIV2,4,6,8,10,12,14,16RSD

// cycles to delay before starting. If the instance name to

// the clock divider is changed, that change needs to be
// reflected in the defparam statements.
defparam CLK_DIV8RSD_inst.DIVIDER_DELAY = 1;
// End of CLK_DIV8RSD_inst instantiation
CLK_DIV10RSD
// CLK_DIV10RSD: Clock Divide by 10 with synchronous reset and start
// delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV10RSD CLK_DIV10RSD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV10RSD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV10RSD_inst instantiation

CLK_DIV12RSD
// CLK_DIV12RSD: Clock Divide by 12 with synchronous reset and start
// delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV12RSD CLK_DIV12RSD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV12RSD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV12RSD_inst instantiation

CLK_DIV14RSD
// CLK_DIV14RSD: Clock Divide by 14 with synchronous reset and start
// delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i

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CLK_DIV2,4,6,8,10,12,14,16RSD

CLK_DIV14RSD CLK_DIV14RSD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV14RSD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV14RSD_inst instantiation

CLK_DIV16RSD
// CLK_DIV16RSD: Clock Divide by 16 with synchronous reset and start
// delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV16RSD CLK_DIV16RSD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV16RSD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV16RSD_inst instantiation

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ISE 6.3i

CLK_DIV2,4,6,8,10,12,14,16SD

CLK_DIV2,4,6,8,10,12,14,16SD
Global Clock Divider with Start Delay
Architectures Supported
CLK_DIV2SD
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

CLK_DIV4SD, CLK_DIV6SD, CLK_DIV8SD, CLK_DIV10SD,

CLK_DIV12SD, CLK_DIV14SD, CLK_DIV16SD

CLKIN
CLKDV
CDRST

X10146

Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

The CLK_DIV2,4,6,8,10,12,14,16SD Global Clock Dividers with Start Delay divide a

user-provided external clock signal gclk<2> by 2, 4, 6, 8, 10, 12, 14, and 16,
respectively. Only one clock divider may be used per design. The global clock divider
is available on the XC2C128, XC2C256, XC2C384, and XC2C512 CoolRunner-II
devices, but not the XC2C32 or XC2C64. The CLKIN input can only be connected to
the device gclk<2> pin. The duty cycle of the CLKDV output is 50-50.
The start delay function delays the CLKDV output (n + 1) clocks, where n is the
divisor for the clock divider.
The CLKDV output is reset low by power-on reset circuitry.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

CLK_DIV2SD
-- CLK_DIV2SD: Clock Divide by 2 with start delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV2SD_inst : CLK_DIV2SD
-- Edit the following generic to specify the number of clock cycles

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CLK_DIV2,4,6,8,10,12,14,16SD

-- to delay before starting.

generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);
-- End of CLK_DIV2SD_inst instantiation
CLK_DIV4SD
-- CLK_DIV4SD: Clock Divide by 4 with start delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV4SD_inst : CLK_DIV4SD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);
-- End of CLK_DIV4SD_inst instantiation
CLK_DIV6SD
-- CLK_DIV6SD: Clock Divide by 6 with start delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV6SD_inst : CLK_DIV6SD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);
-- End of CLK_DIV6SD_inst instantiation
CLK_DIV8SD
-- CLK_DIV8SD: Clock Divide by 8 with start delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV8SD_inst : CLK_DIV8SD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (

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CLKDV => CLKDV,

CLKIN => CLKIN

-- Divided clock output

-- Clock input

);
-- End of CLK_DIV8SD_inst instantiation
CLK_DIV10SD
-- CLK_DIV10SD: Clock Divide by 10 with start delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV10SD_inst : CLK_DIV10SD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);
-- End of CLK_DIV10SD_inst instantiation
CLK_DIV12SD
-- CLK_DIV12SD: Clock Divide by 12 with start delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV12SD_inst : CLK_DIV12SD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);
-- End of CLK_DIV12SD_inst instantiation
CLK_DIV14SD
-- CLK_DIV14SD: Clock Divide by 14 with start delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV14SD_inst : CLK_DIV14SD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);

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-- End of CLK_DIV14SD_inst instantiation

CLK_DIV16SD
-- CLK_DIV16SD: Clock Divide by 16 with start delay
-CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
CLK_DIV16SD_inst : CLK_DIV16SD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV,
-- Divided clock output
CLKIN => CLKIN
-- Clock input
);
-- End of CLK_DIV16SD_inst instantiation

Verilog Instantiation Template

CLK_DIV2SD
// CLK_DIV2SD: Clock Divide by 2 with start delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV2SD CLK_DIV2SD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV2SD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV2SD_inst instantiation

CLK_DIV4SD
// CLK_DIV4SD: Clock Divide by 4 with start delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV4SD CLK_DIV4SD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
// Edit the following defparam to specify the number of clock
// cycles to delay before starting. If the instance name to
// the clock divider is changed, that change needs to be

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// reflected in the defparam statements.

defparam CLK_DIV4SD_inst.DIVIDER_DELAY = 1;
// End of CLK_DIV4SD_inst instantiation
CLK_DIV6SD
// CLK_DIV6SD: Clock Divide by 6 with start delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV6SD CLK_DIV6SD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV6SD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV6SD_inst instantiation

CLK_DIV8SD
// CLK_DIV8SD: Clock Divide by 8 with start delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV8SD CLK_DIV8SD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV8SD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV8SD_inst instantiation

CLK_DIV10SD
// CLK_DIV10SD: Clock Divide by 10 with start delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV10SD CLK_DIV10SD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input

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CLK_DIV2,4,6,8,10,12,14,16SD

);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV10SD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV10SD_inst instantiation

CLK_DIV12SD
// CLK_DIV12SD: Clock Divide by 12 with start delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV12SD CLK_DIV12SD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV12SD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV12SD_inst instantiation

CLK_DIV14SD
// CLK_DIV14SD: Clock Divide by 14 with start delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
CLK_DIV14SD CLK_DIV14SD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV14SD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV14SD_inst instantiation

CLK_DIV16SD
// CLK_DIV16SD: Clock Divide by 16 with start delay
//
CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i

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CLK_DIV16SD CLK_DIV16SD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
//
//
//
//

Edit the following defparam to specify the number of clock

cycles to delay before starting. If the instance name to
the clock divider is changed, that change needs to be
reflected in the defparam statements.
defparam CLK_DIV16SD_inst.DIVIDER_DELAY = 1;

// End of CLK_DIV16SD_inst instantiation

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ISE 6.3i

CLKDLL

CLKDLL
Clock Delay Locked Loop
Architectures Supported
CLKDLL
Spartan-II, Spartan-IIE

Primitive*

Spartan-3

No

Virtex, Virtex-E

Primitive*

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

* Use CLKDLLE for Spartan-IIE and Virtex-E.

CLKDLL
CLKIN

CLK0

CLKFB

CLK90
CLK180
CLK270
CLK2X
CLKDV

RST

LOCKED

X8678

CLKDLL is a clock delay locked loop used to minimize clock skew. CLKDLL
synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal
at the input clock (CLKIN). The locked output (LOCKED) is high when the two
signals are in phase. The signals are considered to be in phase when their rising edges
are within a specific range of each other (see The Programmable Logic Data Sheets for the
most current value).
The frequency of the clock signal at the CLKIN input must be in a specific range
depending on speed grade (see The Programmable Logic Data Sheets for the most
current values). The CLKIN pin must be driven by an IBUFG or a BUFG. If phase
alignment is not required, CLKIN can also be driven by IBUF.
On-chip synchronization is achieved by connecting the CLKFB input to a point on the
global clock network driven by a BUFG, a global clock buffer. The BUFG connected to
the CLKFB input of the CLKDLL must be sourced from either the CLK0 or CLK2X
outputs of the same CLKDLL. The CLKIN input should be connected to the output of
an IBUFG, with the IBUFG input connected to a pad driven by the system clock.
Off-chip synchronization is achieved by connecting the CLKFB input to the output of
an IBUFG, with the IBUFG input connected to a pad. Either the CLK0 or CLK2X
output can be used but not both. The CLK0 or CLK2X must be connected to the input
of OBUF, an output buffer.
The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION
attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN
input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is
the same as that of the CLK0 output. The duty cycle of the CLK2X and CLKDV
outputs is always 50-50. The frequency of the CLKDV output is determined by the
value assigned to the CLKDV_DIVIDE attribute.
The master reset input (RST) resets CLKDLL to its initial (power-on) state. The signal
at the RST input is asynchronous and must be held High for just 2ns.

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CLKDLL

CLKDLL Outputs
Output

Description

CLK0

Clock at 1x CLKIN frequency

CLK180

Clock at 1x CLKIN frequency, shifted 180o with regards to CLK0

CLK270

Clock at 1x CLKIN frequency, shifted 270o with regards to CLK0

CLK2X

Clock at 2x CLKIN frequency, in phase with CLK0

CLK90

Clock at 1x CLKIN frequency, shifted 90o with regards to CLK0

CLKDV

Clock at (1/n)x CLKIN frequency, n=CLKDV_DIVIDE value. CLKDV is in

phase with CLK0.

LOCKED

CLKDLL locked

Note: See the "PERIOD Specifications on CLKDLLs and DCM" in the Constraints Guide for
additional information on using the TNM, TNM_NET, and PERIOD attributes with CLKDLL
components.

Usage
This component is generally instantiated in the code as it can not be easily inferred in
synthesis tools. Some synthesis tools may allow inference via an attribute. See your
synthesis tool's documentation. Generally, global buffers (IBUFG, BUFG) are
instantiated with the CLKDLL component to construct the proper clocking circuit. See
the XAPP 132 application note, "Using the Virtex Delay-Locked Loop" and the Xilinx
Data Sheets for more information on using the CLKDLL component.

VHDL Instantiation Template

-- Component Declaration for CLKDLL should be placed
-- after architecture statement but before begin keyword
component CLKDLL
-- synthesis translate_off
generic map (CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5,
3.0, 4.0, 5.0, 8.0, 16.0)
DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE)
STARTUP_WAIT : boolean := FALSE) -- (TRUE, FALSE)
-- synthesis translate_on
port (CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
RST : in STD_ULOGIC);
end component;
-- Component Attribute specification for CLKDLL
-- should be placed after architecture declaration but
-- before the begin keyword

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CLKDLL

attribute CLKDV_DIVIDE : real;

attribute DUTY_CYCLE_CORRECTION : boolean;
attribute STARTUP_WAIT : boolean;
attribute CLKDV_DIVIDE of CLKDLL_instance_name: label is 2.0;
-- 1.5,2,2.5,3,4, 5, 8, 16 are valid for CLKDV_DIVIDE
attribute DUTY_CYCLE_CORRECTION of CLKDLL_instance_name: label is
"TRUE";
-- TRUE, FALSE are valid for DUTY_CYCLE_CORRECTION
attribute STARTUP_WAIT of CLKDLL_instance_name: label is "FALSE"; -(TRUE,FALSE)

-- Component Instantiation for CLKDLL should be placed

-- in architecture after the begin keyword
CLKDLL_INSTANCE_NAME : CLKDLL
-- synthesis translate_off
generic map (CLKDV_DIVIDE => real_value,
-- (1.5,2,2.5,3,4,5,8,16)
DUTY_CYCLE_CORRECTION => boolean_value, -- (TRUE,
FALSE)
STARTUP_WAIT => boolean_value); -- (TRUE, FALSE)
-- synthesis translate_on
port map (CLK0 => user_CLK0,
CLK180 => user_CLK180,
CLK270 => user_CLK270,
CLK2X => user_CLK2X,
CLK90 => user_CLK90,
CLKDV => user_CLKDV,
LOCKED => user_LOCKED,
CLKFB => user_CLKFB,
CLKIN0 => user_CLKIN,
RST => user_RST);

Verilog Instantiation Template

CLKDLL CLKDLL_instance_name (.CLK0 (user_CLK0),
.CLK180 (user_CLK180),
.CLK270 (user_CLK270),
.CLK2X (user_CLK2X),
.CLK90 (user_CLK90),
.CLKDV (user_CLKDV),
.LOCKED (user_LOCKED),
.CLKFB (user_CLKFB),
.CLKIN (user_CLKIN),
.RST (user_RST));
defparam CLKDLL_instance_name.CLKDV_DIVIDE = integer_value;
//(1.5,2,2.5,3,4,5,8,16)
defparam CLKDLL_instance_name.DUTY_CYCLE_CORRECTION = boolean_value;//
(TRUE, FALSE)
defparam CLKDLL_instance_name.STARTUP_WAIT = boolean_value; // (TRUE,
FALSE)

Note: Additional syntax may be necessary in order to pass the CLKDLL attributes via the
synthesis tool. The above defparam statements may need to be isolated from the synthesis tool
with translate_off/translate_on directives. See your synthesis tool documentation for more

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CLKDLL

information on Verilog attribute passing to ensure that you properly pass these attributes to the
synthesis tool. Otherwise, you may pass these attributes to the UCF file.

Commonly Used Constraints

STARTUP_WAIT, DUTY_CYCLE_CORRECTION, CLKDV_DIVIDE and LOC.

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CLKDLLE

CLKDLLE
Virtex-E Clock Delay Locked Loop
Architectures Supported
CLKDLLE
Spartan-II, Spartan-IIE

Primitive*

Spartan-3

No

Virtex, Virtex-E

Primitive*

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

* Supported for Spartan-IIE and Virtex-E devices only.

CLKDLLE CLK0
CLKIN

CLK90

CLKFB

CLK180
CLK270
CLK2X
CLK2X180
CLKDV

RST

LOCKED

X9400

CLKDLLE is a clock delay locked loop used to minimize clock skew for Virtex-E
devices. CLKDLLE synchronizes the clock signal at the feedback clock input (CLKFB)
to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high
when the two signals are in phase. The signals are considered to be in phase when
their rising edges are within a specific range of each other (see The Programmable Logic
Data Sheets for the most current value).
The frequency of the clock signal at the CLKIN input must be in a specific range
depending on speed grade (see The Programmable Logic Data Sheets for the most
current values). The CLKIN pin must be driven by an IBUFG or a BUFG.
On-chip synchronization is achieved by connecting the CLKFB input to a point on the
global clock network driven by a BUFG, a global clock buffer. The BUFG input can
only be connected to the CLK0 or CLK2X output of CLKDLLE. The BUFG connected
to the CLKFB input of the CLKDLLE must be sourced from either the CLK0 or CLK2X
outputs of the same CLKDLLE. The CLKIN input should be connected to the output
of an IBUFG, with the IBUFG input connected to a pad driven by the system clock.
Off-chip synchronization is achieved by connecting the CLKFB input to the output of
an IBUFG, with the IBUFG input connected to a pad. Either the CLK0 or CLK2X
output can be used but not both. The CLK0 or CLK2X must be connected to the input
of OBUF, an output buffer.
The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION
attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN
input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is
the same as that of the CLK0 output. The duty cycle of the CLK2X, CLK2X180, and
CLKDV outputs is always 50-50. The frequency of the CLKDV output is determined
by the value assigned to the CLKDV_DIVIDE attribute.
The master reset input (RST) resets CLKDLLE to its initial (power-on) state. The signal
at the RST input is asynchronous and must be held High for just 2ns.

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CLKDLLE

CLKDLLE Outputs
Output

Description

CLK0

Clock at 1x CLKIN frequency

CLK180

Clock at 1x CLK0 frequency, shifted 180o with regards to CLK0

CLK270

Clock at 1x CLK0 frequency, shifted 270o with regards to CLK0

CLK2X

Clock at 2x CLK0 frequency, in phase with CLK0

CLK2X180

Clock at 1x CLK2X frequency shifted 180o with regards to CLK2X

CLK90

Clock at 1x CLK0 frequency, shifted 90o with regards to CLK0

CLKDV

Clock at (1/n) x CLK0 frequency, where n=CLKDV_DIVIDE value.

CLKDV is in phase with CLK0.

LOCKED

CLKDLLE locked. CLKIN and CLKFB synchronized.

Usage
This component is generally instantiated in the code as it cannot be easily inferred in
synthesis tools. Some synthesis tools may allow inference via an attribute. See your
synthesis tool documentation. Generally, global buffers (IBUFG, BUFG) are
instantiated with the CLKDLLE component to construct the proper clocking circuit.
See the XAPP 132 application note, "Using the Virtex Delay-Locked Loop" and the
Xilinx Data Sheets for more information on using the CLKDLLE component.

VHDL Instantiation Template

-- Component Declaration for CLKDLLE should be placed
-- after architecture statement but before begin keyword
component CLKDLLE
-- synthesis translate_off
generic map (CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5, 3.0,
3.5, 4.0, 4.5, 5.0,5.5, 6.0, 6.5, 7.5, 8.0, 9.0,
10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0)
DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE)
STARTUP_WAIT :boolean := FALSE) -- (TRUE, FALSE)
-- synthesis translate_on
port (CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK2X180: out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
RST : in STD_ULOGIC);
end component;
-- Component Attribute specification for CLKDLLE
-- should be placed after architecture declaration but
-- before the begin keyword

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CLKDLLE

attribute CLKDV_DIVIDE : real;

attribute DUTY_CYCLE_CORRECTION : boolean;
attribute STARTUP_WAIT : boolean;
attribute CLKDV_DIVIDE of CLKDLLE_instance_name: label is 2.0;
-- (1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.5, 8.0,
9.0, 10.0, 11.0,
-- 12.0, 13.0, 14.0, 15.0, 16.0) are valid for CLKDV_DIVIDE
attribute DUTY_CYCLE_CORRECTION of CLKDLLE_instance_name: label is
TRUE;
-- (TRUE, FALSE) are valid for DUTY_CYCLE_CORRECTION
attribute STARTUP_WAIT of CLKDLLE_instance_name: label is FALSE; -(TRUE,FALSE)

-- Component Instantiation for CLKDLLE should be placed

-- in architecture after the begin keyword
CLKDLLE_INSTANCE_NAME : CLKDLLE
-- synthesis translate_off
generic map (CLKDV_DIVIDE => real_value, -(1.5,2,2.5,3,4,5,8,16)
DUTY_CYCLE_CORRECTION => boolean_value, -- (TRUE, FALSE)
STARTUP_WAIT => boolean_value); -- (TRUE, FALSE)
-- synthesis translate_on
port map (CLK0 => user_CLK0,
CLK180 => user_CLK180,
CLK270 => user_CLK270,
CLK2X => user_CLK2X,
CLK2X180 => user_CLK2X,
CLK90 => user_CLK90,
CLKDV => user_CLKDV,
LOCKED => user_LOCKED,
CLKFB => user_CLKFB,
CLKIN0 => user_CLKIN,
RST => user_RST);

Verilog Instantiation Template

CLKDLLE CLKDLLE_instance_name (.CLK0 (user_CLK0),
.CLK180 (user_CLK180),
.CLK270 (user_CLK270),
.CLK2X (user_CLK2X),
.CLK2X180 (user_CLK2X180),
.CLK90 (user_CLK90),
.CLKDV (user_CLKDV),
.LOCKED (user_LOCKED),
.CLKFB (user_CLKFB),
.CLKIN (user_CLKIN),
.RST (user_RST));
defparam CLKDLLE_instance_name.CLKDV_DIVIDE = integer_value;
// 1.5,2,2.5,3,4,5,8,16 are valid for CLKDV_DIVIDE
defparam CLKDLLE_instance_name.DUTY_CYCLE_CORRECTION =
boolean_value;// (TRUE,FALSE)
defparam CLKDLLE_instance_name.STARTUP_WAIT = boolean_value; // (TRUE,
FALSE)

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Note: Additional syntax may be necessary in order to pass the CLKDLLE attributes via the
synthesis tool. The above defparam statements may need to be isolated from the synthesis tool
with translate_off/translate_on directives. See your synthesis tool documentation for more
information on Verilog attribute passing to ensure that you properly pass these attributes to the
synthesis tool. Otherwise, you may pass these attributes to the UCF file.

Commonly Used Constraints

STARTUP_WAIT, DUTY_CYCLE_CORRECTION, CLKDV_DIVIDE, and LOC

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CLKDLLHF

CLKDLLHF
High Frequency Clock Delay Locked Loop
Architectures Supported
CLKDLLHF
Spartan-II, Spartan-IIE

Primitive

Spartan-3

No

Virtex, Virtex-E

Primitive*

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Use CLKDLLHF for the Virtex-E DLL in HF mode. In LF mode,

both the separate CLKDLLE and CLKDLL primitive can be
used.

CLKDLLHF
CLK0

CLKIN
CLKFB

CLK180

CLKDV
RST

LOCKED

X8680

CLKDLLHF is a high frequency clock delay locked loop used to minimize clock skew.
CLKDLLHF synchronizes the clock signal at the feedback clock input (CLKFB) to the
clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when
the two signals are in phase. The signals are considered to be in phase when their
rising edges are within a specific range of each other (see The Programmable Logic Data
Sheets for the most current value).
The frequency of the clock signal at the CLKIN input must be in a specific range
depending on speed grade (see The Programmable Logic Data Sheets for the most
current values). The CLKIN pin must be driven by an IBUFG or a BUFG.
On-chip synchronization is achieved by connecting the CLKFB input to a point on the
global clock network driven by a BUFG, a global clock buffer. The BUFG input can
only be connected to the CLK0 output of CLKDLLHF. The BUFG connected to the
CLKFB input of the CLKDLLHF must be sourced from the CLK0 output of the same
CLKDLLHF. The CLKIN input should be connected to the output of an IBUFG, with
the IBUFG input connected to a pad driven by the system clock.
Off-chip synchronization is achieved by connecting the CLKFB input to the output of
an IBUFG, with the IBUFG input connected to a pad. Only the CLK0 output can be
used. CLK0 must be connected to the input of OBUF, an output buffer.
The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION
attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN
input. The duty cycle of the phase shifted output (CLK180) is the same as that of the
CLK0 output. The frequency of the CLKDV output is determined by the value
assigned to the CLKDV_DIVIDE attribute.
The master reset input (RST) resets CLKDLLHF to its initial (power-on) state. The
signal at the RST input is asynchronous and must be held High for just 2ns.

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329

CLKDLLHF

CLKDLLHF Outputs
Output

Description

CLK0

Clock at 1x CLKIN frequency

CLK180

Clock at 1x CLKIN frequency, shifted 180o with regards to CLK0

CLKDV

Clock at (1/n)x CLKIN frequency, n=CLKDV_DIVIDE value.

CLKDV is in phase with CLK0.

LOCKED

CLKDLLHF locked

Note: See the "PERIOD Specifications on CLKDLLs and DCM" section of the "Xilinx
Constraints P" chapter in the Constraints Guide for additional information on using the TNM,
TNM_NET, and PERIOD attributes with CLKDLLHF components.

Usage
This component is generally instantiated in the code as it cannot be easily inferred in
synthesis tools. Some synthesis tools may allow inference via an attribute. See your
synthesis tool documentation. Generally, global buffers (IBUFG, BUFG) are
instantiated with the CLKDLLHF component to construct the proper clocking circuit.
See the XAPP 132 application note, "Using the Virtex Delay-Locked Loop" and the
Xilinx Data Sheets for more information on using the CLKDLLHF component.

VHDL Instantiation Template

-- Component Declaration for CLKDLLHF should be placed
-- after architecture statement but before begin keyword
component CLKDLLHF
-- synthesis translate_off
generic map (CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5, 3.0,
4.0, 5.0, 8.0, 16.0)DUTY_CYCLE_CORRECTION : Boolean := TRUE -(TRUE,FALSE)STARTUP_WAIT : boolean := FALSE)-- (TRUE, FALSE)
-- synthesis translate_on
port (CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
RST : in STD_ULOGIC);
end component;
-- Component Attribute specification for CLKDLLHF
-- should be placed after architecture declaration but
-- before the begin keyword
attribute CLKDV_DIVIDE : real;
attribute DUTY_CYCLE_CORRECTION : boolean;
attribute STARTUP_WAIT : boolean;
attribute CLKDV_DIVIDE of CLKDLLHF_instance_name: label is 2.0;
-- (1.5,2,2.5,3,4, 5, 8, 16) are valid for CLKDV_DIVIDE
attribute DUTY_CYCLE_CORRECTION of CLKDLLHF_instance_name: label is
TRUE;

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ISE 6.3i

CLKDLLHF

-- (TRUE, FALSE) are valid for DUTY_CYCLE_CORRECTION

attribute STARTUP_WAIT of CLKDLLHF_instance_name: label is FALSE; -(TRUE,FALSE)
-- Component Instantiation for CLKDLLHF should be placed
-- in architecture after the begin keyword
CLKDLLHF_INSTANCE_NAME : CLKDLLHF
-- synthesis translate_off
generic map(CLKDV_DIVIDE => real_value, -- (1.5,2,2.5,3,4,5,8,16)
DUTY_CYCLE_CORRECTION => boolean_value, -- (TRUE,
FALSE)
STARTUP_WAIT => boolean_value); -- (TRUE, FALSE)
-- synthesis translate_on
port map (CLK0 => user_CLK0,
CLK180 => user_CLK180,
CLKDV => user_CLKDV,
LOCKED => user_LOCKED,
CLKFB => user_CLKFB,
CLKIN => user_CLKIN,
RST => user_RST);
Verilog Instantiation Template
CLKDLLHF CLKDLLHF_instance_name (.CLK0 (user_CLK0),
.CLK180 (user_CLK180),
.CLKDV (user_CLKDV),
.LOCKED (user_LOCKED),
.CLKFB (user_CLKFB),
.CLKIN (user_CLKIN),
.RST (user_RST));
defparam CLKDLLHF_instance_name.CLKDV_DIVIDE = integer_value;
// 1.5,2,2.5,3,4,5,8,16 are valid for CLKDV_DIVIDE
defparam CLKDLLHF_instance_name.DUTY_CYCLE_CORRECTION =
boolean_value;// (TRUE,FALSE)
defparam CLKDLLHF_instance_name.STARTUP_WAIT = boolean_value; //
(TRUE, FALSE)

Note: Additional syntax may be necessary in order to pass the CLKDLLHF attributes via the
synthesis tool. The above defparam statements may need to be isolated from the synthesis tool
with translate_off/translate_on directives. See your synthesis tool documentation for more
information on Verilog attribute passing to ensure that you properly pass these attributes to the
synthesis tool. Otherwise, you may pass these attributes to the UCF file.

Commonly Used Constraints

STARTUP_WAIT, DUTY_CYCLE_CORRECTION, CLKDV_DIVIDE, LOC

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331

332

CLKDLLHF

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Libraries Guide
ISE 6.3i

COMP2, 4, 8, 16

COMP2, 4, 8, 16
2-, 4-, 8-, 16-Bit Identity Comparators
Architectures Supported
COMP2, COMP4, COMP8, COMP16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

A0

COMP2

A1

EQ

B0
B1

X4122

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

COMP2, COMP4, COMP8, and COMP16 are, respectively, 2-, 4-, 8-, and 16-bit identity
comparators. The equal output (EQ) of the COMP2 2-bit, identity comparator is High
when the two words A1 A0 and B1 B0 are equal. EQ is high for COMP4 when A3
A0 and B3 B0 are equal; for COMP8, when A7 A0 and B7 B0 are equal; and for
COMP16, when A15 A0 and B15 B0 are equal.
Equality is determined by a bit comparison of the two words. When any two of the
corresponding bits from each word are not the same, the EQ output is Low.

A0

COMP4

A1
A2
A3

EQ

B0
B1
B2
B3

X4126

A[7:0]

COMP8
EQ

B[7:0]

X4131

A[15:0]

COMP16
EQ

B[15:0]

X4133

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333

COMP2, 4, 8, 16

A0
B0

AB0
XNOR2

A1
B1

AB1
AB03

XNOR2
A2
B2

AB2

AND4

XNOR2
A3
B3

AB3
EQ

XNOR2
A4
B4

AND2

AB4
XNOR2

A5
B5

AB5
AB47

XNOR2
A6
B6

AB6

AND4

XNOR2
A7
B7
A[7:0]

AB7
XNOR2

B[7:0]

X7791

COMP8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

334

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Libraries Guide
ISE 6.3i

COMPM2, 4, 8, 16

COMPM2, 4, 8, 16
2-, 4-, 8-, 16-Bit Magnitude Comparators
Architectures Supported
COMPM2, COMPM4, COMPM8, COMPM16

A0

COMPM2

A1

GT

B0

LT

B1

X4123

A0

COMPM4

A1
A2
A3

GT

B0

LT

B1

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

COMPM2, COMPM4, COMPM8, and COMPM16 are, respectively, 2-, 4-, 8-, and 16bit magnitude comparators that compare two positive binary-weighted words.
COMPM2 compares A1 A0 and B1 B0, where A1 and B1 are the most significant
bits. COMPM4 compares A3 A0 and B3 B0, where A3 and B3 are the most
significant bits. COMPM8 compares A7 A0 and B7 B0, where A7 and B7 are the
most significant bits. COMPM16 compares A15 A0 and B15 B0, where A15 and B15
are the most significant bits.
The greater-than output (GT) is High when A>B, and the less-than output (LT) is High
when A<B. When the two words are equal, both GT and LT are Low. Equality can be
measured with this macro by comparing both outputs with a NOR gate.
COMPM2 Truth Table

B2

Inputs

B3

A1

B1

A0

B0

GT

LT

GT

LT

GT

LT

X4127

A[7:0]

COMPM8

B[7:0]

X4132

A[15:0]

Outputs

COMPM16

B[15:0]

X4134

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335

COMPM2, 4, 8, 16

COMPM4 Truth Table

Inputs

Outputs

A3, B3

A2, B2

A1, B1

A0, B0

GT

LT

A3>B3

A3<B3

A3=B3

A2>B2

A3=B3

A2<B2

A3=B3

A2=B2

A1>B1

A3=B3

A2=B2

A1<B1

A3=B3

A2=A2

A1=B1

A0>B0

A3=B3

A2=B2

A1=B1

A0<B0

A3=B3

A2=B2

A1=B1

A0=B0

COMPM8 Truth Table (also representative of COMPM16)

Inputs

336

Outputs

A7, B7

A6, B6

A5, B5

A4, B4

A3, B3

A2, B2

A1, B1

A0, B0

GT

LT

A7>B7

A7<B7

A7=B7

A6>B6

A7=B7

A6<B6

A7=B7

A6=B6

A5>B5

A7=B7

A6=B6

A5<B5

A7=B7

A6=B6

A5=B5

A4>B4

A7=B7

A6=B6

A5=B5

A4<B4

A7=B7

A6=B6

A5=B5

A4=B4

A3>B3

A7=B7

A6=B6

A5=B5

A4=B4

A3<B3

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2>B2

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2<B2

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2=B2

A1>B1

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2=B2

A1<B1

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2=B2

A1=B1

A0>B0

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2=B2

A1=B1

A0<B0

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2=B2

A1=B1

A0=B0

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ISE 6.3i

COMPM2, 4, 8, 16

EQ_1
XNOR2

LE0_1

AND3B1

A0

LT0_1
LTA

OR2

GE0_1

AND4

B0
AND3B1
A1

GTA
GT0_1

GT_1
B1

AND4
AND2B1
LT_1

OR2

AND2B1
EQ_3

LE2_3

LT2_3
LTB

XNOR2

AND3B1

A2
GE2_3

EQ2_3

AND3
OR4

B2
NOR2

AND3B1
A3

GTB
GT2_3

GT_3

A3

LT

OR2

AND3
AND2B1
LT_3

OR2

AND2B1
EQ_5
XNOR2

LE4_5

AND3B1

A4

LT4_5

LTC

OR2

AND2

GE4_5

EQ4_5

B4
NOR2

AND3B1
A5

AND2B1
LT_5

GT

GTC

GT4_5

GT_5

B5

OR4

AND2

OR2

AND2B1
EQ_7
XNOR2

LE6_7

AND3B1

A6

LTD
OR2

GE6_7

EQ6_7

B6
NOR2

AND3B1
A[7:0]
B[7:0]

A7
B7

GTD

GT_7
AND2B1
LT_7

OR2

X7793

AND2B1

COMPM8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

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337

COMPM2, 4, 8, 16

B0
A0
AND2B1

B1

AND2

A1

OR2
OR2B1
AND2
AND2B1

B2
A2

OR2
OR2B1
AND2
AND2B1

B3
A3

OR2
OR2B1

AND2
AND2B1

B4
A4

OR2
OR2B1

AND2

AND2B1

B5
A5

OR2

OR2B1

AND2
AND2B1

B6
A6

OR2

OR2B1

AND2

AND2B1

B7

LT

A7

OR2

OR2B1

AND2B1

A0
B0
AND2B1

A1
B1

AND2
OR2

OR2B1
AND2
AND2B1

A2
B2

OR2
OR2B1
AND2
AND2B1

A3
B3

OR2
OR2B1

AND2
AND2B1

A4
B4

OR2
OR2B1

AND2

AND2B1

A5
B5

OR2

OR2B1

AND2
AND2B1

A6
B6

OR2

OR2B1

AND2
AND2B1

A7

GT

B7

OR2

A[7:0]

OR2B1

B[7:0]

AND2B1
X7632

COMPM8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are supported for inference rather than instantiation.

338

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ISE 6.3i

COMPMC8, 16

COMPMC8, 16
8-, 16-Bit Magnitude Comparators
Architectures Supported
COMPMC, COMPMC8, COMPMC16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

A[7:0]

COMPMC8
GT
LT

B[7:0]

X4264

A[15:0]

COMPMC16
GT
LT

B[15:0]

No

CoolRunner XPLA3

No

CoolRunner-II

No

COMPMC8 is an 8-bit, magnitude comparator that compares two positive binaryweighted words A7 A0 and B7 B0, where A7 and B7 are the most significant bits.
COMPMC16 is a 16-bit, magnitude comparator that compares two positive binaryweighted words A15 A0 and B15 B0, where A15 and B15 are the most significant
bits.
These comparators are implemented using carry logic with relative location
constraints to ensure efficient logic placement.
The greater-than output (GT) is High when A>B, and the less-than output (LT) is High
when A<B. When the two words are equal, both GT and LT are Low. Equality can be
flagged with this macro by connecting both outputs to a NOR gate.
COMPMC8 Truth Table (also representative of COMPMC16)

X4265

Libraries Guide
ISE 6.3i

Inputs

Outputs

A7, B7

A6, B6

A5, B5

A4, B4

A3, B3

A2, B2

A1, B1

A0, B0

GT

LT

A7>B7

A7<B7

A7=B7

A6>B6

A7=B7

A6<B6

A7=B7

A6=B6

A5>B5

A7=B7

A6=B6

A5<B5

A7=B7

A6=B6

A5=B5

A4>B4

A7=B7

A6=B6

A5=B5

A4<B4

A7=B7

A6=B6

A5=B5

A4=B4

A3>B3

A7=B7

A6=B6

A5=B5

A4=B4

A3<B3

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2>B2

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2<B2

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2=B2

A1>B1

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2=B2

A1<B1

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2=B2

A1=B1

A0>B0

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339

COMPMC8, 16

COMPMC8 Truth Table (also representative of COMPMC16)

Inputs

Outputs

A7, B7

A6, B6

A5, B5

A4, B4

A3, B3

A2, B2

A1, B1

A0, B0

GT

LT

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2=B2

A1=B1

A0<B0

A7=B7

A6=B6

A5=B5

A4=B4

A3=B3

A2=B2

A1=B1

A0=B0

LT

MUXCY
B7
A7

I7

XNOR2

GT

LO
RLOC=R0C0.S1

0 1
DI
CI

MUXCY

B7
A7

I7G

XNOR2

CI

C8

XNOR2

C8G

MUXCY_L
RLOC=R0C0.S1
I6
S
0 1
DI
CI

MUXCY_L
B6
A6

I6G

MUXCY_L
I5

S
DI

XNOR2

CI
C7G

RLOC=R1C0.S1

XNOR2

MUXCY_L

B5
A5

I4

I5G

CI
C6G

RLOC=R1C0.S1

0 1
DI
CI

MUXCY_L
S

XNOR2

MUXCY_L

B4

I4G

CI
C5G

RLOC=R2C0.S1

0 1
DI
CI

MUXCY_L

B3
A3

I3G

XNOR2

CI

MUXCY_L

B2
A2

I2G

MUXCY_L
I0
XNOR2

RLOC=R2C0.S0

0 1
DI

XNOR2

CI

MUXCY_L
B1
A1

I1G

LO
RLOC=R3C0.S0

0 1
DI

XNOR2

CI
C1G

LO
RLOC=R3C0.S1

0 1
CI
DI

LO

C2G

MUXCY_L
RLOC=R3C0.S1
I1
S
0 1
CI
DI
C1

B0
A0

RLOC=R2C0.S0

DI

C4G

MUXCY_L
RLOC=R2C0.S1
S
I2
0 1
DI
CI
C2

XNOR2

LO

0 1

LO

B1
A1

RLOC=R1C0.S0

DI

XNOR2

LO

C4

XNOR2

LO

0 1

LO

B2
A2

RLOC=R1C0.S0

DI

XNOR2

C6
LO

A4

I3

LO

0 1

C5

B3
A3

RLOC=R0C0.S0

0 1

LO

0 1
CI

MUXCY_L

B4
A4

LO

DI

XNOR2

C7

B5
A5

RLOC=R0C0.S0

0 1
DI

LO

B6
A6

LO

MUXCY_L
B0
A0

I0G
XNOR2

LO
RLOC=R3C0.S0

0 1
DI

CI

C0

C0G

GND

GND

A[7:0]
B[7:0]

X8713

COMPMC8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

340

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ISE 6.3i

COMPMC8, 16

LT

O
B7
I7

XNOR2

GT

O RLOC=X1Y3

RLOC=X0Y3
B7

MUXCY
0
1
DI
CI

I7G

XNOR2

A7

MUXCY
0
1
DI
CI

A7

C8G

C8

LO
B6
I6

A6

DI

XNOR2

LO

MUXCY_L
0
1

RLOC=X0Y3

B6
I6G

CI

XNOR2

RLOC=X1Y3

MUXCY_L
0
1
DI
CI

A6
C7

LO
B5
I5

XNOR2

C7G
LO

RLOC=X0Y2
B5

MUXCY_L
0
1
DI
CI

I5G

XNOR2

RLOC=X1Y2

MUXCY_L
0
1
DI
CI

A5
A5
C6

LO
B4
I4

XNOR2

C6G

LO

RLOC=X0Y2
B4

MUXCY_L
0
1
DI
CI

I4G

XNOR2

RLOC=X1Y2

MUXCY_L
0
1
DI
CI

A4
A4
C5

LO
B3
I3

XNOR2

C5G

LO

RLOC=X0Y1
B3

MUXCY_L
0
1
DI
CI

I3G

DI

XNOR2

A3

RLOC=X1Y1

MUXCY_L
0
1
CI

A3
C4G

C4

LO
B2
I2

XNOR2

RLOC=X0Y1

MUXCY_L
0
1
DI
CI

LO
B2
I2G

XNOR2

RLOC=X1Y1

MUXCY_L
0
1
DI
CI

A2
A2
C2

LO
B1
I1

LO

RLOC=X0Y0
B1

MUXCY_L
0
1
DI

XNOR2

C2G

I1G

CI

DI

XNOR2

RLOC=X1Y0

MUXCY_L
0
1
CI

A1
A1
C1

LO
B0
I0
XNOR2

C1G

LO

RLOC=X0Y0

MUXCY_L
0
1
DI
CI

B0
I0G
XNOR2

RLOC=X1Y0

MUXCY_L
0
1
DI
CI

A0
A0
C0

C0G

GND

GND
A[7:0]

B[7:0]
X9313

COMPMC8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide
ISE 6.3i

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341

COMPMC8, 16

Usage
For HDL, these design elements are supported for inference rather than instantiation.

342

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Libraries Guide
ISE 6.3i

CR8CE, CR16CE

CR8CE, CR16CE
8-, 16-Bit Negative-Edge Binary Ripple Counters with Clock Enable and
Asynchronous Clear
Architectures Supported
CR8CE, CR16CE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

CR8CE

Q[7:0]

CE
C

CLR

X4116

CR16CE

Q[15:0]

CE
C

CLR

X4120

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

CR8CE and CR16CE are 8-bit and 16-bit, cascadable, clearable, binary, ripple counters.
The asynchronous clear (CLR), when High, overrides all other inputs and causes the
Q outputs to go to logic level zero. The counter increments when the clock enable
input (CE) is High during the High-to-Low clock (C) transition. The counter ignores
clock transitions when CE is Low.
Larger counters can be created by connecting the last Q output (Q7 for CR8CE, Q15
for CR16CE) of the first stage to the clock input of the next stage. CLR and CE inputs
are connected in parallel. The clock period is not affected by the overall length of a
ripple counter. The overall clock-to-output propagation is n(tC - Q), where n is the
number of stages and the time tC - Q is the C-to-Qz propagation delay of each stage.
The counter is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

CE

Qz Q0

No Chg

Inc

z = 7 for CR8CE; z = 15 for CR16CE.

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CR8CE, CR16CE

Q[7:0]
Q7

FDCE_1
TQ0
CE
C

INV

D
CE
C

FDCE_1
Q0

TQ4
INV
Q3

CLR

D
CE
C

CLR
Q0

Q4

FDCE_1
TQ1
INV

D
CE
C

FDCE_1
Q1

TQ5
INV

D
CE
C

CLR

Q5

FDCE_1
INV

D
CE
C

FDCE_1
Q2

TQ6
INV

D
CE
C

CLR

Q6

FDCE_1
INV

D
CE
C

Q6

CLR

Q2

TQ3

Q5

CLR

Q1

TQ2

Q4

FDCE_1
Q3

TQ7
INV

D
CE
C

CLR
Q3

Q7

CLR
Q7

CLR

VCC

X8142

CR8CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

344

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Libraries Guide
ISE 6.3i

CR8CE, CR16CE

Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0

VCC

Q[7:0]

FDC
D

CE
XOR2

AND2

CLR
Q0

FDC
D
AND2

XOR2

CLR
Q1

FDC
D
AND3

XOR2

CLR
Q2

FDC
D
XOR2
AND4

CLR
Q3

FDC
D
XOR2

CLR

AND5

Q4

FDC
D
XOR2

CLR
AND6

Q5

FDC
D
XOR2

CLR
Q6

AND7

FDC
D
XOR2

CLR
AND8

C
CLR

Q7

INV

X7631

CR8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

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ISE 6.3i

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346

CR8CE, CR16CE

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Libraries Guide
ISE 6.3i

CRD8CE, CRD16CE

CRD8CE, CRD16CE
8-, 16-Bit Dual-Edge Triggered Binary Ripple Counters with Clock
Enable and Asynchronous Clear
Architectures Supported
CRD8CE, CRD16CE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

CRD8CE

Q[7:0]

CE
C

CLR

X9748

CRD16CE

Q[15:0]

CE
C

CLR

X9749

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

CRD8CE and CRD16CE are dual edge triggered 8-bit and 16-bit, cascadable, clearable,
binary, ripple counters. The asynchronous clear (CLR), when High, overrides all other
inputs and causes the Q outputs to go to logic level zero. The counter increments
when the clock enable input (CE) is High during the High-to-Low and Low-to-High
clock (C) transitions. The counter ignores clock transitions when CE is Low.
Larger counters can be created by connecting the last Q output (Q7 for CRD8CE, Q15
for CRD16CE) of the first stage to the clock input of the next stage. CLR and CE inputs
are connected in parallel. The clock period is not affected by the overall length of a
ripple counter. The overall clock-to-output propagation is n(tC - Q), where n is the
number of stages and the time tC - Q is the C-to-Qz propagation delay of each stage.
The counter is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Outputs

CLR

CE

Qz Q0

No Chg

Inc

Inc

z = 7 for CR8CE; z = 15 for CR16CE.

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347

CRD8CE, CRD16CE

Q7
Q6

Q[7:0]

Q5
Q4
Q3
Q2
Q1
Q0

VCC

FDDC
D

CE
XOR2

AND2

C
CLR
Q0

FDDC
D
AND2

XOR2

C
CLR
Q1

FDDC
D
AND3

XOR2

C
CLR
Q2

FDDC
D
XOR2
AND4

C
CLR
Q3

FDDC
D
XOR2

C
CLR

AND5

Q4

FDDC
D
XOR2

C
CLR

AND6

Q5

FDDC
D
XOR2

C
CLR
Q6

AND7

FDDC
D
XOR2

C
CLR

AND8

Q7

C
INV

CLR

X9750

CRD8CE Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

348

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Libraries Guide
ISE 6.3i

D2_4E

D2_4E
2- to 4-Line Decoder/Demultiplexer with Enable
Architectures Supported
D2_4E
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

A0

D2_4E

A1

D0
D1

D3

D2

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

When the enable (E) input of the D2_4E decoder/demultiplexer is High, one of four
active-High outputs (D3 D0) is selected with a 2-bit binary address (A1 A0) input.
The non-selected outputs are Low. Also, when the E input is Low, all outputs are Low.
In demultiplexer applications, the E input is the data input.
Inputs

X3853

Outputs

A1

A0

D3

D2

D1

D0

D0
AND3B2

D1
AND3B1

D2
AND3B1

E
A0
A1

D3
AND3

X7794

D2_4E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

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ISE 6.3i

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349

350

D2_4E

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Libraries Guide
ISE 6.3i

D3_8E

D3_8E
3- to 8-Line Decoder/Demultiplexer with Enable
Architectures Supported
D3_8E
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

A0
A1
A2

D3_8E

D0
D1
D2
D3

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

When the enable (E) input of the D3_8E decoder/demultiplexer is High, one of eight
active-High outputs (D7 D0) is selected with a 3-bit binary address (A2 A0) input.
The non-selected outputs are Low. Also, when the E input is Low, all outputs are Low.
In demultiplexer applications, the E input is the data input.

D4
D5

Inputs

D6
E

D7

X3854

Libraries Guide
ISE 6.3i

Outputs

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

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351

D3_8E

D0

AND4B3

D1

AND4B2
D2

AND4B2
D3

AND4B1
D4

AND4B2
D5

AND4B1
D6

AND4B1

E
A0
A1
A2

D7

AND4
X7795

D3_8E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

352

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Libraries Guide
ISE 6.3i

D4_16E

D4_16E
4- to 16-Line Decoder/Demultiplexer with Enable
Architectures Supported
D4_16E
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

A0

D4_16E

D0

A1

D1

A2

D2

A3

D3
D4
D5

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

When the enable (E) input of the D4_16E decoder/demultiplexer is High, one of 16
active-High outputs (D15 D0) is selected with a 4-bit binary address (A3 A0) input.
The non-selected outputs are Low. Also, when the E input is Low, all outputs are Low.
In demultiplexer applications, the E input is the data input.
See D3_8E for a representative truth table derivation.

D6
D7
D8
D9
D10
D11
D12
D13
D14
E

D15

X3855

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353

D4_16E

D0

AND5B4

D1

AND5B3

D2

AND5B3

D3

AND5B2

D4

AND5B3

D5

AND5B2

D6

AND5B2

D7

AND5B1

D8

AND5B3

D9

AND5B2

D10

AND5B2

D11

AND5B1

D12

AND5B2

D13

AND5B1

D14

AND5B1
E
A0
A1
A2
A3

D15

AND5
X7638

D4_16E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

354

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Libraries Guide
ISE 6.3i

DCM

DCM
Digital Clock Manager
Architectures Supported
DCM
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

CLKIN

CLK0
CLK90
CLK180

RST

CLK270
CLK2X

DSSEN

PSINCDEC
PSEN
PSCLK

No
No

CoolRunner-II

No

DCM is a digital clock manager that provides multiple functions. It can implement a
clock delay locked loop, a digital frequency synthesizer, digital phase shifter, and a
digital spread spectrum.

DCM
CLKFB

XC9500, XC9500XV, XC9500XL

CoolRunner XPLA3

Note: All unused inputs must be driven Low. The program will automatically tie the inputs Low
if they are unused.

CLK2X180

Clock Delay Locked Loop (DLL)

CLKDV
CLKFX
CLKFX180

LOCKED
STATUS [7:0]

PSDONE
X9469

DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3,
Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal
at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN).
The locked output (LOCKED) is high when the two signals are in phase. The signals
are considered to be in phase when their rising edges are within a specified time (ps)
of each other. See The Programmable Logic Data Sheets for the specified time value.
DCM supports two frequency modes for the DLL. By default, the
DLL_FREQUENCY_MODE attribute is set to Low and the frequency of the clock
signal at the CLKIN input must be in the Low (DLL_CLKIN_MIN_LF to
DLL_CLKIN_MAX_LF) frequency range (MHz). See The Programmable Logic Data
Sheets for the current DLL_CLKIN_MIN_LF to DLL_CLKIN_MAX_LF frequency
range values. In Low frequency mode, the CLK0, CLK90, CLK180, CLK270, CLK2X,
CLKDV, and CLK2X180 outputs are available.
When the DLL_FREQUENCY_MODE attribute is set to High, the frequency of the
clock signal at the CLKIN input must be in the High (DLL_CLKIN_MIN_HF to
DLL_CLKIN_MAX_HF) frequency range (MHz). See The Programmable Logic Data
Sheets for the current DLL_CLKIN_MIN_HF to DLL_CLKIN_MAX_HF frequency
range values. In High frequency mode, only the CLK0, CLK180, and CLKDV outputs
are available.
On-chip synchronization is achieved by connecting the CLKFB input to a point on the
global clock network driven by a BUFG, a global clock buffer. The BUFG connected to
the CLKFB input of the DCM must be sourced from either the CLK0 or CLK2X
outputs of the same DCM. The CLKIN input should be connected to the output of an
IBUFG, with the IBUFG input connected to a pad driven by the system clock.
Off-chip synchronization is achieved by connecting the CLKFB input to the output of
an IBUFG, with the IBUFG input connected to a pad. Either the CLK0 or CLK2X

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355

DCM

output can be used but not both. The CLK0 or CLK2X must be connected to the input
of OBUF, an output buffer. The CLK_FEEDBACK attribute controls whether the CLK0
output, the default, or the CLK2X output is the source of the CLKFB input.
The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION
attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN
input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is
the same as that of the CLK0 output. The duty cycle of the CLK2X, CLK2X180, and
CLKDV outputs is 50-50 unless CLKDV_DIVIDE is a non-integer and the
DLL_FREQUENCY_MODE is High (see CLKDV_DIVIDE, in the Constraints Guide
for details). The frequency of the CLKDV output is determined by the value assigned
to the CLKDV_DIVIDE attribute.
DCM Clock Delay Lock Loop Outputs
Output

Description

CLK0

Clock at 1x CLKIN frequency

CLK180

Clock at 1x CLK0 frequency, shifted 180o with regards to CLK0

CLK270*

Clock at 1x CLK0 frequency, shifted 270o with regards to CLK0

CLK2X*

Clock at 2x CLK0 frequency, in phase with CLK0

CLK2X180*

Clock at 2x CLK0 frequency shifted 180o with regards to CLK2X

CLK90*

Clock at 1x CLK0 frequency, shifted 90o with regards to CLK0

CLKDV

Clock at (1/n) x CLK0 frequency, where n=CLKDV_DIVIDE value.

CLKDV is in phase with CLK0.

LOCKED

All enabled DCM features locked.

* The CLK90, CLK270, CLK2X, and CLK2X180 outputs are not available if the
DLL_FREQUENCY_MODE is set to High.

Digital Frequency Synthesizer (DFS)

The CLKFX and CLKFX180 outputs in conjunction with the CLKFX_MULTIPLY and
CLKFX_DIVIDE attributes provide a frequency synthesizer that can be any multiple
or division of CLKIN. CLKFX and CLKIN are in phase every CLKFX_MULTIPLY
cycles of CLKFX and every CLKFX_DIVIDE cycles of CLKIN when a feedback is
provided to the CLKFB input of the DLL. The frequency of CLKFX is defined by the
following equation.
FrequencyCLKFX=
(CLKFX_MULTIPLY_value/CLKFX_DIVIDE_value) * FrequencyCLKIN

Both the CLKFX or CLKFX180 output can be used simultaneously.

CLKFX180 is 1x the CLKFX frequency, shifted 180o with regards to CLKFX. CLKFX
and CLKFX180 always have a 50/50 duty cycle.
The DFS_FREQUENCY_MODE attribute specifies the allowable input clock and
output clock frequency ranges.
The CLK_FEEDBACK attribute set to NONE will cause the DCM to be in the Digital
Frequency Synthesizer mode. The CLKFX and CLKFX180 will be generated without
phase correction with respect to CLKIN.
See The Programmable Logic Data Sheets for the allowable frequency range of CLKFX.

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ISE 6.3i

DCM

Digital Phase Shifter (DPS)

The phase shift (skew) between the rising edges of CLKIN and CLKFB may be
configured as a fraction of the CLKIN period with the PHASE_SHIFT attribute. This
allows the phase shift to remain constant as ambient conditions change. The
CLKOUT_PHASE_SHIFT attribute controls the use of the PHASE_SHIFT value. By
default, the CLKOUT_PHASE_SHIFT attribute is set to NONE and the
PHASE_SHIFT attribute has no effect.
By creating skew between CLKIN and CLKFB, all DCM output clocks are phase
shifted by the amount of the skew.
When the CLKOUT_PHASE_SHIFT attribute is set to FIXED, the skew set by the
PHASE_SHIFT attribute is used at configuration for the rising edges of CLKIN and
CLKFB. The skew remains constant.
When the CLKOUT_PHASE_SHIFT attribute is set to VARIABLE, the skew set at
configuration is used as a starting point and the skew value can be changed
dynamically during operation using the PS* signals. This digital phase shifter feature
is controlled by a synchronous interface. The inputs PSEN (phase shift enable) and
PSINCDEC (phase shift increment/decrement) are set up to the rising edge of PSCLK
(phase shift clock). The PSDONE (phase shift done) output is clocked with the rising
edge of PSCLK (the phase shift clock). PSDONE must be connected to implement the
complete synchronous interface. The rising-edge skew between CLKIN and CLKFB
may be dynamically adjusted after the LOCKED output goes High.
The PHASE_SHIFT attribute value specifies the initial phase shift amount when the
device is configured. Then the PHASE_SHIFT value is changed one unit when PSEN
is activated for one period of PSCLK. The PHASE_SHIFT value is incremented when
PSINCDEC is High and decremented when PSINCDEC is Low during the period that
PSEN is High. When the DCM completes an increment or decrement operation, the
PSDONE output goes High for a single PSCLK cycle to indicate the operation is
complete. At this point the next change may be made. When RST (reset) is High, the
PHASE_SHIFT attribute value is reset to the skew value set at configuration.
If CLKOUT_PHASE_SHIFT is FIXED or NONE, the PSEN, PSINCDEC, and PSCLK
inputs must be tied to GND. The program will automatically tie the inputs to GND if
they are not connected by the user.

Digital Spread Spectrum (DSS)

The DSS feature is not supported in all of the devices supported under the DCM
(Virtex-II, Virtex-II Pro, Spartan-3). However, the DSSEN pin remains an input pin in
the DCM primitive to maintain compatibility with all DCM library versions. For all
designs using DCM, connect the DSSEN pin to GND and leave DSS_MODE at its
default value: NONE. If you are using the Architecture Wizard (DCM/Clocking
Wizard), this connection has been done automatically.

Additional Status Bits

The STATUS output bits return the following information.

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357

DCM

DCM Additional Status Bits

Bit

Description

Phase Shift Overflow*

1 = |PHASE_SHIFT| > 255

DLL CLKIN stopped**

1 = CLKIN stopped toggling

DLL CLKFX stopped

1 = CLKFX stopped toggling

No

No

No

No

No

* Phase Shift Overflow will also go high if the end of the phase shift delay line is
reached (see the product data sheet for the most current value of the maximum
shifting delay).
** If only the DFS outputs are used (CLKFX & CLKFX180), this status bit will not go
high if CLKIN stops.

LOCKED
When LOCKED is high, all enabled signals are locked.

RST
The master reset input (RST) resets DCM to its initial (power-on) state. The signal at
the RST input is asynchronous and must be held High for 2ns.

Usage
This component is generally instantiated in the code as it cannot be easily inferred in
synthesis tools. Some synthesis tools may allow inference via an attribute. See your
synthesis tool documentation.

VHDL Instantiation Template

-- Component Declaration for DCM should be placed
-- after architecture statement but before begin keyword
component DCM
-- synthesis translate_off
generic (CLK_FEEDBACK : string := "1X";
CLKDV_DIVIDE : real:= 2.0; -- (1.5, 2.0, 2.5, 3.0, 4.0, 5.0,
8.0, 16.0)
CLKFX_DIVIDE : integer := 1; -- (1 to 4096)
CLKFX_MULTIPLY : integer := 4; -- (1.5, 2.0, 2.5, 3.0, 3.5,
4.0, 5.0, 5.5,
-- 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0,
14.0, 15.0, 16.0)
CLKIN_DIVIDE_BY_2 : boolean := FALSE; -- (TRUE, FALSE)

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ISE 6.3i

DCM

CLKOUT_PHASE_SHIFT : string := "NONE";

DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE)
PHASE_SHIFT : real := 0;
STARTUP_WAIT : boolean := FALSE); -- (TRUE, FALSE)
-- synthesis translate_on
port (CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK2X180 : out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
CLKFX : out STD_ULOGIC;
CLKFX180 : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
PSDONE : out STD_ULOGIC;
STATUS : out STD_LOGIC_VECTOR (7 downto 0);
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
DSSEN : in STD_ULOGIC;
PSCLK : in STD_ULOGIC;
PSEN : in STD_ULOGIC;
PSINCDEC : in STD_ULOGIC;
RST : in STD_ULOGIC);
end component;
-- Component Attribute specification for DCM
-- should be placed after architecture declaration but
-- before the begin keyword
attribute
attribute
attribute
attribute
attribute
attribute
attribute
attribute
attribute
attribute
attribute
attribute
attribute

CLK_FEEDBACK : string;
CLKDV_DIVIDE : string;
CLKFX_DIVIDE : integer;
CLKFX_MULTIPLY : integer;
CLKIN_DIVIDE_BY_2 : string;
CLKOUT_PHASE_SHIFT : string;
DESKEW_ADJUST : string;
DFS_FREQUENCY_MODE : string;
DLL_FREQUENCY_MODE : string;
DSS_MODE : string;
DUTY_CYCLE_CORRECTION : string;
PHASE_SHIFT : real;
STARTUP_WAIT : boolean;

attribute CLK_FEEDBACK of DCM_instance_name: label is "1X";

attribute CLKDV_DIVIDE of DCM_instance_name: label is 2.0;
-- (1.5,2,2.5,3,4, 5, 8, 16) are valid for CLKDV_DIVIDE
attribute CLKFX_DIVIDE of DCM_instance_name: label is 1;
attribute CLKFX_MULTIPLY of DCM_instance_name: label is 4;
attribute CLKIN_DIVIDE_BY_2 of DCM_instance_name: label is "FALSE";
attribute CLKOUT_PHASE_SHIFT of DCM_instance_name: label is "NONE";
attribute DESKEW_ADJUST of DCM_instance_name : label is
"SYSTEM_SYNCHRONOUS";
attribute DFS_FREQUENCY_MODE of DCM_instance_name: label is "LOW";

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DCM

attribute DLL_FREQUENCY_MODE of DCM_instance_name: label is "LOW";

attribute DSS_MODE of DCM_instance_name: label is "NONE";
attribute DUTY_CYCLE_CORRECTION of DCM_instance_name: label is TRUE;
-- (TRUE, FALSE) are valid for DUTY_CYCLE_CORRECTION
attribute PHASE_SHIFT of DCM_instance_name: label is 0;
attribute STARTUP_WAIT of DCM_instance_name: label is FALSE; -(TRUE,FALSE)
-- Component Instantiation for DCM should be placed
-- in architecture after the begin keyword
DCM_INSTANCE_NAME : DCM
-- synthesis translate_off
generic map(CLK_FEEDBACK => "string_value",
CLKDV_DIVIDE => string_value, -(1.5,2,2.5,3,4,5,8,16)
CLKFX_DIVIDE => integer_value,
CLKFX_MULTIPLY => integer_value,
CLKIN_DIVIDE_BY_2 => boolean_value, -- (TRUE, FALSE)
CLKOUT_PHASE_SHIFT => "string_value",
DESKEW_ADJUST => "string_value",
DFS_FREQUENCY_MODE => "string_value",
DLL_FREQUENCY_MODE => "string_value",
DSS_MODE => "string_value",
DUTY_CYCLE_CORRECTION => boolean_value, -- (TRUE, FALSE)
PHASE_SHIFT => integer_value,
STARTUP_WAIT => boolean) -- (TRUE, FALSE)
-- synthesis translate_on
port map (CLK0 => user_CLK0,
CLK180 => user_CLK180,
CLK270 => user_CLK270,
CLK2X => user_CLK2X,
CLK2X180 => user_CLK2X180,
CLK90 => user_CLK90,
CLKDV => user_CLKDV,
CLKFX => user_CLKFX,
CLKFX180 => user_CLKFX180,
LOCKED => user_LOCKED)
PSDONE => user_PSDONE,
STATUS => user_STATUS,
CLKFB => user_CLKFB,
CLKIN => user_CLKIN,
DSSEN => user_DSSEN,
PSCLK => user_PSCLK,
PSEN => user_PSEN,
PSINCDEC => user_PSINCDEC,
RST => user_RST);

Verilog Instantiation Template

DCM DCM_instance_name (.CLK0 (user_CLK0),
.CLK180 (user_CLK180),
.CLK270 (user_CLK270),
.CLK2X (user_CLK2X),
.CLK2X180 (user_CLK2X180),
.CLK90 (user_CLK90),
.CLKDV (user_CLKDV),
.CLKFX (user_CLKFX),

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ISE 6.3i

DCM

.CLKFX180 (user_CLKFX180),
.LOCKED (user_LOCKED),
.PSDONE (user_PSDONE),
.STATUS (user_STATUS),
.CLKFB (user_CLKFB),
.CLKIN (user_CLKIN),
.DSSEN (user_DSSEN),
.PSCLK (user_PSCLK),
.PSEN (user_PSEN),
.PSINCDEC (user_PSINCDEC),
.RST (user_RST));
defparam DCM_instance_name.CLK_FEEDBACK => "string_value";
defparam DCM_instance_name.CLKDV_DIVIDE = integer_value;
//(1.5,2,2.5,3,4,5,8,16)
defparam DCM_instance_name.CLKFX_DIVIDE => integer_value;
defparam DCM_instance_name.CLKFX_MULTIPLY => integer_value;
defparam DCM_instance_name.CLKIN_DIVIDE_BY_2 => boolean_value; //
(TRUE, FALSE)
defparam DCM_instance_name.CLKOUT_PHASE_SHIFT => "string_value";
defparam DCM_instance_name.DESKEW_ADJUST => "string_value";
defparam DCM_instance_name.DFS_FREQUENCY_MODE => "string_value";
defparam DCM_instance_name.DLL_FREQUENCY_MODE => "string_value";
defparam DCM_instance_name.DSS_MODE => "string_value";
defparam DCM_instance_name.DUTY_CYCLE_CORRECTION => "string_value";//
(TRUE, FALSE)
defparam DCM_instance_name.PHASE_SHIFT => integer_value;
defparam DCM_instance_name.STARTUP_WAIT => boolean_value; // (TRUE,
FALSE)

Note: Additional syntax may be necessary in order to pass the DCM attributes via the
synthesis tool. The above defparam statements may need to be isolated from the synthesis tool
with translate_off/translate_on directives. See your synthesis tool documentation for more
information on Verilog attribute passing to ensure that you properly pass these attributes to the
synthesis tool. Otherwise, you may pass these attributes to the UCF file.

Commonly Used Constraints

CLKDV_DIVIDE, CLK_FEEDBACK, CLKFX_DIVIDE, CLKFX_MULTIPLY,
CLKIN_DIVIDE_BY_2, CLKOUT_PHASE_SHIFT, DUTY_CYCLE_CORRECTION,
DFS_FREQUENCY_MODE, DLL_FREQUENCY_MODE, LOC, PHASE_SHIFT,
STARTUP_WAIT, DESKEW_ADJUST

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362

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Libraries Guide
ISE 6.3i

DEC_CC4, 8, 16

DEC_CC4, 8, 16
4-, 8-, 16-Bit Active Low Decoders
Architectures Supported
DEC_CC4, DEC_CC8, DEC_CC16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

A0
A1

DEC_CC4

A2
O

A3
C_IN

X4927

No

CoolRunner XPLA3

No

CoolRunner-II

No

These decoders are used to build wide-decoder functions. They are implemented by
cascading CY_MUX elements driven by lookup tables (LUTs). The C_IN pin can only
be driven by the output (O) of a previous decode stage. When one or more of the
inputs (A) are Low, the output is Low. When all the inputs are High and the C_IN
input is High, the output is High. You can decode patterns by adding inverters to
inputs.
Inputs

A0
A1

A0

DEC_CC8

A1

Outputs

Az

C_IN

A2

A3
A4

A5

A6
A7

C_IN

z = 3 for DEC_CC4; z = 7 for DEC_CC8; z = 15 for DEC_CC16

X4928

A0
A1

DEC_CC16
A3

A2

A2

A3
A4

A1

MUXCY O
S0

A0

A5

0
DI

1
CI

AND4

A6
A7
A8

GND

A9
A10

C_IN

A11

The C_IN pin can only be initialized

by a CY_INIT or by the output of a
previous decode stage.

A12
A13
A14
O

A15
C_IN

X8717

DEC_CC4 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

X4929

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363

DEC_CC4, 8, 16

DEC_CC4
A0

A0

A1

A1

A0

A2

A3

A3

C_IN

DEC_CC4
A4

A0

A5

A1

A6

A2

A7
C_IN

A3

C_IN

The C_IN pin can only be initialized

by a CY_INIT or by the output of a
previous decode stage.
X6396

DEC_CC8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
DEC_CC4 cannot be directly inferred or instantiated. The proper way to use a
DEC_CC4 is to infer the primitive components that make up the DEC_CC4.

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Libraries Guide
ISE 6.3i

DECODE4, 8, 16

DECODE4, 8, 16
4-, 8-, 16-Bit Active-Low Decoders
Architectures Supported
DECODE4, DECODE8, DECODE16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

A0

DECODE4

A0
A1

A1
A2
O

A3

DECODE16

A2
A3
A4
A5
A6
A7

A0
A1

DECODE8

A8
A9

A2

A10
A11

A3
A4

A12

A5

A13
A14

A6
O

A7

A15

X9807

DECODE Representations
In Spartan-II, , Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X decoders are implemented using combinations of LUTs and MUXCYs.

Inputs

Outputs*

A0

A1

Az

z = 3 for DECODE4, z = 7 for DECODE8; z = 15 for DECODE16

*A pull-up resistor must be connected to the output to establish High-level drive current.

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DECODE4, 8, 16

FMAP
I4
I3
S1
S0
A7
A6

I1
MAP=PUO
RLOC=R0C0.S0

S1

A5
A4

I2

FMAP

AND4
A7
A6

A5
A4

AND2
A3

I4
I3
I2

S1

I1
MAP=PUO
RLOC=R0C0.S1

A2

S0

A1
A0

FMAP
A3

AND4

A2
A1
A0

I4
I3
I2

S0

I1
MAP=PUO
RLOC=R0C0.S1

X8703

DECODE8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I4
I3
S1
S0

I2

I1
MAP=PUO
RLOC=X0Y1

A7
A6

FMAP

S1

A5

A7
A6

A4

A5

AND4

A4

I4
I3
I2

S1

I1

O
MAP=PUO
RLOC=X0Y0

AND2
A3

FMAP

A2

A3

S0

A1

A2

A0

A1
AND4

A0

I4
I3
I2

S0

I1
MAP=PUO
RLOC=X0Y0
X9316

DECODE8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferrred rather than instantiated.

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Libraries Guide
ISE 6.3i

DECODE32, 64

DECODE32, 64
32- and 64-Bit Active-Low Decoders
Architectures Supported
DECODE32, DECODE64
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

DECODE32 and DECODE64 are 32- and 64-bit active-low decoders. These decoders
are implemented using combinations of LUTs and MUXCYs.

A[31:0] DECODE32
O

See DECODE4, 8, 16 for a representative schematic.

X8203

Inputs

Outputs

A0

A1

Az

A[63:0] DECODE64

X8204

z = 31 for DECODE32, z = 63 for DECODE64

Usage
For HDL, these design elements are inferred rather than instantiated.

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368

DECODE32, 64

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Libraries Guide
ISE 6.3i

FD

FD
D Flip-Flop
Architectures Supported
FD
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FD

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FD is a single D-type flip-flop with data input (D) and data output (Q). The data on
the D inputs is loaded into the flip-flop during the Low-to-High clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.

X3715

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
See FD4, 8, 16 for information on multiple D flip-flops for XC9500/XV/XL,
CoolRunner XPLA3, and CoolRunner-II.
Inputs

Outputs

FDCP
D

PRE

C
CLR
Q

X7797
GND

FD Implementation XC9500/XV/XL, CoolRunner XPLA3,

CoolRunner-II

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FD

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FD should be placed
-- after architecture statement but before begin keyword
component FD
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;
-- Component Attribute specification for FD
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FD_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FD should be placed

-- in architecture after the begin keyword
FD_INSTANCE_NAME : FD
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D);

Verilog Instantiation Template

FD FD_instance_name (.Q (user_Q),
.C (user_C),
.D (user_D));
defparam FD_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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ISE 6.3i

FD_1

FD_1
D Flip-Flop with Negative-Edge Clock
Architectures Supported
FD_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FD_1

No

CoolRunner XPLA3

No

CoolRunner-II

No

FD_1 is a single D-type flip-flop with data input (D) and data output (Q). The data on
the D input is loaded into the flip-flop during the High-to-Low clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.

X3726

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FD_1 should be placed
-- after architecture statement but before begin keyword
component FD_1
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;

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FD_1

-- Component Attribute specification for FD_1

-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FD_1_instance_name : label is "0";
-- values can be (0 or 1)

begin
FD_1_INSTANCE_NAME : FD_1
-- synthesis translate_off
generic map (
INIT => bit_value) -- INIT value can be '0' or '1'
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D);
end Behavioral

Verilog Instantiation Template

FD_1 FD_1_instance_name (.Q (user_Q),
.C (user_C),
.D (user_D));
defparam FD_1_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
and XBLKNM

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Libraries Guide
ISE 6.3i

FD4, 8, 16

FD4, 8, 16
Multiple D Flip-Flops
Architectures Supported
FD4, FD8, FD16
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

D0

FD4

Q0

D1

Q1

D2

Q2

D3

Q3

X4608

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FD4, FD8, FD16 are multiple D-type flip-flops with data inputs (D) and data outputs
(Q). FD4, FD8, and FD16 are, respectively, 4-bit, 8-bit, and 16-bit registers, each with a
common clock (C). The data on the D inputs is loaded into the flip-flop during the
Low-to-High clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

D[7:0]

FD8

Outputs

Q[7:0]

X4609

Dz D0

Qz Q0

z = 3 for FD4; z = 7 for FD8; z = 15 for FD16

D[15:0]

FD16

Q[15:0]

C
X4610

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373

FD4, 8, 16

Q[7:0]
FD

FD
D0

Q0

D4

D
C

Q4

Q0
FD

FD
D1

Q1

D5

D
C

Q5
FD

FD
D

Q2

D6

D
C

Q6
FD

FD
D

D[7:0]

Q6

Q2

D3

Q5

Q1

D2

Q4

Q3

D7

Q7

Q3

Q7

X8128

FD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

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ISE 6.3i

FD4CE, FD8CE, FD16CE

FD4CE, FD8CE, FD16CE

4-, 8-, 16-Bit Data Registers with Clock Enable and Asynchronous
Clear
Architectures Supported
FD4CE, FD8CE, FD16CE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D0
D1
D2
D3

FD4CE

Q0
Q1
Q2
Q3

CE
C

CLR

D[7:0]

X3733

FD8CE

Q[7:0]

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FD4CE, FD8CE, and FD16CE are, respectively, 4-, 8-, and 16-bit data registers with
clock enable and asynchronous clear. When clock enable (CE) is High and
asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the
corresponding data outputs (Q) during the Low-to-High clock (C) transition. When
CLR is High, it overrides all other inputs and resets the data outputs (Q) Low. When
CE is Low, clock transitions are ignored.
The flip-flops are asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

CE
C

CLR

D[15:0]

Macro

X3850

FD16CE

Q[15:0]

Inputs

CE
C

CLR

GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

X3736

Outputs

CLR

CE

Dz D0

Qz Q0

No Chg

Dn

Dn

z = 3 for FD4CE; z = 7 for FD8CE; z = 15 for FD16CE.

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FD4CE, FD8CE, FD16CE

Q[7:0]

FDCE
FDCE
D0

D
CE
C

D4
Q

Q0

D
CE
C

Q4

CLR
CLR

Q4
Q0

FDCE
FDCE
D1

D
CE
C

D5
Q

Q1

D
CE
C

Q5

CLR

CLR

Q5
Q1

FDCE
FDCE
D2

D
CE
C

D6
Q

Q2

D
CE
C

Q6

CLR

CLR

Q6
Q2

FDCE
FDCE
D3

D
CE
C

D7
Q

Q3

D
CE
C

Q7

CLR

CLR

Q7
Q3

D[7:0]
CE
C
CLR
X7799

FD8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

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ISE 6.3i

FD4RE, FD8RE, FD16RE

FD4RE, FD8RE, FD16RE

4-, 8-, 16-Bit Data Registers with Clock Enable and Synchronous Reset
Architectures Supported
FD4RE, FD8RE, FD16RE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D0
D1
D2
D3
CE

FD4RE

Q0
Q1
Q2
Q3

D[7:0]

X3734

FD8RE

Q[7:0]

CE

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FD4RE, FD8RE, and FD16RE are, respectively, 4-, 8-, and 16-bit data registers. When
the clock enable (CE) input is High, and the synchronous reset (R) input is Low, the
data on the data inputs (D) is transferred to the corresponding data outputs (Q0)
during the Low-to-High clock (C) transition. When R is High, it overrides all other
inputs and resets the data outputs (Q) Low on the Low-to-High clock transition.
When CE is Low, clock transitions are ignored.
The flip-flops are asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

D[15:0]

Macro

X3735

FD16RE

GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

Q[15:0]

Inputs

CE
C

X3737

Outputs

CE

Dz D0

Qz Q0

No Chg

Dn

Dn

z = 3 for FD4RE; z = 7 for FD8RE; z = 15 for FD16RE

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FD4RE, FD8RE, FD16RE

Q[7:0]

FDRE

FDRE
D0

D
CE
C

Q0

D4

D
CE
C

Q4

Q0

FDRE

FDRE
D1

D
CE
C

Q1

D5

D
CE
C

Q5

FDRE

FDRE
D
CE
C

Q2

D6

D
CE
C

Q6

FDRE

FDRE
D
CE
C

Q6

Q2

D3

Q5

Q1

D2

Q4

Q3

D7

D
CE
C

R
Q3

Q7

R
Q7

D[7:0]
CE
C
R

X8195

FD8RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

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Libraries Guide
ISE 6.3i

FDC

FDC
D Flip-Flop with Asynchronous Clear
Architectures Supported
FDC
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDC

CLR

X3716

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FDC is a single D-type flip-flop with data (D) and asynchronous clear (CLR) inputs
and data output (Q). The asynchronous CLR, when High, overrides all other inputs
and sets the Q output Low. The data on the D input is loaded into the flip-flop when
CLR is Low on the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

FDCP
D

PRE

C
CLR
Q

CLR

X7801
GND

FDC Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

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FDC

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDC should be placed
-- after architecture statement but before begin keyword
component FDC
-- synthesis translate_off
generic (INIT : bit:= '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDC
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDC_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDC should be placed

-- in architecture after the begin keyword
FDC_INSTANCE_NAME : FDC
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
CLR => user_CLR,
D => user_D);

Verilog Instantiation Template

FDC FDC_instance_name (.Q (user_Q),
.C (user_C),
.CLR (user_CLR),
.D (user_D));
defparam FDC_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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Libraries Guide
ISE 6.3i

FDC_1

FDC_1
D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
Architectures Supported
FDC_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDC_1

CLR
X3847

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDC_1 is a single D-type flip-flop with data input (D), asynchronous clear input
(CLR), and data output (Q). The asynchronous CLR, when active, overrides all other
inputs and sets the Q output Low. The data on the D input is loaded into the flip-flop
during the High-to-Low clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDC_1 should be placed
-- after architecture statement but before begin keyword
component FDC_1
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;

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FDC_1

C : in STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDC_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDC_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDC_1 should be placed

-- in architecture after the begin keyword
FDC_1_INSTANCE_NAME : FDC_1
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
CLR => user_CLR,
D => user_D);

Verilog Instantiation Template

FDC_1 FDC_1_instance_name (.Q (user_Q),
.C (user_C),
.CLR (user_CLR),
.D (user_D));
defparam FDC_1_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, U_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
and XBLKNM

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Libraries Guide
ISE 6.3i

FDCE

FDCE
D Flip-Flop with Clock Enable and Asynchronous Clear
Architectures Supported
FDCE
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDCE

CE
C

CLR

X3717

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

FDCE is a single D-type flip-flop with clock enable and asynchronous clear. When
clock enable (CE) is High and asynchronous clear (CLR) is Low, the data on the data
input (D) of FDCE is transferred to the corresponding data output (Q) during the
Low-to-High clock (C) transition. When CLR is High, it overrides all other inputs and
resets the data output (Q) Low. When CE is Low, clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
For XC9500XL and XC9500XV devices, logic connected to the clock enable (CE) input
may be implemented using the clock enable product term (p-term) in the macrocell,
provided the logic can be completely implemented using the single p-term available
for clock enable without requiring feedback from another macrocell. Only FDCE and
FDPE flip-flops primitives may take advantage of the clock-enable p-term.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

CE

No Chg

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

Libraries Guide
ISE 6.3i

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383

FDCE

VHDL Instantiation Template

-- FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
-Clock Enable (posedge clk). All families.
-- Xilinx HDL Libraries Guide version 7.1i
FDCE_inst : FDCE
port map (
Q => Q,
-C => C,
-CE => CE,
-CLR => CLR, -D => D
-);

Data output
Clock input
Clock enable input
Asynchronous clear input
Data input

-- End of FDCE_inst instantiation

Verilog Instantiation Template

// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
//
Clock Enable (posedge clk). All families.
// Xilinx HDL Libraries Guide version 7.1i
FDCE FDCE_inst
.Q(Q),
.C(C),
.CE(CE),
.CLR(CLR),
.D(D)
);
//
//
//
//

(
//
//
//
//
//

Data output
Clock input
Clock enable input
Asynchronous clear input
Data input

The following defparam declaration is only necessary if you wish to

change the initial value of the register to a one. If the instance
name to the FDCE is changed, that change needs to be reflected in
the defparam statements.
defparam FDCE_inst.INIT = 1'b0;

// End of FDCE_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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Libraries Guide
ISE 6.3i

FDCE_1

FDCE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and
Asynchronous Clear
Architectures Supported
FDCE_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDCE_1

CE
C

CLR

X3727

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous
clear (CLR) inputs, and data output (Q). The asynchronous CLR input, when High,
overrides all other inputs and sets the Q output Low. The data on the D input is
loaded into the flip-flop when CLR is Low and CE is High on the High-to-Low clock
(C) transition. When CE is Low, the clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

CE

No Chg

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- FDCE_1: Single Data Rate D Flip-Flop with Asynchronous Clear and
-Clock Enable (negedge clock). All families.
-- Xilinx HDL Libraries Guide version 7.1i
FDCE_1_inst : FDCE_1

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385

FDCE_1

port map (
Q => Q,
C => C,
CE => CE,
CLR => CLR,
D => D
);

------

Data output
Clock input
Clock enable input
Asynchronous clear input
Data input

-- End of FDCE_1_inst instantiation

Verilog Instantiation Template

// FDCE_1: Single Data Rate D Flip-Flop with Asynchronous Clear and
//
Clock Enable (negedge clock). All families.
// Xilinx HDL Libraries Guide version 7.1i
FDCE_1 FDCE_1_inst (
.Q(Q),
// Data output
.C(C),
// Clock input
.CE(CE),
// Clock enable input
.CLR(CLR), // Asynchronous clear input
.D(D)
// Data input
);
//
//
//
//

The following defparam declaration is only necessary if you wish to

change the initial value of the register to a one. If the instance
name to the FDCE_1 is changed, that change needs to be reflected in
the defparam statements.
defparam FDCE_1_inst.INIT = 1'b0;

// End of FDCE_1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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ISE 6.3i

FDCP

FDCP
D Flip-Flop Asynchronous Preset and Clear
Architectures Supported
FDCP
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

FDCP
Q

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

FDCP is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear
(CLR) inputs, and data output (Q). The asynchronous PRE, when High, sets the Q
output High; CLR, when High, resets the output Low. Data on the D input is loaded
into the flip-flop when PRE and CLR are Low on the Low-to-High clock (C) transition.

The flip-flop is asynchronously cleared, output Low, when power is applied.

CLR

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.

X4397

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

PRE

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDCP should be placed
-- after architecture statement but before begin keyword
component FDCP

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ISE 6.3i

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387

FDCP

-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDCP
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDCP_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDCP should be placed

-- in architecture after the begin keyword
FDCP_INSTANCE_NAME : FDCP
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
CLR => user_CLR,
D => user_D,
PRE => user_PRE);

Verilog Instantiation Template

FDCP FDCP_instance_name (.Q (user_Q),
.C (user_C),
.CLR (user_CLR),
.D (user_D),
.PRE (user_PRE));
defparam FDCP_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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ISE 6.3i

FDCP_1

FDCP_1
D Flip-Flop with Negative-Edge Clock and Asynchronous Preset and
Clear
Architectures Supported
FDCP_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

FDCP_1
Q

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDCP_1 is a single D-type flip-flop with data (D), asynchronous preset (PRE) and
clear (CLR) inputs, and data output (Q). The asynchronous PRE, when High, sets the
Q output High; CLR, when High, resets the output Low. Data on the D input is loaded
into the flip-flop when PRE and CLR are Low on the High-to-Low clock (C) transition.

The flip-flop is asynchronously cleared, output Low, when power is applied.

CLR

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

X8357

GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

PRE

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDCP_1 should be placed
-- after architecture statement but before begin keyword
component FDCP_1
-- synthesis translate_off

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389

FDCP_1

generic (INIT : bit := '1');

-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDCP_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDCP_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDCP_1 should be placed

-- in architecture after the begin keyword
FDCP_1_INSTANCE_NAME : FDCP_1
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
CLR => user_CLR,
D => user_D,
PRE => user_PRE);

Verilog Instantiation Template

FDCP_1 FDCP_1_instance_name (.Q (user_Q),
.C (user_C),
.CLR (user_CLR),
.D (user_D),
.PRE (user_PRE));
defparam FDCP_1_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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Libraries Guide
ISE 6.3i

FDCPE

FDCPE
D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
Architectures Supported
FDCPE
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

PRE

FDCPE

CE

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Primitive

FDCPE is a single D-type flip-flop with data (D), clock enable (CE), asynchronous
preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The
asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the
output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are
Low and CE is High on the Low-to-High clock (C) transition. When CE is Low, the
clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.

CLR
X4389

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

PRE

CE

No Chg

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391

FDCPE

VCC

CE
AND2B1

AND2

D
AND2

OR2

FDCP

PRE

D
C

PRE

C
CLR
Q

CLR

X7804

FDCPE Implementation XC9500/XV/XL, CoolRunner XPLA3

Usage
Below are example templates for instantiating this component into a design. These
end

VHDL Instantiation Template

-- FDCPE: Single Data Rate D Flip-Flop with Asynchronous Clear,
-Set and Clock Enable (posedge clk). All families.
-- Xilinx HDL Libraries Guide version 7.1i
FDCPE_inst : FDCPE
port map (
Q => Q,
-C => C,
-CE => CE,
-CLR => CLR, -D => D,
-PRE => PRE
-);

Data output
Clock input
Clock enable input
Asynchronous clear input
Data input
Asynchronous set input

-- End of FDCPE_inst instantiation

Verilog Instantiation Template

// FDCPE: Single Data Rate D Flip-Flop with Asynchronous Clear, Set and
//
Clock Enable (posedge clk). All families.
// Xilinx HDL Libraries Guide version 7.1i
FDCPE FDCPE_inst (
.Q(Q),
// Data output
.C(C),
// Clock input
.CE(CE),
// Clock enable input
.CLR(CLR), // Asynchronous clear input
.D(D),
// Data input
.PRE(PRE)
// Asynchronous set input
);
// The following defparam declaration is only necessary if you wish to

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ISE 6.3i

FDCPE

// change the initial value of the register to a one. If the instance

// name to the FDCPE is changed, that change needs to be reflected in
// the defparam statements.
defparam FDCPE_inst.INIT = 1'b0;
// End of FDCPE_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
and XBLKNM.

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ISE 6.3i

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393

394

FDCPE

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Libraries Guide
ISE 6.3i

FDCPE_1

FDCPE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and
Asynchronous Preset and Clear
Architectures Supported
FDCPE_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

FDCPE_1
Q

CE
C

CLR

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDCPE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous
preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The
asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the
output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are
Low and CE is High on the High-to-Low clock (C) transition. When CE is Low, the
clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.

X8360

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

PRE

CE

No Chg

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- FDCPE_1: Single Data Rate D Flip-Flop with Asynchronous Clear,
-Set and Clock Enable (negedge clock). All families.
-- Xilinx HDL Libraries Guide version 7.1i

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395

FDCPE_1

FDCPE_1_inst : FDCPE_1
port map (
Q => Q,
-- Data output
C => C,
-- Clock input
CE => CE,
-- Clock enable input
CLR => CLR, -- Asynchronous clear input
D => D,
-- Data input
PRE => PRE
-- Asynchronous set input
);
-- End of FDCPE_1_inst instantiation

Verilog Instantiation Template

// FDCPE: Single Data Rate D Flip-Flop with Asynchronous Clear, Set and
//
Clock Enable (posedge clk). All families.
// Xilinx HDL Libraries Guide version 7.1i
FDCPE_1 FDCPE_1_inst (
.Q(Q),
// Data output
.C(C),
// Clock input
.CE(CE),
// Clock enable input
.CLR(CLR), // Asynchronous clear input
.D(D),
// Data input
.PRE(PRE)
// Asynchronous set input
);
//
//
//
//

The following defparam declaration is only necessary if you wish to

change the initial value of the register to a one. If the instance
name to the FDCPE_1 is changed, that change needs to be reflected in
the defparam statements.
defparam FDCPE_1_inst.INIT = 1'b0;

// End of FDCPE_1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

396

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Libraries Guide
ISE 6.3i

FDD

FDD
Dual Edge Triggered D Flip-Flop
Architectures Supported
FDD
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FDD

X9661

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDD is a single dual edge triggered D-type flip-flop with data input (D) and data
output (Q). The data on the D input is loaded into the flip-flop during the Low-toHigh and the High-to-Low clock (C) transitions.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
See FDD4,8,16 for information on multiple D flip-flops for CoolRunner-II.
Inputs

Outputs

FDDCP
D

PRE

C
CLR
Q

GND

X9662

FDD Implementation CoolRunner-II

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

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397

FDD

VHDL Instantiation Template

-- Component Declaration for FDD should be placed
-- after architecture statement but before begin keyword
component FDD
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDD
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDD_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDD should be placed

-- in architecture after the begin keyword
FDD_INSTANCE_NAME : FDD
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D);

Verilog Instantiation Template

FDD FDD_instance_name (.Q (user_Q),
.C (user_C),
.D (user_D));
defparam FDD_instance_name.INIT = bit_value;

398

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Libraries Guide
ISE 6.3i

FDD4,8,16

FDD4,8,16
Multiple Dual Edge Triggered D Flip-Flops
Architectures Supported
FDD4, FDD8, FDD16
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

D0

FDD4

Q0

D1

Q1

D2

Q2

D3

Q3

X9663

D[7:0]

FDD8

X9664

D[15:0]

FDD16

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDD4, FDD8, FDD16 are multiple dual edge triggered D-type flip-flops with data
inputs (D) and data outputs (Q). FDD4, FDD8, and FDD16 are, respectively, 4-bit, 8bit, and 16-bit registers, each with a common clock (C). The data on the D inputs is
loaded into the flip-flop during the Low-to-High and High-to-Low clock (C)
transitions.
The flip-flops are asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.

Q[7:0]

Q[15:0]

No

Inputs

Outputs

Dz D0

Qz Q0

z = 3 for FDD4; z = 7 for FDD8; z = 15 for FDD16

X9665

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ISE 6.3i

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399

FDD4,8,16

Q[7:0]

FDD

FDD
D0

Q0

D4

Q4

Q0

FDD

FDD
D1

Q1

D5

Q5

FDD

FDD
D

Q2

D6

Q6

FDD

FDD
D

Q3

D7

Q7

C
Q7

Q3

D[7:0]

Q6

C
Q2

D3

Q5

C
Q1

D2

Q4

X9666

FDD8 Implementation CoolRunner-II

Usage
For HDL, these deign elements are inferred rather than instantiated.

400

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Libraries Guide
ISE 6.3i

FDD4CE, FDD8CE, FDD16CE

FDD4CE, FDD8CE, FDD16CE

4-, 8-, 16-Bit Dual Edge Triggered Data Registers with Clock Enable
and Asynchronous Clear
Architectures Supported
FDD4CE, FDD8CE, FDD16CE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

D0
D1
D2
D3

FDD4CE

Q0
Q1
Q2
Q3

CE
C

CLR

D[7:0]

X9667

FDD8CE

Q[7:0]

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDD4CE, FDD8CE, and FDD16CE are, respectively, 4-, 8-, and 16-bit data registers
with clock enable and asynchronous clear. When clock enable (CE) is High and
asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the
corresponding data outputs (Q) during the Low-to-High and High-to-Low clock (C)
transitions. When CLR is High, it overrides all other inputs and resets the data
outputs (Q) Low. When CE is Low, clock transitions are ignored.
The flip-flops are asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.

CE
C

Inputs

Outputs

CLR

CE

Dz D0

Qz Q0

No Chg

Dn

Dn

Dn

Dn

CLR
X9668

D[15:0]

FDD16CE

Q[15:0]

CE
C

z = 3 for FDD4CE; z = 7 for FDD8CE; z = 15 for FDD16CE.

CLR

Libraries Guide
ISE 6.3i

X9669

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401

FDD4CE, FDD8CE, FDD16CE

Q[7:0]

FDDCE
FDDCE
D0

D
CE
C

D4
Q

Q0

D
CE
C

Q4

CLR
CLR

Q4
Q0

FDDCE
FDDCE
D1

D
CE
C

D5
Q

Q1

D
CE
C

Q5

CLR

CLR

Q5
Q1

FDDCE
FDDCE
D2

D
CE
C

D6
Q

Q2

D
CE
C

Q6

CLR

CLR

Q6
Q2

FDDCE
FDDCE
D3

D
CE
C

D7
Q

Q3

D
CE
C

CLR

Q7

CLR
Q7

Q3
D[7:0]
CE
C
CLR
X9670

FDD8CE Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

402

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Libraries Guide
ISE 6.3i

FDD4RE, FDD8RE, FDD16RE

FDD4RE, FDD8RE, FDD16RE

4-, 8-, 16-Bit Dual Edge Triggered Data Registers with Clock Enable
and Synchronous Reset
Architectures Supported
FDD4RE, FDD8RE, FDD16RE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

D0
D1
D2
D3
CE

FDD4RE

Q0
Q1
Q2
Q3

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDD4RE, FDD8RE, and FDD16RE are, respectively, 4-, 8-, and 16-bit data registers.
When the clock enable (CE) input is High, and the synchronous reset (R) input is Low,
the data on the data inputs (D) is transferred to the corresponding data outputs (Q0)
during the Low-to-High or High-to-Low clock (C) transition. When R is High, it
overrides all other inputs and resets the data outputs (Q) Low on the Low-to-High
and High-to-Low clock transitions. When CE is Low, clock transitions are ignored.

X9671

D[7:0]

FDD8RE

Q[7:0]

The flip-flops are asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.

CE
C

Inputs

X9672

D[15:0]

FDD16RE

Q[15:0]

CE
C

Libraries Guide
ISE 6.3i

X9673

Outputs

CE

Dz D0

Qz Q0

No Chg

Dn

Dn

Dn

Dn

z = 3 for FDD4RE; z = 7 for FDD8RE; z = 15 for FDD16RE

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403

FDD4RE, FDD8RE, FDD16RE

Q[7:0]

FDDRE

FDDRE
D0

D
CE
C

Q0

D4

D
CE
C

Q4

Q0

FDDRE

FDDRE
D1

D
CE
C

Q1

D5

D
CE
C

Q5

FDDRE

FDDRE
D
CE
C

Q2

D6

D
CE
C

Q6

FDDRE

FDDRE
D
CE
C

Q6

Q2

D3

Q5

Q1

D2

Q4

Q3

D7

D
CE
C

R
Q3

Q7

R
Q7

D[7:0]
CE
C
R

X9674

FDD8RE Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

404

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Libraries Guide
ISE 6.3i

FDDC

FDDC
D Dual Edge Triggered Flip-Flop with Asynchronous Clear
Architectures Supported
FDDC
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FDDC

CLR

X9675

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDDC is a single dual edge triggered D-type flip-flop with data (D) and asynchronous
clear (CLR) inputs and data output (Q). The asynchronous CLR, when High,
overrides all other inputs and sets the Q output Low. The data on the D input is
loaded into the flip-flop when CLR is Low on the Low-to-High and High-to-Low
clock (C) transitions.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Inputs

Outputs

CLR

FDDCP
D

PRE

C
CLR
Q

CLR

GND

X9676

FDDC Implementation CoolRunner-II

Libraries Guide
ISE 6.3i

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405

FDDC

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDDC should be placed
-- after architecture statement but before begin keyword
component FDDC
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDDC
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDDC_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDDC should be placed

-- in architecture after the begin keyword
FDDC_INSTANCE_NAME : FDDC
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
CLR => user_CLR,
D => user_D);

Verilog Instantiation Template

FDDC FDDC_instance_name (.Q (user_Q),
.C (user_C),
.CLR (user_CLR),
.D (user_D));
defparam FDDC_instance_name.INIT = bit_value;

406

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Libraries Guide
ISE 6.3i

FDDCE

FDDCE
Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous
Clear
Architectures Supported
FDDCE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FDDCE

CE
C

CLR

X9677

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

FDDCE is a single dual edge triggered D-type flip-flop with clock enable and
asynchronous clear. When clock enable (CE) is High and asynchronous clear (CLR) is
Low, the data on the data input (D) of FDDCE is transferred to the corresponding data
output (Q) during the Low-to-High and High-to-Low clock (C) transitions. When
CLR is High, it overrides all other inputs and resets the data output (Q) Low. When
CE is Low, clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Logic connected to the clock enable (CE) input may be implemented using the clock
enable product term (p-term) in the macrocell, provided the logic can be completely
implemented using the single p-term available for clock enable without requiring
feedback from another macrocell. Only FDDCE and FDDPE flip-flops primitives may
take advantage of the clock-enable p-term.
Inputs

Outputs

CLR

CE

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

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407

FDDCE

VHDL Instantiation Template

-- Component Declaration for FDDCE should be placed
-- after architecture statement but before begin keyword
component FDDCE
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDDCE
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for FDDCE should be placed

-- in architecture after the begin keyword
FDDCE_INSTANCE_NAME : FDDCE
port map (Q => user_Q,
C => user_C,
CE => user_CE,
CLR => user_CLR,
D => user_D);

Verilog Instantiation Template

FDDCE FDDCE_instance_name (.Q (user_Q),
.C (user_C),
.CE (user_CE),
.CLR (user_CLR),
.D (user_D));

408

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ISE 6.3i

FDDCP

FDDCP
Dual Edge Triggered D Flip-Flop Asynchronous Preset and Clear
Architectures Supported
FDDCP
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

PRE

FDDCP
Q

CLR
X9678

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

FDDCP is a single dual edge triggered D-type flip-flop with data (D), asynchronous
preset (PRE) and clear (CLR) inputs, and data output (Q). The asynchronous PRE,
when High, sets the Q output High; CLR, when High, resets the output Low. Data on
the D input is loaded into the flip-flop when PRE and CLR are Low on the Low-toHigh and High-to-Low clock (C) transitions.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Inputs

Outputs

CLR

PRE

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDDCP should be placed
-- after architecture statement but before begin keyword
component FDDCP
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on

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409

FDDCP

port (Q : out STD_ULOGIC;

C : in STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDDCP
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDDCP_instance_name : label is "0";
-- values can be (0 or 1)
-- Component Instantiation for FDDCP should be placed
-- in architecture after the begin keyword
FDDCP_INSTANCE_NAME : FDDCP
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
CLR => user_CLR,
D => user_D,
PRE => user_PRE);

Verilog Instantiation Template

FDDCP FDDCP_instance_name (.Q (user_Q),
.C (user_C),
.CLR (user_CLR),
.D (user_D),
.PRE (user_PRE));
defparam FDDCP_instance_name.INIT = bit_value;

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ISE 6.3i

FDDCPE

FDDCPE
Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous
Preset and Clear
Architectures Supported
FDDCPE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

PRE

FDDCPE

CE

CLR
X9679

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

FDDCPE is a single dual edge triggered D-type flip-flop with data (D), clock enable
(CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data
output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when
High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE
and CLR are Low and CE is High on the Low-to-High and High-to-Low clock (C)
transitions. When CE is Low, the clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

PRE

CE

No Chg

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411

FDDCPE

VCC

CE
AND2

AND2B1

D
AND2

OR2

FDDCP

PRE

D
C

PRE

C
CLR
Q

CLR

X9680

FDDCPE Implementation CoolRunner-II

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- FDDCPE: Double Data Rate Register with Asynchronous Clear and Set
-and Clock Enable (Clear has priority). CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
FDDCPE_inst : FDDCPE
port map (
Q => Q,
-- Data output
C => C,
-- Clock input
CE => CE,
-- Clock enable input
CLR => CLR, -- Asynchronous clear input
D => D,
-- Data input
PRE => PRE
-- Asynchronous set input
);
-- End of FDDCPE_inst instantiation

Verilog Instantiation Template

// FDDCPE: Double Data Rate Register with Asynchronous Clear and Set
//
and Clock Enable (Clear has priority). CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
FDDCPE FDDCPE_inst (
.Q(Q),
// Data output
.C(C),
// Clock input
.CE(CE),
// Clock enable input
.CLR(CLR), // Asynchronous clear input
.D(D),
// Data input
.PRE(PRE)
// Asynchronous set input
);
// End of FDDCPE_inst instantiation

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ISE 6.3i

FDDP

FDDP
Dual Edge Triggered D Flip-Flop with Asynchronous Preset
Architectures Supported
FDDP
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

PRE

FDDP

X9681

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDDP is a single dual edge triggered D-type flip-flop with data (D) and asynchronous
preset (PRE) inputs and data output (Q). The asynchronous PRE, when High,
overrides all other inputs and presets the Q output High. The data on the D input is
loaded into the flip-flop when PRE is Low on the Low-to-High and High-to-Low
clock (C) transitions.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Inputs

Outputs

PRE

FDDCP

PRE
D

PRE

C
CLR
Q

GND

X9682

FDDP Implementation CoolRunner-II

Usage
For HDL, this design element can be inferred or instantiated.

Libraries Guide
ISE 6.3i

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413

FDDP

VHDL Instantiation Template

-- Component Declaration for FDDP should be placed
-- after architecture statement but before begin keyword
component FDDP
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDDP
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDDP_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDDP should be placed

-- in architecture after the begin keyword
FDDP_INSTANCE_NAME : FDDP
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D,
PRE => user_PRE);

Verilog Instantiation Template

FDDP FDDP_instance_name (.Q (user_Q),
.C (user_C),
.D (user_D),
.PRE (user_PRE));
defparam FDDP_instance_name.INIT = bit_value;

414

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Libraries Guide
ISE 6.3i

FDDPE

FDDPE
Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous
Preset
Architectures Supported
FDDPE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

PRE

FDDPE

CE
C

X9683

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

FDDPE is a single dual edge triggered D-type flip-flop with data (D), clock enable
(CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous
PRE, when High, overrides all other inputs and sets the Q output High. Data on the D
input is loaded into the flip-flop when PRE is Low and CE is High on the Low-toHigh and High-to-Low clock (C) transitions. When CE is Low, the clock transitions are
ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Logic connected to the clock enable (CE) input may be implemented using the clock
enable product term (p-term) in the macrocell, provided the logic can be completely
implemented using the single p-term available for clock enable without requiring
feedback from another macrocell. Only FDDCE and FDDPE flip-flops primitives may
take advantage of the clock-enable p-term.
Inputs

Outputs

PRE

CE

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Libraries Guide
ISE 6.3i

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415

FDDPE

VHDL Instantiation Template

-- Component Declaration for FDDPE should be placed
-- after architecture statement but before begin keyword
component FDDPE
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC;
D : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDDPE
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here
-- Component Instantiation for FDDPE should be placed
-- in architecture after the begin keyword
FDDPE_INSTANCE_NAME : FDDPE
port map (Q => user_Q,
C => user_C,
CE => user_CE,
D => user_D,
PRE => user_PRE);

Verilog Instantiation Template

FDDPE FDDPE_instance_name (.Q (user_Q),
.C (user_C),
.CE (user_CE),
.D (user_D),
.PRE (user_PRE));
defparam FDDPE_instance_name.INIT = bit_value;

416

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Libraries Guide
ISE 6.3i

FDDR

FDDR
Dual Edge Triggered D Flip-Flop with Synchronous Reset
Architectures Supported
FDDR
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FDDR

X9684

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDDR is a single dual edge triggered D-type flip-flop with data (D) and synchronous
reset (R) inputs and data output (Q). The synchronous reset (R) input, when High,
overrides all other inputs and resets the Q output Low on the Low-to-High and Highto-Low clock (C) transitions. The data on the D input is loaded into the flip-flop when
R is Low during the Low-to-High or High-to-Low clock transitions.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Inputs
R

FDD

D_R

R
C

Outputs

AND2B1
C
X9685

FDDR Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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417

418

FDDR

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Libraries Guide
ISE 6.3i

FDDRCPE

FDDRCPE
Dual Data Rate D Flip-Flop with Clock Enable and Asynchronous
Preset and Clear
Architectures Supported
FDDRCPE
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE
D0

FDDRCPE

D1
CE
C0
C1
CLR
X9399

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDDRCPE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1)
phase shifted 180 degrees that allow selection of two separate data inputs (D0 and
D1). It also has clock enable (CE), asynchronous preset (PRE), and asynchronous clear
(CLR) inputs and data output (Q). The asynchronous PRE, when High, sets the Q
output High; CLR, when High, resets the output Low. Data on the D0 input is loaded
into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High C0
clock transition. Data on the D1 input is loaded into the flip-flop when PRE and CLR
are Low and CE is High on the Low-to-High C1 clock transition. When CE is Low, the
clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.
Use the INIT attribute to initialize FDDRCPE during configuration.
Inputs

Outputs

C0

C1

CE

D0

D1

CLR

PRE

No Chg

D0

D0

D1

D1

Usage
For HDL, this design element is instantiated rather than inferred.

Libraries Guide
ISE 6.3i

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419

FDDRCPE

VHDL Instantiation Template

-- Component Declaration for FDDRCPE should be placed
-- after architecture statement but before begin keyword
component FDDRCPE
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLR : in STD_ULOGIC;
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDDRCPE
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDDRCPE_instance_name : label is "0";
-- values can be (0 or 1)
-- Component Instantiation for FDDRCPE should be placed
-- in architecture after the begin keyword
FDDRCPE_INSTANCE_NAME : FDDRCPE
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C0 => user_C0,
C1 => user_C1,
CE => user_CE,
CLR => user_CLR,
D0 => user_D0,
D1 => user_D1,
PRE => user_PRE);

Verilog Instantiation Template

FDDRCPE FDDRCPE_instance_name (.Q (user_Q),
.C0 (user_C0),
.C1 (user_C1),
.CE (user_CE),
.CLR (user_CLR),
.D0 (user_D0),
.D1 (user_D1),
.PRE (user_PRE));
defparam FDDRCPE_instance_name.INIT = bit_value;

420

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ISE 6.3i

FDDRE

FDDRE
Dual Edge Triggered D Flip-Flop with Clock Enable and Synchronous
Reset
Architectures Supported
FDDRE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FDDRE

CE
C

X9686

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDDRE is a single dual edge triggered D-type flip-flop with data (D), clock enable
(CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset
(R) input, when High, overrides all other inputs and resets the Q output Low on the
Low-to-High or High-to-Low clock (C) transition. The data on the D input is loaded
into the flip-flop when R is Low and CE is High during the Low-to-High and High-toLow clock transitions.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

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421

FDDRE

VCC

CE
AND2
R
AND3B2

FDD
OR2

AND3B1
C

C
Q
X9687

FDDRE Implementation CoolRunner-II

Usage
For HDL, this design element can be inferred but not instantiated.

422

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Libraries Guide
ISE 6.3i

FDDRRSE

FDDRRSE
Dual Data Rate D Flip-Flop with Clock Enable and Synchronous Reset
and Set
Architectures Supported
FDDRRSE
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

S
D0

FDDRRSE

D1
CE
C0
C1
R
X9254

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1)
phase shifted 180 degrees that allow selection of two separate data inputs (D0 and
D1). It also has synchronous reset (R), synchronous set (S), and clock enable (CE)
inputs and data output (Q). The reset (R) input, when High, overrides all other inputs
and resets the Q output Low during any Low-to-High clock transition (C0 or C1).
(Reset has precedence over Set.) When the S input is High and R is Low, the flip-flop is
set, output High, during a Low-to-High clock transition (C0 or C1). Data on the D0
input is loaded into the flip-flop when R and S are Low and CE is High during the
Low-to-High C0 clock transition. Data on the D1 input is loaded into the flip-flop
when R and S are Low and CE is High during the Low-to-High C1 clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
Use the INIT attribute to initialize FDDRRSE during configuration.
Inputs

Outputs

C0

C1

CE

D0

D1

No Chg

D0

D0

D1

D1

Usage
For HDL, this design element is instantiated rather than inferred.

Libraries Guide
ISE 6.3i

www.xilinx.com
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423

FDDRRSE

VHDL Instantiation Template

-- Component Declaration for FDDRRSE should be placed
-- after architecture statement but before begin keyword
component FDDRRSE
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
R : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDDRRSE
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDDRRSE_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDDRRSE should be placed

-- in architecture after the begin keyword
FDDRRSE_INSTANCE_NAME : FDDRRSE
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C0 => user_C0,
C1 => user_C1,
CE => user_CE,
D0 => user_D0,
D1 => user_D1,
R => user_R,
S => user_S);

Verilog Instantiation Template

FDDRRSE FDDRRSE_instance_name (.Q (user_Q),
.C0 (user_C0),
.C1 (user_C1),
.CE (user_CE),
.D0 (user_D0),
.D1 (user_D1),
.R (user_R),
.S (user_S));
defparam FDDRRSE_instance_name.INIT = bit_value;

424

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ISE 6.3i

FDDRS

FDDRS
Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set
Architectures Supported
FDDRS
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FDDRS

X9688

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDDRS is a single dual edge triggered D-type flip-flop with data (D), synchronous set
(S), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R)
input, when High, overrides all other inputs and resets the Q output Low during the
Low-to-High or High-to-Low clock (C) transitions. (Reset has precedence over Set.)
When S is High and R is Low, the flip-flop is set, output High, during the Low-toHigh or High-to-Low clock transition. When R and S are Low, data on the (D) input is
loaded into the flip-flop during the Low-to-High and High-to-Low clock transitions.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Inputs

Outputs

D
R
AND2B1

FDD

S
AND2B1

OR2

C
Q

X9689

FDDRS Implementation CoolRunner-II

Libraries Guide
ISE 6.3i

www.xilinx.com
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425

FDDRS

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDDRS should be placed
-- after architecture statement but before begin keyword
component FDDRS
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
R : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDDRS
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDDRS_instance_name : label is "0";
-- values can be (0 or 1)
-- Component Instantiation for FDDRS should be placed
-- in architecture after the begin keyword
FDDRS_INSTANCE_NAME : FDDRS
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D,
R => user_R,
S => user_S);

Verilog Instantiation Template

FDDRS FDDRS_instance_name (.Q
.C
.D
.R
.S

(user_Q),
(user_C),
(user_D),
(user_R),
(user_S));

defparam FDDRS_instance_name.INIT = bit_value;

426

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Libraries Guide
ISE 6.3i

FDDRSE

FDDRSE
Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set and
Clock Enable
Architectures Supported
FDDRSE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

D
CE
C

FDDRSE

X9690

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDDRSE is a single dual edge triggered D-type flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R)
input, when High, overrides all other inputs and resets the Q output Low during the
Low-to-High or High-to-Low clock transitions. (Reset has precedence over Set.) When
the set (S) input is High and R is Low, the flip-flop is set, output High, during the
Low-to-High or High-to-Low clock (C) transition. Data on the D input is loaded into
the flip-flop when R and S are Low and CE is High during the Low-to-High and Highto-Low clock transitions.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

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427

FDDRSE

VCC
CE
AND2

AND2B1

S
OR3

FDD

D
AND2
R

AND2B1

C
X9691

FDDRSE Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

428

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ISE 6.3i

FDDS

FDDS
Dual Edge Triggered D Flip-Flop with Synchronous Set
Architectures Supported
FDDS
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FDDS

X9692

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDDS is a single dual edge triggered D-type flip-flop with data (D) and synchronous
set (S) inputs and data output (Q). The synchronous set input, when High, sets the Q
output High on the Low-to-High or High-to-Low clock (C) transition. The data on the
D input is loaded into the flip-flop when S is Low during the Low-to-High and Highto-Low clock (C) transitions.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Inputs
S

FDD

D
D

S
C

Outputs

OR2
C
Q
X9693

FDDS Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

429

430

FDDS

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Libraries Guide
ISE 6.3i

FDDSE

FDDSE
D Flip-Flop with Clock Enable and Synchronous Set
Architectures Supported
FDDSE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FDDSE

CE
C

X9694

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDDSE is a single dual edge triggered D-type flip-flop with data (D), clock enable
(CE), and synchronous set (S) inputs and data output (Q). The synchronous set (S)
input, when High, overrides the clock enable (CE) input and sets the Q output High
during the Low-to-High or High-to-Low clock (C) transition. The data on the D input
is loaded into the flip-flop when S is Low and CE is High during the Low-to-High and
High-to-Low clock (C) transitions.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Inputs

Outputs

CE

No Chg

VCC
CE
AND2

AND2B1

S
OR3

FDD
AND2
D

C
Q

X9695

FDDSE Implementation CoolRunner-II

Libraries Guide
ISE 6.3i

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431

FDDSE

Usage
For HDL, this design element is inferred rather than instantiated.

432

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Libraries Guide
ISE 6.3i

FDDSR

FDDSR
Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset
Architectures Supported
FDDSR
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FDDSR

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDDSR is a single dual edge triggered D-type flip-flop with data (D), synchronous
reset (R) and synchronous set (S) inputs and data output (Q). When the set (S) input is
High, it overrides all other inputs and sets the Q output High during the Low-to-High
or High-to-Low clock transition. (Set has precedence over Reset.) When reset (R) is
High and S is Low, the flip-flop is reset, output Low, on the Low-to-High or High-toLow clock transition. Data on the D input is loaded into the flip-flop when S and R are
Low on the Low-to-High and High-to-Low clock transitions.

X9696

The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Inputs

Outputs

D
R
AND2B1

FDD
D

S
C

OR2
C
Q

X9697

FDDSR Implementation CoolRunner-II

Libraries Guide
ISE 6.3i

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433

FDDSR

Usage
For HDL, this design element is inferred rather than instantiated.

434

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Libraries Guide
ISE 6.3i

FDDSRE

FDDSRE
Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset and
Clock Enable
Architectures Supported
FDDSRE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

D
CE

FDDSRE

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FDDSRE is a single dual edge triggered D-type flip-flop with synchronous set (S),
synchronous reset (R), and clock enable (CE) inputs and data output (Q). When
synchronous set (S) is High, it overrides all other inputs and sets the Q output High
during the Low-to-High or High-to-Low clock transition. (Set has precedence over
Reset.) When synchronous reset (R) is High and S is Low, output Q is reset Low
during the Low-to-High or High-to-Low clock transition. Data is loaded into the flipflop when S and R are Low and CE is High during the Low-to-High and High-to-Low
clock transitions. When CE is Low, clock transitions are ignored.

X9698

The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated in Verilog by applying a High-level pulse on the
PRLD global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

www.xilinx.com
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435

FDDSRE

VCC

CE
AND2
R
AND3B2

FDD

OR3
D

AND3B1
C

X9699

FDDSRE Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

436

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Libraries Guide
ISE 6.3i

FDE

FDE
D Flip-Flop with Clock Enable
Architectures Supported
FDE
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDE

CE

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDE is a single D-type flip-flop with data input (D), clock enable (CE), and data
output (Q). When clock enable is High, the data on the D input is loaded into the flipflop during the Low-to-High clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.

X8361

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CE

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDE should be placed
-- after architecture statement but before begin keyword
component FDE
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;

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437

FDE

CE : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDE
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDE_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDE should be placed

-- in architecture after the begin keyword
FDE_INSTANCE_NAME : FDE
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
CE => user_CE,
D => user_D);

Verilog Instantiation Template

FDE FDE_instance_name (.Q (user_Q),
.C (user_C),
.CE (user_CE),
.D (user_D));
defparam FDE_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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ISE 6.3i

FDE_1

FDE_1
D Flip-Flop with Negative-Edge Clock and Clock Enable
Architectures Supported
FDE_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDE_1

CE

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDE_1 is a single D-type flip-flop with data input (D), clock enable (CE), and data
output (Q). When clock enable is High, the data on the D input is loaded into the flipflop during the High-to-Low clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.

X8362

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CE

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDE_1 should be placed
-- after architecture statement but before begin keyword
component FDE_1
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;

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FDE_1

CE : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDE_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDE_1_instance_name : label is "0";
-- values can be (0 or 1)
-- Component Instantiation for FDE_1 should be placed
-- in architecture after the begin keyword
FDE_1_INSTANCE_NAME : FDE_1
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
CE => user_CE,
D => user_D);

Verilog Instantiation Template

FDE_1 FDE_1_instance_name (.Q (user_Q),
.C (user_C),
.CE (user_CE),
.D (user_D));
defparam FDE_1_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET,INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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ISE 6.3i

FDP

FDP
D Flip-Flop with Asynchronous Preset
Architectures Supported
FDP
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

FDP

X3720

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FDP is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs
and data output (Q). The asynchronous PRE, when High, overrides all other inputs
and presets the Q output High. The data on the D input is loaded into the flip-flop
when PRE is Low on the Low-to-High clock (C) transition.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is
asynchronously cleared, output Low, when power is applied. The power-on condition
can be simulated by applying a High-level pulse on the PRLD global net.
For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is
applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
The active level of the GSR defaults to active-High but can be inverted by adding an
inverter in front of the GSR input of the STARTUP_SPARTAN2,
STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

PRE

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FDP

FDCP

PRE
D

PRE

C
CLR
Q

GND

X7805

FDP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDP should be placed
-- after architecture statement but before begin keyword
component FDP
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDP
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDP_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDP should be placed

-- in architecture after the begin keyword
FDP_INSTANCE_NAME : FDP
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D,
PRE => user_PRE);

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FDP

Verilog Instantiation Template

FDP FDP_instance_name (.Q (user_Q),
.C (user_C),
.D (user_D),
.PRE (user_PRE));
defparam FDP_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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444

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Libraries Guide
ISE 6.3i

FDP_1

FDP_1
D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
Architectures Supported
FDP_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

FDP_1

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDP_1 is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs
and data output (Q). The asynchronous PRE, when High, overrides all other inputs
and presets the Q output High. The data on the D input is loaded into the flip-flop
when PRE is Low on the High-to-Low clock (C) transition.
The flip-flop is asynchronously preset, output High, when power is applied.

X3728

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
The active level of the GSR defaults to active-High but can be inverted by adding an
inverter in front of the GSR input of the STARTUP_SPARTAN2,
STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

PRE

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDP_1 should be placed
-- after architecture statement but before begin keyword
component FDP_1
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on

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FDP_1

port (Q : out STD_ULOGIC;

C : in STD_ULOGIC;
D : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDP_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDP_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDP_1 should be placed

-- in architecture after the begin keyword
FDP_1_INSTANCE_NAME : FDP_1
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D,
PRE => user_PRE);

Verilog Instantiation Template

FDP_1 FDP_1_instance_name (.Q (user_Q),
.C (user_C),
.D (user_D),
.PRE (user_PRE));
defparam FDP_1_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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ISE 6.3i

FDPE

FDPE
D Flip-Flop with Clock Enable and Asynchronous Preset
Architectures Supported
FDPE
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

FDPE

CE

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

FDPE is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous
preset (PRE) inputs and data output (Q). The asynchronous PRE, when High,
overrides all other inputs and sets the Q output High. Data on the D input is loaded
into the flip-flop when PRE is Low and CE is High on the Low-to-High clock (C)
transition. When CE is Low, the clock transitions are ignored.

X3721

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is

asynchronously cleared, output Low, when power is applied. The power-on condition
can be simulated by applying a High-level pulse on the PRLD global net.
For XC9500XL and XC9500XV devices, logic connected to the clock enable (CE) input
may be implemented using the clock enable product term (p-term) in the macrocell,
provided the logic can be completely implemented using the single p-term available
for clock enable without requiring feedback from another macrocell. Only FDCE and
FDPE flip-flop primitives may take advantage of the clock-enable p-term.
For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is
applied. These devices simulate power-on when global set/reset (GSR) is active.
The active level of the GSR defaults to active-High but can be inverted by adding an
inverter in front of the GSR input of the STARTUP_SPARTAN2,
STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

PRE

CE

No Chg

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FDPE

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDPE should be placed
-- after architecture statement but before begin keyword
component FDPE
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC;
D : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDPE
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of
FDPE_instance_name : label is "0";
-- values can be (0 or 1)
-- Component Instantiation for FDPE should be placed
-- in architecture after the begin keyword FDPE_INSTANCE_NAME : FDPE
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
CE => user_CE,
D => user_D,
PRE => user_PRE);

Verilog Instantiation Template

FDPE FDPE_instance_name (.Q (user_Q),
.C (user_C),
.CE (user_CE),
.D (user_D),
.PRE (user_PRE));
defparam
FDPE_instance_name.INIT = bit_value;

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FDPE

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
and XBLKNM

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450

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ISE 6.3i

FDPE_1

FDPE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and
Asynchronous Preset
Architectures Supported
FDPE_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

FDPE_1

CE
C

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDPE_1 is a single D-type flip-flop with data (D), clock enable (CE), and
asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when
High, overrides all other inputs and sets the Q output High. Data on the D input is
loaded into the flip-flop when PRE is Low and CE is High on the High-to-Low clock
(C) transition. When CE is Low, the clock transitions are ignored.
The flip-flop is asynchronously preset, output High, when power is applied.

X3852

Spartan-II, Spartan-IIE, Spartan-III, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and

Virtex-II Pro X simulate power-on when global set/reset (GSR) is active.
The active level of the GSR defaults to active-High but can be inverted by adding an
inverter in front of the GSR input of the STARTUP_SPARTAN2,
STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

PRE

CE

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDPE_1 should be placed
-- after architecture statement but before begin keyword
component FDPE_1

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FDPE_1

-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC;
D : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDPE_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDPE_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDPE_1 should be placed

-- in architecture after the begin keyword -FDPE_1_INSTANCE_NAME : FDPE_1
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
CE => user_CE,
D => user_D,
PRE => user_PRE);

Verilog Instantiation Template

FDPE_1 FDPE_1_instance_name (.Q (user_Q),
.C (user_C),
.CE (user_CE),
.D (user_D),
.PRE (user_PRE));
defparam FDPE_1_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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ISE 6.3i

FDR

FDR
D Flip-Flop with Synchronous Reset
Architectures Supported
FDR
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDR

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FDR is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and
data output (Q). The synchronous reset (R) input, when High, overrides all other
inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data
on the D input is loaded into the flip-flop when R is Low during the Low-to-High
clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.

X3718

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDR should be placed
-- after architecture statement but before begin keyword
component FDR

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FDR

-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
R : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDR
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDR_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDR should be placed

-- in architecture after the begin keyword
FDR_INSTANCE_NAME : FDR
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D,
R => user_R);

Verilog Instantiation Template

FDR FDR_instance_name (.Q
.C
.D
.R

(user_Q),
(user_C),
(user_D),
(user_R));

defparam FDR_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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FDR_1

FDR_1
D Flip-Flop with Negative-Edge Clock and Synchronous Reset
Architectures Supported
FDR_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDR_1
Q

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDR_1 is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and
data output (Q). The synchronous reset (R) input, when High, overrides all other
inputs and resets the Q output Low on the High-to-Low clock (C) transition. The data
on the D input is loaded into the flip-flop when R is Low during the High-to-Low
clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.

R
X8363

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDR_1 should be placed
-- after architecture statement but before begin keyword
component FDR_1
-- synthesis translate_off
generic (
INIT : bit := '1');

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455

FDR_1

-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
R : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDR_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDR_1_instance_name : label is "0";
-- values can be (0 or 1)
-- Component Instantiation for FDR_1 should be placed
-- in architecture after the begin keyword
FDR_1_INSTANCE_NAME : FDR_1
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D,
R => user_R);

Verilog Instantiation Template

FDR_1 FDR_1_instance_name (.Q
.C
.D
.R

(user_Q),
(user_C),
(user_D),
(user_R));

defparam FDR_1_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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ISE 6.3i

FDRE

FDRE
D Flip-Flop with Clock Enable and Synchronous Reset
Architectures Supported
FDRE
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDRE

CE
C

X3719

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FDRE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous
reset (R) inputs and data output (Q). The synchronous reset (R) input, when High,
overrides all other inputs and resets the Q output Low on the Low-to-High clock (C)
transition. The data on the D input is loaded into the flip-flop when R is Low and CE
is High during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

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457

FDRE

VCC

CE
AND2
R
AND3B2

FD
OR2

AND3B1
C

C
Q
X7808

FDRE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDRE should be placed
-- after architecture statement but before begin keyword
component FDRE
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC;
D : in STD_ULOGIC;
R : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDRE
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDRE_instance_name : label is "0";
-- values can be (0 or 1)
-- Component Instantiation for FDRE should be placed
-- in architecture after the begin keyword
FDRE_INSTANCE_NAME : FDRE
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on

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ISE 6.3i

FDRE

port map (Q => user_Q,

C => user_C,
CE => user_CE,
D => user_D,
R => user_R);

Verilog Instantiation Template

FDRE FDRE_instance_name (.Q (user_Q),
.C (user_C),
.CE (user_CE),
.D (user_D),
.R (user_R));
defparam FDRE_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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459

460

FDRE

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Libraries Guide
ISE 6.3i

FDRE_1

FDRE_1
D Flip-Flop with Negative-Clock Edge, Clock Enable, and Synchronous
Reset
Architectures Supported
FDRE_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDRE_1

CE

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous
reset (R) inputs and data output (Q). The synchronous reset (R) input, when High,
overrides all other inputs and resets the Q output Low on the High-to-Low clock (C)
transition. The data on the D input is loaded into the flip-flop when R is Low and CE
is High during the High-to-Low clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.

R
X8364

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CE

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDRE_1 should be placed
-- after architecture statement but before begin keyword
component FDRE_1

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FDRE_1

-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC;
D : in STD_ULOGIC;
R : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDRE_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDRE_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDRE_1 should be placed

-- in architecture after the begin keyword
FDRE_1_INSTANCE_NAME : FDRE_1
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
CE => user_CE,
D => user_D,
R => user_R);

Verilog Instantiation Template

FDRE_1 FDRE_1_instance_name (.Q (user_Q),
.C (user_C),
.CE (user_CE),
.D (user_D),
.R (user_R));
defparam FDRE_1_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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ISE 6.3i

FDRS

FDRS
D Flip-Flop with Synchronous Reset and Set
Architectures Supported
FDRS
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDRS

X3731

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous
reset (R) inputs and data output (Q). The synchronous reset (R) input, when High,
overrides all other inputs and resets the Q output Low during the Low-to-High clock
(C) transition. (Reset has precedence over Set.) When S is High and R is Low, the flipflop is set, output High, during the Low-to-High clock transition. When R and S are
Low, data on the (D) input is loaded into the flip-flop during the Low-to-High clock
transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

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463

FDRS

D
R
AND2B1

FD

S
AND2B1

OR2

C
Q

X7811

FDRS Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDRS should be placed
-- after architecture statement but before begin keyword
component FDRS
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
R : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDRS
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDRS_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDRS should be placed

-- in architecture after the begin keyword
FDRS_INSTANCE_NAME : FDRS
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D,
R => user_R,
S => user_S);

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ISE 6.3i

FDRS

Verilog Instantiation Template

FDRS FDRS_instance_name (.Q
.C
.D
.R
.S

(user_Q),
(user_C),
(user_D),
(user_R),
(user_S));

defparam FDRS_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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ISE 6.3i

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465

466

FDRS

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Libraries Guide
ISE 6.3i

FDRS_1

FDRS_1
D Flip-Flop with Negative-Clock Edge and Synchronous Reset and Set
Architectures Supported
FDRS_1

Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

FDRS_1
Q

R
X8365

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDRS_1 is a single D-type flip-flop with data (D), synchronous set (S), and
synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input,
when High, overrides all other inputs and resets the Q output Low during the Highto-Low clock (C) transition. (Reset has precedence over Set.) When S is High and R is
Low, the flip-flop is set, output High, during the High-to-Low clock transition. When
R and S are Low, data on the (D) input is loaded into the flip-flop during the High-toLow clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDRS_1 should be placed
-- after architecture statement but before begin keyword

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FDRS_1

component FDRS_1
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
R : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDRS_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDRS_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDRS_1 should be placed

-- in architecture after the begin keyword
FDRS_1_INSTANCE_NAME : FDRS_1
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D,
R => user_R,
S => user_S);

Verilog Instantiation Template

FDRS_1 FDRS_1_instance_name (.Q
.C
.D
.R
.S

(user_Q),
(user_C),
(user_D),
(user_R),
(user_S));

defparam FDRS_1_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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ISE 6.3i

FDRSE

FDRSE
D Flip-Flop with Synchronous Reset and Set and Clock Enable
Architectures Supported
FDRSE
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

D
CE

FDRSE

X3732

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S),
and clock enable (CE) inputs and data output (Q). The reset (R) input, when High,
overrides all other inputs and resets the Q output Low during the Low-to-High clock
transition. (Reset has precedence over Set.) When the set (S) input is High and R is
Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition.
Data on the D input is loaded into the flip-flop when R and S are Low and CE is High
during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

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469

FDRSE

VCC
CE
AND2B1

AND2
S

OR3

FD

D
AND2
R

AND2B1

X7813

FDRSE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- FDRSE: Single Data Rate D Flip-Flop with Synchronous Clear,
-Set and Clock Enable (posedge clk). All families.
-- Xilinx HDL Libraries Guide version 7.1i
FDRSE_inst : FDRSE
port map (
Q => Q,
-- Data output
C => C,
-- Clock input
CE => CE,
-- Clock enable input
D => D,
-- Data input
R => R,
-- Synchronous reset input
S => S
-- Synchronous set input
);
-- End of FDRSE_inst instantiation

Verilog Instantiation Template

// FDRSE: Single Data Rate D Flip-Flop with Synchronous Clear,
//
Set and Clock Enable (posedge clk). All families.
// Xilinx HDL Libraries Guide version 7.1i
FDRSE FDRSE_inst (
.Q(Q),
// Data output
.C(C),
// Clock input
.CE(CE),
// Clock enable input
.D(D),
// Data input
.R(R),
// Synchronous reset input
.S(S)
// Synchronous set input
);
// The following defparam declaration is only necessary if you wish to
// change the initial value of the register to a one. If the instance

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FDRSE

// name to the FDRSE is changed, that change needs to be reflected in

// the defparam statements.
defparam FDRSE_inst.INIT = 1'b0;
// End of FDRSE_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET
and XBLKNM

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471

472

FDRSE

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Libraries Guide
ISE 6.3i

FDRSE_1

FDRSE_1
D Flip-Flop with Negative-Clock Edge, Synchronous Reset and Set,
and Clock Enable
FDRSE_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDRSE_1

CE

R
X8366

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDRSE_1 is a single D-type flip-flop with synchronous reset (R), synchronous set (S),
and clock enable (CE) inputs and data output (Q). The reset (R) input, when High,
overrides all other inputs and resets the Q output Low during the High-to-Low clock
transition. (Reset has precedence over Set.) When the set (S) input is High and R is
Low, the flip-flop is set, output High, during the High-to-Low clock (C) transition.
Data on the D input is loaded into the flip-flop when R and S are Low and CE is High
during the High-to-Low clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CE

No Chg

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- FDRSE_1: Single Data Rate D Flip-Flop with Synchronous Clear,
-Set and Clock Enable (negedge clock). All families.

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FDRSE_1

-- Xilinx

HDL Libraries Guide version 7.1i

FDRSE_1_inst : FDRSE_1
port map (
Q => Q,
-- Data output
C => C,
-- Clock input
CE => CE,
-- Clock enable input
CLR => CLR, -- Asynchronous clear input
D => D,
-- Data input
R => R,
-- Synchronous reset input
S => S
-- Synchronous set input
);
-- End of FDCPE_1_inst instantiation

Verilog Instantiation Template

// FDRSE_1: Single Data Rate D Flip-Flop with Synchronous Clear,
//
Set and Clock Enable (negedge clock). All families.
// Xilinx HDL Libraries Guide version 7.1i
FDRSE_1 FDRSE_1_inst (
.Q(Q),
// Data output
.C(C),
// Clock input
.CE(CE),
// Clock enable input
.CLR(CLR), // Asynchronous clear input
.D(D),
// Data input
.R(R),
// Synchronous reset input
.S(S)
// Synchronous set input
);
//
//
//
//

The following defparam declaration is only necessary if you wish to

change the initial value of the register to a one. If the instance
name to the FDRSE_1 is changed, that change needs to be reflected in
the defparam statements.
defparam FDRSE_1_inst.INIT = 1'b0;

// End of FDRSE_1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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FDS

FDS
D Flip-Flop with Synchronous Set
Architectures Supported
FDS
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDS

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FDS is a single D-type flip-flop with data (D) and synchronous set (S) inputs and data
output (Q). The synchronous set input, when High, sets the Q output High on the
Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop
when S is Low during the Low-to-High clock (C) transition.

X3722

For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is
applied. For all other devices (XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II),
the flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol. FDS will set when GSR is active. For Spartan-II,
Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the
flip-flop is preset to active high when GSR is active.
Inputs

Outputs

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Libraries Guide
ISE 6.3i

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475

FDS

VHDL Instantiation Template

-- Component Declaration for FDS should be placed
-- after architecture statement but before begin keyword
component FDS
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDS
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDS_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDS should be placed

-- in architecture after the begin keyword
FDS_INSTANCE_NAME : FDS
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D,
S => user_S);

Verilog Instantiation Template

FDS FDS_instance_name (.Q
.C
.D
.S

(user_Q),
(user_C),
(user_D),
(user_S));

defparam FDS_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

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ISE 6.3i

FDS_1

FDS_1
D Flip-Flop with Negative-Edge Clock and Synchronous Set
Architectures Supported
FDS_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDS_1
Q

X8367

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDS_1 is a single D-type flip-flop with data (D) and synchronous set (S) inputs and
data output (Q). The synchronous set input, when High, sets the Q output High on
the High-to-Low clock (C) transition. The data on the D input is loaded into the flipflop when S is Low during the High-to-Low clock (C) transition.
For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is
applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol. FDS_1 will set when GSR is active. For Spartan-II,
Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the
flip-flop is preset to active high when GSR is active.
Inputs

Outputs

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDS_1 should be placed
-- after architecture statement but before begin keyword
component FDS_1

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

477

FDS_1

-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDS_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDS_1_instance_name : label is "0";
-- values can be (0 or 1)
-- Component Instantiation for FDS_1 should be placed
-- in architecture after the begin keyword
FDS_1_INSTANCE_NAME : FDS_1
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D,
S => user_S);

Verilog Instantiation Template

FDS_1 FDS_1_instance_name (.Q
.C
.D
.S

(user_Q),
(user_C),
(user_D),
(user_S));

defparam FDS_1_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

478

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Libraries Guide
ISE 6.3i

FDSE

FDSE
D Flip-Flop with Clock Enable and Synchronous Set
Architectures Supported
FDSE
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

FDSE

CE
C

X3723

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FDSE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set
(S) inputs and data output (Q). The synchronous set (S) input, when High, overrides
the clock enable (CE) input and sets the Q output High during the Low-to-High clock
(C) transition. The data on the D input is loaded into the flip-flop when S is Low and
CE is High during the Low-to-High clock (C) transition.
For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is
applied.
For all other devices (XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II), the
flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol. FDSE will set when GSR is active. For Spartan-II,
Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the
flip-flop is preset to active high when GSR is active.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

www.xilinx.com
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479

FDSE

VCC
CE
AND2

AND2B1

S
OR3

FD

D
AND2
D
C

C
Q
X7815

FDSE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for FDSE should be placed
-- after architecture statement but before begin keyword
component FDSE
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC;
D : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDSE
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDSE_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDSE should be placed

-- in architecture after the begin keyword
FDSE_INSTANCE_NAME : FDSE
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on

480

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Libraries Guide
ISE 6.3i

FDSE

port map (Q => user_Q,

C => user_C,
CE => user_CE,
D => user_D,
S => user_S);

Verilog Instantiation Template

FDSE FDSE_instance_name (.Q (user_Q),
.C (user_C),
.CE (user_CE),
.D (user_D),
.S (user_S));
defparam FDSE_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

481

482

FDSE

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

FDSE_1

FDSE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and Synchronous
Set
Architectures Supported
FDSE_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FDSE_1

CE

X8368

No

CoolRunner XPLA3

No

CoolRunner-II

No

FDSE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous
set (S) inputs and data output (Q). The synchronous set (S) input, when High,
overrides the clock enable (CE) input and sets the Q output High during the High-toLow clock (C) transition. The data on the D input is loaded into the flip-flop when S is
Low and CE is High during the High-to-Low clock (C) transition.
For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is
applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol. FDSE_1 will set when GSR is active. For Spartan-II,
Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the
flip-flop is preset to active high when GSR is active.
Inputs

Outputs

CE

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

483

FDSE_1

VHDL Instantiation Template

-- Component Declaration for FDSE_1 should be placed
-- after architecture statement but before begin keyword
component FDSE_1
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC;
D : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for FDSE_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FDSE_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for FDSE_1 should be placed

-- in architecture after the begin keyword

FDSE_1_INSTANCE_NAME : FDSE_1
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
CE => user_CE,
D => user_D,
S => user_S);

Verilog Instantiation Template

FDSE_1 FDSE_1_instance_name (.Q (user_Q),
.C (user_C),
.CE (user_CE),
.D (user_D),
.S (user_S));
defparam FDSE_1_instance_name.INIT = bit_value;

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

484

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1-800-255-7778

Libraries Guide
ISE 6.3i

FDSR

FDSR
D Flip-Flop with Synchronous Set and Reset
Architectures Supported
FDSR
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FDSR

X3729

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FDSR is a single D-type flip-flop with data (D), synchronous reset (R) and
synchronous set (S) inputs and data output (Q). When the set (S) input is High, it
overrides all other inputs and sets the Q output High during the Low-to-High clock
transition. (Set has precedence over Reset.) When reset (R) is High and S is Low, the
flip-flop is reset, output Low, on the Low-to-High clock transition. Data on the D
input is loaded into the flip-flop when S and R are Low on the Low-to-High clock
transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Outputs

D
R
AND2B1

FD
D

S
C

OR2
C
Q

X7817

FDSR Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

485

486

FDSR

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

FDSRE

FDSRE
D Flip-Flop with Synchronous Set and Reset and Clock Enable
Architectures Supported
FDSRE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FDSRE

CE
C

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FDSRE is a single D-type flip-flop with synchronous set (S), synchronous reset (R),
and clock enable (CE) inputs and data output (Q). When synchronous set (S) is High,
it overrides all other inputs and sets the Q output High during the Low-to-High clock
transition. (Set has precedence over Reset.) When synchronous reset (R) is High and S
is Low, output Q is reset Low during the Low-to-High clock transition. Data is loaded
into the flip-flop when S and R are Low and CE is High during the Low-to-high clock
transition. When CE is Low, clock transitions are ignored.

X3730

The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

www.xilinx.com
1-800-255-7778

487

FDSRE

VCC

CE
AND2
R
AND3B2

FD

OR3
D

AND3B1
C
X7819

FDSRE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

488

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

FJKC

FJKC
J-K Flip-Flop with Asynchronous Clear
Architectures Supported
FJKC
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FJKC

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FJKC is a single J-K-type flip-flop with J, K, and asynchronous clear (CLR) inputs and
data output (Q). The asynchronous clear (CLR) input, when High, overrides all other
inputs and resets the Q output Low. When CLR is Low, the output responds to the
state of the J and K inputs, as shown in the following truth table, during the Low-toHigh clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.

CLR

X3753

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

No Chg

Toggle

www.xilinx.com
1-800-255-7778

489

FJKC

AND3B2

A0
AD

A1
A2
OR3

AND3B1

FDC

J
K

AND2B1
C

C
CLR

CLR
X7820

FJKC Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

K
AND2B1

FDC
J

D
AND2B1

OR2
C

CLR
Q

CLR

X7821

FJKC Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

490

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Libraries Guide
ISE 6.3i

FJKCE

FJKCE
J-K Flip-Flop with Clock Enable and Asynchronous Clear
Architectures Supported
FJKCE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FJKCE

CE
C

CLR

X3756

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FJKCE is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous
clear (CLR) inputs and data output (Q). The asynchronous clear (CLR), when High,
overrides all other inputs and resets the Q output Low. When CLR is Low and CE is
High, Q responds to the state of the J and K inputs, as shown in the following truth
table, during the Low-to-High clock transition. When CE is Low, the clock transitions
are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

CE

No Chg

No Chg

Toggle

www.xilinx.com
1-800-255-7778

491

FJKCE

AND3B2

A0
AD

A1
A2
AND3B1

OR3

J
K
AND2B1

FDCE
D
CE

CE

C
CLR

CLR
X7822

FJKCE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X
VCC

CE
AND2
AND2B1
J

FDC
AND3B1
K

OR3
AND2B1

C
CLR

C
CLR
X7823

FJKCE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

492

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1-800-255-7778

Libraries Guide
ISE 6.3i

FJKCP

FJKCP
J-K Flip-Flop with Asynchronous Clear and Preset
Architectures Supported
FJKCP
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

PRE

FJKCP

CLR

X4390

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FJKCP is a single J-K-type flip-flop with J, K, asynchronous clear (CLR), and

asynchronous preset (PRE) inputs and data output (Q). When the asynchronous clear
(CLR) is High, all other inputs are ignored and Q is reset 0. The asynchronous preset
(PRE), when High, and CLR set to Low overrides all other inputs and sets the Q
output High. When CLR and PRE are Low, Q responds to the state of the J and K
inputs during the Low-to-High clock transition, as shown in the following truth table.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Outputs

CLR

PRE

No Chg

Toggle

AND2B1

FDCP

PRE

PRE

OR2
AND2B1

C
CLR
Q

C
CLR

X8124

FJKCP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

493

FJKCP

Usage
For HDL, this design element is inferred rather than instantiated.

494

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1-800-255-7778

Libraries Guide
ISE 6.3i

FJKCPE

FJKCPE
J-K Flip-Flop with Asynchronous Clear and Preset and Clock Enable
Architectures Supported
FJKCPE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

PRE

FJKCPE

CE
C

CLR
X4391

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FJKCPE is a single J-K-type flip-flop with J, K, asynchronous clear (CLR),

asynchronous preset (PRE), and clock enable (CE) inputs and data output (Q). When
the asynchronous clear (CLR) is High, all other inputs are ignored and Q is reset 0.
The asynchronous preset (PRE), when High, and CLR set to Low overrides all other
inputs and sets the Q output High. When CLR and PRE are Low and CE is High, Q
responds to the state of the J and K inputs, as shown in the following truth table,
during the Low-to-High clock transition. Clock transitions are ignored when CE is
Low.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

PRE

CE

No Chg

No Chg

Toggle

www.xilinx.com
1-800-255-7778

495

FJKCPE

VCC
5

FDCP

CE
AND2B1
J

AND2

PRE
D
AND3B1

OR3
C
CLR

K
PRE

AND2B1

C
CLR
X7687

FJKCPE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

496

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1-800-255-7778

Libraries Guide
ISE 6.3i

FJKP

FJKP
J-K Flip-Flop with Asynchronous Preset
Architectures Supported
FJKP
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

PRE

FJKP

X3754

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FJKP is a single J-K-type flip-flop with J, K, and asynchronous preset (PRE) inputs and
data output (Q). The asynchronous preset (PRE) input, when High, overrides all other
inputs and sets the Q output High. When PRE is Low, the Q output responds to the
state of the J and K inputs, as shown in the following truth table, during the Low-toHigh clock transition.
For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is
applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
The GSR active level defaults to active-High but can be inverted by adding an inverter
in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3,
STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is
asynchronously cleared, output Low, when power is applied. The power-on condition
can be simulated by applying a High-level pulse on the PRLD global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

PRE

No Chg

Toggle

www.xilinx.com
1-800-255-7778

497

FJKP

AND3B2

A0
AD

A1
A2
OR3

AND3B1
J
K
AND2B1

FDP

PRE

D
C

PRE

C
RLOC=R0C0
X7824

FJKP Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

AND3B2

A0
AD

A1
A2
AND3B1

OR3

J
K
AND2B1

FDP

PRE

PRE
D
C

C
RLOC=X0Y0
X9317

FJKP Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

J

AND2B1

FDP

PRE

PRE

OR2
AND2B1

C
Q

X8125

FJKP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

498

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1-800-255-7778

Libraries Guide
ISE 6.3i

FJKPE

FJKPE
J-K Flip-Flop with Clock Enable and Asynchronous Preset
Architectures Supported
FJKPE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

PRE

FJKPE

CE
C

X3757

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FJKPE is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous
preset (PRE) inputs and data output (Q). The asynchronous preset (PRE), when High,
overrides all other inputs and sets the Q output High. When PRE is Low and CE is
High, the Q output responds to the state of the J and K inputs, as shown in the truth
table, during the Low-to-High clock (C) transition. When CE is Low, clock transitions
are ignored.
For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is
applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
The GSR active level defaults to active-High but can be inverted by adding an inverter
in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3,
STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is
asynchronously cleared, output Low, when power is applied. The power-on condition
can be simulated by applying a High-level pulse on the PRLD global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

PRE

CE

No Chg

No Chg

Toggle

www.xilinx.com
1-800-255-7778

499

FJKPE

AND3B2

A0
AD

A1
A2
OR3

AND3B1
J
K
AND2B1

FDPE

PRE

PRE

CE

CE

C
RLOC=R0C0
X7825

FJKPE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

AND3B2

A0
A1

AD

A2
AND3B1

OR3

J
K
AND2B1

FDPE

PRE

D
CE

PRE

CE

C
RLOC=X0Y0

X9318

FJKPE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC

CE
AND2

FDP

AND2B1

K
AND2B1

PRE

OR3
C

Q
AND3B1

PRE

X7826

FJKPE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

500

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1-800-255-7778

Libraries Guide
ISE 6.3i

FJKRSE

FJKRSE
J-K Flip-Flop with Clock Enable and Synchronous Reset and Set
Architectures Supported
FJKRSE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FJKRSE

CE
C

X3760

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FJKRSE is a single J-K-type flip-flop with J, K, synchronous reset (R), synchronous set
(S), and clock enable (CE) inputs and data output (Q). When synchronous reset (R) is
High, all other inputs are ignored and output Q is reset Low. (Reset has precedence
over Set.) When synchronous set (S) is High and R is Low, output Q is set High. When
R and S are Low and CE is High, output Q responds to the state of the J and K inputs,
according to the following truth table, during the Low-to-High clock (C) transition.
When CE is Low, clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

No Chg

Toggle

www.xilinx.com
1-800-255-7778

501

FJKRSE

AND3B2

A0
A1

AD_S

A2
AND3B1
J

OR4

FDRE

AND2B1
S
CE

S_CE

CE

OR2

C
R

R
RLOC=R0C0

X7827

FJKRSE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

AND3B2

A0
A1

AD_S

A2
AND3B1

OR4

J
K

FDRE
AND2B1

OR2

D
S_CE

CE

CE
C
R

R
RLOC=X0Y0

X9319

FJKRSE Implementation Spartan-3, Virtex-II, Virtex-II Pro

VCC

CE
K
S

AND2

AND4B1

AND3B3

FD
D

J
AND3B3

NOR4

R
Q
C
X8126

FJKRSE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

502

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Libraries Guide
ISE 6.3i

FJKSRE

FJKSRE
J-K Flip-Flop with Clock Enable and Synchronous Set and Reset
Architectures Supported
FJKSRE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FJKSRE

CE
C

X3759

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FJKSRE is a single J-K-type flip-flop with J, K, synchronous set (S), synchronous reset
(R), and clock enable (CE) inputs and data output (Q). When synchronous set (S) is
High, all other inputs are ignored and output Q is set High. (Set has precedence over
Reset.) When synchronous reset (R) is High and S is Low, output Q is reset Low. When
S and R are Low and CE is High, output Q responds to the state of the J and K inputs,
as shown in the following truth table, during the Low-to-High clock (C) transition.
When CE is Low, clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol. FJKSRE will set when GSR is active. For Spartan-II,
Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the
flip-flop is preset to active high when GSR is active.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

No Chg

Toggle

www.xilinx.com
1-800-255-7778

503

FJKSRE

AND3B2

A0
AD

A1

AD_R

A2
OR3

AND3B1

AND2B1

J
K

FDSE

AND2B1

R_CE

CE

CE

OR2

X7828

FJKSRE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

AND3B2

A0
A1

AD

AD_R

A2
AND3B1

OR3

AND2B1

J
K
AND2B1

FDSE

D
R_CE

CE
OR2

CE
C
RLOC=X0Y0

X9320

FJKSRE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC

CE
AND2

AND2B2

K
AND3
J
R

AND2B2

FD

OR4
D

NAND2B1

C
Q

X8127

FJKSRE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

504

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Libraries Guide
ISE 6.3i

FMAP

FMAP
F Function Generator Partitioning Control Symbol
Architectures Supported
FMAP
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I4

FMAP

I3
I2

I1

X4646

No

CoolRunner XPLA3

No

CoolRunner-II

No

The FMAP symbol is used to map logic to the function generator of a slice. See the
appropriate CAE tool interface user guide for information about specifying this
attribute in your schematic design editor.
The MAP=type parameter can be used with the FMAP symbol to further define how
much latitude you want to give the mapping program. The following table shows
MAP option characters and their meanings.
MAP Option Character

Function

Pins.

Closed Adding logic to or removing logic from the CLB is not

allowed.

Locked Locking CLB pins.

Open Adding logic to or removing logic from the CLB is

allowed.

Unlocked No locking on CLB pins.

Possible types of MAP parameters for FMAP are MAP=PUC, MAP=PLC, MAP=PLO,
and MAP=PUO. The default parameter is PUO. If one of the open parameters is
used (PLO or PUO), only the output signals must be specified.
Note: Currently, only PUC and PUO are observed. PLC and PLO are translated into PUC and
PUO, respectively.
The FMAP symbol can be assigned to specific CLB locations using LOC attributes.

Usage
FMAPs are generally inferred with the logic portions of the HDL code. Xilinx suggests
that you instantiate FMAPs only if you have a need to implicitly specify the logic
mapping, or if you need to manually place or relationally place the logic.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

505

FMAP

VHDL Instantiation Template

-- Component Declaration for FMAP should be placed
-- after architecture statement but before begin keyword
component FMAP
port (I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC;
I3 : in STD_ULOGIC;
I4 : in STD_ULOGIC;
O : in STD_ULOGIC);
end component;
-- Component Attribute specification for FMAP
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter constraints here

-- Component Instantiation for FMAP should be placed

-- in architecture after the begin keyword
FMAP_INSTANCE_NAME : FMAP
port map (I1 => user_I1,
I2 => user_I2,
I3 => user_I3,
I4 => user_I4,
O => user_O);

Verilog Instantiation Template

FMAP FMAP_instanceb_name (.I1 (user_I1),
.I2 (user_I2),
.I3 (user_I3),
.I4 (user_I4),
.O (user_O));

Commonly Used Constraints

BEL, BLKNM, HBLKNM, HU_SET, LOC, MAP, U_SET

506

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Libraries Guide
ISE 6.3i

FTC

FTC
Toggle Flip-Flop with Toggle Enable and Asynchronous Clear
Architectures Supported
FTC
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FTC

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTC is a synchronous, resettable toggle flip-flop. The asynchronous clear (CLR) input,
when High, overrides all other inputs and resets the data output (Q) Low. The Q
output toggles, or changes state, when the toggle enable (T) input is High and CLR is
Low during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.

CLR

X3761

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

No Chg

Toggle

FDC
TQ

T
C

XOR2
C
CLR

CLR
X7830

FTC Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

507

FTC

FDC
TQ

T
C

XOR2
C

CLR

CLR
RLOC=X0Y0

X9321

FTC Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

FTCP
T

PRE

C
CLR
Q

CLR

X7831
GND

FTC Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element can be instantiated or inferred.

VHDL Instantiation Template

-- Component Declaration for FTC should be placed
-- after architecture statement but before begin keyword
component FTC
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CLR : in STD_ULOGIC;
T : in STD_ULOGIC);
end component;
-- Component Attribute specification for FTC
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here
-- Component Instantiation for FTC should be placed
-- in architecture after the begin keyword
FTC_INSTANCE_NAME : FTC
port map (Q => user_Q,
C => user_C,
CLR => user_CLR,
T => user_T);

508

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1-800-255-7778

Libraries Guide
ISE 6.3i

FTC

Verilog Instantiation Template

FTC FTC_instance_name (.Q (user_Q),
.C (user_C),
.CLR (user_CLR),
.T (user_T));

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

509

510

FTC

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

FTCE

FTCE
Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
Architectures Supported
FTCE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FTCE

CE
C

CLR

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTCE is a toggle flip-flop with toggle and clock enable and asynchronous clear. When
the asynchronous clear (CLR) input is High, all other inputs are ignored and the data
output (Q) is reset Low. When CLR is Low and toggle enable (T) and clock enable (CE)
are High, Q output toggles, or changes state, during the Low-to-High clock (C)
transition. When CE is Low, clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.

X3764

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs
CLR

CE

No Chg

No Chg

Toggle

FDCE

TQ

T
CE

Outputs

XOR2

CE
C

CLR

CLR
X7832

FTCE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

511

FTCE

CE

FDCE

TQ

XOR2

CE

CLR

CLR
RLOC=X0Y0

X9322

FTCE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

FTCP
T
CE
C

PRE

AND2
C
CLR
Q

CLR

X7833
GND

FTCE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element can be inferred or instantiated.

VHDL Instantiation Template

-- Component Declaration for FTCE should be placed
-- after architecture statement but before begin keyword
component FTCE
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
T : in STD_ULOGIC);
end component;
-- Component Attribute specification for FTCE
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here
-- Component Instantiation for FTCE should be placed
-- in architecture after the begin keyword
FTCE_INSTANCE_NAME : FTCE
port map (Q => user_Q,
C => user_C,
CE => user_CE,
CLR => user_CLR,
PRE => user_PRE,
T => user_T);

512

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Libraries Guide
ISE 6.3i

FTCE

Verilog Instantiation Template

FTCE FTCE_instance_name (.Q (user_Q),
.C (user_C),
.CE (user_CE),
.CLR (user_CLR),
.PRE (user_PRE),
.T (user_T));

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
and XBLKNM.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

513

514

FTCE

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

FTCLE

FTCLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and
Asynchronous Clear
Architectures Supported
FTCLE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FTCLE

L
T

CE
C

CLR

X3769

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTCLE is a toggle/loadable flip-flop with toggle and clock enable and asynchronous
clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored
and output Q is reset Low. When load enable input (L) is High and CLR is Low, clock
enable (CE) is overridden and the data on data input (D) is loaded into the flip-flop
during the Low-to-High clock (C) transition. When toggle enable (T) and CE are High
and L and CLR are Low, output Q toggles, or changes state, during the Low- to-High
clock transition. When CE is Low, clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

CE

No Chg

No Chg

Toggle

www.xilinx.com
1-800-255-7778

515

FTCLE

TQ

T
XOR2

D0

M2_1
O

D1

D
L

MD

FDCE

S0
D

L_CE

CE

CE
C

OR2

CLR

C
CLR
X8147

RLOC=R0C0

FTCLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

TQ

M2_1

XOR2

D0

D1

S0

MD

FDCE
L_CE

CE

D
CE

OR2

CLR

CLR
RLOC=X0Y0
X9323

FTCLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC
CE
AND3

AND3B2
OR2
GRD
AND4B2
OR4

T
AND3B2

FDC
D

AND2
C

C
CLR
Q

CLR

X7561

FTCLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

516

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1-800-255-7778

Libraries Guide
ISE 6.3i

FTCLEX

FTCLEX
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and
Asynchronous Clear
Architectures Supported
FTCLEX
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FTCLEX

L
T

CE
C

CLR
X7601

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTCLEX is a toggle/loadable flip-flop with toggle and clock enable and asynchronous
clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored
and output Q is reset Low. When load enable input (L) is High, CLR is Low, and CE is
High, the data on data input (D) is loaded into the flip-flop during the Low-to-High
clock (C) transition. When toggle enable (T) and CE are High and L and CLR are Low,
output Q toggles, or changes state, during the Low- to-High clock transition. When
CE is Low, clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

CE

No Chg

No Chg

Toggle

www.xilinx.com
1-800-255-7778

517

FTCLEX

TQ
M2_1

T
D0
D1
S0

XOR2
D
L

MD

FDCE
D

CE

CE
C
CLR

C
CLR

X6995

FTCLEX Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

TQ

T
XOR2

M2_1
D0

D1

S0

MD

FDCE
CE

CE
C

C
CLR

CLR
RLOC=X0Y0

X9324

FTCLEX Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

518

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Libraries Guide
ISE 6.3i

FTCP

FTCP
Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and
Preset
Architectures Supported
FTCP
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

PRE

FTCP
Q

CLR
X4392

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

FTCP is a toggle flip-flop with toggle enable and asynchronous clear and preset.
When the asynchronous clear (CLR) input is High, all other inputs are ignored and
the output (Q) is reset Low. When the asynchronous preset (PRE) is High and CLR is
Low, all other inputs are ignored and Q is set High. When the toggle enable input (T)
is High and CLR and PRE are Low, output Q toggles, or changes state, during the
Low-to-High clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Outputs

CLR

PRE

No Chg

Toggle

Usage
For HDL, this design element can be inferred or instantiated.

VHDL Instantiation Template

-- Component Declaration for FTCP should be placed
-- after architecture statement but before begin keyword
component FTCP
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
T : in STD_ULOGIC);
end component;

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

519

FTCP

-- Component Attribute specification for FTCP

-- should be placed after architecture declaration but
-- before the begin keyword

-- Enter attributes here

-- Component Instantiation for FTCP should be placed

-- in architecture after the begin keyword
FTCP_INSTANCE_NAME : FTCP
port map (Q => user_Q,
C => user_C,
CLR => user_CLR,
PRE => user_PRE,
T => user_T);

Verilog Instantiation Template

FTCP FTCP_instance_name (.Q (user_Q),
.C (user_C),
.CLR (user_CLR),
.PRE (user_PRE),
.T (user_T));

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

520

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Libraries Guide
ISE 6.3i

FTCPE

FTCPE
Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
and Preset
Architectures Supported
FTCPE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

PRE

FTCPE

CE

CLR
X4393

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTCPE is a toggle flip-flop with toggle and clock enable and asynchronous clear and
preset. When the asynchronous clear (CLR) input is High, all other inputs are ignored
and the output (Q) is reset Low. When the asynchronous preset (PRE) is High and
CLR is Low, all other inputs are ignored and Q is set High. When the toggle enable
input (T) and the clock enable input (CE) are High and CLR and PRE are Low, output
Q toggles, or changes state, during the Low-to-High clock (C) transition. Clock
transitions are ignored when CE is Low.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Outputs

CLR

PRE

CE

No Chg

No Chg

Toggle

FTCP

PRE
T

PRE
T

CE
C

AND2
C
CLR

CLR

X7681

FTCPE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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1-800-255-7778

521

522

FTCPE

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Libraries Guide
ISE 6.3i

FTCPLE

FTCPLE
Loadable Toggle Flip-Flop with Toggle and Clock Enable and
Asynchronous Clear and Preset
Architectures Supported
FTCPLE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

PRE

FTCPLE

L
T

CE
C

CLR

X4394

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTCPLE is a loadable toggle flip-flop with toggle and clock enable and asynchronous
clear and preset. When the asynchronous clear (CLR) input is High, all other inputs
are ignored and the output (Q) is reset Low. When the asynchronous preset (PRE) is
High and CLR is Low, all other inputs are ignored and Q is set High. When the load
input (L) is High, the clock enable input (CE) is overridden and data on data input (D)
is loaded into the flip-flop during the Low-to-High clock transition. When the toggle
enable input (T) and the clock enable input (CE) are High and CLR, PRE, and L are
Low, output Q toggles, or changes state, during the Low-to-High clock (C) transition.
Clock transitions are ignored when CE is Low.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

PRE

CE

No Chg

No Chg

Toggle

www.xilinx.com
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523

FTCPLE

VCC

CE
AND2
L
OR2

AND3B2

GND
AND4B2

FDCP

AND3B2
D

OR4
AND2

PRE

C
CLR

PRE
C
CLR
X7845

FTCPLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

524

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Libraries Guide
ISE 6.3i

FTDCE

FTDCE
Dual Edge Triggered Toggle Flip-Flop with Toggle and Clock Enable and
Asynchronous Clear
Architectures Supported
FTDCE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FTDCE

CE
C

CLR

X9751

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FTDCE is a dual edge triggered toggle flip-flop with toggle and clock enable and
asynchronous clear. When the asynchronous clear (CLR) input is High, all other
inputs are ignored and the data output (Q) is reset Low. When CLR is Low and toggle
enable (T) and clock enable (CE) are High, Q output toggles, or changes state, during
the Low-to-High and High-to-Low clock (C) transitions. When CE is Low, clock
transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Outputs

CLR

CE

No Chg

No Chg

Toggle

Toggle

FTCP
T
CE
C

PRE

AND2
C
CLR
Q

CLR

X7833
GND

FTDCE Implementation CoolRunner-II

Libraries Guide
ISE 6.3i

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525

FTDCE

Usage
For HDL, this design element is inferred rather than instantiated.

526

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Libraries Guide
ISE 6.3i

FTDCLE

FTDCLE
Dual Edge Triggered Toggle/Loadable Flip-Flop with Toggle and Clock
Enable and Asynchronous Clear
Architectures Supported
FTDCLE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FTDCLE

L
T

CE
C

CLR

X9752

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FTDCLE is a dual edge triggered toggle/loadable flip-flop with toggle and clock
enable and asynchronous clear. When the asynchronous clear input (CLR) is High, all
other inputs are ignored and output Q is reset Low. When load enable input (L) is
High and CLR is Low, clock enable (CE) is overridden and the data on data input (D)
is loaded into the flip-flop during the Low-to-High and High-to-Low clock (C)
transitions. When toggle enable (T) and CE are High and L and CLR are Low, output
Q toggles, or changes state, during the Low- to-High and High-to-Low clock
transitions. When CE is Low, clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

CE

No Chg

No Chg

Toggle

Toggle

www.xilinx.com
1-800-255-7778

527

FTDCLE

VCC

CE
AND3

AND3B2
OR2
GRD
AND4B2
OR4

T
AND3B2

FDDC
D

AND2
C

C
CLR
Q

CLR

X9753

FTDCLE Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

528

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Libraries Guide
ISE 6.3i

FTDCLEX

FTDCLEX
Dual Edge Triggered Toggle/Loadable Flip-Flop with Toggle and Clock
Enable and Asynchronous Clear
Architectures Supported
FTCLEX
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

FTDCLEX

L
T

CE
C

CLR
X9754

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FTDCLEX is a dual edge triggered toggle/loadable flip-flop with toggle and clock
enable and asynchronous clear. When the asynchronous clear input (CLR) is High, all
other inputs are ignored and output Q is reset Low. When load enable input (L) is
High, CLR is Low, and CE is High, the data on data input (D) is loaded into the flipflop during the Low-to-High and High-to-Low clock (C) transitions. When toggle
enable (T) and CE are High and L and CLR are Low, output Q toggles, or changes
state, during the Low- to-High and High-to-Low clock transitions. When CE is Low,
clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.
Inputs

Outputs

CLR

CE

No Chg

No Chg

Toggle

Toggle

Usage
For HDL, this design element is inferred rather than instantiated.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

529

530

FTDCLEX

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Libraries Guide
ISE 6.3i

FTDCP

FTDCP
Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and
Preset
Architectures Supported
FTDCP
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

PRE

FTDCP
Q

CLR
X9777

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

FTDCP is a toggle flip-flop with toggle enable and asynchronous clear and preset.
When the asynchronous clear (CLR) input is High, all other inputs are ignored and
the output (Q) is reset Low. When the asynchronous preset (PRE) is High and CLR is
Low, all other inputs are ignored and Q is set High. When the toggle enable input (T)
is High and CLR and PRE are Low, output Q toggles, or changes state, during the
Low-to-High and High-to-Low clock (C) transition.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CLR

PRE

No Chg

Toggle

Toggle

www.xilinx.com
1-800-255-7778

531

FTDCP

FTDCP
T
CE
C

PRE

AND2
C
CLR
Q

CLR

GND

X9778

FTDCP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

532

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Libraries Guide
ISE 6.3i

FTDRSE

FTDRSE
Dual Edge Triggered Toggle Flip-Flop with Toggle and Clock Enable and
Synchronous Reset and Set
Architectures Supported
FTDRSE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

T
CE
C

FTDRSE

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

FTDRSE is a dual edge triggered toggle flip-flop with toggle and clock enable and
synchronous reset and set. When the synchronous reset input (R) is High, it overrides
all other inputs and the data output (Q) is reset Low. When the synchronous set input
(S) is High and R is Low, clock enable input (CE) is overridden and output Q is set
High. (Reset has precedence over Set.) When toggle enable input (T) and CE are High
and R and S are Low, output Q toggles, or changes state, during the Low-to-High and
High-to-Low clock transitions.

X9755

The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

No Chg

Toggle

Toggle

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533

FTDRSE

VCC

CE
AND2B1

AND2
T

AND3B1
S
OR4

FDD
AND3B1
D

AND2B1

C
X9756

FTDRSE Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

534

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Libraries Guide
ISE 6.3i

FTDRSLE

FTDRSLE
Dual Edge Triggered Toggle/Loadable Flip-Flop with Toggle and Clock
Enable and Synchronous Reset and Set
Architectures Supported
FTDRSLE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FTDRSLE

L
T

CE
C

X9757

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTDRSLE is a dual edge triggered toggle/loadable flip-flop with toggle and clock
enable and synchronous reset and set. The synchronous reset input (R), when High,
overrides all other inputs and resets the data output (Q) Low. (Reset has precedence
over Set.) When R is Low and synchronous set input (S) is High, the clock enable
input (CE) is overridden and output Q is set High. When R and S are Low and load
enable input (L) is High, CE is overridden and data on data input (D) is loaded into
the flip-flop during the Low-to-High and High-to-Low clock transitions. When R, S,
and L are Low and CE is High, output Q toggles, or changes state, during the Low-toHigh and High-to-Low clock transitions. When CE is Low, clock transitions are
ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

No Chg

Toggle

Toggle

www.xilinx.com
1-800-255-7778

535

FTDRSLE

VCC

CE

FDD

AND2
L
D
OR2

AND3B2
C

GND
T
AND4B2
S
AND2B1
OR5

AND4B2
D
AND2

R
C

X9758

FTDRSLE Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

536

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Libraries Guide
ISE 6.3i

FTP

FTP
Toggle Flip-Flop with Toggle Enable and Asynchronous Preset
Architectures Supported
FTP
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FTP

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTP is a toggle flip-flop with toggle enable and asynchronous preset. When the
asynchronous preset (PRE) input is High, all other inputs are ignored and output Q is
set High. When toggle-enable input (T) is High and PRE is Low, output Q toggles, or
changes state, during the Low-to-High clock (C) transition.

X3762

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is

asynchronously cleared, output Low, when power is applied. The power-on condition
can be simulated by applying a High-level pulse on the PRLD global net.

PRE

Macro

For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, the flip-flop is asynchronously preset to output High, when power is
applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
The GSR active level defaults to active-High but can be inverted by adding an inverter
in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_VIRTEX,
STARTUP_SPARTAN3, or the STARTUP_VIRTEX2 symbol.
Inputs

Outputs

PRE

No Chg

Toggle

FDP

PRE
TQ

T
C

PRE

XOR2
C
RLOC=R0C0
X6371

FTP Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

537

FTP

FDP

PRE

PRE

TQ

XOR2

C
RLOC=X0Y0

X9325

FTP Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

FTCP

PRE

PRE

T
C

C
CLR

X7680

GND

FTP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element can be inferred or instantiated.

VHDL Instantiation Template

-- Component Declaration for FTP should be placed
-- after architecture statement but before begin keyword
component FTP
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
PRE : in STD_ULOGIC;
T : in STD_ULOGIC);
end component;
-- Component Attribute specification for FTP
-- should be placed after architecture declaration but
-- before the begin keyword

-- Enter attributes here

-- Component Instantiation for FTP should be placed

-- in architecture after the begin keyword
FTP_INSTANCE_NAME :
port map (Q
=>
C
=>
PRE =>
T
=>

538

FTP
user_Q,
user_C,
user_PRE,
user_T);

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Libraries Guide
ISE 6.3i

FTP

Verilog Instantiation Template

FTP FTP_instance_name (.Q (user_Q),
.C (user_C),
.PRE (user_PRE),
.T (user_T));

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET,
XBLKNM

Libraries Guide
ISE 6.3i

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539

540

FTP

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1-800-255-7778

Libraries Guide
ISE 6.3i

FTPE

FTPE
Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous
Preset
Architectures Supported
FTPE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

PRE

FTPE

CE
C

X3765

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTPE is a toggle flip-flop with toggle and clock enable and asynchronous preset.
When the asynchronous preset (PRE) input is High, all other inputs are ignored and
output Q is set High. When the toggle enable input (T) is High, clock enable (CE) is
High, and PRE is Low, output Q toggles, or changes state, during the Low-to-High
clock transition. When CE is Low, clock transitions are ignored.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is
asynchronously cleared, output Low, when power is applied. The power-on condition
can be simulated by applying a High-level pulse on the PRLD global net.
For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, the flip-flop is asynchronously preset to output High, when power is
applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
The GSR active level defaults to active-High but can be inverted by adding an inverter
in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3,
STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

PRE

CE

No Chg

No Chg

Toggle

www.xilinx.com
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541

FTPE

FDPE

PRE
TQ

XOR2

PRE

CE

CE

RLOC=R0C0
X8694

FTPE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FDPE

PRE

PRE

TQ

CE

XOR2

CE

C
RLOC=X0Y0

X9326

FTPE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

FTCP

PRE
T

PRE
T

CE
C

AND2
C
CLR
Q

GND

X7683

FTPE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

542

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Libraries Guide
ISE 6.3i

FTPLE

FTPLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and
Asynchronous Preset
Architectures Supported
FTPLE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

PRE

FTPLE

L
T

CE
C

X3770

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTPLE is a toggle/loadable flip-flop with toggle and clock enable and asynchronous
preset. When the asynchronous preset input (PRE) is High, all other inputs are
ignored and output Q is set High. When the load enable input (L) is High and PRE is
Low, the clock enable (CE) is overridden and the data (D) is loaded into the flip-flop
during the Low-to-High clock transition. When L and PRE are Low and toggle-enable
input (T) and CE are High, output Q toggles, or changes state, during the Low-toHigh clock transition. When CE is Low, clock transitions are ignored.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is
asynchronously cleared, output Low, when power is applied. The power-on condition
can be simulated by applying a High-level pulse on the PRLD global net.
For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, the flip-flop is asynchronously preset to output High, when power is
applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
The GSR active level defaults to active-High but can be inverted by adding an inverter
in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3,
STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

PRE

CE

No Chg

No Chg

Toggle

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543

FTPLE

TQ
T

M2_1
XOR2

D0

D1

S0

MD

FDPE

PRE

CE

PRE

CE

OR2

C
RLOC=R0C0
X6372

FTPLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

TQ

T
XOR2

M2_1
D0

D1

S0

MD

FDPE

PRE

PRE
D

CE
C

CE

OR2

C
RLOC=X0Y0

X9327

FTPLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC

CE
AND2
L
AND3B2

OR2
GND

AND4B2

FDP

AND3B2
D

OR4

PRE

AND2
PRE
C
X7846

FTPLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

544

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Libraries Guide
ISE 6.3i

FTRSE

FTRSE
Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Reset
and Set
Architectures Supported
FTRSE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

T
CE
C

FTRSE

X3768

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTRSE is a toggle flip-flop with toggle and clock enable and synchronous reset and
set. When the synchronous reset input (R) is High, it overrides all other inputs and the
data output (Q) is reset Low. When the synchronous set input (S) is High and R is
Low, clock enable input (CE) is overridden and output Q is set High. (Reset has
precedence over Set.) When toggle enable input (T) and CE are High and R and S are
Low, output Q toggles, or changes state, during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

No Chg

Toggle

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545

FTRSE

TQ
T
D_S

XOR2
S

FDRE
OR2
D

CE_S

CE

CE
OR2

C
R

R
RLOC=R0C0
X7658

FTRSE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

TQ

T
S

XOR2

D_S
OR2

FDRE
D
CE_S

CE
C

CE
C

OR2

R
RLOC=X0Y0
X9328

FTRSE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC

CE
AND2B1

AND2
T

AND3B1
S
OR4

FD
AND3B1
D

AND2B1

C
X7847

FTRSE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

546

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Libraries Guide
ISE 6.3i

FTRSLE

FTRSLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and
Synchronous Reset and Set
Architectures Supported
FTRSLE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FTRSLE

L
T

CE
C

X3773

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTRSLE is a toggle/loadable flip-flop with toggle and clock enable and synchronous
reset and set. The synchronous reset input (R), when High, overrides all other inputs
and resets the data output (Q) Low. (Reset has precedence over Set.) When R is Low
and synchronous set input (S) is High, the clock enable input (CE) is overridden and
output Q is set High. When R and S are Low and load enable input (L) is High, CE is
overridden and data on data input (D) is loaded into the flip-flop during the Low-toHigh clock transition. When R, S, and L are Low, CE is High and T is High, output Q
toggles, or changes state, during the Low-to-High clock transition. When CE is Low,
clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

No Chg

Toggle

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547

FTRSLE

TQ
T
D0

XOR2
D

D1

S0

M2_1
O MD

MD_S
S

FDRE

OR2

CE_S_L

CE

CE

OR3
C

R
RLOC=R0C0
X7641

FTRSLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

TQ

M2_1

XOR2

D0

D1

S0

MD

MD_S

S
OR2

FDRE
CE_S_L
D

CE
OR3

CE

R
RLOC=X0Y0
X9329

FTRSLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC

CE

FD

AND2
L
D
OR2

AND3B2
C

GND
T
AND4B2
S
AND2B1
OR5

AND4B2
D
AND2

R
C

X7848

FTRSLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

548

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1-800-255-7778

Libraries Guide
ISE 6.3i

FTSRE

FTSRE
Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Set
and Reset
Architectures Supported
FTSRE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FTSRE

CE
C

X3767

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTSRE is a toggle flip-flop with toggle and clock enable and synchronous set and
reset. The synchronous set input, when High, overrides all other inputs and sets data
output (Q) High. (Set has precedence over Reset.) When synchronous reset input (R)
is High and S is Low, clock enable input (CE) is overridden and output Q is reset Low.
When toggle enable input (T) and CE are High and S and R are Low, output Q toggles,
or changes state, during the Low-to-High clock transition. When CE is Low, clock
transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol. FTSRE will set when GSR is active. For Spartan-II,
Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the
flip-flop is preset to active high when GSR is active.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

No Chg

Toggle

www.xilinx.com
1-800-255-7778

549

FTSRE

TQ
T
D_R

XOR2
R

FDSE

AND2B1

S
D

CE_R

CE

CE
OR2

C
RLOC=R0C0

X7643

FTSRE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

TQ

T
R

D_R

XOR2

FDSE

AND2B1

D
CE_R

CE

CE
C

OR2

RLOC=X0Y0

X9330

FTSRE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC

CE
AND2

R
AND3B2

AND4B2

FD
D
AND3B2

OR4

S
C
X7849

FTSRE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

550

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Libraries Guide
ISE 6.3i

FTSRLE

FTSRLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and
Synchronous Set and Reset
Architectures Supported
FTSRLE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

FTSRLE

L
T

CE
C

X3772

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

FTSRLE is a toggle/loadable flip-flop with toggle and clock enable and synchronous
set and reset. The synchronous set input (S), when High, overrides all other inputs
and sets data output (Q) High. (Set has precedence over Reset.) When synchronous
reset (R) is High and S is Low, clock enable input (CE) is overridden and output Q is
reset Low. When load enable input (L) is High and S and R are Low, CE is overridden
and data on data input (D) is loaded into the flip-flop during the Low-to-High clock
transition. When the toggle enable input (T) and CE are High and S, R, and L are Low,
output Q toggles, or changes state, during the Low-to- High clock transition. When
CE is Low, clock transitions are ignored.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is
asynchronously preset when a High-level pulse is applied on the PRLD global net.
For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X, the flip-flop is asynchronously cleared, output Low, when global
set/reset (GSR) is active.
The GSR active level defaults to active-High but can be inverted by adding an inverter
in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3,
STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FTSRLE will set when GSR is
active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro,
and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

No Chg

No Chg

Toggle

www.xilinx.com
1-800-255-7778

551

FTSRLE

TQ

M2_1

XOR2

D0

D
L

D1
S0

MD

MD_S

R
AND2B1

FDSE

D
CE
C

CE_R_L

CE
OR3

RLOC=R0C0
X7642

FTSRLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

TQ

T
XOR2

M2_1
D0

D1

S0

MD

MD_S

R
AND2B1

FDSE
D

CE_R_L
CE

CE
C

OR3

RLOC=R0C0
X9331

FTSRLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC

CE
AND2

R
AND4B3
T
L
OR2

AND5B3

GND

FD
D

AND4B3
D

AND3B1
S
C

OR5

C
Q
X7850

FTSRLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

552

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Libraries Guide
ISE 6.3i

GND

GND
Ground-Connection Signal Tag
Architectures Supported
GND
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

The GND signal tag, or parameter, forces a net or input function to a Low logic level.
A net tied to GND cannot have any other source.
When the logic-trimming software or fitter encounters a net or input function tied to
GND, it removes any logic that is disabled by the GND signal. The GND signal is only
implemented when the disabled logic cannot be removed.
X3858

Usage
For HDL, this design element can be instantiated or inferred.

VHDL Instantiation Template

-- Component Declaration for GND should be placed
-- after architecture statement but before begin keyword
component GND
port (G : out STD_ULOGIC);
end component;
-- Component Attribute specification for GND
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter constraints here

-- Component Instantiation for GND should be placed

-- in architecture after the begin keyword
GND_INSTANCE_NAME : GND
port map (G => user_G);

Verilog Instantiation Template

GND GND_instance_name (.G (user_G));

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

553

554

GND

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1-800-255-7778

Libraries Guide
ISE 6.3i

GT_AURORA_n

GT_AURORA_n
Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT_AURORA_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro but not for Virtex-II or

Virtex-II Pro X.

This Xilinx protocol gigabit transceiver supports 1, 2, and 4-byte data paths. The letter
n represents number of bytes of the data path. Valid values are 1, 2 or 4.
You can also set attributes for the primitives. For a description of these attributes and
their default attribute values, or to see a list the input and output ports for all values
of n and a description of each of the ports, see the RocketIO Transceiver User Guide.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

555

GT_AURORA_n

GT_AURORA_1
BREFCLK

CHBONDDONE

BREFCLK2

CHBONDO(3:0)
CONFIGOUT

CHBONDI(3:0)

RXBUFSTATUS(1:0)

CONFIGENABLE

RXCHARISCOMMA(0:0)

CONFIGIN

RXCHARISK(0:0)

ENCHANSYNC
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(7:0)

REFCLK
REFCLK2

RXDISPERR(0:0)
RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(0:0)

RXP

RXREALIGN

RXPOLARITY

RXRECCLK

RXRESET

RXRUNDISP(0:0)

RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(0:0)

TXBYPASS8B10B(0:0)
TXCHARDISPMODE(0:0)
TXCHARDISPVAL(0:0)

TXN
TXP
TXRUNDISP(0:0)

TXCHARISK(0:0)
TXDATA(7:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2
X9888

556

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Libraries Guide
ISE 6.3i

GT_AURORA_n

GT_AURORA_2
BREFCLK

CHBONDDONE

BREFCLK2

CHBONDO(3:0)
CONFIGOUT

CHBONDI(3:0)

RXBUFSTATUS(1:0)

CONFIGENABLE

RXCHARISCOMMA(1:0)

CONFIGIN

RXCHARISK(1:0)

ENCHANSYNC
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(15:0)

REFCLK
REFCLK2

RXDISPERR(1:0)
RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(1:0)

RXP

RXREALIGN

RXPOLARITY

RXRECCLK

RXRESET

RXRUNDISP(1:0)

RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(1:0)

TXBYPASS8B10B(1:0)

TXN

TXCHARDISPMODE(1:0)

TXP

TXCHARDISPVAL(1:0)

TXRUNDISP(1:0)

TXCHARISK(1:0)
TXDATA(15:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2
X9889

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

557

GT_AURORA_n

GT_AURORA_4
BREFCLK

CHBONDDONE

BREFCLK2

CHBONDO(3:0)
CONFIGOUT

CHBONDI(3:0)

RXBUFSTATUS(1:0)

CONFIGENABLE

RXCHARISCOMMA(3:0)

CONFIGIN

RXCHARISK(3:0)

ENCHANSYNC
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(31:0)

REFCLK
REFCLK2

RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(3:0)

RXP

RXREALIGN

RXPOLARITY

RXRECCLK

RXRESET

RXRUNDISP(3:0)

RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(3:0)

TXBYPASS8B10B(3:0)

TXN

TXCHARDISPMODE(3:0)

TXP

TXCHARDISPVAL(3:0)

TXRUNDISP(3:0)

TXCHARISK(3:0)
TXDATA(31:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2
X9890

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

558

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Libraries Guide
ISE 6.3i

GT_CUSTOM

GT_CUSTOM
Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT_CUSTOM
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro but not for Virtex-II or

Virtex-II Pro X.

This gigabit transceiver is fully customizable. You can set attributes for the primitives.
You can also set attributes for the primitives. See the RocketIO Transceiver User Guide
for a description of these attributes and their default attribute values.
The following figure lists the input and output ports for all values of n. For a
description of each of the ports, see the RocketIO Transceiver User Guide.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

559

GT_CUSTOM

GT_CUSTOM
BREFCLK

CHBONDDONE

BREFCLK2

CHBONDO(3:0)
CONFIGOUT

CHBONDI(3:0)

RXBUFSTATUS(1:0)

CONFIGENABLE

RXCHARISCOMMA(3:0)

CONFIGIN

RXCHARISK(3:0)

ENCHANSYNC
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(31:0)

REFCLK
REFCLK2

RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(3:0)

RXP

RXREALIGN

RXPOLARITY

RXRECCLK

RXRESET

RXRUNDISP(3:0)

RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(3:0)

TXBYPASS8B10B(3:0)
TXCHARDISPMODE(3:0)
TXCHARDISPVAL(3:0)

TXN
TXP
TXRUNDISP(3:0)

TXCHARISK(3:0)
TXDATA(31:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2
X9891

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

560

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1-800-255-7778

Libraries Guide
ISE 6.3i

GT_ETHERNET_n

GT_ETHERNET_n
Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT_ETHERNET_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro but not for Virtex-II

or Virtex-II Pro X.

This Ethernet gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n
represents number of bytes of the data path. Valid values are 1, 2 or 4.
You can also set attributes for the primitives. See the RocketIO Transceiver User Guide
for a description of these attributes and their default attribute values.
The following figures list the input and output ports for all values of n. For a
description of each of the ports, see the RocketIO Transceiver User Guide.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

561

GT_ETHERNET_n

GT_ETHERNET_1
CONFIGOUT

BREFCLK

RXBUFSTATUS(1:0)

BREFCLK2

RXCHARISCOMMA(0:0)

CONFIGENABLE

RXCHARISK(0:0)

CONFIGIN
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(7:0)

REFCLK

RXDISPERR(0:0)

REFCLK2

RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(0:0)

RXP

RXREALIGN
RXRECCLK

RXPOLARITY

RXRUNDISP(0:0)

RXRESET
RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(0:0)

TXBYPASS8B10B(0:0)
TXCHARDISPMODE(0:0)
TXCHARDISPVAL(0:0)

TXN
TXP
TXRUNDISP(0:0)

TXCHARISK(0:0)
TXDATA(7:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2
X9892

562

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1-800-255-7778

Libraries Guide
ISE 6.3i

GT_ETHERNET_n

GT_ETHERNET_2
CONFIGOUT

BREFCLK

RXBUFSTATUS(1:0)

BREFCLK2

RXCHARISCOMMA(1:0)

CONFIGENABLE

RXCHARISK(1:0)

CONFIGIN
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(15:0)

REFCLK

RXDISPERR(1:0)

REFCLK2

RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(1:0)

RXP

RXREALIGN
RXRECCLK

RXPOLARITY

RXRUNDISP(1:0)

RXRESET
RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(1:0)

TXBYPASS8B10B(1:0)
TXCHARDISPMODE(1:0)
TXCHARDISPVAL(1:0)

TXN
TXP
TXRUNDISP(1:0)

TXCHARISK(1:0)
TXDATA(15:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2
X9893

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

563

GT_ETHERNET_n

GT_ETHERNET_4
CONFIGOUT

BREFCLK

RXBUFSTATUS(1:0)

BREFCLK2

RXCHARISCOMMA(3:0)

CONFIGENABLE

RXCHARISK(3:0)

CONFIGIN
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(31:0)

REFCLK

RXDISPERR(3:0)

REFCLK2

RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(3:0)

RXP

RXREALIGN
RXRECCLK

RXPOLARITY

RXRUNDISP(3:0)

RXRESET
RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(3:0)

TXBYPASS8B10B(3:0)
TXCHARDISPMODE(3:0)
TXCHARDISPVAL(3:0)

TXN
TXP
TXRUNDISP(3:0)

TXCHARISK(3:0)
TXDATA(31:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2

X9894

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

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ISE 6.3i

GT_FIBRE_CHAN_n

GT_FIBRE_CHAN_n
Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT_FIBRE_CHAN_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro but not for Virtex-II or

Virtex-II Pro X.

This Fibre Channel gigabit transceiver supports 1, 2, and 4-byte data paths. The letter
n represents number of bytes of the data path. Valid values are 1, 2 or 4.
You can also set attributes for the primitives. See the RocketIO Transceiver User Guide
for a description of these attributes and their default attribute values.
The following figures list the input and output ports for all values of n. For a
description of each of the ports, see the RocketIO Transceiver User Guide.

Libraries Guide
ISE 6.3i

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565

GT_FIBRE_CHAN_n

GT_FIBRE_CHAN_1
CONFIGOUT

BREFCLK

RXBUFSTATUS(1:0)

BREFCLK2

RXCHARISCOMMA(0:0)

CONFIGENABLE

RXCHARISK(0:0)

CONFIGIN
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(7:0)

REFCLK

RXDISPERR(0:0)

REFCLK2

RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(0:0)

RXP

RXREALIGN
RXRECCLK

RXPOLARITY

RXRUNDISP(0:0)

RXRESET
RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(0:0)

TXBYPASS8B10B(0:0)
TXCHARDISPMODE(0:0)
TXCHARDISPVAL(0:0)

TXN
TXP
TXRUNDISP(0:0)

TXCHARISK(0:0)
TXDATA(7:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2

X9895

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ISE 6.3i

GT_FIBRE_CHAN_n

GT_FIBRE_CHAN_2
CONFIGOUT

BREFCLK

RXBUFSTATUS(1:0)

BREFCLK2

RXCHARISCOMMA(1:0)

CONFIGENABLE

RXCHARISK(1:0)

CONFIGIN
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(15:0)

REFCLK

RXDISPERR(1:0)

REFCLK2

RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(1:0)

RXP

RXREALIGN
RXRECCLK

RXPOLARITY

RXRUNDISP(1:0)

RXRESET
RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(1:0)

TXBYPASS8B10B(1:0)
TXCHARDISPMODE(1:0)
TXCHARDISPVAL(1:0)

TXN
TXP
TXRUNDISP(1:0)

TXCHARISK(1:0)
TXDATA(15:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2

X9896

Libraries Guide
ISE 6.3i

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567

GT_FIBRE_CHAN_n

GT_FIBRE_CHAN_4
CONFIGOUT

BREFCLK

RXBUFSTATUS(1:0)

BREFCLK2

RXCHARISCOMMA(3:0)

CONFIGENABLE

RXCHARISK(3:0)

CONFIGIN
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(31:0)

REFCLK

RXDISPERR(3:0)

REFCLK2

RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(3:0)

RXP

RXREALIGN
RXRECCLK

RXPOLARITY

RXRUNDISP(3:0)

RXRESET
RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(3:0)

TXBYPASS8B10B(3:0)

TXN

TXCHARDISPMODE(3:0)

TXP

TXCHARDISPVAL(3:0)

TXRUNDISP(3:0)

TXCHARISK(3:0)
TXDATA(31:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2
X9897

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

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ISE 6.3i

GT_INFINIBAND_n

GT_INFINIBAND_n
Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT_INFINIBAND_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro but not for Virtex-II or

Virtex-II Pro X.

This Infiniband gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n
represents number of bytes of the data path. Valid values are 1, 2 or 4.
You can also set attributes for the primitives. See the RocketIO Transceiver User Guide
for a description of these attributes and their default attribute values.
The following figures list the input and output ports for all values of n. For a
description of each of the ports, see the RocketIO Transceiver User Guide.

Libraries Guide
ISE 6.3i

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569

GT_INFINIBAND_n

GT_INFINIBAND_1
BREFCLK

CHBONDDONE

BREFCLK2

CHBONDO(3:0)
CONFIGOUT

CHBONDI(3:0)

RXBUFSTATUS(1:0)

CONFIGENABLE

RXCHARISCOMMA(0:0)

CONFIGIN

RXCHARISK(0:0)

ENCHANSYNC
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)
POWERDOWN

RXCRCERR

REFCLK

RXDATA(7:0)

REFCLK2

RXDISPERR(0:0)
RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(0:0)

RXP

RXREALIGN

RXPOLARITY

RXRECCLK

RXRESET

RXRUNDISP(0:0)

RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(0:0)

TXBYPASS8B10B(0:0)
TXCHARDISPMODE(0:0)
TXCHARDISPVAL(0:0)

TXN
TXP
TXRUNDISP(0:0)

TXCHARISK(0:0)
TXDATA(7:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2

X9898

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ISE 6.3i

GT_INFINIBAND_n

GT_INFINIBAND_2
BREFCLK

CHBONDDONE

BREFCLK2

CHBONDO(3:0)
CONFIGOUT

CHBONDI(3:0)

RXBUFSTATUS(1:0)

CONFIGENABLE

RXCHARISCOMMA(1:0)

CONFIGIN

RXCHARISK(1:0)

ENCHANSYNC
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(15:0)

REFCLK
REFCLK2

RXDISPERR(1:0)
RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(1:0)

RXP

RXREALIGN

RXPOLARITY

RXRECCLK

RXRESET

RXRUNDISP(1:0)

RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(1:0)

TXBYPASS8B10B(1:0)
TXCHARDISPMODE(1:0)
TXCHARDISPVAL(1:0)

TXN
TXP
TXRUNDISP(1:0)

TXCHARISK(1:0)
TXDATA(15:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2

X9899

Libraries Guide
ISE 6.3i

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1-800-255-7778

571

GT_INFINIBAND_n

GT_INFINIBAND_4
BREFCLK

CHBONDDONE

BREFCLK2

CHBONDO(3:0)
CONFIGOUT

CHBONDI(3:0)

RXBUFSTATUS(1:0)

CONFIGENABLE

RXCHARISCOMMA(3:0)

CONFIGIN

RXCHARISK(3:0)

ENCHANSYNC
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(31:0)

REFCLK
REFCLK2

RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(3:0)

RXP

RXREALIGN

RXPOLARITY

RXRECCLK

RXRESET

RXRUNDISP(3:0)

RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(3:0)

TXBYPASS8B10B(3:0)
TXCHARDISPMODE(3:0)
TXCHARDISPVAL(3:0)

TXN
TXP
TXRUNDISP(3:0)

TXCHARISK(3:0)
TXDATA(31:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2
X9900

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

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Libraries Guide
ISE 6.3i

GT_XAUI_n

GT_XAUI_n
Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT_XAUI_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro but not for Virtex-II

or Virtex-II Pro X.

This XAUI gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n
represents number of bytes of the data path. Valid values are 1, 2 or 4.
You can also set attributes for the primitives. See the RocketIO Transceiver User Guide
for a description of these attributes and their default attribute values.
The following figures list the input and output ports for all values of n. For a
description of each of the ports, see the RocketIO Transceiver User Guide.

Libraries Guide
ISE 6.3i

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573

GT_XAUI_n

GT_XAUI_1
BREFCLK

CHBONDDONE

BREFCLK2

CHBONDO(3:0)
CONFIGOUT

CHBONDI(3:0)

RXBUFSTATUS(1:0)

CONFIGENABLE

RXCHARISCOMMA(0:0)

CONFIGIN

RXCHARISK(0:0)

ENCHANSYNC
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(7:0)

REFCLK
REFCLK2

RXDISPERR(0:0)
RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(0:0)

RXP

RXREALIGN

RXPOLARITY

RXRECCLK

RXRESET

RXRUNDISP(0:0)

RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(0:0)

TXBYPASS8B10B(0:0)
TXCHARDISPMODE(0:0)
TXCHARDISPVAL(0:0)

TXN
TXP
TXRUNDISP(0:0)

TXCHARISK(0:0)
TXDATA(7:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2
X9902

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ISE 6.3i

GT_XAUI_n

GT_XAUI_2
BREFCLK

CHBONDDONE

BREFCLK2

CHBONDO(3:0)
CONFIGOUT

CHBONDI(3:0)

RXBUFSTATUS(1:0)

CONFIGENABLE

RXCHARISCOMMA(1:0)

CONFIGIN

RXCHARISK(1:0)

ENCHANSYNC
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(15:0)

REFCLK
REFCLK2

RXDISPERR(1:0)
RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(1:0)

RXP

RXREALIGN

RXPOLARITY

RXRECCLK

RXRESET

RXRUNDISP(1:0)

RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(1:0)

TXBYPASS8B10B(1:0)
TXCHARDISPMODE(1:0)
TXCHARDISPVAL(1:0)

TXN
TXP
TXRUNDISP(1:0)

TXCHARISK(1:0)
TXDATA(15:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2
X9903

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575

GT_XAUI_n

GT_XAUI_4
BREFCLK

CHBONDDONE

BREFCLK2

CHBONDO(3:0)
CONFIGOUT

CHBONDI(3:0)

RXBUFSTATUS(1:0)

CONFIGENABLE

RXCHARISCOMMA(3:0)

CONFIGIN

RXCHARISK(3:0)

ENCHANSYNC
ENMCOMMAALIGN

RXCHECKINGCRC

ENPCOMMAALIGN

RXCLKCORCNT(2:0)
RXCOMMADET

LOOPBACK(1:0)

RXCRCERR

POWERDOWN

RXDATA(31:0)

REFCLK
REFCLK2

RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)

REFCLKSEL
RXN

RXNOTINTABLE(3:0)

RXP

RXREALIGN

RXPOLARITY

RXRECCLK

RXRESET

RXRUNDISP(3:0)

RXUSRCLK

TXBUFERR

RXUSRCLK2

TXKERR(3:0)

TXBYPASS8B10B(3:0)

TXN

TXCHARDISPMODE(3:0)

TXP

TXCHARDISPVAL(3:0)

TXRUNDISP(3:0)

TXCHARISK(3:0)
TXDATA(31:0)
TXFORCECRCERR
TXINHIBIT
TXPOLARITY
TXRESET
TXUSRCLK
TXUSRCLK2
X9904

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

576

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ISE 6.3i

GT10_AURORA_n

GT10_AURORA_n
10-Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT10_AURORA_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro X but not for VirtexII or Virtex-II Pro.

This Xilinx protocol 10-gigabit transceiver supports 1, 2, and 4-byte data paths. The
letter n represents number of bytes of the data path. Valid values are 1, 2, or 4.
You can also set attributes for the primitives. For a description of these attributes and
their default attribute values, or to see a list the input and output ports for all values
of n and a description of each of the ports, see the RocketIO Transceiver User Guide.

Libraries Guide
ISE 6.3i

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577

GT10_AURORA_n

GT10_AURORA_1
CHBONDDONE

BREFCLKNIN
BREFCLKPIN

CHBONDO(4:0)

CHBONDI(4:0)
ENCHANSYNC

PMARXLOCK

ENMCOMMAALIGN
ENPCOMMAALIGN

RXBUFSTATUS(1:0)

LOOPBACK(1:0)
PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(0:0)

PMAREGDATAIN(7:0)
RXCHARISK(0:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(7:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(0:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(0:0)

RXDESCRAM64B66BUSE
RXIGNOREBTF

RXREALIGN

RXINTDATAWIDTH(1:0)
RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(0:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(0:0)

RXUSRCLK2
TXBYPASS8B10B(0:0)
TXCHARDISPMODE(0:0)

TXN

TXCHARDISPVAL(0:0)
TXCHARISK(0:0)

TXOUTCLK

TXDATA(7:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(0:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10045

578

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ISE 6.3i

GT10_AURORA_n

GT10_AURORA_2
CHBONDDONE

BREFCLKNIN
BREFCLKPIN

CHBONDO(4:0)

CHBONDI(4:0)
ENCHANSYNC

PMARXLOCK

ENMCOMMAALIGN
ENPCOMMAALIGN
LOOPBACK(1:0)

RXBUFSTATUS(1:0)

PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(1:0)

PMAREGDATAIN(7:0)
RXCHARISK(1:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(15:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(1:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(1:0)

RXDESCRAM64B66BUSE
RXIGNOREBTF

RXREALIGN

RXINTDATAWIDTH(1:0)
RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(0:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(1:0)

RXUSRCLK2
TXBYPASS8B10B(1:0)
TXCHARDISPMODE(1:0)

TXN

TXCHARDISPVAL(1:0)
TXCHARISK(1:0)

TXOUTCLK

TXDATA(15:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(1:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10046

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579

GT10_AURORA_n

GT10_AURORA_4
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
LOOPBACK(1:0)

RXBUFSTATUS(1:0)

PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(3:0)

PMAREGDATAIN(7:0)
PMAREGRW

RXCHARISK(3:0)

PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(31:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(3:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(3:0)

RXDESCRAM64B66BUSE
RXREALIGN

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(3:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(3:0)

RXUSRCLK2
TXBYPASS8B10B(3:0)
TXCHARDISPMODE(3:0)

TXN

TXCHARDISPVAL(3:0)
TXCHARISK(3:0)

TXOUTCLK

TXDATA(31:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(3:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10047

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Template

Use the Architecture Wizard in order to generate and instantiate these components.

580

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ISE 6.3i

GT10_AURORAX_n

GT10_AURORAX_n
10-Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT10_AURORAX_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

*Supported for Virtex-II Pro X but not for VirtexII or Virtex-II Pro.

This Xilinx protocol 10-gigabit transceiver supports 4 and 8-byte data paths. The letter
n represents number of bytes of the data path. Valid values are 4 or 8.
You can also set attributes for the primitives. For a description of these attributes and
their default attribute values, or to see a list the input and output ports for all values
of n and a description of each of the ports, see the RocketIO Transceiver User Guide.

Libraries Guide
ISE 6.3i

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1-800-255-7778

581

GT10_AURORAX_n

GT10_AURORAX_4
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
LOOPBACK(1:0)

RXBUFSTATUS(1:0)

PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(3:0)

PMAREGDATAIN(7:0)
PMAREGRW

RXCHARISK(3:0)

PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(31:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(3:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(3:0)

RXDESCRAM64B66BUSE
RXIGNOREBTF

RXREALIGN

RXINTDATAWIDTH(1:0)
RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(3:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(3:0)

RXUSRCLK2
TXBYPASS8B10B(3:0)
TXCHARDISPMODE(3:0)

TXN

TXCHARDISPVAL(3:0)
TXCHARISK(3:0)

TXOUTCLK

TXDATA(31:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(3:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10048

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ISE 6.3i

GT10_AURORAX_n

GT10_AURORAX_8
CHBONDDONE

BREFCLKNIN
BREFCLKPIN

CHBONDO(4:0)

CHBONDI(4:0)
ENCHANSYNC

PMARXLOCK

ENMCOMMAALIGN
ENPCOMMAALIGN
LOOPBACK(1:0)

RXBUFSTATUS(1:0)

PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(7:0)

PMAREGDATAIN(7:0)
RXCHARISK(7:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(63:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(7:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(7:0)

RXDESCRAM64B66BUSE
RXIGNOREBTF

RXREALIGN

RXINTDATAWIDTH(1:0)
RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(7:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(7:0)

RXUSRCLK2
TXBYPASS8B10B(7:0)
TXCHARDISPMODE(7:0)

TXN

TXCHARDISPVAL(7:0)
TXCHARISK(7:0)

TXOUTCLK

TXDATA(63:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(7:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10049

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583

GT10_AURORAX_n

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Template

Use the Architecture Wizard in order to generate and instantiate these components.

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ISE 6.3i

GT10_CUSTOM

GT10_CUSTOM
10-Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT10_CUSTOM
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro X but not for VirtexII or Virtex-II Pro.

This 10-gigabit transceiver is fully customizable. You can also set attributes for the
primitives. For a description of these attributes and their default attribute values, or to
see a list the input and output ports for all values of n and a description of each of the
ports, see the RocketIO Transceiver User Guide.

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585

GT10_CUSTOM

GT10_CUSTOM
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
RXBUFSTATUS(1:0)

LOOPBACK(1:0)
PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(7:0)

PMAREGDATAIN(7:0)
RXCHARISK(7:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(63:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(7:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(7:0)

RXDESCRAM64B66BUSE
RXREALIGN

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(7:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(7:0)

RXUSRCLK2
TXBYPASS8B10B(7:0)
TXCHARDISPMODE(7:0)

TXN

TXCHARDISPVAL(7:0)
TXOUTCLK

TXCHARISK(7:0)
TXDATA(63:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(7:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10050

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Template

Use the Architecture Wizard in order to generate and instantiate these components.

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ISE 6.3i

GT10_INFINIBAND_n

GT10_INFINIBAND_n
10-Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT10_INFINIBAND_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro X but not for VirtexII or Virtex-II Pro.

This Infiniband 10-gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n
represents number of bytes of the data path. Valid values are 1, 2 or 4.
You can also set attributes for the primitives. For a description of these attributes and
their default attribute values, or to see a list the input and output ports for all values
of n and a description of each of the ports, see the RocketIO Transceiver User Guide.

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587

GT10_INFINIBAND_n

GT10_INFINIBAND_1
CHBONDDONE

BREFCLKNIN
BREFCLKPIN

CHBONDO(4:0)

CHBONDI(4:0)
ENCHANSYNC

PMARXLOCK

ENMCOMMAALIGN
ENPCOMMAALIGN

RXBUFSTATUS(1:0)

LOOPBACK(1:0)
PMAINIT

RXCHARISCOMMA(0:0)

PMAREGADDR(5:0)
PMAREGDATAIN(7:0)

RXCHARISK(0:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(7:0)

REFCLKBSEL
REFCLKSEL
RXBLOCKSYNC64B66BUSE

RXDISPERR(0:0)

RXCOMMADETUSE
RXLOSSOFSYNC(1:0)

RXDATAWIDTH(1:0)
RXDEC64B66BUSE

RXNOTINTABLE(0:0)

RXDEC8B10BUSE
RXDESCRAM64B66BUSE

RXREALIGN

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(0:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(0:0)

RXUSRCLK2
TXBYPASS8B10B(0:0)

TXN

TXCHARDISPMODE(0:0)
TXCHARDISPVAL(0:0)

TXOUTCLK

TXCHARISK(0:0)
TXDATA(7:0)

TXP

TXDATAWIDTH(1:0)
TXENC64B66BUSE

TXRUNDISP(0:0)

TXENC8B10BUSE
TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2

X10051

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ISE 6.3i

GT10_INFINIBAND_n

GT10_INFINIBAND_2
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
LOOPBACK(1:0)

RXBUFSTATUS(1:0)

PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(1:0)

PMAREGDATAIN(7:0)
RXCHARISK(1:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(15:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(1:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(1:0)

RXDESCRAM64B66BUSE
RXREALIGN

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(1:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(1:0)

RXUSRCLK2
TXBYPASS8B10B(1:0)
TXCHARDISPMODE(1:0)

TXN

TXCHARDISPVAL(1:0)
TXCHARISK(1:0)

TXOUTCLK

TXDATA(15:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(1:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10052

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589

GT10_INFINIBAND_n

GT10_INFINIBAND_4
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
RXBUFSTATUS(1:0)

LOOPBACK(1:0)
PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(3:0)

PMAREGDATAIN(7:0)
RXCHARISK(3:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(31:0)

REFCLKBSEL
REFCLKSEL
RXBLOCKSYNC64B66BUSE

RXDISPERR(3:0)

RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXNOTINTABLE(3:0)

RXDEC8B10BUSE
RXDESCRAM64B66BUSE

RXREALIGN

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(3:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(3:0)

RXUSRCLK2
TXBYPASS8B10B(3:0)

TXN

TXCHARDISPMODE(3:0)
TXCHARDISPVAL(3:0)

TXOUTCLK

TXCHARISK(3:0)
TXDATA(31:0)

TXP

TXDATAWIDTH(1:0)
TXENC64B66BUSE

TXRUNDISP(3:0)

TXENC8B10BUSE
TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2

X10053

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

590

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Libraries Guide
ISE 6.3i

GT10_XAUI_n

GT10_XAUI_n
10-Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT10_XAUI_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro but not for Virtex-II or

Virtex-II Pro X.

This XAUI 10-gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n
represents number of bytes of the data path. Valid values are 1, 2 or 4.
You can also set attributes for the primitives. For a description of these attributes and
their default attribute values, or to see a list the input and output ports for all values
of n and a description of each of the ports, see the RocketIO Transceiver User Guide.

Libraries Guide
ISE 6.3i

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591

GT10_XAUI_n

GT10_XAUI_1
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
LOOPBACK(1:0)

RXBUFSTATUS(1:0)

PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(0:0)

PMAREGDATAIN(7:0)
RXCHARISK(0:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(7:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(0:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(0:0)

RXDESCRAM64B66BUSE
RXREALIGN

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(0:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(0:0)

RXUSRCLK2
TXBYPASS8B10B(0:0)
TXCHARDISPMODE(0:0)

TXN

TXCHARDISPVAL(0:0)
TXCHARISK(0:0)

TXOUTCLK

TXDATA(7:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(0:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10062

592

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ISE 6.3i

GT10_XAUI_n

GT10_XAUI_2
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
RXBUFSTATUS(1:0)

LOOPBACK(1:0)
PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(1:0)

PMAREGDATAIN(7:0)
RXCHARISK(1:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(15:0)

REFCLKBSEL
REFCLKSEL
RXBLOCKSYNC64B66BUSE

RXDISPERR(1:0)

RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(1:0)

RXDESCRAM64B66BUSE
RXREALIGN

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(1:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(1:0)

RXUSRCLK2
TXBYPASS8B10B(1:0)
TXCHARDISPMODE(1:0)

TXN

TXCHARDISPVAL(1:0)
TXOUTCLK

TXCHARISK(1:0)
TXDATA(15:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(1:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10063

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593

GT10_XAUI_n

GT10_XAUI_4
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
LOOPBACK(1:0)

RXBUFSTATUS(1:0)

PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(3:0)

PMAREGDATAIN(7:0)
RXCHARISK(3:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(31:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(3:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(3:0)

RXDESCRAM64B66BUSE
RXIGNOREBTF

RXREALIGN

RXINTDATAWIDTH(1:0)
RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(3:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(3:0)

RXUSRCLK2
TXBYPASS8B10B(3:0)
TXCHARDISPMODE(3:0)

TXN

TXCHARDISPVAL(3:0)
TXCHARISK(3:0)

TXOUTCLK

TXDATA(31:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(3:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10064

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

594

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ISE 6.3i

GT10_10GE_n

GT10_10GE_n
10-Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT10_10GE_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro X but not for Virtex-II or

Virtex-II Pro.

This Xilinx protocol 10-gigabit transceiver supports 4 and 8-byte data paths. The letter
n represents number of bytes of the data path. Valid values are 4 or 8.
You can also set attributes for the primitives. For a description of these attributes and
their default attribute values, or to see a list the input and output ports for all values
of n and a description of each of the ports, see the RocketIO Transceiver User Guide.

Libraries Guide
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595

GT10_10GE_n

GT10_10GE_4
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
LOOPBACK(1:0)

RXBUFSTATUS(1:0)

PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(3:0)

PMAREGDATAIN(7:0)
PMAREGRW

RXCHARISK(3:0)

PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(31:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(3:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(3:0)

RXDESCRAM64B66BUSE
RXREALIGN

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(3:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(3:0)

RXUSRCLK2
TXBYPASS8B10B(3:0)
TXCHARDISPMODE(3:0)

TXN

TXCHARDISPVAL(3:0)
TXCHARISK(3:0)

TXOUTCLK

TXDATA(31:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(3:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10041

596

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ISE 6.3i

GT10_10GE_n

GT10_10GE_8
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
RXBUFSTATUS(1:0)

LOOPBACK(1:0)
PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(7:0)

PMAREGDATAIN(7:0)
RXCHARISK(7:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(63:0)

REFCLKBSEL
REFCLKSEL
RXBLOCKSYNC64B66BUSE

RXDISPERR(7:0)

RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(7:0)

RXDESCRAM64B66BUSE
RXREALIGN

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(7:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(7:0)

RXUSRCLK2
TXBYPASS8B10B(7:0)

TXN

TXCHARDISPMODE(7:0)
TXCHARDISPVAL(7:0)

TXOUTCLK

TXCHARISK(7:0)
TXDATA(63:0)

TXP

TXDATAWIDTH(1:0)
TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(7:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10042

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597

GT10_10GE_n

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

598

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ISE 6.3i

GT10_10GFC_n

GT10_10GFC_n
10-Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT10_10GFC_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro X but not for Virtex-II or

Virtex-II Pro.

This Xilinx protocol 10-gigabit transceiver supports 4 and 8-byte data paths. The letter
n represents number of bytes of the data path. Valid values are 4 or 8.
You can also set attributes for the primitives. For a description of these attributes and
their default attribute values, or to see a list the input and output ports for all values
of n and a description of each of the ports, see the RocketIO Transceiver User Guide.

Libraries Guide
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599

GT10_10GFC_n

GT10_10GFC_4
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
LOOPBACK(1:0)

RXBUFSTATUS(1:0)

PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(3:0)

PMAREGDATAIN(7:0)
PMAREGRW

RXCHARISK(3:0)

PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(31:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(3:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(3:0)

RXDESCRAM64B66BUSE
RXREALIGN

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(3:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(3:0)

RXUSRCLK2
TXBYPASS8B10B(3:0)
TXCHARDISPMODE(3:0)

TXN

TXCHARDISPVAL(3:0)
TXOUTCLK

TXCHARISK(3:0)
TXDATA(31:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(3:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10043

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ISE 6.3i

GT10_10GFC_n

GT10_10GFC_8
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
LOOPBACK(1:0)

RXBUFSTATUS(1:0)

PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(7:0)

PMAREGDATAIN(7:0)
PMAREGRW

RXCHARISK(7:0)

PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(63:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(7:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(7:0)

RXDESCRAM64B66BUSE
RXIGNOREBTF

RXREALIGN

RXINTDATAWIDTH(1:0)
RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(7:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(7:0)

RXUSRCLK2
TXBYPASS8B10B(7:0)
TXCHARDISPMODE(7:0)

TXN

TXCHARDISPVAL(7:0)
TXCHARISK(7:0)

TXOUTCLK

TXDATA(63:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(7:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10044

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601

GT10_10GFC_n

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

602

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ISE 6.3i

GT10_OC48_n

GT10_OC48_n
10-Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT10_OC48_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro X but not for Virtex-II

or Virtex-II Pro.

This Xilinx protocol 10-gigabit transceiver supports 1, 2 and 4-byte data paths. The
letter n represents number of bytes of the data path. Valid values are 1, 2, or 4.
You can also set attributes for the primitives. For a description of these attributes and
their default attribute values, or to see a list the input and output ports for all values
of n and a description of each of the ports, see the RocketIO X Transceiver User Guide.

Libraries Guide
ISE 6.3i

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603

GT10_OC48_n

GT10_OC48_1
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
RXBUFSTATUS(1:0)

LOOPBACK(1:0)
PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(0:0)

PMAREGDATAIN(7:0)
PMAREGRW

RXCHARISK(0:0)

PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2
REFCLKBSEL

RXDATA(7:0)

REFCLKSEL
RXBLOCKSYNC64B66BUSE

RXDISPERR(0:0)

RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(0:0)

RXDESCRAM64B66BUSE
RXIGNOREBTF

RXREALIGN

RXINTDATAWIDTH(1:0)
RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(0:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK
RXUSRCLK2

TXKERR(0:0)

TXBYPASS8B10B(0:0)
TXCHARDISPMODE(0:0)

TXN

TXCHARDISPVAL(0:0)
TXCHARISK(0:0)

TXOUTCLK

TXDATA(7:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(0:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10056

604

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ISE 6.3i

GT10_OC48_n

GT10_OC48_2
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
RXBUFSTATUS(1:0)

LOOPBACK(1:0)
PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(1:0)

PMAREGDATAIN(7:0)
RXCHARISK(1:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(15:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(1:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(1:0)

RXDESCRAM64B66BUSE
RXIGNOREBTF

RXREALIGN

RXINTDATAWIDTH(1:0)
RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(1:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(1:0)

RXUSRCLK2
TXBYPASS8B10B(1:0)
TXCHARDISPMODE(1:0)

TXN

TXCHARDISPVAL(1:0)
TXCHARISK(1:0)

TXOUTCLK

TXDATA(15:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(1:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10057

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605

GT10_OC48_n

GT10_OC48_4
CHBONDDONE

BREFCLKNIN
BREFCLKPIN

CHBONDO(4:0)

CHBONDI(4:0)
ENCHANSYNC

PMARXLOCK

ENMCOMMAALIGN
ENPCOMMAALIGN

RXBUFSTATUS(1:0)

LOOPBACK(1:0)
PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(3:0)

PMAREGDATAIN(7:0)
RXCHARISK(3:0)

PMAREGRW
PMAREGSTROBE

RXCLKCORCNT(2:0)

PMARXLOCKSEL(1:0)
POWERDOWN

RXCOMMADET

REFCLK
REFCLK2

RXDATA(31:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(3:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(3:0)

RXDESCRAM64B66BUSE
RXIGNOREBTF

RXREALIGN

RXINTDATAWIDTH(1:0)
RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(3:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK
RXUSRCLK2

TXKERR(3:0)

TXBYPASS8B10B(3:0)
TXCHARDISPMODE(3:0)

TXN

TXCHARDISPVAL(3:0)
TXCHARISK(3:0)

TXOUTCLK

TXDATA(31:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(3:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10058

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

606

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ISE 6.3i

GT10_OC192_n

GT10_OC192_n
10-Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT10_OC192_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro X but not for Virtex-II

or Virtex-II Pro.

This Xilinx protocol 10-gigabit transceiver supports 4 and 8-byte data paths. The letter
n represents number of bytes of the data path. Valid values are 4 or 8.
You can also set attributes for the primitives. See the RocketIO X Transceiver User Guide
for a description of these attributes and their default attribute values.
The following figures list the input and output ports for all values of n. For a
description of each of the ports, see the RocketIO X Transceiver User Guide.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

607

GT10_OC192_n

GT10_OC192_4
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
LOOPBACK(1:0)

RXBUFSTATUS(1:0)

PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(3:0)

PMAREGDATAIN(7:0)
PMAREGRW

RXCHARISK(3:0)

PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLKBSEL
RXBLOCKSYNC64B66BUSE

RXDATA(31:0)

RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXDISPERR(3:0)

RXDEC64B66BUSE
RXDEC8B10BUSE
RXDESCRAM64B66BUSE

RXLOSSOFSYNC(1:0)

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXNOTINTABLE(3:0)

RXN
RXREALIGN

RXP
RXPOLARITY
RXRESET

RXRECCLK

RXSLIDE
RXUSRCLK

RXRUNDISP(3:0)

RXUSRCLK2
TXBYPASS8B10B(3:0)

TXBUFERR

TXCHARDISPMODE(3:0)
TXCHARDISPVAL(3:0)

TXKERR(3:0)

TXCHARISK(3:0)
TXN

TXDATA(31:0)
TXDATAWIDTH(1:0)
TXENC64B66BUSE

TXOUTCLK

TXENC8B10BUSE
TXGEARBOX64B66BUSE

TXP

TXINHIBIT
TXINTDATAWIDTH(1:0)

TXRUNDISP(3:0)

TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10054

608

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ISE 6.3i

GT10_OC192_n

GT10_OC192_8
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
RXBUFSTATUS(1:0)

LOOPBACK(1:0)
PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(7:0)

PMAREGDATAIN(7:0)
RXCHARISK(7:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLKBSEL
RXBLOCKSYNC64B66BUSE

RXDATA(63:0)

RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXDISPERR(7:0)

RXDEC64B66BUSE
RXDEC8B10BUSE
RXDESCRAM64B66BUSE

RXLOSSOFSYNC(1:0)

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXNOTINTABLE(7:0)

RXN
RXREALIGN

RXP
RXPOLARITY
RXRESET

RXRECCLK

RXSLIDE
RXUSRCLK

RXRUNDISP(7:0)

RXUSRCLK2
TXBYPASS8B10B(7:0)

TXBUFERR

TXCHARDISPMODE(7:0)
TXCHARDISPVAL(7:0)

TXKERR(7:0)

TXCHARISK(7:0)
TXN

TXDATA(63:0)
TXDATAWIDTH(1:0)
TXENC64B66BUSE

TXOUTCLK

TXENC8B10BUSE
TXGEARBOX64B66BUSE

TXP

TXINHIBIT
TXINTDATAWIDTH(1:0)

TXRUNDISP(7:0)

TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10055

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609

GT10_OC192_n

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

610

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ISE 6.3i

GT10_PCI_EXPRESS_n

GT10_PCI_EXPRESS_n
10-Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT10_PCI_EXPRESS_n
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

*Supported for Virtex-II Pro X but not for Virtex-II or

Virtex-II Pro.

This Xilinx protocol 10-gigabit transceiver supports 1, 2 and 4-byte data paths. The
letter n represents number of bytes of the data path. Valid values are 1, 2, or 4.
You can also set attributes for the primitives. See the RocketIO X Transceiver User Guide
for a description of these attributes and their default attribute values.
The following figures list the input and output ports for all values of n. For a
description of each of the ports, see the RocketIO X Transceiver User Guide.

Libraries Guide
ISE 6.3i

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611

GT10_PCI_EXPRESS_n

GT10_PCI_EXPRESS_1
CHBONDDONE

BREFCLKNIN
BREFCLKPIN

CHBONDO(4:0)

CHBONDI(4:0)
ENCHANSYNC

PMARXLOCK

ENMCOMMAALIGN
ENPCOMMAALIGN

RXBUFSTATUS(1:0)

LOOPBACK(1:0)
PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(0:0)

PMAREGDATAIN(7:0)
RXCHARISK(0:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(7:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(0:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(0:0)

RXDESCRAM64B66BUSE
RXIGNOREBTF

RXREALIGN

RXINTDATAWIDTH(1:0)
RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(0:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK
RXUSRCLK2

TXKERR(0:0)

TXBYPASS8B10B(0:0)
TXCHARDISPMODE(0:0)

TXN

TXCHARDISPVAL(0:0)
TXCHARISK(0:0)

TXOUTCLK

TXDATA(7:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(0:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10059

612

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ISE 6.3i

GT10_PCI_EXPRESS_n

GT10_PCI_EXPRESS_2
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
LOOPBACK(1:0)

RXBUFSTATUS(1:0)

PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(1:0)

PMAREGDATAIN(7:0)
PMAREGRW

RXCHARISK(1:0)

PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(15:0)

REFCLKBSEL
REFCLKSEL
RXBLOCKSYNC64B66BUSE

RXDISPERR(1:0)

RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(1:0)

RXDESCRAM64B66BUSE
RXREALIGN

RXIGNOREBTF
RXINTDATAWIDTH(1:0)

RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(1:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK

TXKERR(1:0)

RXUSRCLK2
TXBYPASS8B10B(1:0)

TXN

TXCHARDISPMODE(1:0)
TXCHARDISPVAL(1:0)

TXOUTCLK

TXCHARISK(1:0)
TXDATA(15:0)

TXP

TXDATAWIDTH(1:0)
TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(1:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10060

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613

GT10_PCI_EXPRESS_n

GT10_PCI_EXPRESS_4
CHBONDDONE

BREFCLKNIN
BREFCLKPIN
CHBONDI(4:0)

CHBONDO(4:0)

ENCHANSYNC
ENMCOMMAALIGN

PMARXLOCK

ENPCOMMAALIGN
RXBUFSTATUS(1:0)

LOOPBACK(1:0)
PMAINIT
PMAREGADDR(5:0)

RXCHARISCOMMA(3:0)

PMAREGDATAIN(7:0)
RXCHARISK(3:0)

PMAREGRW
PMAREGSTROBE
PMARXLOCKSEL(1:0)

RXCLKCORCNT(2:0)

POWERDOWN
RXCOMMADET

REFCLK
REFCLK2

RXDATA(31:0)

REFCLKBSEL
REFCLKSEL

RXDISPERR(3:0)

RXBLOCKSYNC64B66BUSE
RXCOMMADETUSE
RXDATAWIDTH(1:0)

RXLOSSOFSYNC(1:0)

RXDEC64B66BUSE
RXDEC8B10BUSE

RXNOTINTABLE(3:0)

RXDESCRAM64B66BUSE
RXIGNOREBTF

RXREALIGN

RXINTDATAWIDTH(1:0)
RXRECCLK

RXN
RXP
RXPOLARITY

RXRUNDISP(3:0)

RXRESET
TXBUFERR

RXSLIDE
RXUSRCLK
RXUSRCLK2

TXKERR(3:0)

TXBYPASS8B10B(3:0)
TXCHARDISPMODE(3:0)

TXN

TXCHARDISPVAL(3:0)
TXCHARISK(3:0)

TXOUTCLK

TXDATA(31:0)
TXDATAWIDTH(1:0)

TXP

TXENC64B66BUSE
TXENC8B10BUSE

TXRUNDISP(3:0)

TXGEARBOX64B66BUSE
TXINHIBIT
TXINTDATAWIDTH(1:0)
TXPOLARITY
TXRESET
TXSCRAM64B66BUSE
TXUSRCLK
TXUSRCLK2
X10061

Usage
This design element is instantiated rather than inferred in the design code.
VHDL Start

VHDL Instantiation Templates

Use the Architecture Wizard in order to generate and instantiate these components.

614

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ISE 6.3i

IBUF, 4, 8, 16

IBUF, 4, 8, 16
Single- and Multiple-Input Buffers
IBUF
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive
IBUF4

Spartan-II, Spartan-IIE

Macro

Spartan-3

No

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro
IBUF8, IBUF16

Spartan-II, Spartan-IIE

Macro

Spartan-3

No

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

IBUF
I

O
X9442

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

IBUF, IBUF4, IBUF8, and IBUF16 are single- and multiple-input buffers. An IBUF
isolates the internal circuit from the signals coming into a chip. IBUFs are contained in
input/output blocks (IOBs). IBUF inputs (I) are connected to an IPAD or an IOPAD.
IBUF outputs (O) are connected to the internal circuit.

IBUF4
I0

O0

I1

O1

I2

O2

I3

O3
X9443

Libraries Guide
ISE 6.3i

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615

IBUF, 4, 8, 16

O[7:0]

IBUF8

IO
I1
I2

X3803

I3
I4

IBUF16
I5
I6

X3815
I7
I[7:0]

O0
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF

O1
O2
O3
O4
O5
O6
O7

IBUF
X7652

IBUF8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II,

Spartan-II, Spartan-II E, Virtex, Virtex-E
O[7:0]

I0

O0
IBUF

I1

O1
IBUF

I2

O2
IBUF

I3

O3
IBUF

I4

O4
IBUF

I5

O5
IBUF

I6

O6
IBUF

I7

O7
IBUF

I[7:0]
X9839

IBUF8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

616

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Libraries Guide
ISE 6.3i

IBUF, 4, 8, 16

Available Attributes
Spartan-II, Spartan-IIE, Virtex, and Virtex-E and IOSTANDARD Attributes
Architectures

Attribute Values

Spartan-II,
Virtex

Spartan-IIE,
Virtex-E

Termination
Type Input

VREF

Input VCCO

AGP

None

1.32

No

CTT

None

1.50

No

GTL

None

0.80

No

GTLP

None

1.00

No

HSTL_I

None

0.75

No

HSTL_III

None

0.90

1.5

HSTL_IV

None

0.90

No

LVCMOS2

None

No

2.5

LVCMOS18

None

No

1.8

LVDS

None

No

No

IOSTANDARD

None

No

No

LVTTL (default)

None

No

3.3

PCI33_3

None

No

3.3

PCI33_5

None

No

No

PCI66_3

LVPECL

PCIX66_3

None

No

3.3

None

No

3.3

SSTL2_I

None

1.25

No

SSTL2_II

None

1.25

No

SSTL3_I

None

1.50

No

SSTL3_II

None

1.50

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X IOSTANDARD Attributes

Architectures
IOSTANDARD

Virtex-II

Attribute Values

Virtex-II Pro,
Virtex-II Pro X

Termination
Type Input

VREF
Input*

Input
VCCO

AGP

None

1.32

No

GTL

None

0.80

No

GTL_DCI

Single

0.80

1.2

GTLP

None

1.00

No

GTLP_DCI

Single

1.00

1.5

HSTL_I

None

0..75

No

HSTL_I_18

None

0.9

No

HSTL_I_DCI

Split

0.75

1.5

HSTL_I_DCI_18

Split

0.9

1.8

HSTL_II

None

0.75

No

HSTL_II_18

None

0.9

No

Libraries Guide
ISE 6.3i

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617

IBUF, 4, 8, 16

Virtex-II, Virtex-II Pro, Virtex-II Pro X IOSTANDARD Attributes

Architectures

Attribute Values

Virtex-II

Virtex-II Pro,
Virtex-II Pro X

Termination
Type Input

VREF
Input*

Input
VCCO

HSTL_II_DCI

Split

0.75

1.5

HSTL_II_DCI_18

Split

0.9

1.8

HSTL_III

None

0.90

No

HSTL_III_18

None

1.10

No

HSTL_III_DCI

Single

0.90

1.5

HSTL_III_DCI_18

Single

1.10

1.8

HSTL_IV

None

0.90

No

HSTL_IV_18

None

1.10

No

HSTL_IV_DCI

Single

0.90

1.5

HSTL_IV_DCI_18

Single

1.10

1.8

None

No

1.2

IOSTANDARD

LVCMOS12
LVCMOS15

None

No

1.5

LVCMOS18

None

No

1.8

LVCMOS25

None

No

2.5

LVCMOS33

None

No

3.3

LVDCI_15

None

No

1.5

LVDCI_18

None

No

1.8

LVDCI_25

None

No

2.5

LVDCI_33

None

No

3.3

LVDCI_DV2_15

None

No

1.5

LVDCI_DV2_18

None

No

1.8

LVDCI_DV2_25

None

No

2.5

LVDCI_DV2_33

None

No

3.3

LVTTL (default)

None

No

3.3

PCI33_3

None

No

3.3

PCI66_3

None

No

3.3

PCIX

None

No

3.3

SSTL18_I

None

0.9

No

SSTL18_I_DCI

Split

0.9

1.8

SSTL18_II

None

0.9

No

SSTL18_II_DCI

Split

0.9

1.8

SSTL2_I

None

1.25

No

SSTL2_I_DCI

Split

1.25

2.5

SSTL2_II

None

1.25

No

SSTL2_II_DCI

Split

1.25

2.5

SSTL3_I

None

1.50

No

SSTL3_I_DCI

Split

1.50

3.3

SSTL3_II

None

1.50

No

618

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Libraries Guide
ISE 6.3i

IBUF, 4, 8, 16

Virtex-II, Virtex-II Pro, Virtex-II Pro X IOSTANDARD Attributes

Architectures
IOSTANDARD

Virtex-II

Virtex-II Pro,
Virtex-II Pro X

Attribute Values
Termination
Type Input

VREF
Input*

Input
VCCO

Split

1.50

3.3

SSTL3_II_DCI

* VREF requirement when this IOSTANDARD is an input.

Usage Rules
The Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro
X architectures include a versatile interface to multiple voltage and drive standards.
To select an I/O standard, you must choose the appropriate component from the
library or add an IOSTANDARD attribute to the appropriate buffer component. For
example, for an input buffer that uses the GTL standard, you would choose the
IBUF_GTL component or choose the IBUF component and attach the
IOSTANDARD=GTL attribute to it.
See the following sections for information on the various input/output buffer
components and attributes available to implement the desired standard:

IBUFG

IOBUF

OBUF, 4, 8, 16

OBUFT, 4, 8, 16

The hardware implementation of the various I/O standards requires that certain
usage rules be followed. Each I/O standard has voltage source requirements for input
reference (VREF), output drive (VCCO), or both. In addition,Virtex-II, Virtex-II Pro,
and Virtex-II Pro X have terminate type requirements. Each Spartan-II, Spartan-IIE,
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X device has eight banks
(two on each edge). Each bank has voltage sources shared by all I/O in the bank.
Therefore, in a particular bank, the voltage source (for either input or output) must be
of the same type.

For Spartan-II, Spartan-IIE, Virtex, and Virtex-E, see Virtex, Virtex-E, Spartan-II,
and Spartan-IIE Banking Rules below. Virtex-E follows the same banking rules as
Virtex with a few additions.

See Additional Banking Rules for Virtex-E and Spartan-IIE below for the
additional Virtex-E rules. Virtex-II, Virtex-II Pro, and Virtex-II Pro X have their
own set of banking rules.

See Virtex-II, Virtex-II Pro, Virtex-II Pro X Banking Rules below for Virtex-II,
Virtex-II Pro, and Virtex-II Pro X rules.

Virtex, Virtex-E, Spartan-II, and Spartan-IIE Banking Rules

The hardware implementation of the various I/O standards requires that certain
usage rules be followed. As shown in the following table, each I/O standard has
voltage source requirements for input reference (VREF), output drive (VCCO), or
both. Each Spartan-II, Spartan-IIE, Virtex, and Virtex-E device has eight banks (two on
each edge). Each bank has voltage sources shared by all I/O in the bank. Therefore, in
a particular bank, the voltage source (for either input or output) must be of the same

Libraries Guide
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619

IBUF, 4, 8, 16

type. The Input Banking (VREF) Rules section and the Output Banking (VCCO) Rules
section below summarize the component usage rules based on the hardware
implementation.
I/O Standards Supported in Virtex, Virtex-E, Spartan-II, and Spartan-IIE
I/O Standard

Application

Description

Output
VCCO

Input
VCCO

VREF

3.3

No

1.32

AGP

Graphics

Advanced graphics port

CTT

Memory

Center tap terminated

3.3

No

1.50

LVTTL

General Purpose

Low voltage transistor-transistor logic

3.3

3.3*

No

LVCMOS2

General Purpose

Low voltage complementary metaloxide semiconductor

2.5

2.5*

No

PCI33_3

PCI

Peripheral component interface

(33MHz 3.3V)

3.3

3.3*

No

PCI33_5

PCI

Peripheral component interface

(33MHZ 5.0V)

3.3

No

No

PCI33_5 is not supported for Virtex-E

or Spartan-IIE.
PCI66_3

PCI

Peripheral component interface

(66MHz 3.3V)

3.3

3.3*

No

GTL

Backplane

Gunning transceiver logic interface (to

processors or backplane driver)

No

No

0.80

GTL+ (GTLP)

Backplane

Gunning transceiver logic interface

Plus

No

No

1.00

HSTL_I

Hitachi SRAM

High Speed transceiver logic

1.5

No

0.75

HSTL_III

Hitachi SRAM

High Speed transceiver logic

1.5

No

0.90

HSTL_IV

Hitachi SRAM

High Speed transceiver logic

1.5

No

0.90

SSTL2_I

Synchronous DRAM

Stub-series terminated logic interface

for SDRAM

2.5

No

1.25

SSTL2_II

Synchronous DRAM

Stub-series terminated logic interface

for SDRAM

2.5

No

1.25

SSTL3_I

Synchronous DRAM

Stub-series terminated logic interface

for SDRAM

3.3

No

1.50

SSTL3_II

Synchronous DRAM

Stub-series terminated logic interface

for SDRAM

3.3

No

1.50

*Only LVTTL, LVCMOS, and PCI need Input VCCO in Virtex-E and Spartan-IIE parts.

Input Banking (VREF) Rules

The low-voltage I/O standards that have a differential amplifier input require a
voltage reference input (VREF). The VREF voltage source is provided as an external
signal to the chip.

620

Any input buffer component that does not require a VREF source (LVTTL,
LVCMOS2, PCI) can be placed in any bank.

All input buffer components that require a VREF source (GTL*, HSTL*, SSTL*,
CTT, AGP) must be of the same I/O standard in a particular bank. For example,
IBUF with I/O standard (SSTL2_I) and IBUFG with I/O standard (SSTL2_I) are
compatible since they are the same I/O standard.

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IBUF, 4, 8, 16

If the bank contains any input buffer component that requires a VREF source, the
following conditions apply.

One or more VREF sources must be connected to the bank via an IOB.

The number of VREF sources is dependent on the device and package.

The locations of the VREF sources are fixed for each device/package.

All VREF sources must be used in that bank.

If the bank contains no input buffer component that requires a VREF source, the
IOBs for VREF sources can be used for general I/O.

Output buffer components of any type can be placed in the bank.

Output Banking (VCCO) Rules

Because Virtex, Virtex-E, Spartan-II, and Spartan-IIE have multiple low-voltage
standards, some control is required over the distribution of VCCO, the drive source
voltage for output pins. To provide for maximum flexibility, the output pins are
banked. In comparison to the VREF sources described above, the VCCO voltage
sources are dedicated pins on the device and do not consume valuable IOBs.

Any output buffer component that does not require a VCCO source (GTL, GTL+)
can be placed in any bank.

To be placed in a particular bank, all output buffer components that require

VCCO must have the same supply voltage (VCCO). For example, OBUF with I/O
standard (SSTL3_I) and OBUF with I/O standard (PCI33_3) are compatible in the
same output bank since VCCO=3.3 for both.

Input buffer components of any type can be placed in the bank.

The configuration pins on a Virtex, Virtex-E, Spartan-II, and Spartan-IIE device

are on the right side of the chip. When configuring the device through a serial
ProM, the user is required to use a VCCO of 3.3V in the two banks on the right
hand side of the chip. If the user is not configuring the device through a serial
ProM, the VCCO requirement is dependent upon the configuration source.

Banking Rules for KEEPER

If a KEEPER symbol is attached to a component (3-state output buffer) for an I/O
standard that requires a VREF (for example, OBUFT with I/O standard (GTL),
OBUFT with I/O standard (SSTL3_I)), the KEEPER element requires that the VREF be
properly driven.

Additional Banking Rules for Virtex-E and Spartan-IIE

The Virtex-E and Spartan-IIE architectures requires the same banking rules as
described in the Virtex, Virtex-E, Spartan-II, and Spartan-IIE Banking Rules section.
Additional I/O standards are supported as indicated in the following table.
Additional I/O Standards Supported in Virtex-E and Spartan-IIE
I/O Standard

Application

Description

Output
VCCO

Input
VCCO

VREF

1.8

1.8

No

Single Ended:
LVCMOS18

Libraries Guide
ISE 6.3i

General Purpose

Low voltage complementary metaloxide semiconductor

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621

IBUF, 4, 8, 16

Additional I/O Standards Supported in Virtex-E and Spartan-IIE

I/O Standard

Application

Description

Output
VCCO

Input
VCCO

VREF

2.5

2.5

No

2.5

2.5

No

Differential Signaling:
LVDS

Point-to-point or multi-drop
backplanes, high noise
immunity

Low voltage differential signal

LVPECL

High performance clocking,

Low voltage positive emitter couple
backplanes, differential
logic
100MHz+ clocking, optical
transceiver, high speed
networking and mixed-signal
interfacing

Virtex-II, Virtex-II Pro, Virtex-II Pro X Banking Rules

The hardware implementation of the various I/O standards requires that certain
usage rules be followed. Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices have eight
banks (two on each edge), numbered from 0 through 7. Each bank has voltage sources
shared by all I/O in the bank.
The following table describes each I/O standard.
Descriptions of I/O Standards Supported In Virtex-II, Virtex-II Pro, and Virtex-II Pro X
I/O Standard

Application

Description

Single-Ended:
AGPb

Graphics

Advanced graphics port

GTL

Memory

Gunning transceiver logic interface (to processors or backplace driver)

GTL_DCI

Memory

Gunning transceiver logic interface with on-chip Digital Controlled Impedance

GTL+ (GTLP)

Memory

Gunning transceiver logic interface Plus

GTLP_DCI

Memory

Gunning transceiver logic interface with on-chip Digital Controlled Impedance

HSTL_I

Hitachi SRAM

High Speed transceiver logic

HSTL_I_18

Hitachi SRAM

High Speed transceiver logic

HSTL_I__DCI

Hitachi SRAM

High Speed transceiver logic interface with on-chip Digital Controlled

Impedance

HSTL_I__DCI_18

Hitachi SRAM

High Speed transceiver logic interface with on-chip Digital Controlled

Impedance

HSTL_II

Hitachi SRAM

High Speed transceiver logic

HSTL_II_18

Hitachi SRAM

High Speed transceiver logic

HSTL_II__DCI

Hitachi SRAM

High Speed transceiver logic interface with on-chip Digital Controlled

Impedance

HSTL_II__DCI_18

Hitachi SRAM

High Speed transceiver logic interface with on-chip Digital Controlled

Impedance

HSTL_III

Hitachi SRAM

High Speed transceiver logic

HSTL_III_18

Hitachi SRAM

High Speed transceiver logic

HSTL_III__DCI

Hitachi SRAM

High Speed transceiver logic interface with on-chip Digital Controlled

Impedance

622

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Libraries Guide
ISE 6.3i

IBUF, 4, 8, 16

Descriptions of I/O Standards Supported In Virtex-II, Virtex-II Pro, and Virtex-II Pro X
I/O Standard

Application

Description

HSTL_III__DCI_18

Hitachi SRAM

High Speed transceiver logic interface with on-chip Digital Controlled

Impedance

HSTL_IV

Hitachi SRAM

High Speed transceiver logic

HSTL_IV_18

Hitachi SRAM

High Speed transceiver logic

HSTL_IV__DCI

Hitachi SRAM

High Speed transceiver logic interface with on-chip Digital Controlled

Impedance

HSTL_IV__DCI_18

Hitachi SRAM

High Speed transceiver logic interface with on-chip Digital Controlled

Impedance

LVCMOS12a

General Purpose

Low voltage complementary metal-oxide semiconductor

LVCMOS15a

General Purpose

Low voltage complementary metal-oxide semiconductor

LVCMOS18a

General Purpose

Low voltage complementary metal-oxide semiconductor

LVCMOS25a

General Purpose

Low voltage complementary metal-oxide semiconductor

LVCMOS33a

General Purpose

Low voltage complementary metal-oxide semiconductor

LVDCI_15

General Purpose

Low voltage complementary metal-oxide semiconductor with on-chip Digital

Controlled Impedance

LVDCI_18

General Purpose

Low voltage complementary metal-oxide semiconductor with on-chip Digital

Controlled Impedance

LVDCI_25

General Purpose

Low voltage complementary metal-oxide semiconductor with on-chip Digital

Controlled Impedance

LVDCI_33

General Purpose

Low voltage complementary metal-oxide semiconductor with on-chip Digital

Controlled Impedance

LVDCI_DV2_15

General Purpose

Low voltage complementary metal-oxide semiconductor with on-chip Digital

Controlled Impedance

LVDCI_DV2_18

General Purpose

Low voltage complementary metal-oxide semiconductor with on-chip Digital

Controlled Impedance

LVDCI_DV2_25

General Purpose

Low voltage complementary metal-oxide semiconductor with on-chip Digital

Controlled Impedance

LVDCI_DV2_33

General Purpose

Low voltage complementary metal-oxide semiconductor with on-chip Digital

Controlled Impedance

LVTTLa

General Purpose

Low voltage transistor-transistor logic

PCI33_3

PCI

Peripheral component interface (33MHz 3.3V)

PCI66_3

PCI

Peripheral component interface (66MHz 3.3V)

PCIX

PCI

Peripheral component interface

SSTL18_I

Synchronous DRAM Stub-series terminated logic interface for SDRAM

SSTL18_I_DCI

Synchronous DRAM Stub-series terminated logic interface for SDRAM with on-chip Digital
Controlled Impedance

SSTL18_II

Synchronous DRAM Stub-series terminated logic interface for SDRAM

SSTL18_II_DCI

Synchronous DRAM Stub-series terminated logic interface for SDRAM with on-chip Digital
Controlled Impedance

SSTL2_I

Synchronous DRAM Stub-series terminated logic interface for SDRAM

SSTL2_I_DCI

Synchronous DRAM Stub-series terminated logic interface for SDRAM with on-chip Digital
Controlled Impedance

SSTL2_II

Synchronous DRAM Stub-series terminated logic interface for SDRAM

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623

IBUF, 4, 8, 16

Descriptions of I/O Standards Supported In Virtex-II, Virtex-II Pro, and Virtex-II Pro X
I/O Standard

Application

Description

SSTL2_II_DCI

Synchronous DRAM Stub-series terminated logic interface for SDRAM with on-chip Digital
Controlled Impedance

SSTL3_I

Synchronous DRAM Stub-series terminated logic interface for SDRAM

SSTL3_I_DCI

Synchronous DRAM Stub-series terminated logic interface for SDRAM with on-chip Digital
Controlled Impedance

SSTL3_II

Synchronous DRAM Stub-series terminated logic interface for SDRAM

SSTL3_II_DCI

Synchronous DRAM Stub-series terminated logic interface for SDRAM with on-chip Digital
Controlled Impedance

Notes:
a LVTTL, LVCMOS15, LVCMOS18, and LVCMOS25 also require DRIVE and SLEW (FAST or Slow) attributes.
b Supported for Virtex-II only

The following rules apply for using the various IO standards with Virtex-II, Virtex-II
Pro, or Virtex-II Pro X:

In any particular Virtex-II, Virtex-II Pro, or Virtex-II Pro X I/O bank, the voltage
sources (both input and output) must be compatible. That is, they must have
either the same voltage or an undefined (No) voltage.

VREF, VCCO input, and VCCO output must be compatible within an I/O bank.

In addition, to VREF and VCCO compatibility, the terminate type I/O standards
must be compatible within the bank.
For terminate type compatibility, the following rules apply:

Only one I/O buffer with terminate type of SINGLE can be in a particular
bank.

Only one I/O buffer with terminate type of SPLIT can be in a particular bank.

Multiple I/O buffers with NONE and DRIVER terminate types can be in a
particular bank.

SPLIT and SINGLE can co-exist in the same bank.

NONE and DRIVER types can co-exist with SPLIT and SINGLE types.

The bottom edge of a Virtex-II Pro, or Virtex-II Pro X device is set for 3.3V.
Therefore, on the bottom edge of the device, VCCO output and VCCO input must
be 3.3V or No.

To place an I/O buffer that requires a VREF in a bank, the reserved VREF sites in
that bank must be empty.

To place an I/O buffer that has a terminate type of SINGLE, SPLIT, or DRIVER in
a bank, the reserved VREF sites in that bank must be empty.

For Virtex-II, Virtex-II Pro, and Virtex-II Pro X, differential signaling standards
apply to IBUFDS, IBUFGDS, IBUFGDS_DIFF_OUT, OBUFDS, and OBUFTDS
only (not IBUF or OBUF).

The following table summarizes the values that you need to check for compatibility
for each combination of I/O buffer programming (input, output, or bidirectional
buffer). For example, the table shows that if you configure an output buffer as
LVCMOS25, which has an output voltage of 2.5V, and an input buffer as LVCMOS15,

624

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ISE 6.3i

IBUF, 4, 8, 16

which as an input voltage of 1.5V, the Out/In Voltage is checked. Because they have
different voltages, this combination would not be allowed in a particular I/O bank.
IOB Programming Combinations

VREF

Input

Input

Check

Input

Output

Output VCCO

Input VCCO

Out/In Voltage

Check
Check

Input

Bidirectional

Output

Input

Check

Check

Output

Output

Check

Output

Bidirectional

Check

Bidirectional

Input

Bidirectional

Output

Bidirectional

Bidirectional

Check
Check

Check

Check
Check

Check
Check

Check

Check
Check

Check

Check

Usage
IBUFs are typically inferred for all top level input ports, but they can also be
instantiated if necessary.

VHDL Instantiation Template

-- Component Declaration for IBUF should be placed
-- after architecture statement but before begin keyword
component IBUF
-- synthesis translate_off
generic (
IOSTANDARD: bit_vector := "LVTTL");
-- synthesis translate_on
port (O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for IBUF
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here
attribute IOSTANDARD : string;
attribute IOSTANDARD of IBUF_instance_name : label is "LVTTL";
-- Component Instantiation for IBUF should be placed
-- in architecture after the begin keyword
IBUF_INSTANCE_NAME : IBUF
-- synthesis translate_off
generic map (
IOSTANDARD => string_value)
-- synthesis translate_on
port map (O => user_O,
I => user_I);

Libraries Guide
ISE 6.3i

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625

IBUF, 4, 8, 16

Verilog Instantiation Template

IBUF instance_name (.O (user_O),
.I (user_I));
defparam IBUF_instance_name.IOSTANDARD = string_value;

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Libraries Guide
ISE 6.3i

IBUFDS

IBUFDS
Differential Signaling Input Buffer with Selectable I/O Interface
Architectures Supported
IBUFDS
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I
IB

No

CoolRunner XPLA3

No

CoolRunner-II

No

IBUFDS is an input buffer that supports low-voltage, differential signaling. In

IBUFDS, a design level interface signal is represented as two distinct ports (I and IB),
one deemed the "master" and the other the "slave." The master and the slave are
opposite phases of the same logical signal (for example, MYNET and MYNETB).

X9255

Inputs

Outputs

IB

-*

-*

* The dash (-) means No Change.

Available Attributes
The IOSTANDARD attribute values listed in the following table can be applied to an
IBUFDS component to provide selectIO interface capability.
A separate SelectIO component is not provided. Attach an IOSTANDARD attribute to
an IBUFDS and assign the value indicated in the "IOSTANDARD (Attribute Value)"
column to program the inputs for the I/O standard associated with that value.
Architectures
IOSTANDARD

Spartan-3

BLVDS_25
LDT_25

Attribute Values

Virtex-II

Virtex-II Pro,
Virtex-II Pro X

Termination
Type Input

VREF
Input *

Input VCCO

None

No

No

None

No

No

LDT_25_DT
LVDS_25 (default)

None

No

No

LVDS_25_DCI

Split

No

2.5

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ISE 6.3i

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627

IBUFDS

Architectures
IOSTANDARD

Spartan-3

Virtex-II

Attribute Values

Virtex-II Pro,
Virtex-II Pro X

LVDS_33

Termination
Type Input

VREF
Input *

Input VCCO

None

No

No

LVDSEXT_25

None

No

No

LVDSEXT_25_DCI

Split

No

2.5

None

No

No

None

No

No

None

No

No

None

No

No

LVDSEXT_33

LVDS_25_DT
LVDXEST_25_DT

LVPECL_25

LVPECL_33

ULVDS_25

ULVDS_25_DT
* VREF requirement when this IOSTANDARD is an input.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- IBUFDS: Differential Input Buffer
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
IBUFDS_inst : IBUFDS
-- Edit the following generic to specify the I/O standard for this
port.
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => O, -- Clock buffer output
I => I, -- Diff_p clock buffer input (connect to top-level port)
IB => IB -- Diff_n clock buffer input (connect directly to toplevel port)
);
-- End of IBUFDS_inst instantiation

Verilog Instantiation Template

// IBUFDS: Differential Input Buffer
//
Virtex-II/II-Pro, Spartan-3
// XilinxHDL Libraries Guide version 7.1i
IBUFDS IBUFDS_inst (
.O(O), // Clock buffer output
.I(I), // Diff_p clock buffer input (connect directly to
// top-level port)
.IB(IB) // Diff_n clock buffer input (connect directly to

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Libraries Guide
ISE 6.3i

IBUFDS

// top-level port)
);
// Edit the following defparam to specify the I/O standard for this
// port. If the instance name is change, that change needs to be
// reflecting the this defparam.
defparam IBUFDS_inst.IOSTANDARD = "LVDS_25";
// End of IBUFDS_inst instantiation

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ISE 6.3i

630

IBUFDS

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Libraries Guide
ISE 6.3i

IBUFDS_DIFF_OUT

IBUFDS_DIFF_OUT
Differential I/O Input Buffer with Differential Outputs
Architectures Supported
IBUFDS_DIFF_OUT
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I
IB

No

CoolRunner XPLA3

No

CoolRunner-II

No

IBUFDS_DIFF_OUT is a differential I/O input buffer with differential outputs. The

differential output pair (O&OB) maintains the relation of its differential input pair.

O
OB

Available Attributes

IBUFDS_DIFF_OUT
X10107

Architectures

Attribute Values

Virtex-II

Virtex-II Pro,
Virtex-II Pro X

LVDS_25 (default)

LVDS_25_DCI

IOSTANDARD

Spartan-3

BLVDS_25
LDT_25

Termination
Type Input

VREF Input *

Input VCCO

None

N/A

N/A

None

N/A

N/A

None

N/A

N/A

Split

N/A

2.5

LDT_25_DT

LVDS_25_DT

LVDS_33

None

N/A

N/A

LVDSEXT_25

None

N/A

N/A

LVDSEXT_25_DCI

Split

N/A

2.5

None

N/A

N/A

None

N/A

N/A

None

N/A

N/A

None

N/A

N/A

LVDSEXT_33
LVDXEST_25_DT

LVPECL_25

LVPECL_33

ULVDS_25

ULVDS_25_DT
* VREF requirement when this IOSTANDARD is an input.

Usage
IBUFDS_DIFF_OUT is instantiated rather than inferred.

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ISE 6.3i

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631

IBUFDS_DIFF_OUT

VHDL Instantiation Template

-- Component Declaration for IBUFDS_DIFF_OUT should be placed
-- after architecture statement but before begin keyword
component IBUFDS_DIFF_OUT
-- synthesis translate_off
generic (
IOSTANDARD: bit_vector := "LVDS_25");
-- synthesis translate_on
port (O : out STD_ULOGIC;
OB : out STD_ULOGIC;
I : in STD_ULOGIC;
IB : in STD_ULOGIC);
end component;
-- Component Attribute specification for IBUFDS_DIFF_OUT
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here
attribute IOSTANDARD : string;
attribute IOSTANDARD of IBUFDS_DIFF_OUT_instance_name : label is
"LVDS_25";

-- Component Instantiation for IBUFDS_DIFF_OUT should be placed

-- in architecture after the begin keyword
IBUFDS_INSTANCE_NAME : IBUFDS_DIFF_OUT
-- synthesis translate_off
generic map (
IOSTANDARD => string_value)
-- synthesis translate_on
port map (O => user_O,
OB => user_OB
I => user_I,
IB => user_IB);

Verilog Instantiation Template

IBUFDS_DIFF_OUT instance_name (.O (user_O),
.OB (user_OB),
.I (user_I),
.IB (user_IB));
defparam IBUFDS_DIFF_OUT_instance_name.IOSTANDARD = string_value;

632

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Libraries Guide
ISE 6.3i

IBUFG

IBUFG
Dedicated Input Buffer with Selectable I/O Interface
Architectures Supported
IBUFG
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

IBUFG is dedicated to dedicated input buffers for connecting to the clock buffer BUFG
or CLKDLL. You can attach an IOSTANDARD attribute to an IBUFG instance.
The Xilinx implementation software converts each BUFG to an appropriate type of
global buffer for the target PLD device. The IBUFG input can only be driven by the
global clock pins. The IBUFG output can drive CLKIN of a DLL/DCM, BUFG, or user
logic. IBUFG can be routed to user logic and does not have to be routed to a DLL. The
IBUFG can only be driven by an IPAD.
Attach an IOSTANDARD attribute to an IBUFG and assign the value indicated in the
"IOSTANDARD (Attribute Value)" column to program the input for the I/O standard
asociated with that value.
The hardware implementation of the I/O standards requires that you follow a set of
usage rules for the SelectIO buffers. See the Usage Rules section

Libraries Guide
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633

IBUFG

Available Attributes
Spartan-II, Spartan-IIE, Virtex, and Virtex-E and IOSTANDARD Attributes
Architectures

Attribute Values

Spartan-II,
Virtex

Spartan-IIE,
Virtex-E

Termination
Type Input

VREF

Input VCCO

AGP

None

1.32

No

CTT

None

1.50

No

IOSTANDARD

GTL

None

0.80

No

GTLP

None

1.00

No

HSTL_I

None

0.75

No

HSTL_III

None

0.90

1.5

HSTL_IV

None

0.90

No

LVCMOS2

None

No

2.5

LVCMOS18

None

No

1.8

LVDS

None

No

No

None

No

No

LVTTL (default)

None

No

3.3

PCI33_3

None

No

3.3

PCI33_5

None

No

No

PCI66_3

None

No

3.3

None

No

3.3

LVPECL

PCIX66_3
SSTL2_I

None

1.25

No

SSTL2_II

None

1.25

No

SSTL3_I

None

1.50

No

SSTL3_II

None

1.50

No

Not

supported for Virtex-E.

.
Virtex-II, Virtex-II Pro, Virtex-II Pro X and IOSTANDARD Attributes
Architectures
IOSTANDARD

Virtex-II

Attribute Values

Virtex-II Pro,
Virtex-II Pro X

Termination
Type Input

VREF
Input*

Input
VCCO

None

1.32

No

AGP

GTL

None

0.80

No

GTL_DCI

Single

0.80

1.2

GTLP

None

1.00

No

GTLP_DCI

Single

1.00

1.5

HSTL_I

None

0..75

No

HSTL_I_18

None

0.9

No

HSTL_I_DCI

Split

0.75

1.5

HSTL_I_DCI_18

Split

0.9

1.8

634

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ISE 6.3i

IBUFG

Virtex-II, Virtex-II Pro, Virtex-II Pro X and IOSTANDARD Attributes

Architectures

Attribute Values

Virtex-II

Virtex-II Pro,
Virtex-II Pro X

Termination
Type Input

VREF
Input*

Input
VCCO

HSTL_II

None

0.75

No

HSTL_II_18

None

0.9

No

HSTL_II_DCI

Split

0.75

1.5

HSTL_II_DCI_18

Split

0.9

1.8

HSTL_III

None

0.90

No

HSTL_III_18

None

1.10

No

HSTL_III_DCI

Single

0.90

1.5

HSTL_III_DCI_18

Single

1.10

1.8

HSTL_IV

None

0.90

No

HSTL_IV_18

None

1.10

No

HSTL_IV_DCI

Single

0.90

1.5

HSTL_IV_DCI_18

Single

1.10

1.8

None

No

1.2

LVCMOS15

None

No

1.5

LVCMOS18

None

No

1.8

LVCMOS25

None

No

2.5

LVCMOS33

None

No

3.3

LVDCI_15

None

No

1.5

LVDCI_18

None

No

1.8

LVDCI_25

None

No

2.5

LVDCI_33

None

No

3.3

LVDCI_DV2_15

None

No

1.5

LVDCI_DV2_18

None

No

1.8

LVDCI_DV2_25

None

No

2.5

LVDCI_DV2_33

None

No

3.3

LVTTL (default)

None

No

3.3

PCI33_3

None

No

3.3

PCI66_3

None

No

3.3

PCIX

None

No

3.3

SSTL18_I

None

0.9

No

SSTL18_I_DCI

Split

0.9

1.8

SSTL18_II

None

0.9

No

SSTL18_II_DCI

Split

0.9

1.8

SSTL2_I

None

1.25

No

SSTL2_I_DCI

Split

1.25

2.5

SSTL2_II

None

1.25

No

SSTL2_II_DCI

SSTL3_I

IOSTANDARD

LVCMOS12

Libraries Guide
ISE 6.3i

Split

1.25

2.5

None

1.50

No

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635

IBUFG

Usage
This design element is supported for schematic and instantiation. Synthesis tools
usually infer a BUFGP on any clock net. If there are more clock nets than BUFGPs, the
synthesis tool usually instantiates BUFGPs for the clocks that are most utilized. The
BUFGP contains both a BUFG and an IBUFG.

VHDL Instantiation Template

-- IBUFG: Single-ended global clock input buffer
-All FPGA
-- Xilinx HDL Libraries Guide version 7.1i
IBUFG_inst : IBUFG
-- Edit the following generic to specify the I/O standard for this
port.
generic map (
IOSTANDARD => "LVCMOS25")
port map (
O => O, -- Clock buffer output
I => I -- Clock buffer input (connect directly to top-level
port)
);
-- End of IBUFG_inst instantiation

Verilog Instantiation Template

// IBUFG: Single-ended global clock input buffer
//
All FPGA
// XilinxHDL Libraries Guide version 7.1i
IBUFG IBUFG_inst (
.O(O), // Clock buffer output
.I(I) // Clock buffer input (connect directly to
// top-level port)
);
// Edit the following defparam to specify the I/O standard for this
// port. If the instance name is change, that change needs to be
// reflecting the this defparam.
defparam IBUFG_inst.IOSTANDARD = "LVCMOS25";
// End of IBUFG_inst instantiation

636

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ISE 6.3i

IBUFGDS

IBUFGDS
Dedicated Differential Signaling Input Buffer with Selectable I/O
Interface
Architectures Supported
IBUFGDS
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I
IB

X9255

No

CoolRunner XPLA3

No

CoolRunner-II

No

IBUFGDS is a dedicated differential signaling input buffer for connection to the clock
buffer (BUFG) or DCM. In IBUFGDS, a design level interface signal is represented as
two distinct ports (I and IB), one deemed the "master" and the other the "slave." The
master and the slave are opposite phases of the same logical signal (for example,
MYNET and MYNETB).
Inputs

Outputs

IB

-*

-*

* The dash (-) means No Change.

Available Attributes
The IOSTANDARD attribute values listed in the following table can be applied to an
IBUFGDS component to provide SelectIO interface capability. See the Xilinx
Constraints Guide for information about using these attributes.
A separate SelectIO component is not provided. Attach an IOSTANDARD attribute to
an IBUFGDS and assign the value indicated in the "IOSTANDARD (Attribute Value)"
column to program the inputs for the I/O standard associated with that value.
Architectures
IOSTANDARD

Spartan-3

BLVDS_25
LDT_25

Virtex-II

Virtex-II Pro,
Virtex-II Pro X

Libraries Guide
ISE 6.3i

Termination
Type Input

VREF Input *

Input VCCO

None

No

No

None

No

No

None

No

No

LDT_25_DT
LVDS_25 (default)

Attribute Values

www.xilinx.com
1-800-255-7778

637

IBUFGDS

Architectures
IOSTANDARD
LVDS_25_DCI

Attribute Values

Spartan-3

Virtex-II

Virtex-II Pro,
Virtex-II Pro X

Termination
Type Input

VREF Input *

Input VCCO

Split

No

2.5

None

No

No

None

No

No

LVDS_25_DT

LVDS_33
LVDSEXT_25

LVDSEXT_25_DCI

LVDSEXT_33
LVDXEST_25_DT

LVPECL_25

LVPECL_33

ULVDS_25

Split

No

2.5

None

No

No

None

No

No

None

No

No

None

No

No

ULVDS_25_DT
* VREF requirement when this IOSTANDARD is an input.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- IBUFGDS: Differential Global Clock Input Buffer
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
IBUFGDS_inst : IBUFGDS
-- Edit the following generic to specify the I/O standard for this
port.
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => O, -- Clock buffer output
I => I, -- Diff_p clock buffer input (connect to top-level port)
IB => IB -- Diff_n clock buffer input (connect to top-level port)
);
-- End of IBUFGDS_inst instantiation

Verilog Instantiation Template

// IBUFGDS: Differential Global Clock Input Buffer
//
Virtex-II/II-Pro, Spartan-3
// XilinxHDL Libraries Guide version 7.1i
IBUFGDS IBUFGDS_inst (
.O(O), // Clock buffer output
.I(I), // Diff_p clock buffer input (connect directly to
// top-level port)
.IB(IB) // Diff_n clock buffer input (connect directly to
// top-level port)

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ISE 6.3i

IBUFGDS

);
// Edit the following defparam to specify the I/O standard for this
// port. If the instance name is change, that change needs to be
// reflecting the this defparam.
defparam IBUFGDS_inst.IOSTANDARD = "LVDS_25";
// End of IBUFGDS_inst instantiation

Libraries Guide
ISE 6.3i

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639

640

IBUFGDS

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Libraries Guide
ISE 6.3i

ICAP_VIRTEX2

ICAP_VIRTEX2
User Interface to Virtex-II, Virtex-II Pro, and Virtex-II Pro X Internal
Configuration Access Port
Architectures Supported
ICAP_VIRTEX, ICAP_VIRTEX2
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

ICAP_VIRTEX2
I [7:0]

O [7:0]

WRITE

BUSY

CE

No

CoolRunner XPLA3

No

CoolRunner-II

No

ICAP_VIRTEX2 provides user access to the Virtex-II, Virtex-II Pro, and Virtex-II Pro X
internal configuration access port (ICAP).

Usage

CLK

X9256

Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- ICAP_VIRTEX2: Internal Configuration Access Port
-Virtex-II/II-Pro
-- Xilinx HDL Libraries Guide version 7.1i
ICAP_VIRTEX2_inst : ICAP_VIRTEX2
port map (
BUSY => BUSY,
-- Busy output
O => O,
-- 8-bit data output
CE => CE,
-- Clock enable input
CLK => CLK,
-- Clock input
I => I,
-- 8-bit data input
WRITE => WRITE -- Write input
);

Verilog Instantiation Template

// ICAP_VIRTEX2: Internal Configuration Access Port
//
Virtex-II/II-Pro
// Xilinx HDL Libraries Guide version 7.1i
ICAP_VIRTEX2 ICAP_VIRTEX2_inst (
.BUSY(BUSY),
// Busy output
.O(O),
// 8-bit data output
.CE(CE),
// Clock enable input
.CLK(CLK),
// Clock input
.I(I),
// 8-bit data input

Libraries Guide
ISE 6.3i

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641

ICAP_VIRTEX2

.WRITE(WRITE)

// Write input

);

642

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Libraries Guide
ISE 6.3i

IFD, 4, 8, 16

IFD, 4, 8, 16
Single- and Multiple-Input D Flip-Flops
Architectures Supported
IFD, IFD4, IFD8, IFD16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

IFD

X3776

IFD4

CoolRunner XPLA3

No

CoolRunner-II

No

The IFD D-type flip-flop is contained in an input/output block (IOB), except for
XC9500/XV/XL, CoolRunner XPLA3. The input (D) of the flip-flop is connected to an
IPAD or an IOPAD (without using an IBUF). The D input provides data input for the
flip-flop, which synchronizes data entering the chip. The data on input D is loaded
into the flip-flop during the Low-to-High clock (C) transition and appears at the
output (Q). The clock input can be driven by internal logic or through another
external pin.

D0

No

Q0

D1

Q1

D2

Q2

D3

Q3

The flip-flops are asynchronously cleared with Low outputs when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

X3799

D[7:0]

Q[7:0]

IFD8

X3811

D[15:0]

IFD16

Q[15:0]

X3833

Libraries Guide
ISE 6.3i

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643

IFD, 4, 8, 16

GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

VCC

FDCE
D_IN

IBUF

CE

C
CLR

IOB=TRUE

GND

X9768

IFD Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

VCC

FDCE
D

LVTTL

D_IN

IBUF

CE

CLR

IOB=TRUE
X9333

GND

IFD Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

FDCP
IBUF
D_IN

PRE

IBUF
C

C
CLR
Q

GND

X7852

IFD Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

644

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Libraries Guide
ISE 6.3i

IFD, 4, 8, 16

Q[7:0]

IFD
D0

Q0

Q0

IFD
D1

Q1
D

Q1
IFD

D2

Q2

Q2

IFD
D3

Q3

Q3

IFD
D4

Q4
D

Q4
IFD

D5

Q5
D

Q5
IFD

D6

Q6
D

Q6
IFD

D7

Q7
D

Q7

D[7:0]
C

X6389

IFD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an IFD, you would infer
an FD and put the IOB = TRUE attribute on the component. Or, you could use the
map option pr i to pack all input registers into the IOBs.

Libraries Guide
ISE 6.3i

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645

646

IFD, 4, 8, 16

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Libraries Guide
ISE 6.3i

IFD_1

IFD_1
Input D Flip-Flop with Inverted Clock
Architectures Supported
IFD_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

IFD_1

X3777

No

CoolRunner XPLA3

No

CoolRunner-II

No

The IFD_1 D-type flip-flop is contained in an input/output block (IOB). The input (D)
of the flip-flop is connected to an IPAD or an IOPAD. The D input also provides data
input for the flip-flop, which synchronizes data entering the chip. The D input data is
loaded into the flip-flop during the High-to-Low clock (C) transition and appears at
the output (Q). The clock input can be driven by internal logic or through another
external pin.
The flip-flop is asynchronously cleared with Low output when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

VCC

FDCE
D_IN

D
IBUF

CE
CB

D
C
CLR

INV

IOB=TRUE

GND

X9770

IFD_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

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647

IFD_1

VCC

FDCE
D

LVTTL

D_IN

IBUF

CE
CB

C
INV

CLR

IOB=TRUE
GND

X9334

IFD_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an IFD_1, you would
infer an FD_1 and put the IOB = TRUE attribute on the component. Or, you could use
the map option pr i to pack all input registers into the IOBs.

648

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Libraries Guide
ISE 6.3i

IFDDRCPE

IFDDRCPE
Dual Data Rate Input D Flip-Flop with Clock Enable and Asynchronous
Preset and Clear
Architectures Supported
IFDDRCPE
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE
D

IFDDRCPE Q0

CE

No

CoolRunner XPLA3

No

CoolRunner-II

No

IFDDRCPE is a dual data rate (DDR) input D flip-flop with clock enable (CE) and
asynchronous preset (PRE) and clear (CLR). It consists of one input buffer and two
identical flip-flops (FDCPE).

Q1

C0
C1
CLR
X9398

When the asynchronous PRE is High and CLR is Low, both the Q0 and Q1 outputs are
set High. When CLR is High, both outputs are reset Low. When PRE and CLR are Low
and CE is High, data on the D input is loaded into the Q0 output on the Low-to High
C0 clock transition, and into the Q1 output on the Low-to-High C1 clock transition.
The flip-flops are asynchronously cleared with Low outputs when power is applied.
The INIT attribute does not apply to IFDDRCPE components.
Inputs

Outputs

C0

C1

CE

CLR

PRE

Q0

Q1

No Chg

No Chg

No Chg

No Chg

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an IFDDRCPE, you
would infer an FDDRCPE and put the IOB = TRUE attribute on the component. Or,
you could use the map option pr i to pack all input registers into the IOBs.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

649

IFDDRCPE

VHDL Instantiation Template

-- IFDDRCPE: Double Data Rate Input Register with Async. Clear,
-Async. Preset
-and Clock Enable. Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
IFDDRCPE_inst :
port map (
Q0 => Q0,
Q1 => Q1,
C0 => C0,
C1 => C1,
CE => CE,
CLR => CLR,
D => D,
PRE => PRE
);

IFDDRCPE
---------

Posedge data output

Negedge data output
0 degree clock input
180 degree clock input
Clock enable input
Asynchronous reset input
Data input (connect directly to top-level port)
Asynchronous preset input

-- End of IFDDRCPE_inst instantiation

Verilog Instantiation Template

// IFDDRCPE: Double Data Rate Input Register with Async. Clear, Async.
//
Preset and Clock Enable. Virtex-II/II-Pro, Spartan-3
// Xilinx HDL Libraries Guide version 7.1i
IFDDRCPE IFDDRCPE_inst (
.Q0(Q0),
// Posedge data output
.Q1(Q1),
// Negedge data output
.C0(C0),
// 0 degree clock input
.C1(C1),
// 180 degree clock input
.CE(CE),
// Clock enable input
.CLR(CLR), // Asynchronous reset input
.D(D),
// Data input (connect directly to top-level port)
.PRE(PRE)
// Asynchronous preset input
);
// End of IFDDRCPE_inst instantiation

Commonly Used Constraints

LOC, RLOC, and INIT

650

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Libraries Guide
ISE 6.3i

IFDDRRSE

IFDDRRSE
Dual Data Rate Input D Flip-Flop with Synchronous Reset and Set and
Clock Enable
Architectures Supported
IFDDRRSE
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

S
D

IFDDRRSE Q0

No

CoolRunner XPLA3

No

CoolRunner-II

No

IFDDRRSE is a dual data rate (DDR) input D flip-flop with synchronous reset (R),
synchronous set (S), and clock enable (CE). It consists of one input buffer and two
identical flip-flops (FDRSE).

Q1

CE
C0
C1
R

X9401

For the C0 input and Q0 output, reset (R) has precedence. The R input, when High,
resets the Q0 output Low during the Low-to-High C0 clock transition. When S is High
and R is Low, the Q0 output is set High during the Low-to-High C0 clock transition.
For the C1 input and Q1 output, set (S) has precedence. The R input, when High,
resets the Q1 output Low during the Low-to-High C1 clock transition. When S is High
and R is Low, the Q0 output is set to High during the Low-to-High C1 clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
The INIT attribute does not apply to IFDDRRSE components.
Inputs

Outputs

C0

C1

CE

Q0

Q1

No Chg

No Chg

No Chg

No Chg

No Chg

No Chg

No Chg

No Chg

No Chg

No Chg

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an IFDDRRSE, you

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

651

IFDDRRSE

would infer an FDDRRSE and put the IOB = TRUE attribute on the component. Or,
you could use the map option pr i to pack all input registers into the IOBs.

VHDL Instantiation Template

-- IFDDRRSE: Double Data Rate Input Register with Sync. Clear,
-Sync. Preset
-and Clock Enable. Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
IFDDRRSE_inst : IFDDRRSE
port map (
Q0 => Q0,
-- Posedge data output
Q1 => Q1,
-- Negedge data output
C0 => C0,
-- 0 degree clock input
C1 => C1,
-- 180 degree clock input
CE => CE,
-- Clock enable input
D => D,
-- Data input (connect directly to top-level port)
R => R,
-- Synchronous reset input
S => S
-- Synchronous preset input
);
-- End of IFDDRRSE_inst instantiation

Verilog Instantiation Template

// IFDDRRSE: Double Data Rate Input Register with Sync. Clear, Sync.
//
Preset and Clock Enable. Virtex-II/II-Pro, Spartan-3
// Xilinx HDL Libraries Guide version 7.1i
IFDDRRSE IFDDRRSE_inst (
.Q0(Q0),
// Posedge data output
.Q1(Q1),
// Negedge data output
.C0(C0),
// 0 degree clock input
.C1(C1),
// 180 degree clock input
.CE(CE),
// Clock enable input
.D(D),
// Data input (connect directly to top-level port)
.R(R),
// Synchronous reset input
.S(S)
// Synchronous preset input
);
// End of IFDDRRSE_inst instantiation

Commonly Used Constraints

LOC, RLOC, INIT

652

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Libraries Guide
ISE 6.3i

IFDI

IFDI
Input D Flip-Flop (Asynchronous Preset)
Architectures Supported
IFDI
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

IFDI

X4617

No

CoolRunner XPLA3

No

CoolRunner-II

No

The IFDI D-type flip-flop is contained in an input/output block (IOB). The input (D)
of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data input
for the flip-flop, which synchronizes data entering the chip. The data on input D is
loaded into the flip-flop during the Low-to-High clock (C) transition and appears at
the output (Q). The clock input can be driven by internal logic or through another
external pin.
The flip-flop is asynchronously preset, output High, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

VCC

D
C

D_IN

D
CE

IBUF

PRE

C
FDPE
IOB=TRUE
GND

X8740

IFDI Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

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653

IFDI

VCC

FDPE
D

LVTTL

D_IN

IBUF

PRE

CE

C
IOB=TRUE
X9335

GND

IFDI Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an IFDI, you would infer
an FDP and put the IOB = TRUE attribute on the component. Or, you could use the
map option pr i to pack all input registers into the IOBs.

654

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Libraries Guide
ISE 6.3i

IFDI_1

IFDI_1
Input D Flip-Flop with Inverted Clock (Asynchronous Preset)
Architectures Supported
IFDI_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

IFDI_1

X4386

No

CoolRunner XPLA3

No

CoolRunner-II

No

The IFDI_1 D-type flip-flop is contained in an input/output block (IOB). The input
(D) of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data
input for the flip-flop, which synchronizes data entering the chip. The data on input D
is loaded into the flip-flop during the High-to-Low clock (C) transition and appears at
the output (Q). The clock input can be driven by internal logic or through another
external pin.
The flip-flop is asynchronously preset, output High, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

VCC

D_IN

D
CE

IBUF
C

CB

PRE

INV
FDPE
IOB=TRUE
GND

X8741

IFDI_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

655

IFDI_1

VCC

FDPE
D

LVTTL

D_IN

IBUF
C

PRE

CE
CB

INV
IOB=TRUE
X9336

GND

IFDI_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an IFDI_1, you would
infer an FDP_1 and put the IOB = TRUE attribute on the component. Or, you could
use the map option pr i to pack all input registers into the IOBs.

656

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Libraries Guide
ISE 6.3i

IFDX, 4, 8, 16

IFDX, 4, 8, 16
Single- and Multiple-Input D Flip-Flops with Clock Enable
Architectures Supported
IFDX
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

IFDX4, IFDX8, IFDX16

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

IFDX

CE
C

X6009

D0

IFDX4

Q0

D1

Q1

D2

Q2

D3

Q3

CE
C

X6010

No

CoolRunner XPLA3

No

CoolRunner-II

No

The IFDX D-type flip-flop is contained in an input/output block (IOB). The input (D)
of the flip-flop is connected to an IPAD or an IOPAD (without using an IBUF). The D
input provides data input for the flip-flop, which synchronizes data entering the chip.
When CE is High, the data on input D is loaded into the flip-flop during the Low-toHigh clock (C) transition and appears at the output (Q). The clock input can be driven
by internal logic or through another external pin. When CE is Low, flip-flop outputs
do not change.
The flip-flops are asynchronously cleared with Low outputs when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

D[15:0]
D[7:0]

IFDX16
IFDX8

CE
CE

CC
X6012

X6011

Libraries Guide
ISE 6.3i

Outputs

Q[15:0]
Q[7:0]

CE

Dn

Dn

Dn

No Chg

www.xilinx.com
1-800-255-7778

Qn

657

IFDX, 4, 8, 16

FDCE
D
CE
C

D_IN

D
CE
C

IBUF

CLR

IOB=TRUE
GND

X8742

IFDX Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

658

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Libraries Guide
ISE 6.3i

IFDX, 4, 8, 16

Q[7:0]
IFDX
D0

D
CE

Q0

Q0
IFDX
D1

D
CE

Q1

Q1
IFDX
D2

D
CE

Q2

Q2
IFDX
D3

D
CE

Q3

Q3
IFDX
D4

D
CE

Q4

Q4
IFDX
D5

D
CE

Q5

Q5
IFDX
D6

D
CE

Q6

Q6
IFDX
D7

D
CE

Q7

D[7:0]

Q7

CE
C

X7635

IFDX8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

659

IFDX, 4, 8, 16

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an IFDX, you would
infer an FDCE and put the IOB = TRUE attribute on the component. Or, you could use
the map option pr i to pack all input registers into the IOBs.

VHDL Instantiation Template

-- Component Declaration for IFDX should be placed
-- after architecture statement but before begin keyword
component IFDX
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;
-- Component Attribute specification for IFDX
-- should be placed after architecture declaration but
-- before the begin keyword

-- Enter attributes here

-- Component Instantiation for IFDX should be placed

-- in architecture after the begin keyword
IFDX_INSTANCE_NAME : IFDX
port map (Q => user_Q,
C => user_C,
CE => user_CE,
D => user_D);

Verilog Instantiation Template

IFDX IFDX_instance_name (.Q (user_Q),
.C (user_C),
.CE (user_CE),
.D (user_D));

Commonly Used Constraints

IOB

660

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Libraries Guide
ISE 6.3i

IFDX_1

IFDX_1
Input D Flip-Flop with Inverted Clock and Clock Enable
Architectures Supported
IFDX_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

IFDX_1

CE
C

X6014

No

CoolRunner XPLA3

No

CoolRunner-II

No

The IFDX_1 D-type flip-flop is contained in an input/output block (IOB). The input
(D) of the flip-flop is connected to an IPAD or an IOPAD. The D input also provides
data input for the flip-flop, which synchronizes data entering the chip. When CE is
High, the data on input D is loaded into the flip-flop during the High-to-Low clock
(C) transition and appears at the output (Q). The clock input can be driven by internal
logic or through another external pin. When the CE pin is Low, the output (Q) does
not change.
The flip-flop is asynchronously cleared with Low output, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
For more information on IFDX_1, see ILDX, 4, 8, 16.
Inputs

Outputs

CE

No Chg

FDCE
D
CE
C

D_IN

D
CE

IBUF
CB

INV

CLR

IOB=TRUE
GND

X8743

IFDX_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

661

IFDX_1

FDCE
D
CE

LVTTL

D_IN

IBUF

CE
CB

INV

CLR

IOB=TRUE
X9337

GND

IFDX_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an IFDX_1, you would
infer an FDCE_1 and put the IOB = TRUE attribute on the component. Or, you could
use the map option pr i to pack all input registers into the IOBs.

662

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Libraries Guide
ISE 6.3i

IFDXI

IFDXI
Input D Flip-Flop with Clock Enable (Asynchronous Preset)
Architectures Supported
IFDXI
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

IFDXI

CE
C

X6016

No

CoolRunner XPLA3

No

CoolRunner-II

No

The IFDXI D-type flip-flop is contained in an input/output block (IOB). The input (D)
of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data input
for the flip-flop, which synchronizes data entering the chip. When CE is High, the
data on input D is loaded into the flip-flop during the Low-to-High clock (C)
transition and appears at the output (Q). The clock input can be driven by internal
logic or through another external pin. When the CE pin is Low, the output (Q) does
not change.
The flip-flop is asynchronously preset with High output, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
For information on legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations, see
ILDXI.
Inputs
CE

No Chg

D
CE
C

Outputs

D_IN

D
CE

IBUF

PRE

C
FDPE
IOB=TRUE
GND

X8744

IFDXI Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
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663

IFDXI

FDPE
D
CE

LVTTL

D_IN

IBUF

PRE

CE

C
IOB=TRUE
X9338

GND

IFDXI Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an IFDXI, you would
infer an FDPE and put the IOB = TRUE attribute on the component. Or, you could use
the map option pr i to pack all input registers into the IOBs.

664

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Libraries Guide
ISE 6.3i

IFDXI_1

IFDXI_1
Input D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous
Preset)
Architectures Supported
IFDXI_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

IFDXI_1

CE
C

X6018

No

CoolRunner XPLA3

No

CoolRunner-II

No

The IFDXI_1 D-type flip-flop is contained in an input/output block (IOB). The input
(D) of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data
input for the flip-flop, which synchronizes data entering the chip. When CE is High,
the data on input D is loaded into the flip-flop during the High-to-Low clock (C)
transition and appears at the output (Q). The clock input can be driven by internal
logic or through another external pin. When the CE pin is Low, the output (Q) does
not change.
The flip-flop is asynchronously preset with High output when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
For information on legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations, see
ILDXI.
Inputs
CE

No Chg

D
CE
C

Outputs

D_IN

D
CE

IBUF
CB

PRE

INV

FDPE
IOB=TRUE
GND

X8745

IFDXI_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

665

IFDXI_1

FDPE
D
CE

LVTTL

D_IN

IBUF

PRE

CE
CB

INV
IOB=TRUE
X9339

GND

IFDXI_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an IFDXI_1, you would
infer an FDPE_1 and put the IOB = TRUE attribute on the component. Or, you could
use the map option pr i to pack all input registers into the IOBs.

666

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Libraries Guide
ISE 6.3i

ILD, 4, 8, 16

ILD, 4, 8, 16
Transparent Input Data Latches
Architectures Supported
ILD
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

ILD4, ILD8, ILD16

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

ILD

X3774

D0

ILD4

Q0

D1

Q1

D2

Q2

D3

Q3

No

CoolRunner XPLA3

No

CoolRunner-II

No

ILD, ILD4, ILD8, and ILD16 are single or multiple transparent data latches, which can
be used to hold transient data entering a chip. The ILD latch is contained in an
input/output block (IOB), except for XC9500/XV/XL. The latch input (D) is
connected to an IPAD or an IOPAD (without using an IBUF). When the gate input (G)
is High, data on the inputs (D) appears on the outputs (Q). Data on the D inputs
during the High-to-Low G transition is stored in the latch.
The latch is asynchronously cleared with Low output when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

X3798

GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs
D[7:0]

ILD8

Q[7:0]

X3810

Libraries Guide
ISE 6.3i

Outputs

No Chg

www.xilinx.com
1-800-255-7778

667

D[15:0]

ILD16

ILD, 4, 8, 16

Q[15:0]

X3832

VCC

LDCE
D_IN

D
IBUF

GE

G
CLR

IOB=TRUE

GND

X9767

ILD Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

VCC

LDCE
LVTTL

D_IN

IBUF

GE

CLR

IOB=TRUE
X9340

GND

ILD Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

G
D

FDCP

D_IN
IBUF

AND2
D

PRE

C
CLR
Q
AND2B1

GND

X8123

ILD Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

668

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Libraries Guide
ISE 6.3i

ILD, 4, 8, 16

Q[7:0]
ILD
D0

Q0

Q0
ILD
D1

Q1

Q1
ILD
D2

Q2

Q2
ILD
D3

Q3

Q3
ILD
D4

Q4

Q4
ILD
D5

Q5

Q5
ILD
D6

Q6

Q6
ILD
D7

Q7

D[7:0]

Q7

X7853

ILD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an ILD, you would infer
an LD and put the IOB = TRUE attribute on the component. Or, you could use the
map option pr i to pack all input registers into the IOBs.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

669

ILD, 4, 8, 16

VHDL Instantiation Template

-- Component Declaration for ILD should be placed
-- after architecture statement but before begin keyword
component ILD
port (Q : out STD_ULOGIC;
D : in STD_ULOGIC;
DG : in STD_ULOGIC);
end component;
-- Component Attribute specification for ILD
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for ILD should be placed

-- in architecture after the begin keyword
ILD_INSTANCE_NAME
port map (Q
D
G

: ILD
=> user_Q,
=> user_D,
=> user_G);

Verilog Instantiation Template

ILD ILD_instance_name (.Q (user_Q),
.D (user_D),
.G (user_G));

Commonly Used Constraints

INIT

670

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Libraries Guide
ISE 6.3i

ILD_1

ILD_1
Transparent Input Data Latch with Inverted Gate
Architectures Supported
ILD_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

ILD_1

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

ILD_1 is a transparent data latch, which can be used to hold transient data entering a
chip. When the gate input (G) is Low, data on the data input (D) appears on the data
output (Q). Data on D during the Low-to-High G transition is stored in the latch.
The latch is asynchronously cleared with Low output when power is applied.

X4387

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

VCC

LDCE
D_IN

D
IBUF

GE
GB

D
G
CLR

INV

IOB=TRUE

GND

X9769

ILD_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

671

ILD_1

VCC

LDCE
D

LVTTL

D_IN

IBUF

GE
GB

INV

CLR

IOB=TRUE
GND

X9341

ILD_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an ILD_1, you would
infer an LD_1 and put the IOB = TRUE attribute on the component. Or, you could use
the map option pr i to pack all input registers into the IOBs.

VHDL Instantiation Template

-- Component Declaration for ILD_1 should be placed
-- after architecture statement but before begin keyword
component ILD_1
port (Q : out STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC);
end component;
-- Component Attribute specification for ILD_1
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for ILD_1 should be placed

-- in architecture after the begin keyword
ILD_1_INSTANCE_NAME : ILD_1
port map (Q => user_Q,
D => user_D,
G => user_G);

Verilog Instantiation Template

ILD_1 ILD_1_instance_name (.Q (user_Q),
.D (user_D),
.G (user_G));

Commonly Used Constraints

INIT

672

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Libraries Guide
ISE 6.3i

ILDI

ILDI
Transparent Input Data Latch (Asynchronous Preset)
Architectures Supported
ILDI
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

ILDI

No

CoolRunner XPLA3

No

CoolRunner-II

No

ILDI is a transparent data latch, which can hold transient data entering a chip. When
the gate input (G) is High, data on the input (D) appears on the output (Q). Data on
the D input during the High-to-Low G transition is stored in the latch.
The latch is asynchronously preset, output High, when power is applied.

X4388

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

ILDIs and IFDIs

The ILDI is actually the input flip-flop master latch. It is possible to access two
different outputs from the input flip-flop: one that responds to the level of the clock
signal and another that responds to an edge of the clock signal. When using both
outputs from the same input flip-flop, a transparent High latch (ILDI) corresponds to
a falling edge-triggered flip-flop (IFDI_1). Similarly, a transparent Low latch (ILDI_1)
corresponds to a rising edge-triggered flip-flop (IFDI).
Inputs

Libraries Guide
ISE 6.3i

Outputs

www.xilinx.com
1-800-255-7778

673

ILDI

VCC

D
G

D_IN

D
GE

IBUF

PRE

G
LDPE
IOB=TRUE
GND

X8746

ILDI Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

VCC

LVTTL

D_IN

IBUF

PRE

GE

LDPE
IOB=TRUE
X9342

GND

ILDI Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an ILDI, you would infer
an LDP and put the IOB = TRUE attribute on the component. Or, you could use the
map option pr i to pack all input registers into the IOBs.

674

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Libraries Guide
ISE 6.3i

ILDI_1

ILDI_1
Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)
Architectures Supported
ILDI_1
Spartan-II, Spartan-IIE

Macro*

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Macro

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

* Macros cannot be implemented for Spartan-IIE.

ILDI_1

ILDI_1 is a transparent data latch, which can hold transient data entering a chip.
When the gate input (G) is Low, data on the data input (D) appears on the data output
(Q). Data on D during the Low-to-High G transition is stored in the latch.
The latch is asynchronously preset, output High, when power is applied.

X4618

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
For information on ILDI_1, see ILDI.
Inputs

Outputs

VCC

D
G

D_IN
IBUF

D
GE

GB

PRE

INV
LDPE
IOB=TRUE
GND

X8747

ILDI_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

675

ILDI_1

VCC

LVTTL

D_IN

IBUF
G

PRE

GE
GB

INV

LDPE
IOB=TRUE
GND

X9343

ILDI_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an ILDI_1, you would
infer an LDP_1 and put the IOB = TRUE attribute on the component. Or, you could
use the map option pr i to pack all input registers into the IOBs.

676

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Libraries Guide
ISE 6.3i

ILDX, 4, 8, 16

ILDX, 4, 8, 16
Transparent Input Data Latches
Architectures Supported
ILDX
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

ILDX4, ILDX8, ILDX16

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

ILDX

CoolRunner XPLA3

No

CoolRunner-II

No

GE
G
X6020

D0

No

ILDX4

Q0

D1

Q1

D2

Q2

D3

Q3

GE
G
X6021

ILDX, ILDX4, ILDX8, and ILDX16 are single or multiple transparent data latches,
which can be used to hold transient data entering a chip. The latch input (D) is
connected to an IPAD or an IOPAD (without using an IBUF).
The latch is asynchronously cleared, output Low, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

ILDXs and IFDXs

D[7:0]

ILDX8

Q[7:0]

GE
G
X6022

D[15:0]

ILDX16

The ILDX is actually the input flip-flop master latch. Two different outputs can be
accessed from the input flip-flop: one that responds to the level of the clock signal and
another that responds to an edge of the clock signal. When using both outputs from
the same input flip-flop, a transparent High latch (ILDX) corresponds to a falling
edge-triggered flip-flop (IFDX_1). Similarly, a transparent Low latch (ILDX_1)
corresponds to a rising edge-triggered flip-flop (IFDX).

Q[15:0]

GE
G
X6023

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

677

ILDX, 4, 8, 16

Inputs

Outputs

GE

No Chg

No Chg

LDCE
D

D_IN

GE
G

D
GE
G

IBUF

Q
CLR

IOB=TRUE
GND

X8748

ILDX Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

LDCE
D
GE

LVTTL

D_IN

IBUF

GE

CLR

IOB=TRUE
X9344

GND

ILDX Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

678

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Libraries Guide
ISE 6.3i

ILDX, 4, 8, 16

Q[7:0]

ILDX
D0

Q0

GE
G

Q0
ILDX

D1

Q1

GE
G

Q1
ILDX

D2

Q2

GE
G

Q2
ILDX

D3

Q3

GE
G

Q3
ILDX

D4

Q4

GE
G

Q4
ILDX

D5

Q5

GE
G

Q5
ILDX

D6

Q6

GE
G

Q6
ILDX

D7

Q7

GE
G
D[7:0]

Q7

GE
G
X6405

ILDX8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an ILDX, you would
infer an LDCE and put the IOB = TRUE attribute on the component. Or, you could use
the map option pr i to pack all input registers into the IOBs.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

679

680

ILDX, 4, 8, 16

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1-800-255-7778

Libraries Guide
ISE 6.3i

ILDX_1

ILDX_1
Transparent Input Data Latch with Inverted Gate
Architectures Supported
ILDX_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

ILDX_1

GE

No

CoolRunner XPLA3

No

CoolRunner-II

No

ILDX_1 is a transparent data latch, which can be used to hold transient data entering a
chip. When the gate input (G) is Low, data on the data input (D) appears on the data
output (Q). Data on D during the Low-to-High G transition is stored in the latch.
The latch is asynchronously cleared with Low output, when power is applied.

X6025

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
For more information on ILDX_1, see ILDX, 4, 8, 16.
Inputs

Outputs

GE

No Chg

No Chg

LDCE
D
GE
G

D_IN

D
GE
G

IBUF
GB
INV

CLR

IOB=TRUE
GND

X8749

ILDX_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

681

ILDX_1

LDCE
D
GE

LVTTL

D_IN

IBUF

GE
GB

INV

CLR

IOB=TRUE
X9345

GND

ILDX_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an ILDX_1, you would
infer an LDCE_1 and put the IOB = TRUE attribute on the component. Or, you could
use the map option pr i to pack all input registers into the IOBs.

682

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Libraries Guide
ISE 6.3i

ILDXI

ILDXI
Transparent Input Data Latch (Asynchronous Preset)
Architectures Supported
ILDXI
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

GE

ILDXI is a transparent data latch, which can hold transient data entering a chip. When
the gate input (G) is High, data on the input (D) appears on the output (Q). Data on
the D input during the High-to-Low G transition is stored in the latch.

The latch is asynchronously preset, output High, when power is applied.

ILDXI

X6026

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

ILDXIs and IFDXIs

The ILDXI is actually the input flip-flop master latch. Two different outputs can be
accessed from the input flip-flop: one that responds to the level of the clock signal and
another that responds to an edge of the clock signal. When using both outputs from
the same input flip-flop, a transparent High latch (ILDXI) corresponds to a falling
edge-triggered flip-flop (IFDXI_1). Similarly, a transparent Low latch (ILDXI_1)
corresponds to a rising edge-triggered flip-flop (IFDXI). See the following figure for
legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations.
ILDXI

ILDXI_1

IPAD

IPAD
D

IO_ENABLE

D
IO_ENABLE

GE
G

IFDXI_1
D

IFDXI

CE
CLOCK

GE

CE
CLOCK

X6027

Legal Combinations of IFDXI and ILDXI for a Single IOB

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

683

ILDXI

Inputs
GE

No Chg

No Chg

D
GE
G

Outputs

PRE
D
Q
GE
G

D_IN
IBUF

LDPE
IOB=TRUE
GND

X8750

ILDXI Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

D
GE

LVTTL

D_IN

IBUF

PRE

GE

LDPE
IOB=TRUE
X9346

GND

ILDXI Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an ILDXI, you would
infer an LDPE and put the IOB = TRUE attribute on the component. Or, you could use
the map option pr i to pack all input registers into the IOBs.

684

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Libraries Guide
ISE 6.3i

ILDXI_1

ILDXI_1
Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)
Architectures Supported
ILDXI_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

ILDXI_1

No

CoolRunner XPLA3

No

CoolRunner-II

No

ILDXI_1 is a transparent data latch, which can hold transient data entering a chip. The
latch is asynchronously preset, output High, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

GE
G

X6028

GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
For information on legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations, see
ILDXI.
Inputs
GE

No Chg

No Chg

D
GE
G

Outputs

PRE
Q
D
GE
G

D_IN
IBUF
GB

INV
LDPE
IOB=TRUE
GND

X8751

ILDXI_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

685

ILDXI_1

D
GE

LVTTL

D_IN

IBUF

PRE

GE
GB

INV

LDPE
IOB=TRUE
X9347

GND

ILDXI_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an ILDXI_1, you would
infer an LDPE_1 and put the IOB = TRUE attribute on the component. Or, you could
use the map option pr i to pack all input registers into the IOBs.

686

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Libraries Guide
ISE 6.3i

INV, 4, 8, 16

INV, 4, 8, 16
Single and Multiple Inverters
Architectures Supported
INV
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive
INV4, INV8, INV16

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

INV, INV4, INV8, and INV16 are single and multiple inverters that identify signal
inversions in a schematic.

O
X9422

O[7:0]

I0

IO

O0

I1

O1

I2

O2

I3

O3

I1
I2
I3

O0
INV
INV
INV

O1
O2
O3

X9423
I4
I5
I [7:0]

O [7:0]

I6

INV8

I7

X9853

I[7:0]

INV
INV
INV
INV

O4
O5
O6
O7

INV
X7653

I [15:0]

O [15:0]
INV16

INV8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

X9854

Usage
For HDL, this design element can be instantiated or inferred.

Libraries Guide
ISE 6.3i

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687

INV, 4, 8, 16

VHDL Instantiation Template

-- Component Declaration for INV should be placed
-- after architecture statement but before begin keyword
component INV
port (O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for INV
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for INV should be placed

-- in architecture after the begin keyword
INV_INSTANCE_NAME : INV
port map (O => user_O,
I => user_I);

Verilog Instantiation Template

INV instance_name (.O (user_O),
.I (user_I));

688

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Libraries Guide
ISE 6.3i

IOBUF

IOBUF
Bi-Directional Buffer with Selectable I/O Interface
Architectures Supported
IOBUF
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

T
I

IO

No

CoolRunner XPLA3

No

CoolRunner-II

No

For Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro
X, IOBUF are bi-directional buffers whose I/O interface corresponds to a specific I/O
standard. You can attach an IOSTANDARD attribute to an IOBUF instance. Check
marks () in the "Spartan-II, Virtex" and "Spartan-IIE, Virtex-E" columns indicate the
components and IOSTANDARD attribute values available for each architecture.

X8406

IOBUF components that use the LVTTL, LVCMOS15, LVCMOS18, LVCMOS25,

LVCMOS33 signaling standards have selectable drive and slew rates using the DRIVE
and FAST or SLOW constraints. The defaults are DRIVE=12 mA and SLOW slew.
IOBUFs are composites of IBUF and OBUFT elements. The O output is X (unknown)
when IO (input/output) is Z. IOBUFs can be implemented as interconnections of their
component elements.
The hardware implementation of the I/O standards requires that you follow a set of
usage rules for the buffers. See the Usage Rules section.
Inputs

Bidirectional

Outputs

IO

Available Attributes
Attach an IOSTANDARD attribute to an IOBUF and assign the value indicated in the
"IOSTANDARD (Attribute Value)" column to program the input for the I/O standard
associated with that value.
The LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33 attributes also require
a slew value (FAST or SLOW) and DRIVE value. See the FAST, SLOW, and DRIVE
attribute descriptions in the Xilinx Constraints Guide for valid values for Virtex-II,
Virtex-II Pro, and Virtex-II Pro X.

Libraries Guide
ISE 6.3i

www.xilinx.com
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689

IOBUF

Virtex-II, Virtex-II Pro, Virtex-II Pro X and IOSTANDARD Attributes

Architectures

Attribute Values

Spartan-II,
Virtex

Spartan-IIE,
Virtex-E

Termination
Type Input

LVTTL S_2 to F_24b

None

No

3.3

AGP

None

1.32

No

CTT

None

1.50

No

GTL

None

0.80

No

GTLP

None

1.00

No

HSTL_I

None

0.75

No

HSTL_III

None

0.90

1.5

HSTL_IV

None

0.90

No

LVCMOS2

IOSTANDARD

VREF

Input VCCO

None

No

2.5

LVCMOS18

None

No

1.8

LVDS

None

No

No

LVPECL

None

No

No

LVTTL (default)a

2, 4, 6, 8, 12, 16,
24

Fast/Slow

PCI33_3

None

No

3.3

PCI33_5

None

No

No

PCI66_3

PCIX66_3

None

None

No

3.3

None

No

3.3

SSTL2_I

None

1.25

No

SSTL2_II

None

1.25

No

SSTL3_I

None

1.50

No

SSTL3_II

None

1.50

No

Architectures
IOSTANDARD

Virtex-II
VirtexPro, VirtexII
II Pro X

Attribute Values
Drive

Slew

Terminate
Type
Output

Termination
Type
Input

VREF Output
Input * VCCO

Input
VCCO

AGP

No

No

None

None

1.32

3.3

No

GTL

No

No

None

None

0.80

No

No

GTL_DCI

No

No

Single

Single

0.80

1.2

1.2

GTLP

No

No

None

None

1.00

No

No

GTLP_DCI

No

No

Single

Single

1.00

1.5

1.5

HSTL_I

No

No

None

None

0.75

1.5

No

HSTL_I_18

No

No

None

None

0.9

1.8

No

HSTL_II_18

No

No

None

None

0.9

1.8

No

HSTL_II_DCI_
18

No

No

Split

Split

0.9

1.8

1.8

HSTL_III

No

No

None

None

0.9

1.5

No

HSTL_III_18

No

No

None

None

1.10

1.8

No

690

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Libraries Guide
ISE 6.3i

IOBUF

Architectures
IOSTANDARD

Virtex-II
VirtexPro, VirtexII
II Pro X

Attribute Values
Drive

Slew

Terminate
Type
Output

Termination
Type
Input

VREF Output
Input * VCCO

Input
VCCO

HSTL_IV

No

No

None

None

0.90

1.5

No

HSTL_IV_18

No

No

None

None

1.10

1.8

No

HSTL_IV_DCI

No

No

Single

Single

0.90

1.5

1.5

HSTL_IV_DCI_
18

No

No

Single

Single

1.1

1.8

1.8

2, 4, 6

Fast/Sl None
ow

None

No

1.2

1.2

LVCMOS12a
LVCMOS15a

2, 4, 6, 8, 12

Fast/Sl None
ow

None

No

1.5

1.5

LVCMOS18a

2, 4, 6, 8, 12, 16

Fast/Sl None
ow

None

No

1.8

1.8

LVCMOS25a

2, 4, 6, 8, 12, 16,
24

Fast/Sl None
ow

None

No

2.5

2.5

LVCMOS33a

2, 4, 6, 8, 12, 16,
24

Fast/Sl None
ow

None

No

3.3

3.3

LVDCI_15

No

No

Driver

None

No

1.5

1.5

LVDCI_18

No

No

Driver

None

No

1.8

1.8

LVDCI_25

No

No

Driver

None

No

2.5

2.5

LVDCI_33

No

No

Driver

None

No

3.3

3.3

LVDCI_DV2_1
5

No

No

Driver

None

No

1.5

1.5

LVDCI_DV2_1
8

No

No

Driver

None

No

1.8

1.8

LVDCI_DV2_2
5

No

No

Driver

None

No

2.5

2.5

LVDCI_DV2_3
3

No

No

Driver

None

No

3.3

3.3

LVTTL
(default)a

2, 4, 6, 8, 12, 16,
24

None

No

3.3

3.3

PCI33_3

No

No

None

None

No

3.3

3.3

PCI66_3

No

No

None

None

No

3.3

3.3

PCIX

No

No

None

None

No

3.3

3.3

SSTL18_I

No

No

None

None

0.9

1.8

No

SSTL18_II

No

No

None

None

0.9

1.8

No

SSTL18_II_DCI

No

No

Split

Split

0.9

1.8

1.8

SSTL2_II_DCI

SSTL3_II_DCI

SSTL2_I

SSTL2_II

SSTL3_I

Libraries Guide
ISE 6.3i

Fast/Sl None
ow

No

No

Split

Split

1.25

2.5

2.5

No

No

Split

Split

1.5

3.3

3.3

No

No

None

None

1.25

2.5

No

No

No

None

None

1.25

2.5

No

No

No

None

None

1.50

3.3

No

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691

IOBUF

Architectures
IOSTANDARD
SSTL3_II

Virtex-II
VirtexPro, VirtexII
II Pro X

Attribute Values
Drive

Slew

No

No

Terminate
Type
Output

Termination
Type
Input

None

None

VREF Output
Input * VCCO
1.50

3.3

Input
VCCO
No

* VREF requirement when this IOSTANDARD is an input.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- IOBUF: Single-ended Bi-directional Buffer
-All devices
-- Xilinx HDL Libraries Guide version 7.1i
IOBUF_inst : IOBUF
-- Edit the following generics to specify the I/O standard, drive and
slew rate.
generic map (
DRIVE => 12,
IOSTANDARD => "LVCMOS25",
SLEW => "SLOW")
port map (
O => O,
-- Buffer output
IO => IO,
-- Buffer inout port (connect directly to top-level
port)
I => I,
-- Buffer input
T => T
-- 3-state enable input
);

Verilog Instantiation Template

// IOBUF: Single-ended Bi-directional Buffer
//
All devices
// Xilinx HDL Libraries Guide version 7.1i
IOBUF IOBUF_inst
.O(O),
//
.IO(IO),
//
//
.I(I),
//
.T(T)
//
);

(
Buffer output
Buffer inout port (connect directly to
top-level port)
Buffer input
3-state enable input

// Edit the following defparams to specify the I/O standard, drive and
// slew rate. If the instance name is change, that change needs to be
// reflecting the this defparam.
defparam IOBUF_inst.DRIVE = 12;
defparam IOBUF_inst.IOSTANDARD = "LVCMOS25";
defparam IOBUF_inst.SLEW = "SLOW";
// End of IOBUF_inst instantiation

692

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Libraries Guide
ISE 6.3i

IOBUFDS

IOBUFDS
3-State Differential Signaling I/O Buffer with Active Low Output Enable
Architectures Supported
IOBUFDS
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

T
I

IO
IOB

No

CoolRunner XPLA3

No

CoolRunner-II

No

IOBUFDS is a single 3-state, differential signaling input/output buffer with active

Low output enable.
Bidirectional

Inputs

X9827

Outputs

IO

IOB

-*

* The dash (-) means No Change.

Available Attributes
BLVDS_25 is supported for IOSTANDARD. Attach an IOSTANDARD attribute to an
IOBUFDS and assign the value indicated in the "IOSTANDARD (Attribute Value)"
column to program the outputs for the I/O standard associated with that value.
Architectures
IOSTANDARD

Spartan-3

BLVDS_25

Attribute Values

Virtex-II

Virtex-II Pro,
Virtex-II Pro X

Termination
Type Input
None

VREF
Input *

Output
VCCO

Input
VCCO

No

2.5

No

* VREF requirement when this IOSTANDARD is an input.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

Libraries Guide
ISE 6.3i

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693

IOBUFDS

VHDL Instantiation Template

-- IOBUFDS: Differential Bi-directional Buffer
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
IOBUFDS_inst : IOBUFDS
-- Edit the following generics to specify the I/O standard, drive and
slew rate.
generic map (
DRIVE => 12,
IOSTANDARD => "LVDS_25",
SLEW => "SLOW")
port map (
O => O,
-- Buffer output
IO => IO,
-- Diff_p inout (connect directly to top-level port)
IOB => IOB, -- Diff_n inout (connect directly to top-level port)
I => I,
-- Buffer input
T => T
-- 3-state enable input
);

Verilog Instantiation Template

// IOBUFDS: Differential Bi-directional Buffer
//
Virtex-II/II-Pro, Spartan-3
// Xilinx HDL Libraries Guide version 7.1i
IOBUFDS IOBUFDS_inst (
.O(O),
// Buffer output
.IO(IO),
// Diff_p inout (connect directly to
// top-level port)
.IOB(IOB), // Diff_n inout (connect directly to
// top-level port)
.I(I),
// Buffer input
.T(T)
// 3-state enable input
);
// Edit the following defparams to specify the I/O standard, drive and
// slew rate. If the instance name is change, that change needs to be
// reflecting the this defparam.
defparam IOBUFDS_inst.DRIVE = 12;
defparam IOBUFDS_inst.IOSTANDARD = "LVDS_25";
defparam IOBUFDS_inst.SLEW = "SLOW";
// End of IOBUFDS_inst instantiation

694

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Libraries Guide
ISE 6.3i

IOPAD, 4, 8, 16

IOPAD, 4, 8, 16
Single- and Multiple-Input/Output Pads
Architectures Supported
IOPAD
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

IOPAD4, IOPAD8, IOPAD16

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

IOPAD

X10122

IOPAD4
IO0
IO1
IO2
IO3

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

IOPAD, IOPAD4, IOPAD8, and IOPAD16 are single and multiple input/output pads.
The IOPAD is a connection point from a device pin, used as a bidirectional signal, to a
PLD device. The IOPAD is connected internally to an input/output block (IOB),
which is configured by the software as a bidirectional block. Bidirectional blocks can
consist of any combination of a 3-state output buffer (such as OBUFT or OFDE) and
any available input buffer (such as IBUF or IFD). See the appropriate CAE tool
interface user guide for details on assigning pin location and identification.
Note: The LOC attribute cannot be used on IOPAD multiples.

X3838

IOPAD8
IO[7:0]
X3841

IOPAD16
IO[15:0]

X3845

Libraries Guide
ISE 6.3i

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695

IOPAD, 4, 8, 16

IO [7:0 ]

IO 0

IOPAD

IO 1

IOPAD

IO 2

IOPAD

IO 3

IOPAD

IO 4

IOPAD

IO 5

IOPAD

IO 6

IOPAD

IO 7

IOPAD

X 7854

IOPAD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II,

Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, it is not necessary to use these elements in the design. They will be added
automatically.

Commonly Used Constraints

IOBDELAY, PULLDOWN

696

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Libraries Guide
ISE 6.3i

IPAD, 4, 8, 16

IPAD, 4, 8, 16
Single- and Multiple-Input Pads
Architectures Supported
IPAD
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

IPAD4, IPAD8, IPAD16

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

IPAD
IPAD

X10124

IPAD4
I0
I1
I2
I3
X3837

IPAD, IPAD4, IPAD8, and IPAD16 are single and multiple input pads. The IPAD is a
connection point from a device pin used for an input signal to the PLD device. It is
connected internally to an input/output block (IOB), which is configured by the
software as an IBUF, IFD, or ILD. See the appropriate CAE tool interface user guide
for details on assigning pin location and identification.
For Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro
X, pads must be used to drive IBUF and IBUFG inputs. An IPAD can be inferred by
NGDBUILD if one is missing on an IBUF or IBUFG input.
Note: The LOC attribute cannot be used on IPAD multiples.

IPAD8
I[7:0]

X3840

IPAD16
I[15:0]

X3844

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ISE 6.3i

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697

IPAD, 4, 8, 16

I[7:0]

IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD

I0
I1
I2
I3
I4
I5
I6
I7
X7655

IPAD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II,

Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, it is not necessary to use these elements in the design. They will be added
automatically.

Commonly Used Constraints

IOBDELAY, PULLDOWN

698

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Libraries Guide
ISE 6.3i

JTAGPPC

JTAGPPC
JTAG Primitive for the Power PC
Architectures Supported
JTAGPPC
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

* Not supported for Virtex-II. Supported for Virtex-II

Pro and Virtex-II Pro X only.

The JTAGPPC block allows connection from the JTAG logic in the PPC405 core to the
JTAG logic of Virtex-II Pro and Virtex-II Pro X devices. The connections are made
through programmable routing and so the connection only exists after configuration.
Following is an example instantiation of the JTAGPPC block in Verilog:
JTAGPPC IJTAGPPC(.TDOTSPPC(TDO_TS_PPC),
.TDOPPC(TDO_PPC),.TMS(TMS_PPC),
.TDIPPC(TDI_PPC), .TCK(TCK_PPC));
PPC405 IPPC405 (
...
.JTGC405TCK (TCK_PPC),
.JTGC405TDI (TDI_PPC),
.JTGC405TMS (TMS_PPC),
.C405JTGTDO (TDO_PPC),
.C405JTGTDOEN (TDO_TS_PPC),
...
)

When the block is instantiated in this fashion, the instruction registers of the PPC405
and the Virtex-II Pro and Virtex-II Pro X devices are linked in series.
The following table lists the input and output pins for JTAGPPC.
Inputs

Outputs

TDOPPC

TCK

TDOTSPPC

TDIPPC
TMS

Usage
For HDL, this design element is instantiated rather than inferred.

Libraries Guide
ISE 6.3i

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699

JTAGPPC

VHDL Instantiation Template

-- Component Declaration for JTAGPPC should be placed
-- after architecture statement but before begin keyword
component JTAGPPC
port (TCK : out STD_ULOGIC;
TDIPPC : out STD_ULOGIC;
TMS : out STD_ULOGIC;
TDOPPC : in STD_ULOGIC;
TDOTSPPC : in STD_ULOGIC);
end component;
-- Component Attribute specification for JTAGPPC
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for JTAGPPC should be placed

-- in architecture after the begin keyword
JTAGPPC_INSTANCE_NAME : JTAGPPC
port map (TCK => user_TCK,
TDIPPC => user_TDIPPC,
TMS => user_TMS,
TDOPPC => user_TDOPPC,
TDOTSPPC => user_TDOTSPPC);

Verilog Instantiation Template

JTAGPPC JTAGPPC_instance_name (.TCK (user_TCK),
.TDIPPC (user_TDIPPC),
.TMS (user_TMS),
.TDOPPC (user_TDOPPC),
.TDOTSPPC (user_TDOTSPPC));

700

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Libraries Guide
ISE 6.3i

KEEPER

KEEPER
KEEPER Symbol
Architectures Supported
KEEPER
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive

XC9500, XC9500XV, XC9500XL

Primitive*

CoolRunner XPLA3

No

CoolRunner-II

Primitive

* Supported for only XC9500XL and XC9500XV.

KEEPER is a weak keeper element used to retain the value of the net connected to its
bidirectional O pin. For example, if a logic 1 is being driven onto the net, KEEPER
drives a weak/resistive 1 onto the net. If the net driver is then 3-stated, KEEPER
continues to drive a weak/resistive 1 onto the net.
For additional information on using a KEEPER element with SelectIO components,
see the Usage Rules section in IBUF, 4, 8, 16.

O
X8718

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- KEEPER: I/O Buffer Weak Keeper
-All FPGA, CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
KEEPER_inst : KEEPER
port map (
O => O
-- Keeper output (connect directly to top-level port)
);
-- End of KEEPER_inst instantiation

Verilog Instantiation Template

// KEEPER: I/O Buffer Weak Keeper
//
All FPGA, CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
KEEPER KEEPER_inst (
.O(O),
// Keeper output (connect directly to top-level port)
);
// End of KEEPER_inst instantiation

Libraries Guide
ISE 6.3i

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701

702

KEEPER

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Libraries Guide
ISE 6.3i

LD

LD
Transparent Data Latch
Architectures Supported
LD
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LD

Macro

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

LD is a transparent data latch. The data output (Q) of the latch reflects the data (D)
input while the gate enable (G) input is High. The data on the D input during the
High-to-Low gate transition is stored in the latch. The data on the Q output remains
unchanged as long as G remains Low.

The latch is asynchronously cleared, output Low, when power is applied.

X3740

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

No Chg

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703

LD

G
D

FDCP
AND2
D

PRE

C
CLR

AND2B1

GND

X7855

LD Implementation XC9500/XV/XL

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for LD should be placed
-- after architecture statement but before begin keyword
component LD
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC);
end component;
-- Component Attribute specification for LD
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LD_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LD should be placed

-- in architecture after the begin keyword
LD_INSTANCE_NAME : LD
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
D => user_D,
G => user_G);

704

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Libraries Guide
ISE 6.3i

LD

Verilog Instantiation Template

LD LD_instance_name (.Q (user_Q),
.D (user_D),
.G (user_G));
defparam LD_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

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ISE 6.3i

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705

706

LD

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Libraries Guide
ISE 6.3i

LD4, 8, 16

LD4, 8, 16
Multiple Transparent Data Latches
Architectures Supported
LD4, LD8, LD16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D0

LD4

Q0

D1

Q1

D2

Q2

D3

Q3

X4611

D[7:0]

LD8

Q[7:0]

X4612

D[15:0]

LD16

Q[15:0]

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

LD4, LD8, and LD16 have, respectively, 4, 8, and 16 transparent data latches with a
common gate enable (G). The data output (Q) of the latch reflects the data (D) input
while the gate enable (G) input is High. The data on the D input during the High-toLow gate transition is stored in the latch. The data on the Q output remains
unchanged as long as G remains Low.
The latch is asynchronously cleared, output Low, when power is applied, or when
global reset is active.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
See LD for information on single transparent data latches.

Inputs

Outputs

X4613

Libraries Guide
ISE 6.3i

No Chg

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707

LD4, 8, 16

Q[7:0]

LD

LD
D0

Q0

D4

Q4

Q0
LD

LD
D1

Q1

D5

Q5

Q1
LD

LD
D

Q2

D6

Q6

Q2
LD

LD
D

Q3

D7

Q7

G
D[7:0]

Q6

D3

Q5

D2

Q4

Q7

Q3

X9470

LD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

708

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Libraries Guide
ISE 6.3i

LD_1

LD_1
Transparent Data Latch with Inverted Gate
Architectures Supported
LD_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LD_1

No

CoolRunner XPLA3

No

CoolRunner-II

No

LD_1 is a transparent data latch with an inverted gate. The data output (Q) of the latch
reflects the data (D) input while the gate enable (G) input is Low. The data on the D
input during the Low-to-High gate transition is stored in the latch. The data on the Q
output remains unchanged as long as G remains High.
The latch is asynchronously cleared with Low output when power is applied, or when
global reset is active.

X3741

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for LD_1 should be placed
-- after architecture statement but before begin keyword
component LD_1

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ISE 6.3i

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709

LD_1

-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC);
end component;
-- Component Attribute specification for LD_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LD_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LD_1 should be placed

-- in architecture after the begin keyword
LD_1_INSTANCE_NAME : LD_1
-- synthesis translate_off
generic map(
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
D => user_D,
G => user_G);

Verilog Instantiation Template

LD_1 LD_1_instance_name (.Q (user_Q),
.D (user_D),
.G (user_G));
defparam LD_1_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

710

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Libraries Guide
ISE 6.3i

LDC

LDC
Transparent Data Latch with Asynchronous Clear
Architectures Supported
LDC
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LDC

CLR
X4070

Macro

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

LDC is a transparent data latch with asynchronous clear. When the asynchronous
clear input (CLR) is High, it overrides the other inputs and resets the data (Q) output
Low. Q reflects the data (D) input while the gate enable (G) input is High and CLR is
Low. The data on the D input during the High-to-Low gate transition is stored in the
latch. The data on the Q output remains unchanged as long as G remains low.
The latch is asynchronously cleared with Low output when power is applied, or when
global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for LDC should be placed
-- after architecture statement but before begin keyword

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ISE 6.3i

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711

LDC

component LDC
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDC
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDC_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDC should be placed

-- in architecture after the begin keyword
LDC_INSTANCE_NAME : LDC
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
CLR => user_CLR,
D => user_D,
G => user_G);

Verilog Instantiation Template

LDC LDC_instance_name (.Q (user_Q),
.CLR (user_CLR),
.D (user_D),
.G (user_G));
defparam LDC_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

712

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Libraries Guide
ISE 6.3i

LDC_1

LDC_1
Transparent Data Latch with Asynchronous Clear and Inverted Gate
Architectures Supported
LDC_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LDC_1

CLR
X3752

No

CoolRunner XPLA3

No

CoolRunner-II

No

LDC_1 is a transparent data latch with asynchronous clear and inverted gate. When
the asynchronous clear input (CLR) is High, it overrides the other inputs (D and G)
and resets the data (Q) output Low. Q reflects the data (D) input while the gate enable
(G) input and CLR are Low. The data on the D input during the Low-to-High gate
transition is stored in the latch. The data on the Q output remains unchanged as long
as G remains High.
The latch is asynchronously cleared with Low output when power is applied, or when
global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Libraries Guide
ISE 6.3i

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713

LDC_1

VHDL Instantiation Template

-- Component Declaration for LDC_1 should be placed
-- after architecture statement but before begin keyword
component LDC_1
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDC_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDC_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDC_1 should be placed

-- in architecture after the begin keyword
LDC_1_INSTANCE_NAME : LDC_1
-- synthesis translate_off
generic map(
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
CLR => user_CLR,
D => user_D,
G => user_G);

Verilog Instantiation Template

LDC_1 LDC_1_instance_name (.Q (user_Q),
.CLR (user_CLR),
.D (user_D),
.G (user_G));
defparam LDC_1_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

714

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Libraries Guide
ISE 6.3i

LDCE

LDCE
Transparent Data Latch with Asynchronous Clear and Gate Enable
Architectures Supported
LDCE
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LDCE

GE
G

CLR
X4979

No

CoolRunner XPLA3

No

CoolRunner-II

No

LDCE is a transparent data latch with asynchronous clear and gate enable. When the
asynchronous clear input (CLR) is High, it overrides the other inputs and resets the
data (Q) output Low. Q reflects the data (D) input while the gate (G) input and gate
enable (GE) are High and CLR is Low. If GE is Low, data on D cannot be latched. The
data on the D input during the High-to-Low gate transition is stored in the latch. The
data on the Q output remains unchanged as long as G or GE remains low.
The latch is asynchronously cleared with Low output when power is applied, or when
global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

GE

No Chg

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Libraries Guide
ISE 6.3i

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715

LDCE

VHDL Instantiation Template

-- Component Declaration for LDCE should be placed
-- after architecture statement but before begin keyword
component LDCE
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC;
GE : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDCE
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDCE_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDCE should be placed

-- in architecture after the begin keyword
LDCE_INSTANCE_NAME : LDCE
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
CLR => user_CLR,
D => user_D,
G => user_G,
GE => user_GE);

Verilog Instantiation Template

LDCE LDCE_instance_name (.Q (user_Q),
.CLR (user_CLR),
.D (user_D),
.G (user_G),
.GE (user_GE));
defparam LDCE_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

716

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Libraries Guide
ISE 6.3i

LDCE_1

LDCE_1
Transparent Data Latch with Asynchronous Clear, Gate Enable, and
Inverted Gate
Architectures Supported
LDCE_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LDCE_1

GE
G

CLR
X4930

No

CoolRunner XPLA3

No

CoolRunner-II

No

LDCE_1 is a transparent data latch with asynchronous clear, gate enable, and inverted
gate. When the asynchronous clear input (CLR) is High, it overrides the other inputs
and resets the data (Q) output Low. Q reflects the data (D) input while the gate (G)
input and CLR are Low and gate enable (GE) is High. The data on the D input during
the Low-to-High gate transition is stored in the latch. The data on the Q output
remains unchanged as long as G remains High or GE remains Low.
The latch is asynchronously cleared with Low output when power is applied, or when
global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

GE

No Chg

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Libraries Guide
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717

LDCE_1

VHDL Instantiation Template

-- Component Declaration for LDCE_1 should be placed
-- after architecture statement but before begin keyword
component LDCE_1
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC;
GE : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDCE_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDCE_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDCE_1 should be placed

-- in architecture after the begin keyword
LDCE_1_INSTANCE_NAME : LDCE_1
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
CLR => user_CLR,
D => user_D,
G => user_G,
GE => user_GE);

Verilog Instantiation Template

LDCE_1 LDCE_1_instance_name (.Q (user_Q),
.CLR (user_CLR),
.D (user_D),
.G (user_G),
.GE (user_GE));
defparam LDCE_1_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

718

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Libraries Guide
ISE 6.3i

LD4CE, LD8CE, LD16CE

LD4CE, LD8CE, LD16CE

Transparent Data Latches with Asynchronous Clear and Gate Enable
Architectures Supported
LD4CE, LD8CE, LD16CE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

LD4CE

D0

Q1

D2

Q2

D3

Q3

CoolRunner XPLA3

No

CoolRunner-II

No

LD4CE, LD8CE, and LD16CE have, respectively, 4, 8, and 16 transparent data latches
with asynchronous clear and gate enable. When the asynchronous clear input (CLR) is
High, it overrides the other inputs and resets the data (Q) outputs Low. Q reflects the
data (D) inputs while the gate (G) and gate enable (GE) are High, and CLR is Low. If
GE is Low, data on D cannot be latched. The data on the D input during the High-toLow gate transition is stored in the latch. The data on the Q output remains
unchanged as long as G or GE remains Low.

Q0

D1

No

GE
G

CLR
X6947

The latch is asynchronously cleared with Low output when power is applied, or when
global reset is active.
D[7:0]

LD8CE

Q[7:0]

GE

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

CLR
X6948

Inputs

Outputs

CLR

GE

Dn

Qn

GE

No Chg

No Chg

Dn

Dn

D[15:0]

LD16CE

Q[15:0]

CLR
X6949

Dn = referenced input, for example, D0, D1, D2

Qn = referenced output, for example, Q0, Q1, Q2

Libraries Guide
ISE 6.3i

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719

LD4CE, LD8CE, LD16CE

LDCE
D0

Q0

D
Q
GE
G
CLR
Q0
LDCE

D1

Q1

D
Q
GE
G
CLR
Q1
LDCE

D2

Q2

D
Q
GE
G
CLR
Q2
LDCE

D3
GE
G

Q3

D
Q
GE
G
CLR

CLR

Q3
X6538

LD4CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Q[7:0]
LDCE

LDCE
D0

D
GE
G

Q0

D4

D
GE
G

CLR

CLR

Q0

Q4
LDCE

LDCE
D1

D
GE
G

Q1

D5

D
GE
G

CLR

D
GE
G

Q5
LDCE

Q2

D6

D
GE
G

CLR

Q6
LDCE

LDCE
D
GE
G

Q3

D7

D
GE
G

CLR
Q3

D[7:0]

Q6

CLR

Q2
D3

Q5

CLR

Q1
LDCE
D2

Q4

Q7

CLR
Q7

GE
G
CLR
X6385

LD8CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are supported for inference only.

720

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Libraries Guide
ISE 6.3i

LDCP

LDCP
Transparent Data Latch with Asynchronous Clear and Preset
Architectures Supported
LDCP
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

LDCP
Q

CLR
X8369

Macro

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

LDCP is a transparent data latch with data (D), asynchronous clear (CLR) and preset
(PRE) inputs. When CLR is High, it overrides the other inputs and resets the data (Q)
output Low. When PRE is High and CLR is low, it presets the data (Q) output High. Q
reflects the data (D) input while the gate (G) input is High and CLR and PRE are Low.
The data on the D input during the High-to-Low gate transition is stored in the latch.
The data on the Q output remains unchanged as long as G remains Low.
The latch is asynchronously cleared, output Low, when power is applied, or when
global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

PRE

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Libraries Guide
ISE 6.3i

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1-800-255-7778

721

LDCP

VHDL Instantiation Template

-- Component Declaration for LDCP should be placed
-- after architecture statement but before begin keyword
component LDCP
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDCP
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDCP_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDCP should be placed

-- in architecture after the begin keyword
LDCP_INSTANCE_NAME : LDCP
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
CLR => user_CLR,
D => user_D,
G => user_G,
PRE => user_PRE);

Verilog Instantiation Template

LDCP LDCP_instance_name (.Q (user_Q),
.CLR (user_CLR),
.D (user_D),
.G (user_G),
.PRE (user_PRE));
defparam LDCP_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

722

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Libraries Guide
ISE 6.3i

LDCP_1

LDCP_1
Transparent Data Latch with Asynchronous Clear and Preset and
Inverted Gate
Architectures Supported
LDCP_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

LDCP_1
Q

CLR
X8370

No

CoolRunner XPLA3

No

CoolRunner-II

No

LDCP_1 is a transparent data latch with data (D), asynchronous clear (CLR), preset
(PRE) inputs, and inverted gate (G). When CLR is High, it overrides the other inputs
and resets the data (Q) output Low. When PRE is High and CLR is Low, it presets the
data (Q) output High. Q reflects the data (D) input while gate (G) input, CLR, and
PRE are Low. The data on the D input during the Low-to-High gate transition is
stored in the latch. The data on the Q output remains unchanged as long as G remains
High.
The latch is asynchronously cleared, output Low, when power is applied, or when
global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

PRE

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Libraries Guide
ISE 6.3i

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723

LDCP_1

VHDL Instantiation Template

-- Component Declaration for LDCP_1 should be placed
-- after architecture statement but before begin keyword
component LDCP_1
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDCP_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDCP_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDCP_1 should be placed

-- in architecture after the begin keyword
LDCP_1_INSTANCE_NAME : LDCP_1
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
CLR => user_CLR,
D => user_D,
G => user_G,
PRE => user_PRE);

Verilog Instantiation Template

LDCP_1 LDCP_1_instance_name (.Q (user_Q),
.CLR (user_CLR),
.D (user_D),
.G (user_G),
.PRE (user_PRE));
defparam LDCP_1_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

724

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Libraries Guide
ISE 6.3i

LDCPE

LDCPE
Transparent Data Latch with Asynchronous Clear and Preset and Gate
Enable
Architectures Supported
LDCPE
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

LDCPE
Q

GE
G

CLR
X8371

No

CoolRunner XPLA3

No

CoolRunner-II

No

LDCPE is a transparent data latch with data (D), asynchronous clear (CLR),
asynchronous preset (PRE), and gate enable (GE). When CLR is High, it overrides the
other inputs and resets the data (Q) output Low. When PRE is High and CLR is Low, it
presets the data (Q) output High. Q reflects the data (D) input while the gate (G) input
and gate enable (GE) are High and CLR and PRE are Low. The data on the D input
during the High-to-Low gate transition is stored in the latch. The data on the Q output
remains unchanged as long as G or GE remains Low.
The latch is asynchronously cleared, output Low, when power is applied, or when
global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

PRE

GE

No Chg

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

725

LDCPE

VHDL Instantiation Template

-- Component Declaration for LDCPE should be placed
-- after architecture statement but before begin keyword
component LDCPE
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC;
GE : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDCPE
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDCPE_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDCPE should be placed

-- in architecture after the begin keyword
LDCPE_INSTANCE_NAME : LDCPE
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
CLR => user_CLR,
D => user_D,
G => user_G,
GE => user_GE,
PRE => user_PRE);

Verilog Instantiation Template

LDCPE LDCPE_instance_name (.Q (user_Q),
.CLR (user_CLR),
.D (user_D),
.G (user_G),
.GE (user_D),
.PRE (user_PRE));
defparam LDCPE_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

726

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Libraries Guide
ISE 6.3i

LDCPE_1

LDCPE_1
Transparent Data Latch with Asynchronous Clear and Preset, Gate
Enable, and Inverted Gate
Architectures Supported
LDCPE_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

LDCPE_1
Q

GE
G

CLR
X8372

No

CoolRunner XPLA3

No

CoolRunner-II

No

LDCPE_1 is a transparent data latch with data (D), asynchronous clear (CLR),
asynchronous preset (PRE), gate enable (GE), and inverted gate (G). When CLR is
High, it overrides the other inputs and resets the data (Q) output Low. When PRE is
High and CLR is Low, it presets the data (Q) output High. Q reflects the data (D) input
while gate enable (GE) is High and gate (G), CLR, and PRE are Low. The data on the D
input during the Low-to-High gate transition is stored in the latch. The data on the Q
output remains unchanged as long as G is High or GE is Low.
The latch is asynchronously cleared, output Low, when power is applied, or when
global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

PRE

GE

No Chg

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

727

LDCPE_1

VHDL Instantiation Template

-- Component Declaration for LDCPE_1 should be placed
-- after architecture statement but before begin keyword
component LDCPE_1
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC;
GE : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDCPE_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDCPE_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDCPE_1 should be placed

-- in architecture after the begin keyword
LDCPE_1_INSTANCE_NAME : LDCPE_1
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
CLR => user_CLR,
D => user_D,
G => user_G,
GE => user_GE,
PRE => user_PRE);

Verilog Instantiation Template

LDCPE_1 LDCPE_1_instance_name (.Q (user_Q),
.CLR (user_CLR),
.D (user_D),
.G (user_G),
.GE (user_D),
.PRE (user_PRE));
defparam LDCPE_1_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

728

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Libraries Guide
ISE 6.3i

LDE

LDE
Transparent Data Latch with Gate Enable
Architectures Supported
LDE
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LDE

GE

No

CoolRunner XPLA3

No

CoolRunner-II

No

LDE is a transparent data latch with data (D) and gate enable (GE) inputs. Output Q
reflects the data (D) while the gate (G) input and gate enable (GE) are High. The data
on the D input during the High-to-Low gate transition is stored in the latch. The data
on the Q output remains unchanged as long as G or GE remains Low.
The latch is asynchronously cleared, output Low, when power is applied, or when
global reset is active.

X8373

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

GE

No Chg

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for LDE should be placed
-- after architecture statement but before begin keyword
component LDE

Libraries Guide
ISE 6.3i

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729

LDE

-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC;
GE : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDE
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDE_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDE should be placed

-- in architecture after the begin keyword
LDE_INSTANCE_NAME : LDE
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
D => user_D,
G => user_G,
GE => user_GE);

Verilog Instantiation Template

LDE LDE_instance_name (.Q (user_Q),
.D (user_D),
.G (user_G),
.GE (user_GE));
defparam LDE_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

730

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Libraries Guide
ISE 6.3i

LDE_1

LDE_1
Transparent Data Latch with Gate Enable and Inverted Gate
Architectures Supported
LDE_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LDE_1

GE

X8374

No

CoolRunner XPLA3

No

CoolRunner-II

No

LDE_1 is a transparent data latch with data (D), gate enable (GE), and inverted gate
(G). Output Q reflects the data (D) while the gate (G) input is Low and gate enable
(GE) is High. The data on the D input during the Low-to-High gate transition is stored
in the latch. The data on the Q output remains unchanged as long as G is High or GE
is Low.
The latch is asynchronously cleared, output Low, when power is applied, or when
global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

GE

No Chg

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for LDE_1 should be placed
-- after architecture statement but before begin keyword

Libraries Guide
ISE 6.3i

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731

LDE_1

component LDE_1
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC;
GE : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDE_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDE_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDE_1 should be placed

-- in architecture after the begin keyword
LDE_1_INSTANCE_NAME : LDE_1
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
D => user_D,
G => user_G,
GE => user_GE);

Verilog Instantiation Template

LDE_1 LDE_1_instance_name (.Q (user_Q),
.D (user_D),
.G (user_G),
.GE (user_GE));
defparam LDE_1_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

732

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Libraries Guide
ISE 6.3i

LDG

LDG
Transparent Datagate Latch
Architectures Supported
LDG
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

LDG

X9813

No

CoolRunner XPLA3

No

CoolRunner-II

Primitive

LDG is a transparent DataGate latch used for gating input signals to decrease power
dissipation. The data output (Q) of the latch reflects the data (D) input while the gate
enable (G) input is Low. The data on the D input during the Low-to-High gate
transition is stored in the latch. The data on the Q output remains unchanged as long
as G remains High.
The D input(s) of the LDG must be connected to a device input pad(s) and must have
no other fan-outs (must not branch). The CPLD fitter maps the G input to the device's
DataGate Enable control pin (DGE). There must be no more than one DataGate Enable
signal in the design. The DataGate Enable signal may be driven either by a device
input pin or any on-chip logic source. The DataGate Enable signal may be reused by
other ordinary logic in the design.
The latch is asynchronously cleared, output Low, when power is applied, or when
global reset is active. For CPLDs, the power-on condition can be simulated by
applying a High-level pulse on the PRLD global net. See LDG4, 8, 16 for
information on multiple transparent datagate latches for the CoolRunner-II series.
Inputs

Outputs

No Chg

Usage
For HDL, these design elements are supported for inference and instantiation.

VHDL Instantiation Template

component LDG
port (Q : out STD_ULOGIC;
D : in STD_ULOGIC;

Libraries Guide
ISE 6.3i

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733

LDG

G : in STD_ULOGIC);
end component;
...
begin
...
INSTANCE_NAME : LDG
port map (Q => user_Q,
D => user_D,
G => user_G);

Verilog Instantiation Template

LDG instance_name (.Q (user_Q),
.D (user_D),
.G (user_G));

734

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Libraries Guide
ISE 6.3i

LDG4, 8, 16

LDG4, 8, 16
Multiple Transparent Datagate Latches
Architectures Supported
LDG4, LDG8, LDG16
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

D0

LDG4

Q1

D2

Q2

D3

Q3

CoolRunner XPLA3

No

CoolRunner-II

Macro

LDG4, LDG8, and LDG16 have, respectively, 4, 8, and 16 transparent DataGate latches
with a common gate enable (G). These latches are used to gate input signals in order
to decrease power dissipation during periods when activity on the input pins is not of
interest to the CPLD. The data output (Q) of the latch reflects the data (D) input while
the gate enable (G) input is Low. The data on the D input during the Low-to-High gate
transition is stored in the latch. The data on the Q output remains unchanged as long
as G remains High.

Q0

D1

No

X9809

D[7:0]

LDG8

Q[7:0]

The D input(s) of the LDG must be connected to a device input pad(s) and must have
no other fan-outs (must not branch). The CPLD fitter maps the G input to the device's
DataGate Enable control pin (DGE). There must be no more than one DataGate Enable
signal in the design. The DataGate Enable signal may be driven either by a device
input pin or any on-chip logic source. The DataGate Enable signal may be reused by
other ordinary logic in the design.
The latch is asynchronously cleared, output Low, when power is applied. See LDG
for information on single transparent data latches.

X9810

Inputs

D[15:0]

LDG16

Q[15:0]

Outputs

No Chg

X9811

Libraries Guide
ISE 6.3i

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735

LDG4, 8, 16

Q[7:0]

LDG

LDG
D0

Q0

D4

Q4

Q0
LDG

LDG
D1

Q1

D5

Q5

Q1
LDG

LDG
D

Q2

D6

Q6

Q2
LDG

LDG
D

Q3

D7

Q7

G
D[7:0]

Q6

D3

Q5

D2

Q4

Q7

Q3

X9812

LDG8 Implementation

736

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Libraries Guide
ISE 6.3i

LDP

LDP
Transparent Data Latch with Asynchronous Preset
Architectures Supported
LDP
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

LDP
Q

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

LDP is a transparent data latch with asynchronous preset (PRE). When the PRE input
is High, it overrides the other inputs and presets the data (Q) output High. Q reflects
the data (D) input while gate (G) input is High and PRE is Low. The data on the D
input during the High-to-Low gate transition is stored in the latch. The data on the Q
output remains unchanged as long as G remains Low.
The latch is asynchronously preset, output High, when power is applied.

X8375

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

PRE

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for LDP should be placed
-- after architecture statement but before begin keyword
component LDP

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ISE 6.3i

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737

LDP

-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDP
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDP_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDP should be placed

-- in architecture after the begin keyword
LDP_INSTANCE_NAME : LDP
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
D => user_D,
G => user_G,
PRE => user_PRE);

Verilog Instantiation Template

LDP LDP_instance_name (.Q (user_Q),
.D (user_D),
.G (user_G),
.PRE (user_PRE));
defparam LDP_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

738

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Libraries Guide
ISE 6.3i

LDP_1

LDP_1
Transparent Data Latch with Asynchronous Preset and Inverted Gate
Architectures Supported
LDP_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

LDP_1
Q

No

CoolRunner XPLA3

No

CoolRunner-II

No

LDP_1 is a transparent data latch with asynchronous preset (PRE) and inverted gate
(G). When the PRE input is High, it overrides the other inputs and presets the data (Q)
output High. Q reflects the data (D) input while gate (G) input and PRE are Low. The
data on the D input during the Low-to-High gate transition is stored in the latch. The
data on the Q output remains unchanged as long as G remains High.
The latch is asynchronously preset, output High, when power is applied.

X8376

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

PRE

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for LDP_1 should be placed
-- after architecture statement but before begin keyword
component LDP_1

Libraries Guide
ISE 6.3i

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739

LDP_1

-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDP_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDP_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDP_1 should be placed

-- in architecture after the begin keyword
LDP_1_INSTANCE_NAME : LDP_1
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
D => user_D,
G => user_G,
PRE => user_PRE);

Verilog Instantiation Template

LDP_1 LDP_1_instance_name (.Q (user_Q),
.D (user_D),
.G (user_G),
.PRE (user_PRE));
defparam LDP_1_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

740

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Libraries Guide
ISE 6.3i

LDPE

LDPE
Transparent Data Latch with Asynchronous Preset and Gate Enable
Architectures Supported
LDPE
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

LDPE

GE
G

X6954

No

CoolRunner XPLA3

No

CoolRunner-II

No

LDPE is a transparent data latch with asynchronous preset and gate enable. When the
asynchronous preset (PRE) is High, it overrides the other input and presets the data
(Q) output High. Q reflects the data (D) input while the gate (G) input and gate enable
(GE) are High. The data on the D input during the High-to-Low gate transition is
stored in the latch. The data on the Q output remains unchanged as long as G or GE
remains Low.
The latch is asynchronously preset, output High, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

PRE

GE

No Chg

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

VHDL Instantiation Template

-- Component Declaration for LDPE should be placed
-- after architecture statement but before begin keyword

Libraries Guide
ISE 6.3i

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741

LDPE

component LDPE
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC;
GE : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDPE
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDPE_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDPE should be placed

-- in architecture after the begin keyword
LDPE_INSTANCE_NAME : LDPE
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
D => user_D,
G => user_G,
GE => user_GE,
PRE => user_PRE);

Verilog Instantiation Template

LDPE LDPE_instance_name (.Q (user_Q),
.D (user_D),
.G (user_G),
.GE (user_GE),
.PRE (user_PRE));
defparam LDPE_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

742

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Libraries Guide
ISE 6.3i

LDPE_1

LDPE_1
Transparent Data Latch with Asynchronous Preset, Gate Enable, and
Inverted Gate
Architectures Supported
LDPE_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE

LDPE_1

GE
G
X7573

No

CoolRunner XPLA3

No

CoolRunner-II

No

LDPE_1 is a transparent data latch with asynchronous preset, gate enable, and
inverted gate. When the asynchronous preset (PRE) is High, it overrides the other
input and presets the data (Q) output High. Q reflects the data (D) input while the
gate (G) and PRE are Low and gate enable (GE) is High.
The data on the D input during the Low-to-High gate transition is stored in the latch.
The data on the Q output remains unchanged as long as G remains High or GE
remains Low.
The latch is asynchronously preset, output High, when power is applied.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

PRE

GE

No Chg

No Chg

Usage
This design element typically should be inferred in the design code; however, the
element can be instantiated for cases where strict placement control, relative
placement control, or initialization attributes need to be applied.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

743

LDPE_1

VHDL Instantiation Template

-- Component Declaration for LDPE_1 should be placed
-- after architecture statement but before begin keyword
component LDPE_1
-- synthesis translate_off
generic (
INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
D : in STD_ULOGIC;
G : in STD_ULOGIC;
GE : in STD_ULOGIC;
PRE : in STD_ULOGIC);
end component;
-- Component Attribute specification for LDPE_1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LDPE_1_instance_name : label is "0";
-- values can be (0 or 1)

-- Component Instantiation for LDPE_1 should be placed

-- in architecture after the begin keyword
LDPE_1_INSTANCE_NAME : LDPE_1
-- synthesis translate_off
generic map (
INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
D => user_D,
G => user_G,
GE => user_GE,
PRE => user_PRE);

Verilog Instantiation Template

LDPE_1 LDPE_1_instance_name (.Q (user_Q),
.D (user_D),
.G (user_G),
.GE (user_GE),
.PRE (user_PRE));
defparam LDPE_1_instance_name.INIT = bit_value;

Commonly Used Constraints

INIT

744

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Libraries Guide
ISE 6.3i

LUT1, 2, 3, 4

LUT1, 2, 3, 4
1-, 2-, 3-, 4-Bit Look-Up-Table with General Output
Architectures Supported
LUT1, LUT2, LUT3, LUT4
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL
CoolRunner XPLA3

No

CoolRunner-II

No

LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables
(LUTs) with general output (O).

LUT1
O

A mandatory INIT attribute, with an appropriate number of hexadecimal digits for

the number of inputs, must be attached to the LUT to specify its function.

I0

X9852

I1

No

LUT1 provides a look-up-table version of a buffer or inverter.

LUT2
O

I0

X8379

LUTs are the basic Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, Spartan-II,
Spartan-IIE, and Spartan-3 building blocks. Two LUTs are available in each CLB slice;
four LUTs are available in each CLB. The variants, LUT1_D, LUT2_D, LUT3_D,
LUT4_D and LUT1_L, LUT2_L, LUT3_L, LUT4_L provide additional types of
outputs that can be used by different timing models for more accurate pre-layout
timing estimation.
LUT3 Function Table

I2

LUT3

Inputs

I1
O

I0

X8382

I3

LUT4

I2
O

Outputs

I2

I1

I0

INIT[0]

INIT[1]

INIT[2]

INIT[3]

INIT[4]

INIT[5]

INIT[6]

INIT[7]

I1
I0

X8385

INIT = binary equivalent of the hexadecimal number assigned to the INIT attribute

Usage
LUTs are generally inferred with the logic portions of the HDL code. Xilinx suggests
that you instantiate LUTs only if you have a need to implicitly specify the logic
mapping, or if you need to manually place or relationally place the logic.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

745

LUT1, 2, 3, 4

VHDL Instantiation Template for LUT1

-- Component Declaration for LUT1 should be placed
-- after architecture statement but before begin keyword
component LUT1
-- synthesis translate_off
generic (
INIT : bit_vector := X"2");
-- synthesis translate_on
port (O : out STD_ULOGIC;
IO : in STD_ULOGIC);
end component;
-- Component Attribute specification for LUT1
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LUT1_instance_name : label is "2";
-- values can be 0, 1, 2,or 3
-- Component Instantiation for LUT1 should be placed
-- in architecture after the begin keyword
LUT1_INSTANCE_NAME : LUT1
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (O => user_O,
IO => user_IO);

Verilog Instantiation Template For LUT1

LUT1 LUT1_instance_name (.O (user_O),
.IO (user_IO));
defparam LUT1_instance_name.INIT = hex_value;

VHDL Instantiation Template for LUT2

-- Component Declaration for LUT2 should be placed
-- after architecture statement but before begin keyword
component LUT2
-- synthesis translate_off
generic (
INIT : bit_vector := X"4");
-- synthesis translate_on
port (O : out STD_ULOGIC;
IO : in STD_ULOGIC;
I1 : in STD_ULOGIC);
end component;
-- Component Attribute specification for LUT2
-- should be placed after architecture declaration but
-- before the begin keyword

746

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Libraries Guide
ISE 6.3i

LUT1, 2, 3, 4

attribute INIT : string;

attribute INIT of LUT2_instance_name : label is "4";
-- values can be 0, 1, 2,3, or 4
-- Component Instantiation for LUT2 should be placed
-- in architecture after the begin keyword
LUT2_INSTANCE_NAME : LUT2
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (O => user_O,
I0 => user_I0,
I1 => user_I1);

Verilog Instantiation Template For LUT2

LUT2 LUT2_instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1));
defparam LUT2_instance_name.INIT = hex_value;

VHDL Instantiation Template for LUT3

-- Component Declaration for LUT3 should be placed
-- after architecture statement but before begin keyword
component LUT3
-- synthesis translate_off
generic (
INIT : bit_vector := X"8");
-- synthesis translate_on
port (O : out STD_ULOGIC;
IO : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC);
end component;
-- Component Attribute specification for LUT3
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LUT3_instance_name : label is "8";
-- values can be 0, 1, 2, 3, 4, 5, 6, 7, 8
-- Component Instantiation for LUT3 should be placed
-- in architecture after the begin keyword -LUT3_INSTANCE_NAME : LUT3
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (O => user_O,

Libraries Guide
ISE 6.3i

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747

LUT1, 2, 3, 4

I0 => user_I0,
I1 => user_I1,
I2 => user_I2);

Verilog Instantiation Template For LUT3

LUT3 LUT3_instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.I2 (user_I2));
defparam LUT4_instance_name.INIT = hex_value;

VHDL Instantiation Template for LUT4

-- Component Declaration for LUT4 should be placed
-- after architecture statement but before begin keyword
component LUT4
-- synthesis translate_off
generic (
INIT : bit_vector := X"16");
-- synthesis translate_on
port (O : out STD_ULOGIC;
IO : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC;
I3 : in STD_ULOGIC);
end component;
-- Component Attribute specification for LUT4
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LUT4_instance_name : label is "16";
-- values can be 0 through 16
-- Component Instantiation for LUT4 should be placed
-- in architecture after the begin keyword
LUT4_INSTANCE_NAME : LUT4
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2,
I3 => user_I3);

Verilog Instantiation Template For LUT4

LUT4 LUT4_instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.I2 (user_I2),

748

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Libraries Guide
ISE 6.3i

LUT1, 2, 3, 4

.I3 (user_I3));
defparam LUT4_instance_name.INIT = hex_value;

Commonly Used Constraints

BEL, INIT, LOC, U_SET

Libraries Guide
ISE 6.3i

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1-800-255-7778

749

750

LUT1, 2, 3, 4

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1-800-255-7778

Libraries Guide
ISE 6.3i

LUT1_D, LUT2_D, LUT3_D, LUT4_D

LUT1_D, LUT2_D, LUT3_D, LUT4_D

1-, 2-, 3-, 4-Bit Look-Up-Table with Dual Output
Architectures Supported
LUT1_D, LUT2_D, LUT3_D, LUT4_D
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LUT1_D

LO

I0

X8377

No

CoolRunner XPLA3

No

CoolRunner-II

No

LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit lookup-tables (LUTs) with two functionally identical outputs, O and LO. The O output is a
general interconnect. The LO output is used to connect to another output within the
same CLB slice and to the fast connect buffer.
A mandatory INIT attribute, with an appropriate number of hexadecimal digits for
the number of inputs, must be attached to the LUT to specify its function.

I1

LUT2_D

LO

I0

X8380

LUT1_D provides a look-up-table version of a buffer or inverter.

See also LUT1, 2, 3, 4 and LUT1_L, LUT2_L, LUT3_L, LUT4_L.
LUT3_D Function Table
Inputs

I2

LUT3_D

I1
O

I0

X8383

I3

Outputs

LO

LUT4_D

I2

LO

I1

I0

X8386

I2

I1

I0

LO

INIT[0]

INIT[0]

INIT[1]

INIT[1]

INIT[2]

INIT[2]

INIT[3]

INIT[3]

INIT[4]

INIT[4]

INIT[5]

INIT[5]

INIT[6]

INIT[6]

INIT[7]

INIT[7]

INIT = binary equivalent of the hexadecimal number assigned to the INIT attribute

Usage
LUTs are generally inferred with the logic portions of the HDL code. Xilinx suggests
that you instantiate LUTs only if you have a need to implicitly specify the logic
mapping, or if you need to manually place or relationally place the logic.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

751

LUT1_D, LUT2_D, LUT3_D, LUT4_D

VHDL Instantiation Template for LUT1_D

-- Component Declaration for LUT1_D should be placed
-- after architecture statement but before begin keyword
component LUT1_D
-- synthesis translate_off
generic (
INIT : bit_vector := X"2");
-- synthesis translate_on
port (LO : out STD_ULOGIC;
O : out STD_ULOGIC;
I0 : in STD_ULOGIC);
end component;
-- Component Attribute specification for LUT1_D
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LUT1_D_instance_name : label is "2";
-- values can be 0, 1, 2,or 3

-- Component Instantiation for LUT1_D should be placed

-- in architecture after the begin keyword
LUT1_D_INSTANCE_NAME : LUT1_D
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (LO => user_LO,
O => user_O,
IO => user_IO);

Verilog Instantiation Template For LUT1_D

LUT1_D LUT1_D_instance_name (.LO (user_LO),
.O (user_O),
.IO (user_IO));
defparam LUT1_D_instance_name.INIT = hex_value;

VHDL Instantiation Template for LUT2_D

-- Component Declaration for LUT2_D should be placed
-- after architecture statement but before begin keyword
component LUT2_D
-- synthesis translate_off
generic (
INIT : bit_vector := X"4");
-- synthesis translate_on
port (LO : out STD_ULOGIC;
O : out STD_ULOGIC;
IO : in STD_ULOGIC;
I1 : in STD_ULOGIC);

752

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Libraries Guide
ISE 6.3i

LUT1_D, LUT2_D, LUT3_D, LUT4_D

end component;
-- Component Attribute specification for LUT2_D
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LUT2_D_instance_name : label is "4";
-- Component Instantiation for LUT2_D should be placed
-- in architecture after the begin keyword
LUT2_D_INSTANCE_NAME : LUT2_D
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (LO => user_LO,
O => user_O,
I0 => user_I0,
I1 => user_I1);

Verilog Instantiation Template For LUT2_D

LUT2_D LUT2_D_instance_name (.LO (user_O),
.O (user_O),
.I0 (user_I0),
.I1 (user_I1));
defparam LUT2_D_instance_name.INIT = hex_value;

VHDL Instantiation Template for LUT3_D

-- Component Declaration for LUT3_D should be placed
-- after architecture statement but before begin keyword
component LUT3_D
-- synthesis translate_off
generic (
INIT : bit_vector := X"8");
-- synthesis translate_on
port (LO : out STD_ULOGIC;
O : out STD_ULOGIC;
IO : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC);
end component;
-- Component Attribute specification for LUT3_D
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LUT3_D_instance_name : label is "8";
-- Component Instantiation for LUT3_D should be placed
-- in architecture after the begin keyword

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753

LUT1_D, LUT2_D, LUT3_D, LUT4_D

LUT3_D_INSTANCE_NAME : LUT3_D
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (LO => user_LO,
O => user_O,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2);

Verilog Instantiation Template For LUT3_D

LUT3_D LUT3_D_instance_name (.LO (user_LO),
.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.I2 (user_I2));
defparam LUT3_D_instance_name.INIT = hex_value;

VHDL Instantiation Template for LUT4_D

-- Component Declaration for LUT4_D should be placed
-- after architecture statement but before begin keyword
component LUT4_D
-- synthesis translate_off
generic (
INIT : bit_vector := X"16");
-- synthesis translate_on
port (LO : out STD_ULOGIC;
O : out STD_ULOGIC;
IO : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC;
I3 : in STD_ULOGIC);
end component;
-- Component Attribute specification for LUT4_D
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LUT4_D_instance_name : label is "16";
-- values can be 0 through 16
-- Component Instantiation for LUT4_D should be placed
-- in architecture after the begin keyword
LUT4_D_INSTANCE_NAME : LUT4_D
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (LO => user_LO,
O => user_O,
I0 => user_I0,

754

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Libraries Guide
ISE 6.3i

LUT1_D, LUT2_D, LUT3_D, LUT4_D

I1 => user_I1,
I2 => user_I2,
I3 => user_I3);

Verilog Instantiation Template For LUT4_D

LUT4_D LUT4_D_instance_name (.LO (user_LO),
.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.I2 (user_I2),
.I3 (user_I3));
defparam LUT4_D_instance_name.INIT = hex_value;

Commonly Used Constraints

INIT, LOC, RLOC, BEL, U_SET

Libraries Guide
ISE 6.3i

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755

756

LUT1_D, LUT2_D, LUT3_D, LUT4_D

www.xilinx.com
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Libraries Guide
ISE 6.3i

LUT1_L, LUT2_L, LUT3_L, LUT4_L

LUT1_L, LUT2_L, LUT3_L, LUT4_L

1-, 2-, 3-, 4-Bit Look-Up-Table with Local Output
Architectures Supported
LUT1_L, LUT2_L, LUT3_L, LUT4_L
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I3

LUT4_L

I2
LO
I1
I0

X8387

No

CoolRunner XPLA3

No

CoolRunner-II

No

LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-uptables (LUTs) with a local output (LO) that is used to connect to another output within
the same CLB slice and to the fast connect buffer.
A mandatory INIT attribute, with an appropriate number of hexadecimal digits for
the number of inputs, must be attached to the LUT to specify its function.
LUT1_L provides a look-up-table version of a buffer or inverter.

LUT1_L

LO

See also LUT1, 2, 3, 4 and LUT1_D, LUT2_D, LUT3_D, LUT4_D.

LUT3_L Function Table

I0

Inputs

X8378

I1

LUT2_L

LO

I0

X8381

I2

LUT3_L

LO

I1
I0

Outputs

I2

I1

I0

LO

INIT[0]

INIT[1]

INIT[2]

INIT[3]

INIT[4]

INIT[5]

INIT[6]

INIT[7]

INIT = binary equivalent of the hexadecimal number assigned to the INIT attribute
X8384

Usage
LUTs are generally inferred with the logic portions of the HDL code. Xilinx suggests
that you instantiate LUTs only if you have a need to implicitly specify the logic
mapping, or if you need to manually place or relationally place the logic.

Libraries Guide
ISE 6.3i

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757

LUT1_L, LUT2_L, LUT3_L, LUT4_L

VHDL Instantiation Template for LUT1_L

-- Component Declaration for LUT1_L should be placed
-- after architecture statement but before begin keyword
component LUT1_L
-- synthesis translate_off
generic (
INIT : bit_vector := X"2");
-- synthesis translate_on
port (LO : out STD_ULOGIC;
IO : inSTD_ULOGIC);
end component;
-- Component Attribute specification for LUT1_L
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LUT1_L_instance_name : label is "2";
-- values can be 0, 1, 2,or 3
-- Component Instantiation for LUT1_L should be placed
-- in architecture after the begin keyword
LUT1_L_INSTANCE_NAME : LUT1_L
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (LO => user_LO,
IO => user_IO);

Verilog Instantiation Template For LUT1_L

LUT1_L LUT1_L_instance_name (.LO (user_LO),
.IO (user_IO));
defparam LUT1_L_instance_name.INIT = hex_value;

VHDL Instantiation Template for LUT2_L

-- Component Declaration for LUT2_L should be placed
-- after architecture statement but before begin keyword
component LUT2_L
-- synthesis translate_off
generic (
INIT : bit_vector := X"4");
-- synthesis translate_on
port (LO : out STD_ULOGIC;
IO : in STD_ULOGIC;
I1 : in STD_ULOGIC);
end component;
-- Component Attribute specification for LUT2_L
-- should be placed after architecture declaration but
-- before the begin keyword

758

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ISE 6.3i

LUT1_L, LUT2_L, LUT3_L, LUT4_L

attribute INIT : string;

attribute INIT of LUT2_L_instance_name : label is "4";
-- Component Instantiation for LUT2_L should be placed
-- in architecture after the begin keyword
LUT2_L_INSTANCE_NAME : LUT2_L
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (LO => user_LO,
I0 => user_I0,
I1 => user_I1);

Verilog Instantiation Template For LUT2_L

LUT2_L LUT2_L_instance_name (.LO (user_O),
.I0 (user_I0),
.I1 (user_I1));
defparam LUT2_L_instance_name.INIT = hex_value;

VHDL Instantiation Template for LUT3_L

-- Component Declaration for LUT3_L should be placed
-- after architecture statement but before begin keyword
component LUT3_L
-- synthesis translate_off
generic (
INIT : bit_vector := X"8");
-- synthesis translate_on
port (LO : out STD_ULOGIC;
IO : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC);
end component;
-- Component Attribute specification for LUT3_L
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LUT3_L_instance_name : label is "8";
-- Component Instantiation for LUT3_L should be placed
-- in architecture after the begin keyword -LUT3_L_INSTANCE_NAME : LUT3_L
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (LO => user_LO,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2);

Libraries Guide
ISE 6.3i

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759

LUT1_L, LUT2_L, LUT3_L, LUT4_L

Verilog Instantiation Template For LUT3_L

LUT3_L LUT3_L_instance_name (.LO
.I0
.I1
.I2

(user_LO),
(user_I0),
(user_I1),
(user_I2));

defparam LUT3_L_instance_name.INIT = hex_value;

VHDL Instantiation Template for LUT4_L

-- Component Declaration for LUT4_L should be placed
-- after architecture statement but before begin keyword -component LUT4_L
-- synthesis translate_off
generic (
INIT : bit_vector := X"16");
-- synthesis translate_on
port (LO : out STD_ULOGIC;
IO : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC;
I3 : in STD_ULOGIC);
end component;
-- Component Attribute specification for LUT4_L
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of LUT4_L_instance_name : label is "16";
-- values can be 0 through 16
-- Component Instantiation for LUT4_L should be placed
-- in architecture after the begin keyword -LUT4_L_INSTANCE_NAME : LUT4_L
-- synthesis translate_off
generic map (
INIT => hex_value)
-- synthesis translate_on
port map (LO => user_LO,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2,
I3 => user_I3);

Verilog Instantiation Template For LUT4_L

LUT4_L LUT4_L_instance_name (.LO
.I0
.I1
.I2
.I3

(user_LO),
(user_I0),
(user_I1),
(user_I2),
(user_I3));

defparam LUT4_L_instance_name.INIT = hex_value;

760

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Libraries Guide
ISE 6.3i

LUT1_L, LUT2_L, LUT3_L, LUT4_L

Commonly Used Constraints

INIT,LOC,RLOC,BEL,U_SET

Libraries Guide
ISE 6.3i

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761

762

LUT1_L, LUT2_L, LUT3_L, LUT4_L

www.xilinx.com
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Libraries Guide
ISE 6.3i

M2_1

M2_1
2-to-1 Multiplexer
Architectures Supported
M2_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D0
D1
S0

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

The M2_1 multiplexer chooses one data bit from two sources (D1 or D0) under the
control of the select input (S0). The output (O) reflects the state of the selected data
input. When Low, S0 selects D0 and when High, S0 selects D1.
Inputs

X4026

S0

D1

D0

D0

S0

Outputs

M0
AND2B1

M1

D1

OR2

AND2

X7661

M2_1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-3, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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763

764

M2_1

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Libraries Guide
ISE 6.3i

M2_1B1

M2_1B1
2-to-1 Multiplexer with D0 Inverted
Architectures Supported
M2_1B1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D0
D1
S0

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

The M2_1B1 multiplexer chooses one data bit from two sources (D1 or D0) under the
control of select input (S0). When S0 is Low, the output (O) reflects the inverted value
of D0. When S0 is High, O reflects the state of D1.
Inputs

X4027

S0

D1

D0

D0

S0

Outputs

M0
AND2B2

M1

D1

OR2

AND2

X7662

M2_1B1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-3, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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1-800-255-7778

765

766

M2_1B1

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Libraries Guide
ISE 6.3i

M2_1B2

M2_1B2
2-to-1 Multiplexer with D0 and D1 Inverted
Architectures Supported
M2_1B2
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D0

D1
S0

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

The M2_1B2 multiplexer chooses one data bit from two sources (D1 or D0) under the
control of select input (S0). When S0 is Low, the output (O) reflects the inverted value
of D0. When S0 is High, O reflects the inverted value of D1.
Inputs

X4028

S0

D1

D0

D0

S0

Outputs

M0
AND2B2

M1

D1

OR2

AND2B1

X7663

M2_1B2 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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767

768

M2_1B2

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Libraries Guide
ISE 6.3i

M2_1E

M2_1E
2-to-1 Multiplexer with Enable
Architectures Supported
M2_1E
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D0
D1

S0

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

M2_1E is a 2-to-1 multiplexer with enable. When the enable input (E) is High, the
M2_1E chooses one data bit from two sources (D1 or D0) under the control of select
input (S0). When Low, S0 selects D0 and when High, S0 selects D1. When E is Low, the
output is Low.

Inputs

Outputs

X4029
E

S0

D1

D0

D0
E
S0

M0
AND3B1
O
OR2
M1

D1
AND3

X7858

M2_1E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

Libraries Guide
ISE 6.3i

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769

770

M2_1E

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

M4_1E

M4_1E
4-to-1 Multiplexer with Enable
Architectures Supported
M4_1E
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D0
D1
D2

D3
S0
S1
E

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

M4_1E is an 4-to-1 multiplexer with enable. When the enable input (E) is High, the
M4_1E multiplexer chooses one data bit from four sources (D3, D2, D1, or D0) under
the control of the select inputs (S1 S0). The output (O) reflects the state of the
selected input as shown in the truth table. When E is Low, the output is Low.
Inputs

Outputs

S1

S0

D0

D1

D2

D3

D0

D0

D1

D1

D2

D2

D3

D3

X4030

M2_1E
D0
D1

D0
D1
S0
E

M2_1
M01

M01
M23

M2_1E
D2

D0

D3

D1
S0
E

S0
E

D0
D1
S0

M23

S1
X7859

M4_1E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Libraries Guide
ISE 6.3i

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1-800-255-7778

771

M4_1E

M2_1E
D0

D0

D1

D1
S0
E

MUXF5
M01

M01
M23

M2_1E
D2

D0

D3

D1
S0
E

S0
E

I0
I1
S

M23

S1

X9348

M4_1E Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II,

Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

772

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Libraries Guide
ISE 6.3i

M8_1E

M8_1E
8-to-1 Multiplexer with Enable
Architectures Supported
M8_1E
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D0
D1
D2
D3

D4

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

M8_1E is an 8-to-1 multiplexer with enable. When the enable input (E) is High, the
M8_1E multiplexer chooses one data bit from eight sources (D7 D0) under the
control of the select inputs (S2 S0). The output (O) reflects the state of the selected
input as shown in the truth table. When E is Low, the output is Low.

D5

Inputs

Outputs

D6
D7
S0
S1
S2
E
X4031

S2

S1

S0

D7 D0

D0

D0

D1

D1

D2

D2

D3

D3

D4

D4

D5

D5

D6

D6

D7

D7

Dn represents signal on the Dn input; all other data inputs are dont-cares (X).

Libraries Guide
ISE 6.3i

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773

M8_1E

M2_1
D0

D0

D1

D1
S0

M01
M2_1
M01

D0

M23

D1

M03

S0

M2_1
D2

D0

D3

D1
S0

M23
M2_1E
M03

D0

M47

D1
S0
E

M2_1
D4

D0

D5

D1
S0

M45
M2_1
M45

D0

M67

D1

M2_1
D6

D0

D7

D1

S0
S1

S0

M47

S0
O

M67

S2
E
X7640

M8_1E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

M2_1E
D0
D1

D0
D1
S0
E

MUXF5_L
M01

M2_1E
D2

D0

D3

D1
S0
E

M01
M23

I0
I1
S

LO
M03

MUXF6
M03

M23

M47

M2_1E
D4

D0

D5

D1
S0
E
D0

D7

D1

S0

S0
E

MUXF5_L
M45

M2_1E
D6

I0
I1
S

M45
M67

I0
I1
S

LO
M47

M67

S1
S2
E

X8716

M8_1E Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

774

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Libraries Guide
ISE 6.3i

M16_1E

M16_1E
16-to-1 Multiplexer with Enable
Architectures Supported
M16_1E
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

M16_1E is a 16-to-1 multiplexer with enable. When the enable input (E) is High, the
M16_1E multiplexer chooses one data bit from 16 sources (D15 D0) under the
control of the select inputs (S3 S0). The output (O) reflects the state of the selected
input as shown in the truth table. When E is Low, the output is Low.

D0
D1
D2
D3
D4
D5

Inputs

D6
D7

Outputs

S3

S2

S1

S0

D15 D0

D11

D0

D0

D12

D1

D1

D14

D2

D2

D15

D3

D3

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

D12

D12

D13

D13

D14

D14

D15

D15

D8
D9
D10

D13

S0
S1
S2
S3
E
X4032

Dn represents signal on the Dn input; all other data inputs are don't-cares (X).

Usage
For HDL, this design element is inferred rather than instantiated.

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ISE 6.3i

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775

776

M16_1E

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Libraries Guide
ISE 6.3i

MULT_AND

MULT_AND
Fast Multiplier AND
Architectures Supported
MULT_AND
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I1
I0

LO

No

CoolRunner XPLA3

No

CoolRunner-II

No

MULT_AND is an AND component used exclusively for building fast and smaller
multipliers. The I1 and I0 inputs must be connected to the I1 and I0 inputs of the
associated LUT. The LO output must be connected to the DI input of the associated
MUXCY, MUXCY_D, or MUXCY_L.
Inputs

X8405

Output

I1

I0

LO

LO
S

MUXCY_L

0 1
DI
CI

LUT4
B1
A1
B0
A0

I3
I2
I1
IO

LI
CI

SUM1

XORCY

I1
I0

LO

MULT_AND
CO

X8733

Example Multiplier Using MULT_AND

Usage
For HDL, this design element is instantiated rather than inferred.

Libraries Guide
ISE 6.3i

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1-800-255-7778

777

MULT_AND

VHDL Instantiation Template

-- Component Declaration for MULT_AND should be placed
-- after architecture statement but before begin keyword
component MULT_AND
port (LO : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC);
end component;
-- Component Attribute specification for MULT_AND
-- should be placed after architecture declaration but
-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for MULT_AND should be placed
-- in architecture after the begin keyword
MULT_AND_INSTANCE_NAME : MULT_AND
port map (LO => user_LO,
I0 => user_I0,
I1 => user_I1);

Verilog Instantiation Template

MULT_AND MULT_AND_instance_name (.LO (user_LO),
.I0 (user_I0),
.I1 (user_I1));

Commonly Used Constraints

U_SET, MULT_STYLE

778

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Libraries Guide
ISE 6.3i

MULT18X18

MULT18X18
18 x 18 Signed Multiplier
Architectures Supported
MULT18, MULT18X
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

MULT18x18
A [17:0]
P [35:0]
B [17:0]

X9258

No

CoolRunner XPLA3

No

CoolRunner-II

No

MULT18X18 is a combinational signed 18-bit by 18-bit multiplier. The value

represented in the 18-bit input A is multiplied by the value represented in the 18-bit
input B. Output P is the 36-bit product of A and B.
A, B, and P are two's complement.
Inputs

Output

A*B

XST, Synplify, Exemplar and Synopsys all have the ability to infer the MULT18X18.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- MULT18X18: 18 x 18 signed asynchronous multiplier
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
MULT18X18_inst :
port map (
P => P,
-A => A,
-B => B
-);

MULT18X18
36-bit multiplier output
18-bit multiplier input
18-bit multiplier input

-- End of MULT18X18_inst instantiation

Verilog Instantiation Template

// MULT18X18: 18 x 18 signed asynchronous multiplier
//
Virtex-II/II-Pro, Spartan-3
// Xilinx HDL Libraries Guide version 7.1i

Libraries Guide
ISE 6.3i

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779

MULT18X18

MULT18X18 MULT18X18_inst (
.P(P),
// 36-bit multiplier output
.A(A),
// 18-bit multiplier input
.B(B)
// 18-bit multiplier input
);
// End of MULT18X18_inst instantiation

Commonly Used Constraints

MULT_STYLE

780

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Libraries Guide
ISE 6.3i

MULT18X18S

MULT18X18S
18 x 18 Signed Multiplier -- Registered Version
Architectures Supported
MULT18X, MULT18S
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

A [17:0]

MULT18X18S

P [35:0]

B [17:0]

No

CoolRunner XPLA3

No

CoolRunner-II

No

MULT18X18S is the registered version of the 18 x 18 signed multiplier with output P

and inputs A, B, C, CE, and R. The registers are initialized to 0 after the GSR pulse.

C
CE
R
X9733

The value represented in the 18-bit input A is multiplied by the value represented in
the 18-bit input B. Output P is the 36-bit product of A and B.
A, B, and P are two's complement.
Inputs

Output

CE

Am

Bn

Am

Bn

A*B

No Chg

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- MULT18X18S: 18 x 18 signed synchronous multiplier
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
MULT18X18S_inst : MULT18X18S
port map (
P => P,
-- 36-bit multiplier output
A => A,
-- 18-bit multiplier input
B => B,
-- 18-bit multiplier input
C => C,
-- Clock input
CE => CE, -- Clock enable input
R => R
-- Synchronous reset input
);
-- End of MULT18X18S_inst instantiation

Libraries Guide
ISE 6.3i

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781

MULT18X18S

Verilog Instantiation Template

// MULT18X18S: 18 x 18 signed synchronous multiplier
//
Virtex-II/II-Pro, Spartan-3
// Xilinx HDL Libraries Guide version 7.1i
MULT18X18S MULT18X18S_inst (
.P(P),
// 36-bit multiplier output
.A(A),
// 18-bit multiplier input
.B(B),
// 18-bit multiplier input
.C(C),
// Clock input
.CE(CE), // Clock enable input
.R(R)
// Synchronous reset input
);
// End of MULT18X18S_inst instantiation

Commonly Used Constraints

HU_SET, MULT_STYLE

782

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Libraries Guide
ISE 6.3i

MUXCY

MUXCY
2-to-1 Multiplexer for Carry Logic with General Output
Architectures Supported
MUXCY
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

MUXCY

CoolRunner XPLA3

No

CoolRunner-II

No

MUXCY is used to implement a 1-bit high-speed carry propagate function. One such
function can be implemented per logic cell (LC), for a total of:

O
S

No

DI CI
X8728

2-bits per CLB for Virtex, Virtex-E, Spartan-II, and Spartan-IIE

4-bits per configurable logic block (CLB) for Spartan-3, Virtex-II, Virtex-II Pro, and
Virtex-II Pro X

The direct input (DI) of an LC is connected to the DI input of the MUXCY. The carry in
(CI) input of an LC is connected to the CI input of the MUXCY. The select input (S) of
the MUXCY is driven by the output of the lookup table (LUT) and configured as a
MUX function. The carry out (O) of the MUXCY reflects the state of the selected input
and implements the carry out function of each LC. When Low, S selects DI; when
High, S selects CI.
The variants, MUXCY_D and MUXCY_L provide additional types of outputs that
can be used by different timing models for more accurate pre-layout timing
estimation.
Inputs

Outputs

DI

CI

Usage
For HDL, this design element can only be instantiated.

Libraries Guide
ISE 6.3i

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783

MUXCY

VHDL Instantiation Template

-- Component Declaration for MUXCY should be placed
-- after architecture statement but before begin keyword
component MUXCY
port (O : out STD_ULOGIC;
CI : in STD_ULOGIC;
DI : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for MUXCY
-- should be placed after architecture declaration but
-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for MUXCY should be placed
-- in architecture after the begin keyword
MUXCY_INSTANCE_NAME : MUXCY
port map (O => user_O,
CI => user_CI,
DI => user_DI,
S => user_S);

Verilog Instantiation Template

MUXCY MUXCY_instance_name (.O (user_O),
.CI (user_CI),
.DI (user_DI),
.S (user_S));

Commonly Used Constraints

U_SET

784

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Libraries Guide
ISE 6.3i

MUXCY_D

MUXCY_D
2-to-1 Multiplexer for Carry Logic with Dual Output
Architectures Supported
MUXCY_D
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LO O
S

MUXCY_D

DI CI
X8729

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXCY_D is used to implement a 1-bit high-speed carry propagate function. One

such function can be implemented per logic cell (LC), for a total of 4-bits per
configurable logic block (CLB). The direct input (DI) of an LC is connected to the DI
input of the MUXCY_D. The carry in (CI) input of an LC is connected to the CI input
of the MUXCY_D. The select input (S) of the MUX is driven by the output of the
lookup table (LUT) and configured as an XOR function. The carry out (O and LO) of
the MUXCY_D reflects the state of the selected input and implements the carry out
function of each LC. When Low, S selects DI; when High, S selects CI.
Outputs O and LO are functionally identical. The O output is a general interconnect.
See also MUXCY and MUXCY_L
Inputs

Outputs

DI

CI

LO

Usage
For HDL, this design element can only be instantiated.

Libraries Guide
ISE 6.3i

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1-800-255-7778

785

MUXCY_D

VHDL Instantiation Template

-- Component Declaration for MUXCY_D should be placed
-- after architecture statement but before begin keyword
component MUXCY_D
port (LO : out STD_ULOGIC;
O : out STD_ULOGIC;
CI : in STD_ULOGIC;
DI : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for MUXCY_D
-- should be placed after architecture declaration but
-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for MUXCY_D should be placed
-- in architecture after the begin keyword
MUXCY_D_INSTANCE_NAME
port map (LO =>
O =>
CI =>
DI =>
S =>

: MUXCY_D
user_O,
user_O,
user_CI,
user_DI,
user_S);

Verilog Instantiation Template

MUXCY_D MUXCY_D_instance_name (.LO (user_LO),
.O (user_O),
.CI (user_CI),
.DI (user_DI),
.S (user_S));

Commonly Used Constraints

U_SET

786

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Libraries Guide
ISE 6.3i

MUXCY_L

MUXCY_L
2-to-1 Multiplexer for Carry Logic with Local Output
Architectures Supported
MUXCY_L
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LO
S

MUXCY_L

DI CI
X8730

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXCY_L is used to implement a 1-bit high-speed carry propagate function. One

such function can be implemented per logic cell (LC), for a total of 4-bits per
configurable logic block (CLB). The direct input (DI) of an LC is connected to the DI
input of the MUXCY_L. The carry in (CI) input of an LC is connected to the CI input
of the MUXCY_L. The select input (S) of the MUXCY_L is driven by the output of the
lookup table (LUT) and configured as an XOR function. The carry out (LO) of the
MUXCY_L reflects the state of the selected input and implements the carry out
function of each LC. When Low, S selects DI; when High, S selects CI.
See also MUXCY and MUXCY_D
Inputs

Outputs

DI

CI

LO

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXCY_L should be placed
-- after architecture statement but before begin keyword
component MUXCY_L
port (LO : out STD_ULOGIC;
CI : in STD_ULOGIC;
DI : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for MUXCY_L

Libraries Guide
ISE 6.3i

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787

MUXCY_L

-- should be placed after architecture declaration but

-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for MUXCY_L should be placed
-- in architecture after the begin keyword
MUXCY_L_INSTANCE_NAME : MUXCY_L
port map (LO => user_O,
CI => user_CI,
DI => user_DI,
S => user_S);

Verilog Instantiation Template

MUXCY_L MUXCY_L_instance_name (.LO (user_LO),
.CI (user_CI),
.DI (user_DI),
.S (user_S));

Commonly Used Constraints

U_SET

788

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Libraries Guide
ISE 6.3i

MUXF5

MUXF5
2-to-1 Lookup Table Multiplexer with General Output
Architectures Supported
MUXF5
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I0
I1

S
X8431

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXF5 provides a multiplexer function in a CLB slice for creating a function-of-5

lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables.
The local outputs (LO) from the two lookup tables are connected to the I0 and I1
inputs of the MUXF5. The S input is driven from any internal net. When Low, S selects
I0. When High, S selects I1.
The variants, MUXF5_D and MUXF5_L, provide additional types of outputs that
can be used by different timing models for more accurate pre-layout timing
estimation.
Inputs

Outputs

I0

I1

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXF5 should be placed
-- after architecture statement but before begin keyword
component MUXF5
port (O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for MUXF5
-- should be placed after architecture declaration but

Libraries Guide
ISE 6.3i

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789

MUXF5

-- before the begin keyword

-- Attributes should be placed here
-- Component Instantiation for MUXF5 should be placed
-- in architecture after the begin keyword
MUXF5_INSTANCE_NAME : MUXF5
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
S => user_S);

Verilog Instantiation Template

MUXF5 MUXF5_instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

790

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Libraries Guide
ISE 6.3i

MUXF5_D

MUXF5_D
2-to-1 Lookup Table Multiplexer with Dual Output
Architectures Supported
MUXF5_D
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I0
I1

LO
O

S
X8432

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXF5_D provides a multiplexer function in a CLB slice for creating a function-of-5

lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables.
The local outputs (LO) from the two lookup tables are connected to the I0 and I1
inputs of the MUXF5. The S input is driven from any internal net. When Low, S selects
I0. When High, S selects I1.
Outputs O and LO are functionally identical. The O output is a general interconnect.
The LO output is used to connect to other inputs within the same CLB slice.
See also MUXF5 and MUXF5_L
Inputs

Outputs

I0

I1

LO

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXF5_D should be placed
-- after architecture statement but before begin keyword
component MUXF5_D
port (LO : out STD_ULOGIC;
O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for MUXF5_D

Libraries Guide
ISE 6.3i

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791

MUXF5_D

-- should be placed after architecture declaration but

-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for MUXF5_D should be placed
-- in architecture after the begin keyword
MUXF5_D_INSTANCE_NAME
port map (LO =>
O =>
I0 =>
I1 =>
S =>

: MUXF5_D
user_LO,
user_O,
user_I0,
user_I1,
user_S);

Verilog Instantiation Template

MUXF5_D MUXF5_D_instance_name (.LO (user_LO),
.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

792

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Libraries Guide
ISE 6.3i

MUXF5_L

MUXF5_L
2-to-1 Lookup Table Multiplexer with Local Output
Architectures Supported
MUXF5_L
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I0

LO

I1
S
X8433

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXF5_L provides a multiplexer function in a CLB slice for creating a function-of-5

lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables.
The local outputs (LO) from the two lookup tables are connected to the I0 and I1
inputs of the MUXF5. The S input is driven from any internal net. When Low, S selects
I0. When High, S selects I1.
The LO output is used to connect to other inputs within the same CLB slice.
See also MUXF5 and MUXF5_D.
Inputs

Output

I0

I1

LO

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXF5_L should be placed
-- after architecture statement but before begin keyword
component MUXF5_L
port (LO : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for MUXF5_L
-- should be placed after architecture declaration but
-- before the begin keyword

Libraries Guide
ISE 6.3i

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793

MUXF5_L

-- Attributes should be placed here

-- Component Instantiation for MUXF5_L should be placed
-- in architecture after the begin keyword
MUXF5_L_INSTANCE_NAME
port map (LO =>
I0 =>
I1 =>
S =>

: MUXF5_L
user_LO,
user_I0,
user_I1,
user_S);

Verilog Instantiation Template

MUXF5_L MUXF5_L_instance_name (.LO (user_LO),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

794

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Libraries Guide
ISE 6.3i

MUXF6

MUXF6
2-to-1 Lookup Table Multiplexer with General Output
Architectures Supported
MUXF6
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I0
I1

S
X8434

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXF6 provides a multiplexer function in a full Virtex, Virtex-E, Spartan-II, or

Spartan-IIE CLB, or one half of a Spartan-3, Virtex-II, Virtex-II Pro, or Virtex-II Pro X
CLB (two slices) for creating a function-of-6 lookup table or an 8-to-1 multiplexer in
combination with the associated four lookup tables and two MUXF5s. The local
outputs (LO) from the two MUXF5s in the CLB are connected to the I0 and I1 inputs of
the MUXF6. The S input is driven from any internal net. When Low, S selects I0. When
High, S selects I1.
The variants, MUXF6_D and MUXF6_L, provide additional types of outputs that
can be used by different timing models for more accurate pre-layout timing
estimation.
Inputs

Outputs

I0

I1

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXF6 should be placed
-- after architecture statement but before begin keyword
component MUXF6
port (O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;

Libraries Guide
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795

MUXF6

-- Component Attribute specification for MUXF6

-- should be placed after architecture declaration but
-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for MUXF6 should be placed
-- in architecture after the begin keyword
MUXF6_INSTANCE_NAME : MUXF6
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
S => user_S);

Verilog Instantiation Template

MUXF6 MUXF6_instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

796

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Libraries Guide
ISE 6.3i

MUXF6_D

MUXF6_D
2-to-1 Lookup Table Multiplexer with Dual Output
Architectures Supported
MUXF6_D
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I0
I1

LO
O

S
X8435

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXF6_D provides a multiplexer function in a full Virtex, Virtex-E, Virtex-II, Virtex-II

Pro, Virtex-II Pro X, Spartan-II, Spartan-IIE, or Spartan-3 CLB, or one half of a Spartan3, Virtex-II, Virtex-II Pro, or Virtex-II Pro X CLB (two slices) for creating a function-of6 lookup table or an 8-to-1 multiplexer in combination with the associated four
lookup tables and two MUXF5s. The local outputs (LO) from the two MUXF5s in the
CLB are connected to the I0 and I1 inputs of the MUXF6. The S input is driven from
any internal net. When Low, S selects I0. When High, S selects I1.
Outputs O and LO are functionally identical. The O output is a general interconnect.
The LO output is used to connect to other inputs within the same CLB slice.
See also MUXF6 and MUXF6_L
Inputs

Outputs

I0

I1

LO

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXF6_D should be placed
-- after architecture statement but before begin keyword
component MUXF6_D
port (LO : out STD_ULOGIC;
O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;

Libraries Guide
ISE 6.3i

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797

MUXF6_D

-- Component Attribute specification for MUXF6_D

-- should be placed after architecture declaration but
-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for MUXF6_D should be placed
-- in architecture after the begin keyword
MUXF6_D_INSTANCE_NAME : MUXF6_D
port map (LO => user_LO,
O => user_O,
I0 => user_I0,
I1 => user_I1,
S => user_S);

Verilog Instantiation Template

MUXF6_D MUXF6_D_instance_name (.LO (user_LO),
.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

798

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Libraries Guide
ISE 6.3i

MUXF6_L

MUXF6_L
2-to-1 Lookup Table Multiplexer with Local Output
Architectures Supported
MUXF6_L
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I0

LO

I1
S
X8436

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXF6_L provides a multiplexer function in a full Virtex, Virtex-E, Virtex-II, Virtex-II

Pro, Virtex-II Pro X, Spartan-II, Spartan-II E, or Spartan-3 CLB, or one half of a
Spartan-3, Virtex-II, Virtex-II Pro, or Virtex-II Pro X CLB (two slices) for creating a
function-of-6 lookup table or an 8-to-1 multiplexer in combination with the associated
four lookup tables and two MUXF5s. The local outputs (LO) from the two MUXF5s in
the CLB are connected to the I0 and I1 inputs of the MUXF6. The S input is driven
from any internal net. When Low, S selects I0. When High, S selects I1.
The LO output is used to connect to other inputs within the same CLB slice.
See also MUXF6 and MUXF6_D.
Inputs

Output

I0

I1

LO

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXF6_L should be placed
-- after architecture statement but before begin keyword
component MUXF6_L
port (LO : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for MUXF6_L

Libraries Guide
ISE 6.3i

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799

MUXF6_L

-- should be placed after architecture declaration but

-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for MUXF6_L should be placed
-- in architecture after the begin keyword
MUXF6_L_INSTANCE_NAME : MUXF6_L
port map (LO => user_LO,
I0 => user_I0,
I1 => user_I1,
S => user_S);

Verilog Instantiation Template

MUXF6_L MUXF6_L_instance_name (.LO (user_LO),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

800

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Libraries Guide
ISE 6.3i

MUXF7

MUXF7
2-to-1 Lookup Table Multiplexer with General Output
Architectures Supported
MUXF7
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I0
I1

S
X8431

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXF7 provides a multiplexer function in a full Spartan-3, Virtex-II, Virtex-II Pro,

and Virtex-II Pro X CLB for creating a function-of-7 lookup table or a 16-to-1
multiplexer in combination with the associated lookup tables. Local outputs (LO) of
MUXF6 are connected to the I0 and I1 inputs of the MUXF7. The S input is driven
from any internal net. When Low, S selects I0. When High, S selects I1.
The variants, MUXF7_D and MUXF7_L, provide additional types of outputs that
can be used by different timing models for more accurate pre-layout timing
estimation.
Inputs

Outputs

I0

I1

I0

I0

I1

I1

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXF7 should be placed
-- after architecture statement but before begin keyword
component MUXF7
port (O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for MUXF7
-- should be placed after architecture declaration but

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801

MUXF7

-- before the begin keyword

-- Attributes should be placed here
-- Component Instantiation for MUXF7 should be placed
-- in architecture after the begin keyword
MUXF7_INSTANCE_NAME : MUXF7
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
S => user_S);

Verilog Instantiation Template

MUXF7 MUXF7_instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

802

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Libraries Guide
ISE 6.3i

MUXF7_D

MUXF7_D
2-to-1 Lookup Table Multiplexer with Dual Output
Architectures Supported
MUXF7_D
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I0
I1

LO
O

S
X8432

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXF7_D provides a multiplexer function in one full Spartan-3, Virtex-II, Virtex-II

Pro, and Virtex-II Pro X CLB for creating a function-of-7 lookup table or a 16-to-1
multiplexer in combination with the associated lookup tables. Local outputs (LO) of
MUXF6 are connected to the I0 and I1 inputs of the MUXF7. The S input is driven
from any internal net. When Low, S selects I0. When High, S selects I1.
Outputs O and LO are functionally identical. The O output is a general interconnect.
The LO output is used to connect to other inputs within the same CLB slice.
See also MUXF7 and MUXF7_L.
Inputs

Outputs

I0

I1

LO

I0

I0

I0

I1

I1

I1

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXF7_D should be placed
-- after architecture statement but before begin keyword
component MUXF7_D
port (LO : out STD_ULOGIC;
O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for MUXF7_D

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803

MUXF7_D

-- should be placed after architecture declaration but

-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for MUXF7_D should be placed
-- in architecture after the begin keyword
MUXF7_D_INSTANCE_NAME : MUXF7_D
port map (LO => user_LO,
O => user_O,
I0 => user_I0,
I1 => user_I1,
S => user_S);

Verilog Instantiation Template

MUXF7_D MUXF7_D_instance_name (.LO (user_LO),
.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

804

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ISE 6.3i

MUXF7_L

MUXF7_L
2-to-1 Lookup Table Multiplexer with Local Output
Architectures Supported
MUXF7_L
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I0

LO

I1
S
X8433

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXF7_L provides a multiplexer function in a full Spartan-3, Virtex-II, Virtex-II Pro,

and Virtex-II Pro X CLB for creating a function-of-7 lookup table or a 16-to-1
multiplexer in combination with the associated lookup tables. Local outputs (LO) of
MUXF6 are connected to the I0 and I1 inputs of the MUXF7. The S input is driven
from any internal net. When Low, S selects I0. When High, S selects I1.
The LO output is used to connect to other inputs within the same CLB slice.
See also MUXF7 and MUXF7_D.
Inputs

Output

I0

I1

LO

I0

I0

I1

I1

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXF7_L should be placed
-- after architecture statement but before begin keyword
component MUXF7_L
port (LO : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for MUXF7_L
-- should be placed after architecture declaration but
-- before the begin keyword

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805

MUXF7_L

-- Attributes should be placed here

-- Component Instantiation for MUXF7_L should be placed
-- in architecture after the begin keyword
MUXF7_L_INSTANCE_NAME : MUXF7_L
port map (LO => user_LO,
I0 => user_I0,
I1 => user_I1,
S => user_S);

Verilog Instantiation Template

MUXF7_L MUXF7_L_instance_name (.LO (user_LO),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

806

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ISE 6.3i

MUXF8

MUXF8
2-to-1 Lookup Table Multiplexer with General Output
Architectures Supported
MUXF8
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

I0
I1

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

MUXF8 provides a multiplexer function in two full Spartan-3, Virtex-II, Virtex-II Pro,
and Virtex-II Pro X CLBs for creating a function-of-8 lookup table or a 32-to-1
multiplexer in combination with the associated lookup tables, MUXF5s, MUXF6s, and
MUXF7s. Local outputs (LO) of MUXF7 are connected to the I0 and I1 inputs of the
MUXF8. The S input is driven from any internal net. When Low, S selects I0. When
High, S selects I1.

X8434

Inputs

Outputs

I0

I1

I0

I0

I1

I1

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXF8 should be placed
-- after architecture statement but before begin keyword
component MUXF8
port (O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for MUXF8
-- should be placed after architecture declaration but
-- before the begin keyword
-- Attributes should be placed here

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807

MUXF8

-- Component Instantiation for MUXF8 should be placed

-- in architecture after the begin keyword
MUXF8_INSTANCE_NAME : MUXF8
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
S => user_S);

Verilog Instantiation Template

MUXF8 MUXF8_instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

808

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ISE 6.3i

MUXF8_D

MUXF8_D
2-to-1 Lookup Table Multiplexer with Dual Output
Architectures Supported
MUXF8_D
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I0
I1

LO
O

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXF8_D provides a multiplexer function in two full Spartan-3, Virtex-II, Virtex-II

Pro, and Virtex-II Pro X CLBs for creating a function-of-8 lookup table or a 32-to-1
multiplexer in combination with the associated four lookup tables and two MUXF8s.
Local outputs (LO) of MUXF7 are connected to the I0 and I1 inputs of the MUXF8. The
S input is driven from any internal net. When Low, S selects I0. When High, S selects
I1.

X8435

Outputs O and LO are functionally identical. The O output is a general interconnect.

The LO output is used to connect to other inputs within the same CLB slice.
See also MUXF8 and MUXF8_L.
Inputs

Outputs

I0

I1

LO

I0

I0

I0

I1

I1

I1

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXF8_D should be placed
-- after architecture statement but before begin keyword
component MUXF8_D
port (LO : out STD_ULOGIC;
O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;

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809

MUXF8_D

-- Component Attribute specification for MUXF8_D

-- should be placed after architecture declaration but
-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for MUXF8_D should be placed
-- in architecture after the begin keyword
MUXF8_D_INSTANCE_NAME : MUXF8_D
port map (LO => user_LO,
O => user_O,
I0 => user_I0,
I1 => user_I1,
S => user_S);

Verilog Instantiation Template

MUXF8_D MUXF8_D_instance_name (.LO (user_LO),
.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

810

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ISE 6.3i

MUXF8_L

MUXF8_L
2-to-1 Lookup Table Multiplexer with Local Output
Architectures Supported
MUXF8_L
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

I0

LO

I1
S
X8436

No

CoolRunner XPLA3

No

CoolRunner-II

No

MUXF8_L provides a multiplexer function in two full Spartan-3, Virtex-II, Virtex-II

Pro, and Virtex-II Pro X CLBs for creating a function-of-8 lookup table or a 32-to-1
multiplexer in combination with the associated four lookup tables and two MUXF8s.
Local outputs (LO) of MUXF7 are connected to the I0 and I1 inputs of the MUXF8. The
S input is driven from any internal net. When Low, S selects I0. When High, S selects
I1.
The LO output is used to connect to other inputs within the same CLB slice.
See also MUXF8 and MUXF8_D.
Inputs

Output

I0

I1

LO

I0

I0

I1

I1

Usage
For HDL, this design element can only be instantiated.

VHDL Instantiation Template

-- Component Declaration for MUXF8_L should be placed
-- after architecture statement but before begin keyword
component MUXF8_L
port (LO : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
-- Component Attribute specification for MUXF8_L
-- should be placed after architecture declaration but

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811

MUXF8_L

-- before the begin keyword

-- Attributes should be placed here
-- Component Instantiation for MUXF8_L should be placed
-- in architecture after the begin keyword
MUXF8_L_INSTANCE_NAME : MUXF8_L
port map (LO => user_LO,
I0 => user_I0,
I1 => user_I1,
S => user_S);

Verilog Instantiation Template

MUXF8_L MUXF8_L_instance_name (.LO (user_LO),
.I0 (user_I0),
.I1 (user_I1),
.S (user_S));

812

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Libraries Guide
ISE 6.3i

NAND2-9

NAND2-9
2- to 9-Input NAND Gates with Inverted and Non-Inverted Inputs
Architectures Supported
NAND2, NAND3, NAND4, NAND5
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

NAND2B1, NAND2B2, NAND3B1, NAND3B2, NAND3B3,

NAND4B1, NAND4B2, NAND4B3, NAND4B4, NAND5B1,
NAND5B2, NAND5B3, NAND5B4, NAND5B5
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro
NAND6, NAND7, NAND8, NAND9

Libraries Guide
ISE 6.3i

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

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813

NAND2-9

I1
I0

NAND2

I5
I4

I4

I3

I2
I1
I0

I3

I2
I1
I0

I3

I2

I2

I1

I1

I0

NAND3

I0

NAND4

NAND5

NAND6
I6

I1
I0

I2
I1
I0

I4

I3
I2
I1
I0

I3

I5
I4

I2

I3

I1

I2

I0

I1
I0

NAND2B1

I1
I0

NAND3B1

I2
I1
I0

NAND4B1

NAND5B1
I7
I6

I4
I3

I3
I2
I1
I0

NAND7

I5
I4

I2
I1
I0

I3
I2
I1
I0

NAND2B2

NAND3B2

NAND4B2

NAND5B2

NAND8
IA

I2
I1
I0

I7
I6

I4
I3

I3
I2
I1
I0

I5
I4

I2

I3

I1

I2

I0

I1
I0

NAND3B3

NAND4B3

NAND5B3

NAND9

I4
I3

I3
I2
I1
I0

I2
I1
I0
NAND4B4

NAND5B4

I4
I3
I2
I1
I0
NAND5B5

X9429

NAND Gate Representations

NAND gates of up to five inputs are available in any combination of inverting and
non-inverting inputs. NAND gates of six to nine inputs are available with only noninverting inputs. To invert inputs, use external inverters. Since each input uses a CLB
resource, replace gates with unused inputs with gates having the necessary number of
inputs.
See NAND12, 16 for information on additional NAND functions.

814

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Libraries Guide
ISE 6.3i

NAND2-9

FMAP
I4
I3
S1

I2

S0

RLOC=R0C0.S0

S1

I5
I4

I1

I7
I6

FMAP

AND4
I7

I4

I6

I3

I5
I4

NAND2
I3

I2

S1

I1
RLOC=R0C0.S1

I2

S0

I1
I0

FMAP
I3

AND4

I4

I2

I3

I1
I0
X8701

I2

S0

I1
RLOC=R0C0.S1

NAND8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I4
I3
S1

I2

S0

I1

RLOC=X0Y1
I7
I6

S1

FMAP

I5
I4
AND4

I7

I4

I6

I3

I5

I2

I4

I1

S1

RLOC=X0Y0

NAND2

FMAP

I3
I2

S0

I1
I0
AND4

I3

I4

I2

I3

I1

I2

I0

I1

S0

RLOC=X0Y0
X9349

NAND8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
NAND2 through NAND5 are primitives that can be inferred or instantiated. NAND6
through NAND9 are macros which can be inferred.

VHDL Instantiation Template for NAND5

Following is the VHDL code for NAND5. To instantiate NAND2, remove I2, I3, and
I4. To instantiate NAND3, remove I3 and I4, For NAND4, remove I4. NAND2B1, and
NAND2B2 have the same code as NAND2. NAND3B1, 3B2, and 3B3 have the same
code as NAND3 and so forth.

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815

NAND2-9

-- Component Declaration for NAND5 should be placed

-- after architecture statement but before begin keyword
component NAND5
port (O : out
I0 : in
I1 : in
I2 : in
I3 : in
I4 : in
end component;
-----

STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC);

Component Attribute specification for NAND5

should be placed after architecture declaration but
before the begin keyword
Attributes should be placed here

-- Component Instantiation for NAND5 should be placed

-- in architecture after the begin keyword
NAND5_INSTANCE_NAME : NAND5
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2,
I3 => user_I3,
I4 => user_I4);

Verilog Instantiation Template for NAND5

NAND5 NAND5_instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.I2 (user_I2),
.I3 (user_I3),
.I4 (user_I4));

816

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Libraries Guide
ISE 6.3i

NAND12, 16

NAND12, 16
12- and 16-Input NAND Gates with Non-Inverted Inputs
Architectures Supported
NAND12, NAND16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

The NAND function is performed in the Configurable Logic Block (CLB) function
generators for Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II
Pro, and Virtex-II Pro X. The 12- and 16-input NAND functions are available only
with non-inverting inputs. To invert some or all inputs, use external inverters.

I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0

See NAND2-9 for more information on NAND functions.

FMAP

NAND12

S2

X9430

S1
S0

I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0

I4
I3
I2

I1
RLOC=R0C0.S0

I11

FMAP

I10

S2

I9
I8

I11
I10
I9
I8

AND4
I7
I6

I7
I6

I3

NAND16
X9431

I2

S0

I1
I0

S2

I1

FMAP

NAND3

AND4

I2

RLOC=R0C0.S0

S1

I5
I4

I4
I3

I5
I4

I4
I3
I2

S1

I1
RLOC=R0C0.S1

AND4

FMAP
I3
I2
I1
I0

I4
I3
I2

S0

I1
RLOC=R0C0.S1

X8704

NAND12 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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817

NAND12, 16

FMAP
I4
I11
I10

S2

I9

S2

I3

S1

I2

S0

I1

I8
RLOC=X0Y1

AND4

FMAP
I7
I6

S1

I5

I11

I4

I10

I3

I9

I2

I8

I4

S2

I1

NAND3

AND4

RLOC=X0Y1

FMAP
I3
I2

S0

I1
I0
AND4

I7

I4

I6

I3

I5

I2

I4

I1

S1

RLOC=X0Y0

FMAP
I3

I4

I2

I3

I1

I2

I0

I1

S0

RLOC=X0Y0
X9350

NAND12 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

818

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Libraries Guide
ISE 6.3i

NAND12, 16

FMAP
I15

I15

MUXCY

I14

S3

I13

0
VCC

I12

I14
RLOC=R0C0.S1

I13

DI

I12

CI

I4
I3
O

S3

I2
I1

AND4
RLOC=R0C0.S1
C2
FMAP
I11

LO

I11

MUXCY_L

I10

S2

I9

I10
RLOC=R0C0.S1

S
0

DI

I8

I9
I8

CI

I4
I3
O

S2

I2
I1

AND4
RLOC=R0C0.S1
C1
FMAP
I7

LO

I7

MUXCY_L

I6

S1

I5

I6
RLOC=R1C0.S1

S
0
DI

I4

I5

1
I4

CI

I4
I3
O

S1

I2
I1

AND4
RLOC=R1C0.S1

C0

FMAP
LO

I3

I3

MUXCY_L

I2

S0

I1

RLOC=R1C0.S1

S
0
DI

I0

I2
I1

1
CI

AND4

I0

I4
I3
O

S0

I2
I1
RLOC=R1C0.S1

CIN

X8709
GND

NAND16 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

819

NAND12, 16

FMAP
I15
I15

I14
S3

MUXCY

I13

0
VCC

DI

I12

I14
RLOC=X0Y1
I13

1
I12

CI

AND4

I4
I3
O

S3

I2
I1
RLOC=X0Y1

C2

FMAP
I11
I11

LO

I10
S2

I9

0
DI

I8

I10

MUXCY_L

RLOC=X0Y1
I9

1
I8

CI

AND4

I4
I3
O

S2

I2
I1
RLOC=X0Y1

C1

FMAP
I7
I7

LO

I6
S1

I5

0
DI

I4

I6

MUXCY_L

RLOC=X0Y0
I5

1
I4

CI

AND4

I4
I3
O

S1

I2
I1
RLOC=X0Y0

C0

FMAP
I3

I3

LO

I2
S0

I1

MUXCY_L
0
DI

I0

RLOC=X0Y0

1
CI

I2
I1
I0

I4
I3
O

S0

I2
I1

AND4
RLOC=X0Y0
CIN

GND

X9351

NAND16 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, NAND12 and NAND16 are macros that are inferred. See NAND2-9 for
more information about inferring NAND gates.

820

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

NOR2-9

NOR2-9
2- to 9-Input NOR Gates with Inverted and Non-Inverted Inputs
Architectures Supported
NOR2, NOR3, NOR4, NOR5
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

NOR2B1, NOR2B2, NOR3B1, NOR3B2, NOR3B3,

NOR4B1, NOR4B2, NOR4B3, NOR4B4, NOR5B1,
NOR5B2, NOR5B3, NOR5B4, NOR5B5
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro
NOR6, NOR7

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro
NOR8, NOR9

Libraries Guide
ISE 6.3i

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

www.xilinx.com
1-800-255-7778

821

NOR2-9

I5
I4

I3
0
I0

I4

I3

I2

I1

I2

I1

I3

0
I1

I0

I2

I0

I2

I1

I1

I0

I0
NOR3

NOR2

NOR4

NOR5
I4

I3

I3

I2
I1
0
I0

I2

I1

0
I1

I0

NOR3B1

I2

I1

I0

NOR2B1

NOR6

I6

I0

I5
I4

NOR5B1

NOR4B1

I3
I3
I2
I1
0
I0

I2

I1

I0

I0

I1
I0

NOR2B2

I1

I3

I2

I1

I2

I4

NOR3B2

NOR7

I0

NOR4B2

NOR5B2
I7
I6

I4

I3

I5

I3

I2

I2
0

I1
I0

0
I1

I2

0
I3

I1

I0

I4

I2

I0

I1
I0
NOR3B3

NOR4B3

NOR5B3

NOR8

I4
I3

I3

I2
0

I1

IA

I2

I1

I0

I6

I0
NOR4B4

I7

I5
I4

NOR5B4

I3

I4

I2

I3
I2

I1
I0

I1
I0

NOR9
NOR5B5
X9432

NOR Gate Representations

NOR gates of up to five inputs are available in any combination of inverting and noninverting inputs. NOR gates of six to nine inputs are available with only noninverting inputs. To invert some or all inputs, use external inverters. Since each input
uses a CLB resource, replace gates with unused inputs with gates having the
necessary number of inputs.
See NOR12, 16 for information on additional NOR functions.

822

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

NOR2-9

FMAP
I4
I3
S1
S0

I2

RLOC=R0C0.S0

S1

I5
I4

I1

I7
I6

FMAP

OR4

I7

I4

I6

I3

I5
I4

NOR2

I2

S1

I1

I3

RLOC=R0C0.S1

I2

S0

I1
I0

FMAP
I3

OR4

I4

I2

I3

I1
I0

I2

S0

I1

X8700

RLOC=R0C0.S1

NOR8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I4
I7

I3

I6

S1

I5

S1

I2

S0

I1

I4
OR4

RLOC=X0Y1
O

FMAP
NOR2
I3
I2

S0

I1

I7

I4

I6

I3

I5

I2

I4

I1

S1

I0
OR4

RLOC=X0Y0

FMAP
I3

I4

I2

I3

I1

I2

I0

I1

S0

RLOC=X0Y0
X9352

NOR8 Implementation Spartan-3, Virtex-II, Virtex-II Pro , Virtex-II Pro X

Usage
NOR2 through NOR5 are primitives that can be inferred or instantiated. NOR6
through NOR9 are macros which can be inferred.

VHDL Instantiation Template for NOR5

Following is the VHDL code for NOR5. To instantiate NOR2, remove I2, I3, and I4. To
instantiate NOR3, remove I3 and I4, For NOR4, remove I4. NOR2B1, and NOR2B2

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

823

NOR2-9

have the same code as NOR2. NOR3B1, 3B2, and 3B3 have the same code as NOR3
and so forth.
-- Component Declaration for NOR5 should be placed
-- after architecture statement but before begin keyword
component NOR5
port (O : out
I0 : in
I1 : in
I2 : in
I3 : in
I4 : in
end component;

STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC);

-- Component Attribute specification for NOR5

-- should be placed after architecture declaration but
-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for NOR5 should be placed
-- in architecture after the begin keyword
NOR5_INSTANCE_NAME : NOR5
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2,
I3 => user_I3,
I4 => user_I4);

Verilog Instantiation Template for NOR5

NOR5 NOR5_instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.I2 (user_I2),
.I3 (user_I3),
.I4 (user_I4));

824

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

NOR12, 16

NOR12, 16
12- and 16-Input NOR Gates with Non-Inverted Inputs
Architectures Supported
NOR12, NOR16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0

No

CoolRunner XPLA3

No

CoolRunner-II

No

The 12- and 16-input NOR functions are available only with non-inverting inputs. To
invert some or all inputs, use external inverters.
See NOR2-9 for more information on NOR functions.

NOR12
X9433

I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
NOR16
X9434

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

825

NOR12, 16

FMAP
I15

I15

MUXCY
S3

I13

RLOC=R0C0.S1

S
0

I3
O

I13
I12

CI

S3

I2

DI

I12

I4

I14

I14

I1

NOR4
RLOC=R0C0.S1
C2
FMAP
I11

LO

I11

MUXCY_L

I10

S2

I10
RLOC=R0C0.S1

I9

DI

I8

I4
I3
O

I9
I8

CI

NOR4

S2

I2
I1
RLOC=R0C0.S1

C1
FMAP
I7

LO

I7

MUXCY_L

I6

S1

I5

I6
RLOC=R1C0.S1

S
0

I3
O

I5
I4

CI

S1

I2

DI

I4

I4

I1

NOR4
RLOC=R1C0.S1

C0

FMAP
LO

I3

I3

MUXCY_L

I2

S0

RLOC=R1C0.S1

S
0

I1
DI

I0

I4

I2

I3
O

I1

1
CI

S0

I2

I0

I1

NOR4
RLOC=R1C0.S1

CIN
GND
VCC

X8707

NOR16 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

826

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

NOR12, 16

FMAP
I15

I15

I14
S3

I13

MUXCY
0
1
DI

I12

RLOC=X0Y1

I14
I13

CI

I12

I4
I3
O

S3

I2
I1

NOR4
C2

RLOC=X0Y1

FMAP
I11

I11

LO

I10
S2

I9
I8

MUXCY_L
0
1
DI
CI

RLOC=X0Y1

I10
I9
I8

I4
I3
O

S2

I2
I1

NOR4
RLOC=X0Y1

C1

FMAP
I7

I7

LO

I6
S1

I5

MUXCY_L
0
1
DI

I4

RLOC=X0Y0

I6
I5

CI

I4

I4
I3
O

S1

I2
I1

NOR4
RLOC=X0Y0

C0

FMAP
I3

I3

LO

I2
S0

I1

MUXCY_L
0
1
DI

I0

RLOC=X0Y0

CI

I2
I1
I0

I4
I3
O

S0

I2
I1

NOR4
RLOC=X0Y0
CIN
GND
VCC
X9353

NOR16 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, NOR12 and NOR16 are macros that can be inferred. See NOR2-9 for more
information about inferring NOR gates.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

827

828

NOR12, 16

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OBUF, 4, 8, 16

OBUF, 4, 8, 16
Single- and Multiple-Output Buffers
Architectures Supported
OBUF
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

OBUF4, OBUF8, OBUF16

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

O
X9445

O0

I1

O1

I2

O2

I3

O3

Macro

CoolRunner-II

Macro

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, if a high impedance (Z)

signal from an on-chip 3-state buffer (like BUFE) is applied to the input of an OBUF, it
is propagated to the CPLD device output pin.

OBUF4
I0

CoolRunner XPLA3

OBUF, OBUF4, OBUF8, and OBUF16 are single and multiple output buffers. An
OBUF isolates the internal circuit and provides drive current for signals leaving a
chip. OBUFs exist in input/output blocks (IOB). The output (O) of an OBUF is
connected to an OPAD or an IOPAD.

OBUF
I

Macro

The interface standard used by OBUF, 4, 8, and 16 is LVTTL. Also, Virtex, Virtex-E,
Spartan-II, and Spartan-IIE OBUF, 4, 8, and 16 have selectable drive and slew rates
using the DRIVE and SLOW or FAST constraints. The defaults are DRIVE=12 mA and
SLOW slew.

X9446

OBUF8
I [7:0]

O [7:0]
X9850

OBUF16
I [15:0]

O [15:0]
X9851

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

829

OBUF, 4, 8, 16

O[7:0]
IO

O0
OBUF

I1

O1

OBUF

I2

O2

OBUF

I3

O3

OBUF

I4

O4

OBUF

I5

O5

OBUF

I6

O6

OBUF

I7
I[7:0]

O7

OBUF
X7654

OBUF8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II,

Spartan-II, Spartan-IIE, Virtex, Virtex-E
O[7:0]

I0

O0
OBUF

I1

O1
OBUF

I2

O2
OBUF

I3

O3
OBUF

I4

O4
OBUF

I5

O5
OBUF

I6

O6
OBUF

I7

O7
OBUF

I[7:0]
X9840

OBUF8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Available Attributes
Attach an IOSTANDARD attribute to an OBUF and assign the value indicated in the
"IOSTANDARD (Attribute Value)" column to program the output for the I/O
standard associated with that value.
The LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33 attributes also require
a slew value (FAST or SLOW) and DRIVE value. See the FAST, SLOW, and DRIVE
attribute descriptions in the Xilinx Constraints Guide.
Spartan-II, Spartan-IIE, Virtex, and Virtex-E and IOSTANDARD Attributes
Architectures

Attribute Values
Termina
tion
Type
Output

Spartan-II,
Virtex

Spartan-IIE,
Virtex-E

Drive

Slew

AGP

No

No

None

1.32

3.3

CTT

No

No

None

No

3.3

GTL

No

No

None

.8

No

GTLP

No

No

None

1.0

No

IOSTANDARD

830

www.xilinx.com
1-800-255-7778

VREF
Input *

Output VCCO

Libraries Guide
ISE 6.3i

OBUF, 4, 8, 16

Spartan-II, Spartan-IIE, Virtex, and Virtex-E and IOSTANDARD Attributes

Architectures

Attribute Values
Termina
tion
Type
Output

Spartan-II,
Virtex

Spartan-IIE,
Virtex-E

Drive

Slew

HSTL_I

No

No

None

.75

1.5

HSTL_III

No

No

None

.9

1.5

HSTL_IV

No

No

None

.9

1.5

LVCMOS2

No

No

None

No

2.5

LVCMOS18

2, 4, 6, 8,
12, 16

Fast/Slo None
w

No

1.8

LVDS

No

No

None

No

2.5

LVPECL

No

No

None

No

3.3

2, 4, 6, 8,
12, 16, 24

Fast/Slo None
w

No

3.3

IOSTANDARD

VREF
Input *

Output VCCO

LVTTLa

PCI33_3

No

No

None

No

3.3

PCI33_5

No

No

None

No

3.3

PCI66_3

No

No

None

No

3.3

No

No

None

No

3.3

PCIx66_3
SSTL2_I

No

No

None

1.25

2.5

SSTL2_II

No

No

None

1.25

2.5

SSTL3_I

No

No

None

1.5

3.3

SSTL3_II

No

No

None

1.5

3.3

Not

supported for Virtex-E.

b The LVTTL an LVCMOS18 attributes also require a slew value (FAST or SLOW) and DRIVE value. See the FAST, SLOW,

and DRIVE attribute descriptions in the Xilinx Constraints Guide for valid values for each architecture.

Virtex-II, Virtex-II Pro, Virtex-II Pro X and IOSTANDARD Attributes

Architectures

IOSTANDARD

Virtex-II

AGP

GTL

Attribute Values

Virtex-II Pro,
Virtex-II Pro
X

Terminati
on
Type
Output

VREF
Input *

Output
VCCO

Drive

Slew

No

No

None

1.32

3.3

No

No

None

.8

No

GTL_DCI

No

No

Single

.8

1.2

GTLP

No

No

None

1.0

No

GTLP_DCI

No

No

Single

1.0

1.5

HSTL_I

No

No

None

.75

1.5

HSTL_I_18

No

No

None

.90

1.8

HSTL_I_DCI

No

No

None

.75

1.5

HSTL_I_DCI_18

No

No

None

.9

1.8

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

831

OBUF, 4, 8, 16

Virtex-II, Virtex-II Pro, Virtex-II Pro X and IOSTANDARD Attributes

Architectures

Attribute Values
Terminati
on
Type
Output

Virtex-II

Virtex-II Pro,
Virtex-II Pro
X

Drive

Slew

HSTL_II

No

No

None

.75

1.5

HSTL_II_18

No

No

None

.9

1.8

HSTL_II_DCI

No

No

Split

.75

1.5

HSTL_II_DCI_18

No

No

Split

.9

1.8

HSTL_III

No

No

None

.9

1.5

HSTL_III_18

No

No

None

1.1

1.8

IOSTANDARD

VREF
Input *

Output
VCCO

HSTL_III_DCI

No

No

None

.9

1.5

HSTL_III_DCI_18

No

No

None

1.1

1.8

HSTL_IV

No

No

None

.9

1.5

HSTL_IV_18

No

No

None

1.1

1.8

HSTL_IV_DCI

No

No

Single

.9

1.5

HSTL_IV_DCI_18

No

No

Single

1.1

1.8

2, 4, 6, 8

Fast/Slo None
w

No

1.2

LVCMOS12a
LVCMOS15a

2, 4, 6, 8,
12, 16

Fast/Slo None
w

No

1.5

LVCMOS18a

2, 4, 6, 8,
12, 16

Fast/Slo None
w

No

1.8

LVCMOS25a

2, 4, 6, 8,
12, 16, 24

Fast/Slo None
w

No

2.5

LVCMOS33a

2, 4, 6, 8,
12, 16, 24

Fast/Slo None
w

No

3.3

LVDCI_15

No

No

Driver

No

1.5

LVDCI_18

No

No

Driver

No

1.8

LVDCI_25

No

No

Driver

No

2.5

LVDCI_33

No

No

Driver

No

3.3

LVDCI_DV2_15

No

No

Driver

No

1.5

LVDCI_DV2_18

No

No

Driver

No

1.8

LVDCI_DV2_25

No

No

Driver

No

2.5

LVDCI_DV2_33

No

No

Driver

No

3.3

LVTTLa

2, 4, 6, 8,
12, 16, 24

No

3.3

PCI33_3

No

No

None

No

3.3

PCI66_3

No

No

None

No

3.3

PCIX

No

No

None

No

3.3

SSTL18_I

No

No

None

.9

1.8

SSTL18_I_DCI

No

No

None

.9

1.8

SSTL18_II

No

No

None

.9

1.8

832

www.xilinx.com
1-800-255-7778

Fast/Slo None
w

Libraries Guide
ISE 6.3i

OBUF, 4, 8, 16

Virtex-II, Virtex-II Pro, Virtex-II Pro X and IOSTANDARD Attributes

Architectures

Attribute Values
Terminati
on
Type
Output

Virtex-II

Virtex-II Pro,
Virtex-II Pro
X

Drive

Slew

SSTL18_II_DCI

No

No

Split

.9

1.8

SSTL2_I

No

No

None

1.25

2.5

IOSTANDARD

VREF
Input *

Output
VCCO

SSTL2_I_DCI

No

No

None

1.25

2.5

SSTL2_II

No

No

None

1.25

2.5

SSTL2_II_DCI

No

No

Split

1.25

2.5

SSTL3_I

No

No

None

1.5

3.3

SSTL3_I_DCI

No

No

None

1.5

3.3

SSTL3_II

No

No

None

1.5

3.3

SSTL3_II_DCI

No

No

Split

1.5

3.3

* VREF requirement when this IOSTANDARD is an input.

Usage
OBUFs are typically inferred for all top level input ports, but they can also be
instantiated if necessary.

VHDL Instantiation Template

-- Component Declaration for OBUF should be placed
-- after architecture statement but before begin keyword
component OBUF
-- synthesis translate_off
generic (
IOSTANDARD : string:= "LVTTL";
DRIVE : integer := 2;
SLEW : string := "FAST");
-- synthesis translate_on
port (O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for OBUF
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here
attribute IOSTANDARD : string;
attribute DRIVE : integer;
attribute SLEW : string;
attribute IOSTANDARD of OBUF_instance_name : label is "LVTTL";
attribute DRIVE of OBUF_instance_name : label is 2;
attribute SLEW of OBUF_instance_name : label is "FAST";

-- Component Instantiation for OBUF should be placed

Libraries Guide
ISE 6.3i

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1-800-255-7778

833

OBUF, 4, 8, 16

-- in architecture after the begin keyword

OBUF_INSTANCE_NAME : OBUF
-- synthesis translate_off
generic map (
IOSTANDARD => string_value,
DRIVE => integer := integer_value,
SLEW => string := string_value);
-- synthesis translate_on
port map (O => user_O,
I => user_I);

Verilog Instantiation Template

OBUF_instance_name (.O (user_O),
.I (user_I));
defparam OBUF_instance_name.IOSTANDARD => string_value;
defparam OBUF_instance_name.DRIVE => integer_value;
defparam OBUF_instance_name.SLEW => string_value;

834

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Libraries Guide
ISE 6.3i

OBUFDS

OBUFDS
Differential Signaling Output Buffer with Selectable I/O Interface
Architectures Supported
OBUFDS
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

O
OB

OBUFDS
X9259

No

CoolRunner XPLA3

No

CoolRunner-II

No

OBUFDS is a single output buffer that supports low-voltage, differential signaling

(1.8v CMOS). OBUFDS isolates the internal circuit and provides drive current for
signals leaving the chip. Its output is represented as two distinct ports (O and OB),
one deemed the "master" and the other the "slave." The master and the slave are
opposite phases of the same logical signal (for example, MYNET and MYNETB).
Inputs

Outputs

OB

Available Attributes
The IOSTANDARD attribute values listed in the following table can be applied to an
OBUFDS component to provide SelectIO interface capability. See the Xilinx
Constraints Guide for information using these attributes.
Attach an IOSTANDARD attribute to an OBUFDS and assign the value indicated in the
"IOSTANDARD (Attribute Value)" column to program the output for the I/O standard
associated with that value.
Architectures
IOSTANDARD

Spartan-3

BLVDS_25

Attribute Values

Virtex-II

Virtex-II Pro,
Virtex-II Pro X

Termination
Type Output

VREF
Input *

Output VCCO

None

No

2.5

LDT_25

None

No

2.5

LVDS_25 (default)

None

No

2.5

None

No

3.3

None

No

2.5

None

No

3.3

None

No

2.5

None

No

3.3

LVDS_33
LVDSEXT_25
LVDSEXT_33

LVPECL_25
LVPECL_33

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

835

OBUFDS

Architectures
IOSTANDARD

Spartan-3

ULVDS_25

Attribute Values

Virtex-II

Virtex-II Pro,
Virtex-II Pro X

Termination
Type Output
None

VREF
Input *

Output VCCO

No

2.5

* VREF requirement when this IOSTANDARD is an input.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- OBUFDS: Differential Output Buffer
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
OBUFDS_inst : OBUFDS
-- Edit the following generics to specify the I/O standard, drive and
slew rate.
generic map (
DRIVE => 12,
IOSTANDARD => "LVDS_25",
SLEW => "SLOW")
port map (
O => O,
-- Diff_p output (connect to top-level port)
OB => OB, -- Diff_n output (connect to top-level port)
I => I
-- Buffer input
);
-- End of OBUFDS_inst instantiation

Verilog Instantiation Template

// OBUFDS: Differential Output Buffer
//
Virtex-II/II-Pro, Spartan-3
// Xilinx HDL Libraries Guide version 7.1i
OBUFDS OBUFDS_inst (
.O(O),
// Diff_p output(connect directly to top-level port)
.OB(OB), // Diff_n output (connect directly to top-level port)
.I(I)
// Buffer input
);
// Edit the following defparams to specify the I/O standard, drive and
// slew rate. If the instance name is change, that change needs to be
// reflecting the this defparam.
defparam OBUFDS_inst.DRIVE = 12;
defparam OBUFDS_inst.IOSTANDARD = "LVDS_25";
defparam OBUFDS_inst.SLEW = "SLOW";
// End of OBUFDS_inst instantiation

836

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Libraries Guide
ISE 6.3i

OBUFE, 4, 8, 16

OBUFE, 4, 8, 16
3-State Output Buffers with Active-High Output Enable
Architectures Supported
OBUFE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

OBUFE4, OBUFE8, OBUFE16

Spartan-II, Spartan-IIE

Macro

Spartan-3

No

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OBUFE

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

OBUFE, OBUFE4, OBUFE8, and OBUFE16 are 3-state buffers with inputs I, I3 I0, I7
I0, and I15-I0, respectively; outputs O, O3 O0, O7 O0, and O15-O0, respectively;
and active-High output enable (E). When E is High, data on the inputs of the buffers is
transferred to the corresponding outputs. When E is Low, the output is High
impedance (off or Z state). An OBUFE isolates the internal circuit and provides drive
current for signals leaving a chip. An OBUFE output is connected to an OPAD or an
IOPAD. An OBUFE input is connected to the internal circuit.

E
I

Macro

O
X9447

OBUFE4
E
I0

O0

I1

O1

I2

O2

I3

O3

X9448

Inputs

Outputs

OBUFE8
E
I [7:0]

O [7:0]
OBUFE16

E
I

INV

O
OBUFT
X7860

X9848

OBUFE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

I [15:0]

O [15:0]
X9849

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

837

OBUFE, 4, 8, 16

LVTTL

SLOW 12

T
INV

O
OBUFT
X9355

OBUFE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

O[7:0]
E
IO

O0
E

OBUFE

OBUFE

OBUFE

OBUFE

OBUFE

OBUFE

OBUFE

I1

O1

I2

O2

I3

O3

I4

O4

I5

O5

I6

O6

I7
I[7:0]

O7
OBUFE

X7649

OBUFE8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are instantiated rather than inferred.

VHDL Instantiation Template

-- Component Declaration for OBUFE should be placed
-- after architecture statement but before begin keyword
component OBUFE
port (O : out STD_ULOGIC;
E : in STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for OBUFE
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here
-- Component Instantiation for OBUFE should be placed
-- in architecture after the begin keyword
OBUFE_INSTANCE_NAME : OBUFE
port map (O => user_O,
E => user_E,
I => user_I);

838

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Libraries Guide
ISE 6.3i

OBUFE, 4, 8, 16

Verilog Instantiation Template

OBUFE_instance_name (.O (user_O),
.E (user_E),
.I (user_I));

Commonly Used Constraints

IOBDELAY

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

839

840

OBUFE, 4, 8, 16

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OBUFT, 4, 8, 16

OBUFT, 4, 8, 16
Single and Multiple 3-State Output Buffers with Active-Low Output
Enable
Architectures Supported
OBUFT
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

OBUFT4, OBUFT8, OBUFT16

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OBUFT
T
I

O
X9449

OBUFT4
T
I0

O0

I1

O1

I2

O2

I3

O3

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

OBUFT, OBUFT4, OBUFT8, and OBUFT16 are single and multiple 3-state output
buffers with inputs I, I3 I0, I7 I0, I15 I0, outputs O, O3 O0, O7 O0, O15 O0,
and active-Low output enables (T). When T is Low, data on the inputs of the buffers is
transferred to the corresponding outputs. When T is High, the output is high
impedance (off or Z state). OBUFTs isolate the internal circuit and provide extra drive
current for signals leaving a chip. An OBUFT output is connected to an OPAD or an
IOPAD.
OBUFT, 4, 8, and 16 use the LVTTL standard. Also, Virtex, Virtex-E, Virtex-II, Virtex-II
Pro, Virtex-II Pro X, Spartan-II, Spartan-IIE, and Spartan-3 OBUFT, 4, 8, and 16 have
selectable drive and slew rates using the DRIVE and SLOW or FAST constraints. The
defaults are DRIVE=12 mA and SLOW slew.
Inputs

X9450

Outputs

OBUFT16

I[15:0]

O[15:0]

X3817

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

841

OBUFT, 4, 8, 16

O[7:0]

OBUFT8

T
I

IO

O[7:0]

O0
T

OBUFT

OBUFT

OBUFT

OBUFT

OBUFT

OBUFT

OBUFT

I1

X3805

O1

I2

O2

I3

O3

I4

O4

I5

O5

I6

O6

I7
I[7:0]

O7
OBUFT

X7651

OBUFT8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II,

Spartan-II, Spartan-IIE, Virtex, Virtex-E
O[7:0]
T
O0

I0
T

OBUFT
O1

I1
T

OBUFT
O2

I2
T

OBUFT
O3

I3
T

OBUFT
O4

I4
T

OBUFT
O5

I5
T

OBUFT

I6

O6
T

OBUFT
O7

I7
OBUFT
I[7:0]
T

X9838

OBUFT8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Available Attributes
Attach an IOSTANDARD attribute to an OBUFT and assign the value indicated in the
"IOSTANDARD (Attribute Value)" column to program the output for the I/O
standard associated with that value.

842

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1-800-255-7778

Libraries Guide
ISE 6.3i

OBUFT, 4, 8, 16

The LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33 attributes also require a slew
value (FAST or SLOW) and DRIVE value. See the FAST, SLOW, and DRIVE attribute
descriptions in the Xilinx Constraints Guide.

Spartan-II, Spartan-IIE, Virtex, and Virtex-E and IOSTANDARD Attributes

Architectures

Attribute Values
Termination
Type
Output

VREF
Input *

Output
VCCO

Spartan-II,
Virtex

Spartan-IIE,
Virtex-E

Drive

Slew

AGP

No

No

None

1.32

3.3

CTT

No

No

None

No

3.3

GTL

No

No

None

.8

No

IOSTANDARD

GTLP

No

No

None

No

No

HSTL_I

No

No

None

.75

1.5

HSTL_III

No

No

None

.9

1.5

HSTL_IV

No

No

None

.9

1.5

LVCMOS2

No

No

None

No

2.5

LVCMOS18 b

2, 4, 6, 8,
12, 16

Fast/Slo
w

None

No

1.8

LVDS

No

No

None

No

2.5

No

No

None

No

3.3

LVTTLa

2, 4, 6, 8,
12, 16, 24

Fast/Slo
w

None

No

3.3

PCI33_3

No

No

None

No

3.3

PCI33_5

No

No

None

No

3.3

PCI66_3

No

No

None

No

3.3

No

No

None

No

3.3

LVPECL

PCIX66_3
SSTL2_I

No

No

None

1.25

2.5

SSTL2_II

No

No

None

1.25

2.5

SSTL3_I

No

No

None

1.5

3.3

SSTL3_II

No

No

None

1.5

3.3

Not supported for Virtex-E.

The LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33 attributes also require a slew value (FAST or SLOW)
and DRIVE value. See the FAST, SLOW, and DRIVE attribute descriptions in the Xilinx Constraints Guide for valid
values for each architecture.

.
Virtex-II, Virtex-II Pro, Virtex-II Pro X and IOSTANDARD Attributes
Architectures

IOSTANDARD

Virtex-II

AGP

GTL

Libraries Guide
ISE 6.3i

Attribute Values

Virtex-II Pro,
Virtex-II Pro
X

Terminati
on
Type
Output

VREF
Input *

Output
VCCO

Drive

Slew

No

No

None

1.32

3.3

No

No

None

.8

No

www.xilinx.com
1-800-255-7778

843

OBUFT, 4, 8, 16

Virtex-II, Virtex-II Pro, Virtex-II Pro X and IOSTANDARD Attributes

Architectures

Attribute Values
Terminati
on
Type
Output

Virtex-II

Virtex-II Pro,
Virtex-II Pro
X

Drive

Slew

GTL_DCI

No

No

Single

.8

1.2

GTLP

No

No

None

1.0

No

GTLP_DCI

No

No

Single

1.0

1.5

HSTL_I

No

No

None

.75

1.5

HSTL_I_18

No

No

None

.90

1.8

HSTL_I_DCI

No

No

None

.75

1.5

HSTL_I_DCI_1
8

No

No

None

.9

1.8

HSTL_II_18

No

No

None

.9

1.8

HSTL_II_DCI_
18

No

No

Split

.9

1.8

HSTL_III

No

No

None

.9

1.5

HSTL_III_18

No

No

None

1.1

1.8

HSTL_III_DCI

No

No

None

.9

1.5

HSTL_III_DCI_
18

No

No

None

1.1

1.8

HSTL_IV

No

No

None

.9

1.5

HSTL_IV_18

No

No

None

1.1

1.8

HSTL_IV_DCI

No

No

Single

.9

1.5

HSTL_IV_DCI_
18

No

No

Single

1.1

1.8

2, 4, 6

Fast/Slow None

No

1.2

IOSTANDARD

LVCMOS12a

VREF
Input *

Output
VCCO

LVCMOS15a

2, 4, 6, 8, 12

Fast/Slow None

No

1.5

LVCMOS18a

2, 4, 6, 8, 12,
16

Fast/Slow None

No

1.8

LVCMOS25a

2, 4, 6, 8, 12,
16, 24

Fast/Slow None

No

2.5

LVCMOS33a

2, 4, 6, 8, 12,
16, 24

Fast/Slow None

No

3.3

LVDCI_15

No

No

Driver

No

1.5

LVDCI_18

No

No

Driver

No

1.8

LVDCI_25

No

No

Driver

No

2.5

LVDCI_33

No

No

Driver

No

3.3

LVDCI_DV2_1
5

No

No

Driver

No

1.5

LVDCI_DV2_1
8

No

No

Driver

No

1.8

LVDCI_DV2_2
5

No

No

Driver

No

2.5

844

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Libraries Guide
ISE 6.3i

OBUFT, 4, 8, 16

Virtex-II, Virtex-II Pro, Virtex-II Pro X and IOSTANDARD Attributes

Architectures

Attribute Values

Virtex-II Pro,
Virtex-II Pro
X

IOSTANDARD

Virtex-II

Drive

Slew

LVDCI_DV2_3
3

No

No

LVTTLa

2, 4, 6, 8, 12,
16, 24

PCI33_3

No

No

PCI66_3

No

No

Terminati
on
Type
Output
Driver

VREF
Input *

Output
VCCO

No

3.3

No

3.3

None

No

3.3

None

No

3.3

Fast/Slow None

PCIX

No

No

None

No

3.3

SSTL18_I

No

No

None

.9

1.8

SSTL18_I_DCI

No

No

None

.9

1.8

SSTL18_II

No

No

None

.9

1.8

SSTL18_II_DCI

No

No

Split

.9

1.8

SSTL2_I

No

No

None

1.25

2.5

SSTL2_I_DCI

No

No

None

1.25

2.5

SSTL2_II

No

No

None

1.25

2.5

SSTL2_II_DCI

No

No

Split

1.25

2.5

SSTL3_I

No

No

None

1.5

3.3

SSTL3_I_DCI

No

No

None

1.5

3.3

SSTL3_II

No

No

None

1.5

3.3

SSTL3_II_DCI

No

No

Split

1.5

3.3

* VREF requirement when this IOSTANDARD is an input.

OBUFT and its variants have selectable drive and slew rates using the DRIVE and
FAST or SLOW constraints. The defaults are DRIVE=12 mA and SLOW slew.
When T is Low, data on the input of the buffer is transferred to the output. When T is
High, the output is high impedance (off or Z state). OBUFTs isolate the internal circuit
and provide extra drive current for signals leaving a chip.

Usage
For HDL, these design elements are instantiated rather than inferred.

VHDL Instantiation Template

-- Component Declaration for OBUFT should be placed
-- after architecture statement but before begin keyword
component OBUFT
-- synthesis translate_off
generic (
IOSTANDARD : string:= "LVTTL";
DRIVE : integer := 2;
SLEW : string := "FAST");
-- synthesis translate_on

Libraries Guide
ISE 6.3i

www.xilinx.com
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845

OBUFT, 4, 8, 16

port (O : out STD_ULOGIC;

I : in STD_ULOGIC;
T : in STD_ULOGIC);
end component;
-- Component Attribute specification for OBUFT
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here
attribute
attribute
attribute
attribute
attribute
attribute

IOSTANDARD : string;
DRIVE : integer;
SLEW : string;
IOSTANDARD of OBUFT_instance_name : label is "LVTTL";
DRIVE of OBUFT_instance_name : label is 2;
SLEW of OBUFT_instance_name : label is "FAST";

-- Component Instantiation for OBUFT should be

-- placed in architecture after the begin keyword
OBUFT_INSTANCE_NAME : OBUFT
-- synthesis translate_off
generic map (
IOSTANDARD => string_value,
DRIVE => integer := integer_value,
SLEW => string := string_value);
-- synthesis translate_on
port map (O => user_O,
I => user_I,
T => user_T);

Verilog Instantiation Template

OBUFT instance_name (.O (user_O),
.I (user_I),
.T (user_T));
defparam OBUFT_instance_name.IOSTANDARD => string_value;
defparam OBUFT_instance_name.DRIVE => integer_value;
defparam OBUFT_instance_name.SLEW => string_value;

846

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Libraries Guide
ISE 6.3i

OBUFTDS

OBUFTDS
3-State Differential Signaling Output Buffer with Active Low Output
Enable and Selectable I/O Interface
Architectures Supported
OBUFTDS
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

OBUFTDS is a single 3-state, differential signaling output buffer with active Low
enable and a Select I/O interface.

T
O
OB

OBUFTDS

When T is Low, data on the input of the buffer is transferred to the output (O) and
inverted output (OB). When T is High, both outputs are high impedance (off or Z
state).

X9260

Inputs

Outputs

OB

Available Attributes
Attach an IOSTANDARD attribute to an OBUFTDS and assign the value indicated in
the "IOSTANDARD (Attribute Value)" column to program the outputs for the I/O
standard associated with that value.
Architectures
IOSTANDARD

Spartan-3

Attribute Values

Virtex-II

Virtex-II Pro,
Virtex-II Pro X

Termination
Type Output

VREF
Input *

Output VCCO

None

No

2.5

LDT_25

None

No

2.5

LVDS_25 (default)

None

No

2.5

None

No

3.3

None

No

2.5

None

No

3.3

None

No

2.5

None

No

3.3

BLVDS_25

LVDS_33

LVPECL_25

LVPECL_33
LVDSEXT_25
LVDSEXT_33

Libraries Guide
ISE 6.3i

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1-800-255-7778

847

OBUFTDS

Architectures
IOSTANDARD
ULVDS_25

Attribute Values

Spartan-3

Virtex-II

Virtex-II Pro,
Virtex-II Pro X

Termination
Type Output
None

VREF
Input *

Output VCCO

No

2.5

* VREF requirement when this IOSTANDARD is an input.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- OBUFTDS: Differential 3-state Output Buffer
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
OBUFTDS_inst : OBUFTDS
-- Edit the following generics to specify the I/O standard, drive and
slew rate.
generic map (
DRIVE => 12,
IOSTANDARD => "LVDS_25",
SLEW => "SLOW")
port map (
O => O,
-- Diff_p output (connect directly to top-level port)
OB => OB,
-- Diff_n output (connect directly to top-level port)
I => I,
-- Buffer input
T => T
-- 3-state enable input
);
-- End of OBUFTDS_inst instantiation

Verilog Instantiation Template

// OBUFTDS: Differential 3-state Output Buffer
//
Virtex-II/II-Pro, Spartan-3
// Xilinx HDL Libraries Guide version 7.1i
OBUFTDS OBUFTDS_inst (
.O(O),
// Diff_p output (connect directly to top-level port)
.OB(OB), // Diff_n output (connect directly to top-level port)
.I(I),
// Buffer input
.T(T)
// 3-state enable input
);
// Edit the following defparams to specify the I/O standard, drive and
// slew rate. If the instance name is change, that change needs to be
// reflecting the this defparam.
defparam OBUFTDS_inst.DRIVE = 12;
defparam OBUFTDS_inst.IOSTANDARD = "LVDS_25";
defparam OBUFTDS_inst.SLEW = "SLOW";
// End of OBUFTDS_inst instantiation

848

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Libraries Guide
ISE 6.3i

OFD, 4, 8, 16

OFD, 4, 8, 16
Single- and Multiple-Output D Flip-Flops
Architectures Supported
OFD, OFD4, OFD8, OFD16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OFD

X3778

D0

OFD4

Q0

D1

Q1

D2

Q2

D3

Q3

CoolRunner XPLA3

No

CoolRunner-II

No

OFD, OFD4, OFD8, and OFD16 are single and multiple output D flip-flops.
The outputs (for example, Q3 Q0) are connected to OPADs or IOPADs. The data on
the D inputs is loaded into the flip-flops during the Low-to-High clock (C) transition
and appears on the Q outputs.
The flip-flops are asynchronously cleared with Low outputs when power is applied,
or when global reset is active.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

X3800

D[7:0]

GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

Q[7:0]

OFD8

Inputs

C
X3812

D[15:0]

No

OFD16

Outputs

Q[15:0]

C
VCC

FDCE

X3834
D

CE
C

O_OUT

Q
OBUF

C
CLR

IOB=TRUE

GND

X9766

OFD Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

849

OFD, 4, 8, 16

VCC

FDCE
D

Q_OUT

CE
C

LVTTL SLOW 12

OBUF

CLR

IOB=TRUE
X9361

GND

OFD Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

FD
D

Q_OUT

Q
OBUF

C
X6378

OFD Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

850

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1-800-255-7778

Libraries Guide
ISE 6.3i

OFD, 4, 8, 16

Q[7:0]
OFD
D0

Q0

Q0
OFD
D1

Q1

Q1
OFD
D2

Q2

Q2
OFD
D3

Q3

Q3
OFD
D4

Q4

Q4
OFD
D5

Q5

Q5
OFD
D6

Q6

Q6
OFD
D7

Q7

D[7:0]

Q7

X7644

OFD8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

851

OFD, 4, 8, 16

Q[7:0]
FD
D0

Q0

OBUF
C

Q0
FD
D1

Q1

OBUF
C

Q1
FD
D2

Q2

OBUF
C

Q2
FD
D3

Q3

OBUF
C

Q3
FD
D4

Q4

OBUF
C

Q4
FD
D5

Q5

OBUF
C

Q5
FD
D6

Q6

OBUF
C

Q6
FD
D7

Q7

OBUF
C

Q7

D[7:0]
C

X7648

OFD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

852

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Libraries Guide
ISE 6.3i

OFD, 4, 8, 16

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an OFD, you would infer
an FD and put the IOB = TRUE attribute on the component. Or, you could use the
map option pr o to pack all output registers into the IOBs.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

853

854

OFD, 4, 8, 16

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFD_1

OFD_1
Output D Flip-Flop with Inverted Clock
Architectures Supported
OFD_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OFD_1

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFD_1 is located in an input/output block (IOB). The output (Q) of the D flip-flop is
connected to an OPAD or an IOPAD. The data on the D input is loaded into the flipflop during the High-to-Low clock (C) transition and appears on the Q output.
The flip-flop is asynchronously cleared, output Low, when power is applied, or when
global reset is active.

X3779

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

VCC

FDCE
D

CB
INV

O
OBUF

CE
C

Q_OUT

CLR

IOB=TRUE
GND

X9771

OFD_1 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

855

OFD_1

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an OFD_1, you would
infer an FD_1 and put the IOB = TRUE attribute on the component. Or, you could use
the map option pr o to pack all output registers into the IOBs.

856

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Libraries Guide
ISE 6.3i

OFDDRCPE

OFDDRCPE
Dual Data Rate Output D Flip-Flop with Clock Enable and
Asynchronous Preset and Clear
Architectures Supported
OFDDRCPE
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

PRE
D0

OFDDRCPE

D1
CE
C0
C1
CLR
X9387

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFDDRCPE is a dual data rate (DDR) output D flip-flop with clock enable (CE) and
asynchronous preset (PRE) and clear (CLR). It consists of one output buffer and one
dual data rate flip-flop (FDDRCPE).
When the asynchronous PRE is High and CLR is Low, the Q output is preset High.
When CLR is High, Q is set Low. Data on the D0 input is loaded into the flip-flop
when PRE and CLR are Low and CE is High on the Low-to-High C0 clock transition.
Data on the D1 input is loaded into the flip-flop when PRE and CLR are Low and CE
is High on the Low-to-High C1 clock transition.
The INIT attribute does not apply to OFDDRCPE components.
The flip-flops are asynchronously cleared with Low outputs when power is applied.
Inputs

Outputs

C0

C1

CE

D0

D1

PRE
D0
D1
CE
C0
C1
CLR

CLR

PRE

No Chg

D0

D0

D1

D1

FDDRCPE
D0

PRE

LVTTL SLOW 12

Q_OUT

Q
OBUF

D1
CE
C0
C1
CLR
INIT = 0

X9362

OFDDRCPE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

857

OFDDRCPE

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- OFDDRCPE: Double Data Rate Output Register with Async. Clear,
-Async. Preset
-and Clock Enable. Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
OFDDRCPE_inst :
port map (
Q => Q,
C0 => C0,
C1 => C1,
CE => CE,
CLR => CLR,
D0 => D0,
D1 => D1,
PRE => PRE
);

OFDDRCPE
---------

Data output (connect directly to top-level port)

0 degree clock input
180 degree clock input
Clock enable input
Asynchronous reset input
Posedge data input
Negedge data input
Asynchronous preset input

-- End of OFDDRCPE_inst instantiation

Verilog Instantiation Template

// OFDDRCPE: Double Data Rate Output Register with Async. Clear,
//
Async. Preset and Clock Enable. Virtex-II/II-Pro, Spartan-3
// Xilinx HDL Libraries Guide version 7.1i
OFDDRCPE OFDDRCPE_inst (
.Q(Q),
// Data output (connect directly to top-level port)
.C0(C0),
// 0 degree clock input
.C1(C1),
// 180 degree clock input
.CE(CE),
// Clock enable input
.CLR(CLR), // Asynchronous reset input
.D0(D0),
// Posedge data input
.D1(D1),
// Negedge data input
.PRE(PRE)
// Asynchronous preset input
);
// End of OFDDRCPE_inst instantiation

858

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Libraries Guide
ISE 6.3i

OFDDRRSE

OFDDRRSE
Dual Data Rate Output D Flip-Flop with Synchronous Reset and Set
and Clock Enable
Architectures Supported
OFDDRRSE
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

S
D0

OFDDRRSE

D1
CE
C0
C1
R
X9386

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFDDRRSE is a dual data rate (DDR) output D flip-flop with synchronous reset (R)
and set (S) and clock enable (CE). It consists of one output buffer and one dual data
rate flip-flop (FDDRRSE).
On a Low-to-High clock transition (C0 or C1), a High R input resets the Q output
Low; a Low R input with a High S input sets Q High. When both R and S are Low and
clock enable is High, data on the D0 input is loaded into the flip-flop on a Low-toHigh C0 clock transition and data on the D1 input is loaded into the flip-flop on a
Low-to-High C1 clock transition.
The flip-flops are asynchronously cleared with Low outputs when power is applied,
or when global reset is active.
The INIT attribute does not apply to OFDDRRSE components.
Inputs

Libraries Guide
ISE 6.3i

Outputs

C0

C1

CE

D0

D1

No Chg

D0

D0

D1

D1

www.xilinx.com
1-800-255-7778

859

OFDDRRSE

S
D0
D1
CE
C0
C1
R

FDDRRSE
D0

LVTTL SLOW 12

Q_OUT

Q
OBUF

D1
CE
C0
C1
R
INIT = 0

X9363

OFDDRRSE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- OFDDRRSE: Double Data Rate Input Register with Sync. Clear,
-Sync. Preset
-and Clock Enable. Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
OFDDRRSE_inst : OFDDRRSE
port map (
Q => Q,
-- Data output (connect directly to top-level port)
C0 => C0,
-- 0 degree clock input
C1 => C1,
-- 180 degree clock input
CE => CE,
-- Clock enable input
D0 => D0,
-- Posedge data input
D1 => D1,
-- Negedge data input
R => R,
-- Synchronous reset input
S => S
-- Synchronous preset input
);
-- End of OFDDRRSE_inst instantiation

Verilog Instantiation Template

// OFDDRTCPE: Double Data Rate Output Register with Async. Clear,
//
Async.
//
Preset`and Clock Enable with 3-state. Virtex-II/II-Pro,
//
Spartan-3
// Xilinx HDL Libraries Guide version 7.1i
OFDDRRSE OFDDRRSE_inst (
.Q(Q),
// Data output (connect directly to top-level port)
.C0(C0),
// 0 degree clock input
.C1(C1),
// 180 degree clock input
.CE(CE),
// Clock enable input
.D0(D0),
// Posedge data input
.D1(D1),
// Negedge data input
.R(R),
// Synchronous reset input
.S(S)
// Synchronous preset input
);
// End of OFDDRRSE_inst instantiation

860

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Libraries Guide
ISE 6.3i

OFDDRTCPE

OFDDRTCPE
Dual Data Rate D Flip-Flop with Active-Low 3-State Output Buffer,
Clock Enable, and Asynchronous Preset and Clear
Architectures Supported
OFDDRTCPE
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

T
PRE
D0 OFDDRTCPE

D1
CE
C0
C1
CLR

X9389

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFDDRTCPE is a dual data rate (DDR) D flip-flop with clock enable (CE) and
asynchronous preset and clear whose output is enabled by a 3-state buffer. It consists
of a dual data rate flip-flop (FDDRCPE) and a 3-state output buffer (OBUFT). The data
output (O) of the flip-flop is connected to the input of the output buffer (OBUFT). The
output of the OBUFT is connected to an OPAD or IOPAD.
When the active-Low enable input (T) is Low, output is enabled and the data on the
flip-flop's Q output appears on the OBUFT's O output. When the asynchronous PRE
is High and CLR is Low, the O output is preset High. When CLR is High, O is set Low.
Data on the D0 input is loaded into the flip-flop when PRE and CLR are Low and CE
is High on the Low-to-High C0 clock transition. Data on the D1 input is loaded into
the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High C1 clock
transition.
When T is High, outputs are high impedance (Off). When CE is Low and T is Low, the
outputs do not change.
The flip-flops are asynchronously cleared with Low outputs when power is applied.
The INIT attribute does not apply to OFDDRTCPE components.
Inputs

Libraries Guide
ISE 6.3i

Outputs

C0

C1

CE

D0

D1

PRE

No Chg

D0

D0

D1

D1

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CLR

861

OFDDRTCPE

T
PRE
D0
D1
CE
C0
C1
CLR

LVTTL SLOW 12

FDDRCPE
D0

PRE

T
Q_OUT

O
OBUFT

D1
CE
C0
C1
CLR
IOB=TRUE

X9364

OFDDRTCPE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- OFDDRTCPE: Double Data Rate Output Register with Async. Clear,
-Async. Preset
-and Clock Enable with 3-state. Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
OFDDRTCPE_inst : OFDDRTCPE
port map (
Q => Q,
-- Data output (connect directly to top-level port)
C0 => C0,
-- 0 degree clock input
C1 => C1,
-- 180 degree clock input
CE => CE,
-- Clock enable input
CLR => CLR, -- Asynchronous reset input
D0 => D0,
-- Posedge data input
D1 => D1,
-- Negedge data input
PRE => PRE, -- Asynchronous preset input
T => T
-- 3-state enable input
);
-- End of OFDDRTCPE_inst instantiation
-- Component Instantiation for OFDDRTCPE should be placed
-- in architecture after the begin keyword

Verilog Instantiation Template

// OFDDRTCPE:
Async.
//
//
// Xilinx HDL

Double Data Rate Output Register with Async. Clear,

Preset`and Clock Enable with 3-state. Virtex-II/II-Pro,
Spartan-3
Libraries Guide version 7.1i

OFDDRTCPE OFDDRTCPE_inst (
.Q(Q),
// Data output (connect directly to top-level port)
.C0(C0),
// 0 degree clock input
.C1(C1),
// 180 degree clock input
.CE(CE),
// Clock enable input
.CLR(CLR), // Asynchronous reset input
.D0(D0),
// Posedge data input

862

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Libraries Guide
ISE 6.3i

OFDDRTCPE

.D1(D1),
.PRE(PRE),
.T(T)

// Negedge data input

// Asynchronous preset input
// 3-state enable input

);
// End of OFDDRTCPE_inst instantiation

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

863

864

OFDDRTCPE

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFDDRTRSE

OFDDRTRSE
Dual Data Rate D Flip-Flop with Active-Low 3-State Output Buffer,
Synchronous Reset and Set, and Clock Enable
Architectures Supported
OFDDRTRSE
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

T
S
D0 OFDDRTRSE

D1
CE
C0
C1
R

X9388

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFDDRTRSE is a dual data rate (DDR) D flip-flop with clock enable (CE) and
synchronous reset and set whose output is enabled by a 3-state buffer. It consists of a
dual data rate flip-flop (FDDRRSE) and a 3-state output buffer (OBUFT). The data
output (O) of the flip-flop is connected to the input of the output buffer (OBUFT). The
output of the OBUFT is connected to an OPAD or IOPAD.
When the active-Low enable input (T) is Low, output is enabled and the data on the
flip-flop's Q output appears on the OBUFT's O output. On a Low-to-High clock
transition (C0 or C1), a High R input resets the Q output Low; a Low R input with a
High S input sets O High. When both R and S are Low and clock enable is High, data
on the D0 input is loaded into the flip-flop on a Low-to-High C0 clock transition and
data on the D1 input is loaded into the flip-flop on a Low-to-High C1 clock transition.
When T is High, outputs are high impedance (Off). When CE is Low and T is Low, the
outputs do not change.
The flip-flops are asynchronously cleared with Low outputs when power is applied.
The INIT attribute does not apply to OFDDRTRSE components.
Inputs

Libraries Guide
ISE 6.3i

Outputs

C0

C1

CE

D0

D1

No Chg

D0

D0

D1

D1

www.xilinx.com
1-800-255-7778

865

OFDDRTRSE

T
S
D0
D1
CE
C0
C1
R

LVTTL SLOW 12

FDDRRSE
D0

T
Q_OUT

O
OBUFT

D1
CE
C0
C1
R
IOB=TRUE

X9365

OFDDRTRSE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- OFDDRTRSE: Double Data Rate Input Register with Sync. Clear,
-Sync. Preset
-and Clock Enable with 3-state. Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Libraries Guide version 7.1i
OFDDRTRSE_inst : OFDDRTRSE
port map (
Q => Q,
-- Data output (connect directly to top-level port)
C0 => C0,
-- 0 degree clock input
C1 => C1,
-- 180 degree clock input
CE => CE,
-- Clock enable input
D0 => D0,
-- Posedge data input
D1 => D1,
-- Negedge data input
R => R,
-- Synchronous reset input
S => S,
-- Synchronous preset input
T => T
-- 3-state enable input
);
-- End of OFDDRTRSE_inst instantiation

Verilog Instantiation Template

// OFDDRTRSE: Double Data Rate Input Register with Sync. Clear, Sync.
//
Preset and Clock Enable with 3-state. Virtex-II/II-Pro,
//
Spartan-3
// Xilinx HDL Libraries Guide version 7.1i
OFDDRTRSE OFDDRTRSE_inst (
.Q(Q),
// Data output (connect directly to top-level port)
.C0(C0),
// 0 degree clock input
.C1(C1),
// 180 degree clock input
.CE(CE),
// Clock enable input
.D0(D0),
// Posedge data input
.D1(D1),
// Negedge data input
.R(R),
// Synchronous reset input
.S(S),
// Synchronous preset input
.T(T)
// 3-state enable input
);
// End of OFDDRTRSE_inst instantiation

866

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1-800-255-7778

Libraries Guide
ISE 6.3i

OFDE, 4, 8, 16

OFDE, 4, 8, 16
D Flip-Flops with Active-High Enable Output Buffers
Architectures Supported
OFDE, OFDE4, OFDE8, OFDE16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFDE

X3782

D0

OFDE4

Q0

D1

Q1

D2

Q2

D3

Q3

X3802

OFDE, OFDE4, OFDE8, and OFDE16 are single or multiple D flip-flops whose
outputs are enabled by 3-state buffers. The flip-flop data outputs (Q) are connected to
the inputs of output buffers (OBUFE). The OBUFE outputs (O) are connected to
OPADs or IOPADs. The data on the data inputs (D) is loaded into the flip-flops during
the Low-to-High clock (C) transition. When the active-High enable inputs (E) are
High, the data on the flip-flop outputs (Q) appears on the O outputs. When E is Low,
outputs are high impedance (Z state or Off).
The flip-flops are asynchronously cleared with Low outputs when power is applied,
or when global reset is active.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

D[7:0]

OFDE8

Q[7:0]

C
X3814

D[15:0]

OFDE16

Inputs

Outputs

Q[15:0]

X3836

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

867

OFDE, 4, 8, 16

VCC

E
INV

FDCE

T
Q_OUT

O
OBUFT

CE
C
CLR

IOB=TRUE
GND

X9775

OFDE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X
E

T
INV

OBUFT
FD
D

X8044

OFDE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

868

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFDE, 4, 8, 16

O[7:0]
E
D0

E
D1

E
D2

E
D3

E
D4

E
D5

E
D6

E
D[7:0]
E
C

D7

OFDE
D

O0

O0

OFDE
D

O1

O1

OFDE
D

O2

O2

OFDE
D

O3

O3

OFDE
D

O4

O4

OFDE
D

O5

O5

OFDE
D

O6

O6

OFDE
D

O7

O7

X6379

OFDE8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an OFDE, you would
infer an FDE and put the IOB = TRUE attribute on the component. Or, you could use
the map option pr o to pack all output registers into the IOBs.

869

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

870

OFDE, 4, 8, 16

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFDE_1

OFDE_1
D Flip-Flop with Active-High Enable Output Buffer and Inverted Clock
Architectures Supported
OFDE_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OFDE_1

X3783

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFDE_1 and its output buffer are located in an input/output block (IOB). The data
output of the flip-flop (Q) is connected to the input of an output buffer or OBUFE. The
output of the OBUFE is connected to an OPAD or an IOPAD. The data on the data
input (D) is loaded into the flip-flop on the High-to-Low clock (C) transition. When
the active-High enable input (E) is High, the data on the flip-flop output (Q) appears
on the O output. When E is Low, the output is high impedance (Z state or Off).
The flip-flop is asynchronously cleared with Low output when power is applied, or
when global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

VCC

E
INV

FDCE

T
Q_OUT

CE
C

CB

O
OBUFT

C
CLR

INV

IOB=TRUE
X9774

GND

OFDE_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

871

OFDE_1

VCC
T

LVTTL SLOW 12

FDCE

INV
D

Q_OUT

CE
CB

C
INV

O
OBUFT

CLR

IOB=TRUE
X9370

GND

OFDE_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an OFDE_1, you would
infer an FDE_1 and put the IOB = TRUE attribute on the component. Or, you could
use the map option pr o to pack all output registers into the IOBs.

872

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFDI

OFDI
Output D Flip-Flop (Asynchronous Preset)
Architectures Supported
OFDI
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OFDI

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFDI is contained in an input/output block (IOB). The output (Q) of the D flip-flop is
connected to an OPAD or an IOPAD. The data on the D input is loaded into the flipflop during the Low-to-High clock (C) transition and appears at the output (Q).
The flip-flop is asynchronously preset, output High, when power is applied.

X4582

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

VCC

D
CE

PRE

Q_OUT
OBUF

C
FDPE
IOB=TRUE
GND

X8752

OFDI Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

VCC

FDPE
D

PRE

CE
C

Q_OUT

LVTTL SLOW 12

OBUF

C
IOB=TRUE
X9368

GND

OFDI Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

873

OFDI

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an OFDI, you would
infer an FDP and put the IOB = TRUE attribute on the component. Or, you could use
the map option pr o to pack all output registers into the IOBs.

874

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFDI_1

OFDI_1
Output D Flip-Flop with Inverted Clock (Asynchronous Preset)
Architectures Supported
OFDI_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OFDI_1

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFDI_1 exists in an input/output block (IOB). The D flip-flop output (Q) is connected
to an OPAD or an IOPAD. The data on the D input is loaded into the flip-flop during
the High-to-Low clock (C) transition and appears on the Q output.
The flip-flop is asynchronously preset, output High, when power is applied.

X4384

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

VCC

D
CE

CB

PRE

Q_OUT
OBUF

INV
FDPE
IOB=TRUE
GND

X8753

OFDI_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

875

OFDI_1

VCC

FDPE
D

PRE

Q_OUT

CE
C

CB
INV

LVTTL SLOW 12

OBUF

C
IOB=TRUE
X9369

GND

OFDI_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an OFDI_1, you would
infer an FDP_1 and put the IOB = TRUE attribute on the component. Or, you could
use the map option pr o to pack all output registers into the IOBs.

876

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFDT, 4, 8, 16

OFDT, 4, 8, 16
Single and Multiple D Flip-Flops with Active-Low 3-State Output Enable
Buffers
Architectures Supported
OFDT, OFDT4, OFDT8, OFDT16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OFDT

CoolRunner XPLA3

No

CoolRunner-II

No

OFDT, OFDT4, OFDT8, and OFDT16 are single or multiple D flip-flops whose outputs
are enabled by a 3-state buffers. The data outputs (Q) of the flip-flops are connected to
the inputs of output buffers (OBUFT). The outputs of the OBUFTs (O) are connected
to OPADs or IOPADs. The data on the data inputs (D) is loaded into the flip-flops
during the Low-to-High clock (C) transition. When the active-Low enable inputs (T)
are Low, the data on the flip-flop outputs (Q) appears on the O outputs. When T is
High, outputs are high impedance (Off).

X3780

The flip-flops are asynchronously cleared with Low outputs, when power is applied,
or when global reset is active.

OFDT4

D0

Q0

D1

Q1

D2

Q2

D3

Q3

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

X3801

Inputs

D[15:0]

No

OFDT16

Q[15:0]

Outputs

X3835

D[7:0]

OFDT8

Q[7:0]

X3813

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

877

OFDT, 4, 8, 16

VCC

FDCE
D

T
O_OUT

O
OBUFT

CE
C

C
CLR

IOB=TRUE
GND

X9773

OFDT Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

VCC
T

LVTTL SLOW 12

FDCE
D

O_OUT

O
OBUFT

CE
CLR

IOB=TRUE
X9366

GND

OFDT Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

T

OBUFT
FD
D

C
O
X8043

OFDT Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

878

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFDT, 4, 8, 16

T
D0

D
C
T

D1

D3

O1

D4

C
T

O3

OFDT

C
T

O5

O5

OFDT
D
C

O4

O4

D6

O3

OFDT
D

D5

O2

O2

O1

OFDT

D7

OFDT

D[7:0]

O0

O0

OFDT

T
C

D2

O[7:0]

OFDT

O6

O6

OFDT
D
C

Q
O7

O7

X6377

OFDT8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an OFDT, you would
infer an FDCE and put the IOB = TRUE attribute on the component. Or, you could use
the map option pr o to pack all output registers into the IOBs.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

879

880

OFDT, 4, 8, 16

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFDT_1

OFDT_1
D Flip-Flop with Active-Low 3-State Output Buffer and Inverted Clock
Architectures Supported
OFDT_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OFDT_1

X3781

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFDT_1 and its output buffer are located in an input/output block (IOB). The flipflop data output (Q) is connected to the input of an output buffer (OBUFT). The
OBUFT output is connected to an OPAD or an IOPAD. The data on the data input (D)
is loaded into the flip-flop on the High-to-Low clock (C) transition. When the activeLow enable input (T) is Low, the data on the flip-flop output (Q) appears on the O
output. When T is High, the output is high impedance (Off).
The flip-flop is asynchronously cleared with Low output when power is applied, or
when global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

VCC

FDCE
D

T
Q_OUT

CE
C

CB

O
OBUFT

C
CLR

INV

IOB=TRUE
GND

X9772

OFDT_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

881

OFDT_1

VCC
T
LVTTL SLOW 12

FDCE
D

Q_OUT

CE
CB

C
INV

O
OBUFT

CLR

IOB=TRUE
X9367

GND

OFDT_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an OFDT_1, you would
infer an FDCE_1 and put the IOB = TRUE attribute on the component. Or, you could
use the map option pr o to pack all output registers into the IOBs.

882

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFDX, 4, 8, 16

OFDX, 4, 8, 16
Single- and Multiple-Output D Flip-Flops with Clock Enable
Architectures Supported
OFDX, OFDX4, OFDX8, OFDX16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OFDX

CE
C

X4988

D0

OFDX4

CoolRunner XPLA3

No

CoolRunner-II

No

OFDX, OFDX4, OFDX8, and OFDX16 are single and multiple output D flip-flops. The
Q outputs are connected to OPADs or IOPADs. The data on the D inputs is loaded
into the flip-flops during the Low-to-High clock (C) transition and appears on the Q
outputs. When CE is Low, flip-flop outputs do not change.
The flip-flops are asynchronously cleared with Low outputs, when power is applied,
or when global reset is active.

Q0

D1

Q1

D2

Q2

D3

Q3

CE
C

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

X4989

D[7:0]

OFDX8

No

Q[7:0]

CE

Outputs

CE

Dn

Dn

No Chg

FDCE

X4990

D
CE

CE
C
D[15:0]

OFDX16

Q[15:0]

Q_OUT
OBUF

CLR

IOB=TRUE

CE
C

GND

X8754

X4991

OFDX Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

883

OFDX, 4, 8, 16

FDCE
D

CE

LVTTL SLOW 12

Q_OUT

CE

OBUF

CLR

IOB=TRUE
X9357

GND

OFDX Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Q[7:0]

OFDX
D0

D
CE
C

Q0

Q0

OFDX
D1

D
CE
C

Q1

Q1

OFDX
D2

D
CE
C

Q2

Q2

OFDX
D3

D
CE
C

Q3

Q3

OFDX
D4

D
CE
C

Q4

Q4

OFDX
D5

D
CE
C

Q5

Q5

OFDX
D6

D
CE
C

Q6

Q6

OFDX
D7

D[7:0]

D
CE
C

Q7

Q7

C
CE

X6408

OFDX8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

884

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFDX, 4, 8, 16

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an OFDX, you would
infer an FDCE and put the IOB = TRUE attribute on the component. Or, you could use
the map option pr o to pack all output registers into the IOBs.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

885

886

OFDX, 4, 8, 16

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFDX_1

OFDX_1
Output D Flip-Flop with Inverted Clock and Clock Enable
Architectures Supported
OFDX_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OFDX_1

CE
C

X4992

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFDX_1 is located in an input/output block (IOB). The output (Q) of the D flip-flop is
connected to an OPAD or an IOPAD. The data on the D input is loaded into the flipflop during the High-to-Low clock (C) transition and appears on the Q output. When
the CE pin is Low, the output (Q) does not change.
The flip-flop is asynchronously cleared with Low output when power is applied, or
when global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CE

No Chg

FDCE
D
CE
C

D
CE

CB

INV

Q_OUT
OBUF

CLR

IOB=TRUE
GND

X8755

OFDX_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

887

OFDX_1

FDCE
D

CE

Q_OUT

CE
CB

C
INV

LVTTL SLOW 12

OBUF

CLR

IOB=TRUE
X9358

GND

OFDX_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an OFDX_1, you would
infer an FDCE_1 and put the IOB = TRUE attribute on the component. Or, you could
use the map option pr o to pack all output registers into the IOBs.

888

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

OFDXI

OFDXI
Output D Flip-Flop with Clock Enable (Asynchronous Preset)
Architectures Supported
OFDXI
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OFDXI

CE
C

X6000

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFDXI is contained in an input/output block (IOB). The output (Q) of the D flip-flop
is connected to an OPAD or an IOPAD. The data on the D input is loaded into the flipflop during the Low-to-High clock (C) transition and appears at the output (Q). When
CE is Low, the output does not change.
The flip-flop is asynchronously preset with High output when power is applied, or
when global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CE

No Chg

D
CE

CE
C

PRE

Q_OUT
OBUF

C
FDPE
IOB=TRUE
GND

X8756

OFDXI Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

889

OFDXI

FDPE
D

CE

PRE

Q_OUT

CE

LVTTL SLOW 12

OBUF

C
IOB=TRUE
GND

X9359

OFDXI Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an OFDXI, you would
infer an FDPE and put the IOB = TRUE attribute on the component. Or, you could use
the map option pr o to pack all output registers into the IOBs.

890

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Libraries Guide
ISE 6.3i

OFDXI_1

OFDXI_1
Output D Flip-Flop with Inverted Clock and Clock Enable
(Asynchronous Preset)
Architectures Supported
OFDXI_1
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OFDXI_1

CE
C

X6001

No

CoolRunner XPLA3

No

CoolRunner-II

No

OFDXI_1 is located in an input/output block (IOB). The D flip-flop output (Q) is

connected to an OPAD or an IOPAD. The data on the D input is loaded into the flipflop during the High-to-Low clock (C) transition and appears on the Q output. When
CE is Low, the output (Q) does not change.
The flip-flop is asynchronously preset with High output when power is applied, or
when global reset is active.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CE

No Chg

D
CE
C

D
CE

CB

PRE

Q_OUT
OBUF

INV
FDPE
IOB=TRUE
GND

X8757

OFDXI_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

891

OFDXI_1

FDPE
D

CE

PRE

CE
CB

Q_OUT

LVTTL SLOW 12

OBUF

INV
IOB=TRUE
X9360

GND

OFDXI_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This component is inside of the IOB. It cannot be directly inferred. The most common
design practice is to infer a regular component and put an IOB=TRUE attribute on the
component in the UCF file or in the code. For instance, to get an OFDXI_1, you would
infer an FDPE_1 and put the IOB = TRUE attribute on the component. Or, you could
use the map option pr o to pack all output registers into the IOBs.

892

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Libraries Guide
ISE 6.3i

OPAD, 4, 8, 16

OPAD, 4, 8, 16
Single- and Multiple-Output Pads
Architectures Supported
OPAD
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

OPAD4, OPAD8, OPAD16

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

OPAD
OPAD

X10123

OPAD4

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

OPAD, OPAD4, OPAD8, and OPAD16 are single and multiple output pads. An OPAD
connects a device pin to an output signal of a PLD. It is internally connected to an
input/output block (IOB), which is configured by the software as an OBUF, an
OBUFT, an OBUFE, an OFD, or an OFDT.
See the appropriate CAE tool interface user guide for details on assigning pin location
and identification.

O0
O1
O2

O[7:0]

O3
X3839

O0
OPAD
O1
OPAD
O2

OPAD8

OPAD

O[7:0]

O3
OPAD
X3842

O4
OPAD
O5
OPAD
O6
OPAD

OPAD16

O7

O[15:0]

OPAD
X3846

X7656

OPAD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

893

OPAD, 4, 8, 16

Usage
For HDL, it is not necessary to use these elements in the design. They will be added
automatically.

Commonly Used Constraints

IOBDELAY, PULLDOWN

894

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Libraries Guide
ISE 6.3i

OR2-9

OR2-9
2- to 9-Input OR Gates with Inverted and Non-Inverted Inputs
Architectures Supported
OR2, OR2B1, OR2B2, OR3, OR3B1, OR3B2, OR3B3,
OR4, OR4B1, OR4B2, OR4B3, OR4B4
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

OR5, OR5B1, OR5B2, OR5B3, OR5B4, OR5B5

Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro
OR6, OR7, OR8, OR9

Libraries Guide
ISE 6.3i

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Macro

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

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895

OR2-9

I5
I4

I3
0
I0

I4

I3

I2

I1

I3

I2

I1

0
I1

I0

I2

I1

I0

I2
I1

I0

I0
OR3

OR2

OR4

OR6

OR5
I6
I4

I3
I1
0
I0

I5

I3

I2

I4

I2

I1

0
I1

I0

I0

I2

I3

I1

I2

I0

I1
I0

OR2B1

OR3B1

OR5B1

OR4B1

OR7
I7
I6

I4

I3
0
I0

I5

I3

I2

I1

I2
0

I1

0
I1

I0

I4

I2

I0

0
I3

I1

I2

I0

I1
I0
OR2B2

OR3B2

OR5B2

OR4B2

OR8
IA
I7

I3
I2

I2
0
I1

I0

I5

I3

I1

I6

I4

I0

I2

I4

I1

I3

I0

I2

I1
I0
OR3B3

OR4B3

OR5B3

OR9

I4

I3

I3
I2
0

I1

I2

I1

I0

I0
OR4B4

OR5B4

I4
I3
I2

I1
I0
OR5B5

X9435

OR Gate Representations

896

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Libraries Guide
ISE 6.3i

OR2-9

The OR function is performed in the Configurable Logic Block (CLB) function

generators for Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II
Pro, and Virtex-II Pro X. OR functions of up to five inputs are available in any
combination of inverting and non-inverting inputs. OR functions of six to nine inputs
are available with only non-inverting inputs. To invert some or all inputs, use external
inverters. Since each input uses a CLB resource, replace functions with unused inputs
with functions having the necessary number of inputs.
See OR2-9 for information on additional OR functions for the Spartan-II, SpartanIIE, Virtex, and Virtex-E.
FMAP
I4
I3
S1
S2

RLOC=R0C0.S0

S1

I5

I1

I7
I6

I2

I4

FMAP

OR4

I7

I4

I6

I3

I5
I4

OR2

I2

S1

I1

I3

RLOC=R0C0.S1

I2

S0

I1
I0

FMAP
I3

OR4

I4

I2

I3

I1
I0

I2

S0

I1

X8698

RLOC=R0C0.S1

OR8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I7

I4

I6

I3

S1

S1

I5

S0

I4

I2

I1

OR4
RLOC=X0Y1
O
OR2
I3
I2

S0

I1

FMAP
I7

I4

I6

I3

I5

I2

I4

I1

S1

I0
OR4

RLOC=X0Y0

FMAP
I3

I4

I2

I3

I1

I2

I0

I1

S0

RLOC=X0Y0
X9371

OR8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

897

OR2-9

Usage
OR2 through OR5 are primitives that can be inferred or instantiated. OR6 through
OR9 are macros which can be inferred.

VHDL Instantiation Template for OR5

Following is the VHDL code for OR5. To instantiate OR2, remove I2, I3, and I4. To
instantiate OR3, remove I3 and I4, For OR4, remove I4. OR2B1, and OR2B2 have the
same code as OR2. OR3B1, 3B2, and 3B3 have the same code as OR3 and so forth.
-- Component Declaration for OR5 should be placed
-- after architecture statement but before begin keyword
component OR5
port (O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;
I2 : in STD_ULOGIC;
I3 : in STD_ULOGIC;
I4: in STD_ULOGIC);
end component;
-- Component Attribute specification for OR5
-- should be placed after architecture declaration but
-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for OR5 should be placed
-- in architecture after the begin keyword
OR5_INSTANCE_NAME : OR5
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2,
I3 => user_I3,
I4 => user_I4);

Verilog Instantiation Template for OR5

OR5 OR5_instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.I2 (user_I2),
.I3 (user_I3),
.I4 (user_I4));

898

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Libraries Guide
ISE 6.3i

OR12, 16

OR12, 16
12- and 16-Input OR Gates with Non-Inverted Inputs
Architectures Supported
OR12, OR16
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Macro

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

See OR2-9 for information on OR functions.

I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0

OR12
X9436

I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0

OR16
X9437

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

899

OR12, 16

FMAP
I15

I15

MUXCY

I14

I14
S3

I13

RLOC=R0C0.S1

S
0
VCC

I12

I13

DI

I12

CI

I4
I3
O

S3

I2
I1

NOR4
RLOC=R0C0.S1
C2
FMAP
I11

LO

I11

MUXCY_L

I10

S2

I10
RLOC=R0C0.S1

I9

DI

I8

I9
I8

CI

NOR4

I4
I3
O

S2

I2
I1
RLOC=R0C0.S1

C1
FMAP
I7

LO

I7

MUXCY_L

I6

S1

I5

I6
RLOC=R1C0.S1

S
0
DI

I4

I5

1
I4

CI

I4
I3
O

S1

I2
I1

NOR4
RLOC=R1C0.S1

C0

FMAP
LO

I3

I3

MUXCY_L

I2

S0

RLOC=R1C0.S1

S
0

I1
DI

I0

I2
I1

1
CI

I0

I4
I3
O

S0

I2
I1

NOR4
RLOC=R1C0.S1

CIN

X8706
GND

OR16 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

900

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Libraries Guide
ISE 6.3i

OR12, 16

FMAP
I15
I15

I14
S3
I13

MUXCY

VCC

DI

I12

I14
RLOC=X0Y1
I13

1
I12

CI

I4
I3
I2

S3

I1

NOR4
RLOC=X0Y1
C2

FMAP
I11
I11

LO

I10
S2

I9

DI

I8

I10

MUXCY_L
0
1

RLOC=X0Y1
I9
I8

CI

I4
I3
I2

S2

I1

NOR4
RLOC=X0Y1
C1

FMAP
I7
I7

LO

I6
S1

I5

DI

I4

I6

MUXCY_L
0
1

RLOC=X0Y0
I5
I4

CI

I4
I3
I2

S1

I1

NOR4
RLOC=X0Y0
C0

FMAP
I3
I3

LO

I2
S0

I1

DI

I0

I2

MUXCY_L
0
1

RLOC=X0Y0

CI

I1
I0

I4
I3
I2

S0

I1

NOR4
RLOC=X0Y0
CIN

X9372

GND

OR16 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, OR12 and OR16 are macros that are inferred. See OR2-9 for information
about inferring OR gates.

Libraries Guide
ISE 6.3i

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1-800-255-7778

901

902

OR12, 16

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Libraries Guide
ISE 6.3i

ORCY

ORCY
OR with Carry Logic
Architectures Supported
ORCY
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

CI
ORCY

X9403

No

CoolRunner XPLA3

No

CoolRunner-II

No

ORCY is a special OR with general O output used for generating faster and smaller
arithmetic functions.
Each Virtex-II, Virtex-II Pro, and Virtex-II Pro X slice contains a dedicated 2-input OR
gate that ORs together carry out values for a series of horizontally adjacent carry
chains. The OR gate gets one input external to the slice and the other input from the
output of the high order carry mux. The OR gate's output drives the next slice's OR
gate horizontally across the die.
Only MUXCY outputs can drive the signal on the CI pin. Only ORCY outputs or logic
zero can drive the I pin.

Usage
For HDL, the ORCY design element should be instantiated rather than inferred.

VHDL Instantiation Template

-- Component Declaration for ORCY should be placed
-- after architecture statement but before begin keyword
component ORCY
port (O : out STD_ULOGIC;
CI : in STD_ULOGIC;
I : in STD_ULOGIC);
end component;
-- Component Attribute specification for ORCY
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for ORCY should be placed

-- in architecture after the begin keyword
ORCY_INSTANCE_NAME : ORCY

Libraries Guide
ISE 6.3i

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903

ORCY

port map (O => user_O,

CI => user_CI,
I => user_I);

Verilog Instantiation Template

ORCY instance_name (.O (user_O),
.CI (user_CI),
.I (user_I));

904

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Libraries Guide
ISE 6.3i

PPC405

PPC405
Primitive for the Power PC Core
Architectures Supported
PPC405
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive*

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

* Not supported for Virtex-II. Supported for

Virtex-II Pro and Virtex-II Pro X only.

The PowerPC 405 embedded core is a 32-bit RISC core integrating a PowerPC 405
CPU, separate instruction and data caches, a JTAG port, trace FIFO, multiple timers,
and a memory management unit (MMU). Integrated on-chip memory (OCM)
controllers provide dedicated interfaces between Block SelectRAM memory and the
processor core instruction and data paths for high-speed access. The PowerPC 405
core implements the PowerPC User Instruction Set.
For complete information about the PowerPC 405, see the following documents:

Virtex-II Pro Datasheet

Virtex-II Pro Handbook

The PowerPC 405 Core Processor Block Manual

The PowerPC 405 User Guide

The following table lists the inputs and outputs of the primitive. For detailed
information about the pinouts, see the DS083 Virtex-II Pro Data Sheet.

Inputs

Libraries Guide
ISE 6.3i

Outputs

BRAMDSOCMCLK

C405CPMCORESLEEPREQ

BRAMDSOCMRDDBUS [0:31]

C405CPMMSRCE

BRAMISOCMCLK

C405CPMMSREE

BRAMISOCMRDDBUS [0:63]

C405CPMTIMERIRQ

CPMC405CLOCK

C405CPMTIMERRESETREQ

CPMC405CORECLKINACTIVE

C405DBGMSRWE

CPMC405CPUCLKEN

C405DBGSTOPACK

CPMC405JTAGCLKEN

C405DBGWBCOMPLETE

CPMC405TIMERCLKEN

C405DBGWBFULL

CPMC405TIMERTICK

C405DBGWBIAR[0:29]

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905

PPC405

Inputs

906

Outputs

DBGC405DEBUGHALT

C405DCRABUS [0:9]

DBGC405EXTBUSHOLDACK

C405DCRDBUSOUT [0:31]

DBGC405UNCONDDEBUGEVENT

C405DCRREAD

DCRC405ACK

C405DCRWRITE

DCRC405DBUSIN [0:31]

C405JTGCAPTUREDR

DSARCVALUE [0:7]

C405JTGEXTEST

DSCNTLVALUE [0:7]

C405JTGPGMOUT

EICC405CRITINPUTIRQ

C405JTGSHIFTDR

EICC405EXTINPUTIRQ

C405JTGTDO

ISARCVALUE [0:7]

C405JTGTDOEN

ISCNTLVALUE [0:7]

C405JTGUPDATEDR

JTGC405BNDSCANTDO

C405PLBDCUABORT

JTGC405TCK

C405PLBDCUABUS [0:31]

JTGC405TDI

C405PLBDCUBE [0:7]

JTGC405TMS

C405PLBDCUCACHEABLE

JTGC405TRSTNEG

C405PLBDCUGUARDED

MCBCPUCLKEN

C405PLBDCUPRIORITY [0:1]

MCBJTAGEN

C405PLBDCUREQUEST

MCBTIMEREN

C405PLBDCURNW

MCPPCRST

C405PLBDCUSIZE2

PLBC405DCUADDRACK

C405PLBDCUU0ATTR

PLBC405DCUBUSY

C405PLBDCUWRDBUS [0:63]

PLBC405DCUERR

C405PLBDCUWRITETHRU

PLBC405DCURDDACK

C405PLBICUABORT

PLBC405DCURDDBUS [0:63]

C405PLBICUABUS [0:29]

PLBC405DCURDWDADDR [1:3]

C405PLBICUCACHEABLE

PLBC405DCUSSIZE1

C405PLBICUPRIORITY [0:1]

PLBC405DCUWRDACK

C405PLBICUREQUEST

PLBC405ICUADDRACK

C405PLBICUSIZE [2:3]

PLBC405ICUBUSY

C405PLBICUU0ATTR

PLBC405ICUERR

C405RSTCHIPRESETREQ

PLBC405ICURDDACK

C405RSTCORERESETREQ

PLBC405ICURDDBUS [0:63]

C405RSTSYSRESETREQ

PLBC405ICURDWDADDR [1:3]

C405TRCCYCLE

PLBC405ICUSSIZE1

C405TRCEVENEXECUTIONSTATUS [0:1]

PLBCLK

C405TRCODDEXECUTIONSTATUS [0:1]

RSTC405RESETCHIP

C405TRCTRACESTATUS [0:3]

RSTC405RESETCORE

C405TRCTRIGGEREVENTOUT

RSTC405RESETSYS

C405TRCTRIGGEREVENTTYPE [0:10]

TIEC405DETERMINISTICMULT

C405XXXMACHINECHECK

TIEC405DISOPERANDFWD

DSOCMBRAMABUS [8:29]

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Libraries Guide
ISE 6.3i

PPC405

Inputs

Outputs

TIEC405MMUEN

DSOCMBRAMBYTEWRITE [0:3]

TIEDSOCMDCRADDR [0:7]

DSOCMBRAMEN

TIEISOCMDCRADDR [0:7]

DSOCMBRAMWRDBUS [0:31]

TRCC405TRACEDISABLE

DSOCMBUSY

TRCC405TRIGGEREVENTIN

ISOCMBRAMEN
ISOCMBRAMEVENWRITEEN
ISOCMBRAMODDWRITEEN
ISOCMBRAMRDABUS [8:28]
ISOCMBRAMWRABUS [8:28]
ISOCMBRAMWRDBUS [0:31]

Libraries Guide
ISE 6.3i

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907

PPC405

PPC405
C405CPMCORESLEEPREQ

BRAMDSOCMCLK

C405CPMMSRCE

BRAMDSOCMRDDBUS(0:31)
BRAMISOCMCLK

C405CPMMSREE
C405CPMTIMERIRQ

BRAMISOCMRDDBUS(0:63)
CPMC405CLOCK

C405CPMTIMERRESETREQ

CPMC405CORECLKINACTIVE

C405DBGMSRWE

CPMC405CPUCLKEN

C405DBGSTOPACK

CPMC405JTAGCLKEN

C405DBGWBCOMPLETE

CPMC405TIMERCLKEN

C405DBGWBFULL
C405DBGWBIAR(0:29)

CPMC405TIMERTICK
DBGC405DEBUGHALT

C405DCRABUS(0:9)
C405DCRDBUSOUT(0:31)

DBGC405EXTBUSHOLDACK
DBGC405UNCONDDEBUGEVENT

C405DCRREAD
C405DCRWRITE

DCRC405ACK
DCRC405DBUSIN(0:31)

C405JTGCAPTUREDR

DSARCVALUE(0:7)

C405JTGEXTEST

DSCNTLVALUE(0:7)

C405JTGPGMOUT

EICC405CRITINPUTIRQ

C405JTGSHIFTDR

EICC405EXTINPUTIRQ

C405JTGTDO
C405JTGTDOEN

ISARCVALUE(0:7)
ISCNTLVALUE(0:7)

C405JTGUPDATEDR

JTGC405BNDSCANTDO

C405PLBDCUABORT

JTGC405TCK

C405PLBDCUABUS(0:31)
C405PLBDCUBE(0:7)

JTGC405TDI
JTGC405TMS

C405PLBDCUCACHEABLE
C405PLBDCUGUARDED

JTGC405TRSTNEG
MCBCPUCLKEN

C405PLBDCUPRIORITY(0:1)
C405PLBDCUREQUEST

MCBJTAGEN
MCBTIMEREN

C405PLBDCURNW
C405PLBDCUSIZE2

MCPPCRST
PLBC405DCUADDRACK

C405PLBDCUU0ATTR
C405PLBDCUWRDBUS(0:63)

PLBC405DCUBUSY
PLBC405DCUERR

C405PLBDCUWRITETHRU
C405PLBICUABORT

PLBC405DCURDDACK
PLBC405DCURDDBUS(0:63)

C405PLBICUABUS(0:29)
C405PLBICUACHEABLE

PLBC405DCURDWDADDR(1:3)
PLBC405DCUSSIZE1

C405PLBICUPRIORITY(0:1)

PLBC405DCUWRDACK

C405PLBICUREQUEST

PLBC405ICUADDRACK

C405PLBICUSIZE(2:3)
C405PLBICUU0ATTR

PLBC405ICUBUSY
PLBC405ICUERR

C405RSTCHIPRESETREQ

PLBC405ICURDDACK

C405RSTCORERESETREQ

PLBC405ICURDDBUS(0:63)

C405RSTSYSRESETREQ
C405TRCCYCLE

PLBC405ICURDWDADDR(1:3)
PLBC405ICUSSIZE1

C405TRCEVENEXECUTIONSTATUS(0:1)
C405TRCODDEXECUTIONSTATUS(0:1)

PLBCLK
RSTC405RESETCHIP
RSTC405RESETCORE
RSTC405RESETSYS

C405TRCTRACESTATUS(0:3)
C405TRCTRIGGEREVENTOUT
C405TRCTRIGGEREVENTTYPE(0:10)

TIEC405DETERMINISTICMULT

C405XXXMACHINECHECK

TIEC405DISOPERANDFWD
TIEC405MMUEN

DSOCMBRAMABUS(8:29)
DSOCMBRAMBYTEWRITE(0:3)
DSOCMBRAMEN

TIEDSOCMDCRADDR(0:7)
TIEISOCMDCRADDR(0:7)

DSOCMBRAMWRDBUS(0:31)
DSOCMBUSY

TRCC405TRACEDISABLE
TRCC405TRIGGEREVENTIN

ISOCMBRAMEN
ISOCMBRAMEVENWRITEEN
ISOCMBRAMODDWRITEEN
ISOCMBRAMRDABUS(8:28)
ISOCMBRAMWRABUS(8:28)
ISOCMBRAMWRDBUS(0:31)

X9929

908

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

PPC405

Usage
For HDL, the PPC405 design element is instantiated rather than inferred.

VHDL Instantiation Template

-- Component Declaration for PPC405 should be placed
-- after architecture statement but before begin keyword
component PPC405
port (C405CPMCORESLEEPREQ
C405CPMMSRCE
C405CPMMSREE
C405CPMTIMERIRQ
C405CPMTIMERRESETREQ
C405DBGMSRWE
C405DBGSTOPACK
C405DBGWBCOMPLETE
C405DBGWBFULL
C405DBGWBIAR
0);
C405DCRABUS
C405DCRDBUSOUT
0);
C405DCRREAD
C405DCRWRITE
C405JTGCAPTUREDR
C405JTGEXTEST
C405JTGPGMOUT
C405JTGSHIFTDR
C405JTGTDO
C405JTGTDOEN
C405JTGUPDATEDR
C405PLBDCUABORT
C405PLBDCUABUS
0);
C405PLBDCUBE
C405PLBDCUCACHEABLE
C405PLBDCUGUARDED
C405PLBDCUPRIORITY
C405PLBDCUREQUEST
C405PLBDCURNW
C405PLBDCUSIZE2
C405PLBDCUU0ATTR
C405PLBDCUWRDBUS
0);
C405PLBDCUWRITETHRU
C405PLBICUABORT
C405PLBICUABUS
0);
C405PLBICUCACHEABLE
C405PLBICUPRIORITY
C405PLBICUREQUEST
C405PLBICUSIZE
C405PLBICUU0ATTR
C405RSTCHIPRESETREQ
C405RSTCORERESETREQ

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

:
:
:
:
:
:
:
:
:
:

out
out
out
out
out
out
out
out
out
out

STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_LOGIC_VECTOR (29 downto

: out STD_LOGIC_VECTOR (9 downto 0);

: out STD_LOGIC_VECTOR (31 downto
:
:
:
:
:
:
:
:
:
:
:

out
out
out
out
out
out
out
out
out
out
out

STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_LOGIC_VECTOR (31 downto

:
:
:
:
:
:
:
:
:

out
out
out
out
out
out
out
out
out

STD_LOGIC_VECTOR (7 downto 0);

STD_ULOGIC;
STD_ULOGIC;
STD_LOGIC_VECTOR (1 downto 0);
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_LOGIC_VECTOR (63 downto

: out STD_ULOGIC;
: out STD_ULOGIC;
: out STD_LOGIC_VECTOR (29 downto
:
:
:
:
:
:
:

out
out
out
out
out
out
out

STD_ULOGIC;
STD_LOGIC_VECTOR (1 downto 0);
STD_ULOGIC;
STD_LOGIC_VECTOR (3 downto 2);
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;

909

PPC405

C405RSTSYSRESETREQ
: out STD_ULOGIC;
C405TRCCYCLE
: out STD_ULOGIC;
C405TRCEVENEXECUTIONSTATUS: out STD_LOGIC_VECTOR (1 downto
0);
C405TRCODDEXECUTIONSTATUS : out STD_LOGIC_VECTOR (1 downto
0);
C405TRCTRACESTATUS

: out STD_LOGIC_VECTOR (3 downto

C405TRCTRIGGEREVENTOUT
C405TRCTRIGGEREVENTTYPE

: out STD_ULOGIC;
: out STD_LOGIC_VECTOR (10 downto

C405XXXMACHINECHECK
DSOCMBRAMABUS

: out STD_ULOGIC;
: out STD_LOGIC_VECTOR (29 downto

DSOCMBRAMBYTEWRITE

: out STD_LOGIC_VECTOR (3 downto

DSOCMBRAMEN
DSOCMBRAMWRDBUS

: out STD_ULOGIC;
: out STD_LOGIC_VECTOR (31 downto

DSOCMBUSY
ISOCMBRAMEN
ISOCMBRAMEVENWRITEEN
ISOCMBRAMODDWRITEEN
ISOCMBRAMRDABUS

:
:
:
:
:

ISOCMBRAMWRABUS

: out STD_LOGIC_VECTOR (28 downto

ISOCMBRAMWRDBUS

: out STD_LOGIC_VECTOR (31 downto

BRAMDSOCMCLK
BRAMDSOCMRDDBUS

: in STD_ULOGIC;
: in STD_LOGIC_VECTOR (31 downto

BRAMISOCMCLK
BRAMISOCMRDDBUS

: in STD_ULOGIC;
: in STD_LOGIC_VECTOR (63 downto

CPMC405CLOCK
CPMC405CORECLKINACTIVE
CPMC405CPUCLKEN
CPMC405JTAGCLKEN
CPMC405TIMERCLKEN
CPMC405TIMERTICK
DBGC405DEBUGHALT
DBGC405EXTBUSHOLDACK
DBGC405UNCONDDEBUGEVENT
DCRC405ACK
DCRC405DBUSIN

:
:
:
:
:
:
:
:
:
:
:

in
in
in
in
in
in
in
in
in
in
in

STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_LOGIC_VECTOR (31 downto

DSARCVALUE
DSCNTLVALUE
EICC405CRITINPUTIRQ
EICC405EXTINPUTIRQ
ISARCVALUE
ISCNTLVALUE
JTGC405BNDSCANTDO
JTGC405TCK
JTGC405TDI
JTGC405TMS
JTGC405TRSTNEG

:
:
:
:
:
:
:
:
:
:
:

in
in
in
in
in
in
in
in
in
in
in

STD_LOGIC_VECTOR
STD_LOGIC_VECTOR
STD_ULOGIC;
STD_ULOGIC;
STD_LOGIC_VECTOR
STD_LOGIC_VECTOR
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;

0);

0);

8);
0);

0);
out
out
out
out
out

STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_LOGIC_VECTOR (28 downto

8);
8);
0);

0);

0);

0);

910

www.xilinx.com
1-800-255-7778

(7 downto 0);
(7 downto 0);

(7 downto 0);
(7 downto 0);

Libraries Guide
ISE 6.3i

PPC405

MCBCPUCLKEN
MCBJTAGEN
MCBTIMEREN
MCPPCRST
PLBC405DCUADDRACK
PLBC405DCUBUSY
PLBC405DCUERR
PLBC405DCURDDACK
PLBC405DCURDDBUS

:
:
:
:
:
:
:
:
:

in
in
in
in
in
in
in
in
in

STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_LOGIC_VECTOR (63 downto

PLBC405DCURDWDADDR
PLBC405DCUSSIZE1
PLBC405DCUWRDACK
PLBC405ICUADDRACK
PLBC405ICUBUSY
PLBC405ICUERR
PLBC405ICURDDACK
PLBC405ICURDDBUS

:
:
:
:
:
:
:
:

in
in
in
in
in
in
in
in

STD_LOGIC_VECTOR (3 downto 1);

STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_LOGIC_VECTOR (63 downto

:
:
:
:
:
:
:
:
:
:
:
:
:

in
in
in
in
in
in
in
in
in
in
in
in
in

STD_LOGIC_VECTOR (3 downto 1);

STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_LOGIC_VECTOR (7 downto 0);
STD_LOGIC_VECTOR (7 downto 0);
STD_ULOGIC;
STD_ULOGIC);

0);

0);
PLBC405ICURDWDADDR
PLBC405ICUSSIZE1
PLBCLK
RSTC405RESETCHIP
RSTC405RESETCORE
RSTC405RESETSYS
TIEC405DETERMINISTICMULT
TIEC405DISOPERANDFWD
TIEC405MMUEN
TIEDSOCMDCRADDR
TIEISOCMDCRADDR
TRCC405TRACEDISABLE
TRCC405TRIGGEREVENTINE
end component;

-- Component Attribute specification for PPC405

-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here
-- Component Instantiation for PPC405 should be placed
-- in architecture after the begin keyword
PPC405_INSTANCE_NAME : PPC405
port map (C405CPMCORESLEEPREQ
C405CPMMSRCE
C405CPMMSREE
C405CPMTIMERIRQ
C405CPMTIMERRESETREQ
C405DBGMSRWE
C405DBGSTOPACK
C405DBGWBCOMPLETE
C405DBGWBFULL
C405DBGWBIAR
C405DCRABUS
C405DCRDBUSOUT
C405DCRREAD

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>

user_C405CPMCORESLEEPREQ,
user_C405CPMMSRCE,
user_C405CPMMSREE,
user_C405CPMTIMERIRQ,
user_ C405CPMTIMERRESETREQ,
user_C405DBGMSRWE,
user_C405DBGSTOPACK,
user_C405DBGWBCOMPLETE,
user_C405DBGWBFULL,
user_C405DBGWBIAR,
user_C405DCRABUS,
user_C405DCRDBUSOUT,
user_C405DCRREAD,

911

912

PPC405

C405DCRWRITE
C405JTGCAPTUREDR
C405JTGEXTEST
C405JTGPGMOUT
C405JTGSHIFTDR
C405JTGTDO

=>
=>
=>
=>
=>
=>

user_C405DCRWRITE,
user_C405JTGCAPTUREDR,
user_C405JTGEXTEST,
user_C405JTGPGMOUT,
user_C405JTGSHIFTDR,
user_C405JTGTDO,

C405JTGTDOEN
C405JTGUPDATEDR
C405PLBDCUABORT
C405PLBDCUABUS
C405PLBDCUBE
C405PLBDCUCACHEABLE
C405PLBDCUGUARDED
C405PLBDCUPRIORITY
C405PLBDCUREQUEST
C405PLBDCURNW
C405PLBDCUSIZE2
C405PLBDCUU0ATTR
C405PLBDCUWRDBUS
C405PLBDCUWRITETHRU
C405PLBICUABORT
C405PLBICUABUS
C405PLBICUCACHEABLE
C405PLBICUPRIORITY
C405PLBICUREQUEST
C405PLBICUSIZE
C405PLBICUU0ATTR
C405RSTCHIPRESETREQ
C405RSTCORERESETREQ
C405RSTSYSRESETREQ
C405TRCCYCLE
C405TRCEVENEXECUTIONSTATUS
user_C405TRCEVENEXECUTIONSTATUS,
C405TRCODDEXECUTIONSTATUS
user_C405TRCODDEXECUTIONSTATUS,
C405TRCTRACESTATUS
C405TRCTRIGGEREVENTOUT
user_C405TRCTRIGGEREVENTOUT,
C405TRCTRIGGEREVENTTYPE
user_C405TRCTRIGGEREVENTTYPE,
C405XXXMACHINECHECK
DSOCMBRAMABUS
DSOCMBRAMBYTEWRITE
DSOCMBRAMEN
DSOCMBRAMWRDBUS
DSOCMBUSY
ISOCMBRAMEN
ISOCMBRAMEVENWRITEEN
ISOCMBRAMODDWRITEEN
ISOCMBRAMRDABUS
ISOCMBRAMWRABUS
ISOCMBRAMWRDBUS
BRAMDSOCMCLK
BRAMDSOCMRDDBUS
BRAMISOCMCLK
BRAMISOCMRDDBUS
CPMC405CLOCK

=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>

user_C405JTGTDOEN,
user_C405JTGUPDATEDR,
user_C405PLBDCUABORT,
user_C405PLBDCUABUS,
user_C405PLBDCUBE,
user_C405PLBDCUCACHEABLE,
user_C405PLBDCUGUARDED,
user_C405PLBDCUPRIORITY,
user_C405PLBDCUREQUEST,
user_C405PLBDCURNW,
user_C405PLBDCUSIZE2,
user_C405PLBDCUU0ATTR,
user_C405PLBDCUWRDBUS,
user_C405PLBDCUWRITETHRU,
user_C405PLBICUABORT,
user_C405PLBICUABUS,
user_C405PLBICUCACHEABLE,
user_C405PLBICUPRIORITY,
user_C405PLBICUREQUEST,
user_C405PLBICUSIZE,
user_C405PLBICUU0ATTR,
user_C405RSTCHIPRESETREQ,
user_C405RSTCORERESETREQ,
user_C405RSTSYSRESETREQ,
user_C405TRCCYCLE,

www.xilinx.com
1-800-255-7778

=>
=> user_C405TRCTRACESTATUS,
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>

user_C405XXXMACHINECHECK,
user_DSOCMBRAMABUS,
user_DSOCMBRAMBYTEWRITE,
user_DSOCMBRAMEN,
user_DSOCMBRAMWRDBUS,
user_DSOCMBUSY,
user_ISOCMBRAMEN,
user_ISOCMBRAMEVENWRITEEN,
user_ISOCMBRAMODDWRITEEN,
user_ISOCMBRAMRDABUS,
user_ISOCMBRAMWRABUS,
user_ISOCMBRAMWRDBUS,
user_BRAMDSOCMCLK,
user_BRAMDSOCMRDDBUS,
user_BRAMISOCMCLK,
user_BRAMISOCMRDDBUS,
user_CPMC405CLOCK,

Libraries Guide
ISE 6.3i

PPC405

Libraries Guide
ISE 6.3i

CPMC405CORECLKINACTIVE
user_CPMC405CORECLKINACTIVE,
CPMC405CPUCLKEN
CPMC405JTAGCLKEN
CPMC405TIMERCLKEN
CPMC405TIMERTICK
DBGC405DEBUGHALT

=>

DBGC405EXTBUSHOLDACK
DBGC405UNCONDDEBUGEVENT
user_DBGC405UNCONDDEBUGEVENT,
DCRC405ACK
DCRC405DBUSIN
DSARCVALUE
DSCNTLVALUE
EICC405CRITINPUTIRQ
EICC405EXTINPUTIRQ
ISARCVALUE
ISCNTLVALUE
JTGC405BNDSCANTDO
JTGC405TCK
JTGC405TDI
JTGC405TMS
JTGC405TRSTNEG
MCBCPUCLKEN
MCBJTAGEN
MCBTIMEREN
MCPPCRST
PLBC405DCUADDRACK
PLBC405DCUBUSY
PLBC405DCUERR
PLBC405DCURDDACK
PLBC405DCURDDBUS
PLBC405DCURDWDADDR
PLBC405DCUSSIZE1
PLBC405DCUWRDACK
PLBC405ICUADDRACK
PLBC405ICUBUSY
PLBC405ICUERR
PLBC405ICURDDACK
PLBC405ICURDDBUS
PLBC405ICURDWDADDR
PLBC405ICUSSIZE1
PLBCLK
RSTC405RESETCHIP
RSTC405RESETCORE
RSTC405RESETSYS
TIEC405DETERMINISTICMULT
user_TIEC405DETERMINISTICMULT,
TIEC405DISOPERANDFWD
TIEC405MMUEN
TIEDSOCMDCRADDR
TIEISOCMDCRADDR
TRCC405TRACEDISABLE
TRCC405TRIGGEREVENTINE
user_TRCC405TRIGGEREVENTINE);

=> user_DBGC405EXTBUSHOLDACK,
=>

www.xilinx.com
1-800-255-7778

=>
=>
=>
=>
=>

user_CPMC405CPUCLKEN,
user_CPMC405JTAGCLKEN,
user_CPMC405TIMERCLKEN,
user_CPMC405TIMERTICK,
user_DBGC405DEBUGHALT,

=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>

user_DCRC405ACK,
user_DCRC405DBUSIN,
user_DSARCVALUE,
user_DSCNTLVALUE,
user_EICC405CRITINPUTIRQ,
user_EICC405EXTINPUTIRQ,
user_ISARCVALUE,
user_ISCNTLVALUE,
user_JTGC405BNDSCANTDO,
user_JTGC405TCK,
user_JTGC405TDI,
user_JTGC405TMS,
user_JTGC405TRSTNEG,
user_MCBCPUCLKEN,
user_MCBJTAGEN,
user_MCBTIMEREN,
user_MCPPCRST,
user_PLBC405DCUADDRACK,
user_PLBC405DCUBUSY,
user_PLBC405DCUERR,
user_PLBC405DCURDDACK,
user_PLBC405DCURDDBUS,
user_PLBC405DCURDWDADDR,
user_PLBC405DCUSSIZE1,
user_PLBC405DCUWRDACK,
user_PLBC405ICUADDRACK,
user_PLBC405ICUBUSY,
user_PLBC405ICUERR,
user_PLBC405ICURDDACK,
user_PLBC405ICURDDBUS,
user_PLBC405ICURDWDADDR,
user_PLBC405ICUSSIZE1,
user_PLBCLK,
user_RSTC405RESETCHIP,
user_RSTC405RESETCORE,
user_RSTC405RESETSYS,

=>
=>
=>
=>
=>
=>

user_TIEC405DISOPERANDFWD,
user_TIEC405MMUEN,
user_TIEDSOCMDCRADDR,
user_TIEISOCMDCRADDR,
user_TRCC405TRACEDISABLE,

913

PPC405

Verilog Instantiation Template

PPC405 instance_name (.C405CPMCORESLEEPREQ
(user_C405CPMCORESLEEPREQ),
.C405CPMMSRCE (user_C405CPMMSRCE),
.C405CPMMSREE (user_C405CPMMSREE),
.C405CPMTIMERIRQ (user_C405CPMTIMERIRQ),
.C405CPMTIMERRESETREQ
(user_ C405CPMTIMERRESETREQ),
.C405DBGMSRWE (user_C405DBGMSRWE),
.C405DBGSTOPACK (user_C405DBGSTOPACK),
.C405DBGWBCOMPLETE (user_C405DBGWBCOMPLETE),
.C405DBGWBFULL (user_C405DBGWBFULL),
.C405DBGWBIAR (user_C405DBGWBIAR),
.C405DCRABUS (user_C405DCRABUS),
.C405DCRDBUSOUT (user_C405DCRDBUSOUT),
.C405DCRREAD (user_C405DCRREAD),
.C405DCRWRITE (user_C405DCRWRITE),
.C405JTGCAPTUREDR (user_C405JTGCAPTUREDR),
.C405JTGEXTEST (user_C405JTGEXTEST),
.C405JTGPGMOUT (user_C405JTGPGMOUT),
.C405JTGSHIFTDR (user_C405JTGSHIFTDR),
.C405JTGTDO (user_C405JTGTDO),
.C405JTGTDOEN (user_C405JTGTDOEN),
.C405JTGUPDATEDR (user_C405JTGUPDATEDR),
.C405PLBDCUABORT (user_C405PLBDCUABORT),
.C405PLBDCUABUS (user_C405PLBDCUABUS),
.C405PLBDCUBE (user_C405PLBDCUBE),
.C405PLBDCUCACHEABLE (user_C405PLBDCUCACHEABLE),
.C405PLBDCUGUARDED (user_C405PLBDCUGUARDED),
.C405PLBDCUPRIORITY (user_C405PLBDCUPRIORITY),
.C405PLBDCUREQUEST (user_C405PLBDCUREQUEST),
.C405PLBDCURNW (user_C405PLBDCURNW),
.C405PLBDCUSIZE2 (user_C405PLBDCUSIZE2),
.C405PLBDCUU0ATTR (user_C405PLBDCUU0ATTR),
.C405PLBDCUWRDBUS (user_C405PLBDCUWRDBUS),
.C405PLBDCUWRITETHRU (user_C405PLBDCUWRITETHRU),
.C405PLBICUABORT (user_C405PLBICUABORT),
.C405PLBICUABUS (user_C405PLBICUABUS),
.C405PLBICUCACHEABLE (user_C405PLBICUCACHEABLE),
.C405PLBICUPRIORITY (user_C405PLBICUPRIORITY),
.C405PLBICUREQUEST (user_C405PLBICUREQUEST),
.C405PLBICUSIZE (user_C405PLBICUSIZE),
.C405PLBICUU0ATTR (user_C405PLBICUU0ATTR),
.C405RSTCHIPRESETREQ (user_C405RSTCHIPRESETREQ),
.C405XXXMACHINECHECK (user_C405XXXMACHINECHECK),
.DSOCMBRAMABUS (user_DSOCMBRAMABUS),
.DSOCMBRAMBYTEWRITE (user_DSOCMBRAMBYTEWRITE),
.DSOCMBRAMEN (user_DSOCMBRAMEN),
.DSOCMBRAMWRDBUS(user_DSOCMBRAMWRDBUS),
.DSOCMBUSY (user_DSOCMBUSY),
.ISOCMBRAMEN (user_ISOCMBRAMEN),
.ISOCMBRAMEVENWRITEEN
(user_ISOCMBRAMEVENWRITEEN),
.ISOCMBRAMODDWRITEEN (user_ISOCMBRAMODDWRITEEN),
.ISOCMBRAMRDABUS (user_ISOCMBRAMRDABUS),
.ISOCMBRAMWRABUS (user_ISOCMBRAMWRABUS),

914

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Libraries Guide
ISE 6.3i

PPC405

.ISOCMBRAMWRDBUS (user_ISOCMBRAMWRDBUS),
.BRAMDSOCMCLK (user_BRAMDSOCMCLK),
.BRAMDSOCMRDDBUS (user_BRAMDSOCMRDDBUS),
.BRAMISOCMCLK (user_BRAMISOCMCLK),
.BRAMISOCMRDDBUS (user_BRAMISOCMRDDBUS),
.CPMC405CLOCK (user_CPMC405CLOCK),
.CPMC405CORECLKINACTIVE
(user_CPMC405CORECLKINACTIVE),
.CPMC405CPUCLKEN (user_CPMC405CPUCLKEN),
.CPMC405JTAGCLKEN (user_CPMC405JTAGCLKEN),
.CPMC405TIMERCLKEN (user_CPMC405TIMERCLKEN),
.CPMC405TIMERTICK (user_CPMC405TIMERTICK),
.DBGC405DEBUGHALT (user_DBGC405DEBUGHALT),
.DBGC405EXTBUSHOLDACK
(user_DBGC405EXTBUSHOLDACK),
.DBGC405UNCONDDEBUGEVENT
(user_DBGC405UNCONDDEBUGEVENT),
.DCRC405ACK (user_DCRC405ACK),
.DCRC405DBUSIN (user_DSARCVALUE),
.DSCNTLVALUE (user_DSCNTLVALUE),
.EICC405CRITINPUTIRQ (user_EICC405CRITINPUTIRQ),
.EICC405EXTINPUTIRQ (user_EICC405EXTINPUTIRQ),
.ISARCVALUE (user_ISARCVALUE),
.ISCNTLVALUE (user_ISCNTLVALUE),
.JTGC405BNDSCANTDO (user_JTGC405BNDSCANTDO),
.JTGC405TCK (user_JTGC405TCK),
.JTGC405TDI (user_JTGC405TDI),
.JTGC405TMS (user_JTGC405TMS),
.JTGC405TRSTNEG (user_JTGC405TRSTNEG),
.MCBCPUCLKEN (user_MCBCPUCLKEN),
.MCBJTAGEN (user_MCBJTAGEN),
.MCBTIMEREN (user_MCBTIMEREN),
.MCPPCRST (user_MCPPCRST),
.PLBC405DCUADDRACK (user_PLBC405DCUADDRACK),
.PLBC405DCUBUSY (user_PLBC405DCUBUSY),
.PLBC405DCUERR (user_PLBC405DCUERR),
.PLBC405DCURDDACK (user_PLBC405DCURDDACK),
.PLBC405DCURDDBUS (user_PLBC405DCURDDBUS),
.PLBC405DCURDWDADDR (user_PLBC405DCURDWDADDR),
.PLBC405DCUSSIZE1 (user_PLBC405DCUSSIZE1),
.PLBC405DCUWRDACK (user_PLBC405DCUWRDACK),
.PLBC405ICUADDRACK (user_PLBC405ICUADDRACK),
.PLBC405ICUBUSY (user_PLBC405ICUBUSY),
.PLBC405ICUERR (user_PLBC405ICUERR),
.PLBC405ICURDDACK (user_PLBC405ICURDDACK),
.PLBC405ICURDDBUS (user_PLBC405ICURDDBUS),
.PLBC405ICURDWDADDR (user_PLBC405ICURDWDADDR),
.PLBC405ICUSSIZE1 (user_PLBC405ICUSSIZE1),
.PLBCLK (user_PLBCLK),
.RSTC405RESETCHIP (user_RSTC405RESETCHIP),
.RSTC405RESETCORE (user_RSTC405RESETCORE),
.RSTC405RESETSYS (user_RSTC405RESETSYS),
.TIEC405DETERMINISTICMULT
(user_TIEC405DETERMINISTICMULT),
.TIEC405DISOPERANDFWD
(user_TIEC405DISOPERANDFWD),
.TIEC405MMUEN (user_TIEC405MMUEN),
.TIEDSOCMDCRADDR (user_TIEDSOCMDCRADDR),

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ISE 6.3i

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915

PPC405

.TIEISOCMDCRADDR (user_TIEISOCMDCRADDR),
.TRCC405TRACEDISABLE (user_TRCC405TRACEDISABLE),
.TRCC405TRIGGEREVENTINE
(user_TRCC405TRIGGEREVENTINE));

916

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1-800-255-7778

Libraries Guide
ISE 6.3i

PULLDOWN

PULLDOWN
Resistor to GND for Input Pads
Architectures Supported
PULLDOWN
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

PULLDOWN resistor elements are connected to input, output, or bidirectional pads

to guarantee a logic Low level for nodes that might float.

Usage
X3860

Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- Component Declaration for PULLDOWN should be placed
-- after architecture statement but before begin keyword
-- <Cut code below this line and paste into the architecture body>
-- PULLDOWN: I/O Buffer Weak Pull-down
-All FPGA, CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
PULLDOWN_inst : PULLDOWN
port map (
O => O
-- Pulldown output (connect directly to top-level port)
);
-- End of PULLDOWN_inst instantiation

Verilog Instantiation Template

// PULLDOWN: I/O Buffer Weak Pull-down
//
All FPGA, CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i
PULLDOWN PULLDOWN_inst (
.O(O),
// Pulldown output (connect directly to
// top-level port)
);
// End of PULLDOWN_inst instantiation

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ISE 6.3i

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917

918

PULLDOWN

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Libraries Guide
ISE 6.3i

PULLUP

PULLUP
Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs
Architectures Supported
PULLUP
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

Primitive*

CoolRunner-II

Primitive

* Supported only on input-only pins for CoolRunner

XPLA3.

The pull-up elements establish a High logic level for open-drain elements and macros
(DECODE, WAND, WORAND) or 3-state nodes (TBUF) when all the drivers are off.
The buffer outputs are connected together as a wired-AND to form the output (O).
When all the inputs are High, the output is off. To establish an output High level, a
PULLUP resistor(s) is tied to output (O). One PULLUP resistor uses the least power,
two pull-up resistors achieve the fastest Low-to-High speed.
X3861

To indicate two PULLUP resistors, append a DOUBLE parameter to the pull-up

symbol attached to the output (O) node. See the appropriate CAE tool interface user
guide for details.

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Template

-- PULLUP: I/O Buffer Weak Pull-up
-All FPGA, CoolRunner-II
-- Xilinx HDL Libraries Guide version 7.1i
PULLUP_inst : PULLUP
port map (
O => O
-- Pullup output (connect directly to top-level port)
);
-- End of PULLUP_inst instantiation

Verilog Instantiation Template

// PULLUP: I/O Buffer Weak Pull-up
//
All FPGA, CoolRunner-II
// Xilinx HDL Libraries Guide version 7.1i

Libraries Guide
ISE 6.3i

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919

PULLUP

PULLUP PULLUP_inst (
.O(O),
// Pullup output (connect directly to top-level port)
);
// End of PULLUP_inst instantiation

Commonly Used Constraints

DOUBLE, HBLKNM

920

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Libraries Guide
ISE 6.3i

RAM16X1D

RAM16X1D
16-Deep by 1-Wide Static Dual Port Synchronous RAM
Architectures Supported
RAM16X1D
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE

RAM16X1D

SPO

D
DPO

WCLK
A0
A1
A2
A3
DPRA0
DPRA1
DPRA2
DPRA3

X4950

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM16X1D is a 16-word by 1-bit static dual port random access memory with
synchronous write capability. The device has two separate address ports: the read
address (DPRA3 DPRA0) and the write address (A3 A0). These two address ports
are completely asynchronous. The read address controls the location of the data
driven out of the output pin (DPO), and the write address controls the destination of a
valid write transaction.
When the write enable (WE) is Low, transitions on the write clock (WCLK) are
ignored and data stored in the RAM is not affected. When WE is High, any positive
transition on WCLK loads the data on the data input (D) into the word selected by the
4-bit write address. For predictable performance, write address and data inputs must
be stable before a Low-to-High WCLK transition. This RAM block assumes an activeHigh WCLK. WCLK can be active-High or active-Low. Any inverter placed on the
WCLK input net is absorbed into the block.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

SPO

DPO

0 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (write)

data_d

1 (read)

data_a

data_d

data_a = word addressed by bits A3-A0

data_d = word addressed by bits DPRA3-DPRA0

The SPO output reflects the data in the memory cell addressed by A3 A0. The DPO
output reflects the data in the memory cell addressed by DPRA3 DPRA0.
Note: The write process is not affected by the address on the read address port.

Libraries Guide
ISE 6.3i

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921

RAM16X1D

Specifying Initial Contents of a RAM

You can use the INIT attribute to specify an initial value directly on the symbol if the
RAM is 1 bit wide and 16, 32, 64, or 128 bits deep. The value must be a hexadecimal
number, for example, INIT=ABAC. If the INIT attribute is not specified, the RAM is
initialized with zero.
For Virtex, Virtex-E, Spartan-II, and Spartan-IIE, lower INIT values get mapped to the
G function generator and upper INIT values get mapped to the F function generator.
See the "INIT" section of the Constraints Guide for more information on the INIT
attribute.
For Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, wide RAMs (2, 4, and 8-bit
wide single port synchronous RAMs with a WCLK) can also be initialized. These
RAMs, however, require INIT_xx attributes. See Specifying Initial Contents of a
Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X Wide RAM in the RAM16X2S
section for more information on initializing Virtex-II wide RAM.

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template

-- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port
-- distributed RAM
-All FPGAs
-- Xilinx HDL Language Template version 6.1i
RAM16X1D_inst : RAM16X1D
-- The following generic INIT declaration is only necessary
-- if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT => X"0000")
port map (
DPO => DPO,
-- Port A 1-bit data output
SPO => SPO,
-- Port B 1-bit data output
A0 => A0,
-- Port A address[0] input bit
A1 => A1,
-- Port A address[1] input bit
A2 => A2,
-- Port A address[2] input bit
A3 => A3,
-- Port A address[3] input bit
D => D,
-- Port A 1-bit data input
DPRA0 => DPRA0, -- Port B address[0] input bit
DPRA1 => DPRA1, -- Port B address[1] input bit
DPRA2 => DPRA2, -- Port B address[2] input bit
DPRA3 => DPRA3, -- Port B address[3] input bit
WCLK => WCLK,
-- Port A write clock input
WE => WE
-- Port A write enable input
);
-- End of RAM16X1D_inst instantiation

922

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Libraries Guide
ISE 6.3i

RAM16X1D

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how toinclude INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM16X1D RAM16X1D_inst (
.DPO(DPO),
// Port
.SPO(SPO),
// Port
.A0(A0),
// Port
.A1(A1),
// Port
.A2(A2),
// Port
.A3(A3),
// Port
.D(D),
// Port
.DPRA0(DPRA0), // Port
.DPRA1(DPRA1), // Port
.DPRA2(DPRA2), // Port
.DPRA3(DPRA3), // Port
.WCLK(WCLK),
// Port
.WE(WE)
// Port
);
//
//
//
//

A
B
A
A
A
A
A
B
B
B
B
A
A

1-bit data output

1-bit data output
address[0] input bit
address[1] input bit
address[2] input bit
address[3] input bit
1-bit data input
address[0] input bit
address[1] input bit
address[2] input bit
address[3] input bit
write clock input
write enable input

The following defparam INIT declaration is only necessary if you

wish to change the initial contents of the RAM to anything other
than all zero's. If the instance name for the RAM is is changes,
that change needs to be reflected in the defparam statement.

defparam RAM16X1D_inst.INIT = 16'h0000;

// End of RAM16X1D_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, XBLKNM

Libraries Guide
ISE 6.3i

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923

924

RAM16X1D

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Libraries Guide
ISE 6.3i

RAM16X1D_1

RAM16X1D_1
16-Deep by 1-Wide Static Dual Port Synchronous RAM with NegativeEdge Clock
Architectures Supported
RAM16X1D_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE RAM16X1D_1 SPO
D
DPO
WCLK
A0
A1
A2
A3
DPRA0
DPRA1
DPRA2
DPRA3

X8419

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with
synchronous write capability and negative-edge clock. The device has two separate
address ports: the read address (DPRA3 DPRA0) and the write address (A3 A0).
These two address ports are completely asynchronous. The read address controls the
location of the data driven out of the output pin (DPO), and the write address controls
the destination of a valid write transaction.
When the write enable (WE) is Low, transitions on the write clock (WCLK) are
ignored and data stored in the RAM is not affected. When WE is High, any negative
transition on WCLK loads the data on the data input (D) into the word selected by the
4-bit write address. For predictable performance, write address and data inputs must
be stable before a High-to-Low WCLK transition. This RAM block assumes an activeHigh WCLK. WCLK can be active-High or active-Low. Any inverter placed on the
WCLK input net is absorbed into the block.
You can initialize RAM16X1D_1 during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

SPO

DPO

0 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (write)

data_d

1 (read)

data_a

data_d

data_a = word addressed by bits A3-A0

data_d = word addressed by bits DPRA3-DPRA0

The SPO output reflects the data in the memory cell addressed by A3 A0. The DPO
output reflects the data in the memory cell addressed by DPRA3 DPRA0.
Note: The write process is not affected by the address on the read address port.

Libraries Guide
ISE 6.3i

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925

RAM16X1D_1

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template

-- RAM16X1D_1: 16 x 1 negative edge write, asynchronous read
-- dual-port distributed RAM
-All FPGA
-- Xilinx HDL Language Template version 6.1i
RAM16X1D_1_inst : RAM16X1D_1
-- The following generic INIT declaration is only necessary if
-- you wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT => X"0000")
port map (
DPO => DPO,
-- Port A 1-bit data output
SPO => SPO,
-- Port B 1-bit data output
A0 => A0,
-- Port A address[0] input bit
A1 => A1,
-- Port A address[1] input bit
A2 => A2,
-- Port A address[2] input bit
A3 => A3,
-- Port A address[3] input bit
D => D,
-- Port A 1-bit data input
DPRA0 => DPRA0, -- Port B address[0] input bit
DPRA1 => DPRA1, -- Port B address[1] input bit
DPRA2 => DPRA2, -- Port B address[2] input bit
DPRA3 => DPRA3, -- Port B address[3] input bit
WCLK => WCLK,
-- Port A write clock input
WE => WE
-- Port A write enable input
);
-- End of RAM16X1D_1_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how toinclude INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM16X1D_1 RAM16X1D_1_inst (
.DPO(DPO),
// Port A 1-bit data output
.SPO(SPO),
// Port B 1-bit data output
.A0(A0),
// Port A address[0] input bit
.A1(A1),
// Port A address[1] input bit
.A2(A2),
// Port A address[2] input bit
.A3(A3),
// Port A address[3] input bit
.D(D),
// Port A 1-bit data input
.DPRA0(DPRA0), // Port B address[0] input bit
.DPRA1(DPRA1), // Port B address[1] input bit
.DPRA2(DPRA2), // Port B address[2] input bit
.DPRA3(DPRA3), // Port B address[3] input bit
.WCLK(WCLK),
// Port A write clock input
.WE(WE)
// Port A write enable input
);

926

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Libraries Guide
ISE 6.3i

RAM16X1D_1

//
//
//
//

The following defparam INIT declaration is only necessary if you

wish to change the initial contents of the RAM to anything other
than all zero's. If the instance name for the RAM is is changes,
that change needs to be reflected in the defparam statement.

defparam RAM16X1D_1_inst.INIT = 16'h0000000000000000;

// End of RAM16X1D_1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, XBLKNM

Libraries Guide
ISE 6.3i

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927

928

RAM16X1D_1

www.xilinx.com
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Libraries Guide
ISE 6.3i

RAM16X1S

RAM16X1S
16-Deep by 1-Wide Static Synchronous RAM
Architectures Supported
RAM16X1S
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE

RAM16X1S

D
WCLK
A0
A1
A2
A3
X4942

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM16X1S is a 16-word by 1-bit static random access memory with synchronous

write capability. When the write enable (WE) is Low, transitions on the write clock
(WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
any positive transition on WCLK loads the data on the data input (D) into the word
selected by the 4-bit address (A3 A0). For predictable performance, address and data
inputs must be stable before a Low-to-High WCLK transition. This RAM block
assumes an active-High WCLK. However, WCLK can be active-High or active-Low.
Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at
the location defined by the values on the address pins.
You can initialize RAM16X1S during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE(mode)

WCLK

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

1 (read)

Data

Data = word addressed by bits A3 A0

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

929

RAM16X1S

VHDL Instantiation Template

-- Note that the use of INIT below is for simulation only
-- For examples on how to include INIT as an implementation
-- constraint,please refer to the Constraints Guide
-- <Cut code below this line and paste into the architecture body>
-- RAM16X1S: 16 x 1 posedge write distributed
-All FPGA
-- Xilinx HDL Language Template version 6.1i

=> LUT RAM

RAM16X1S_inst : RAM16X1S
-- Edit the following generic to change the inital contents of the RAM.
generic map (
INIT => X"0000")
port map (
O => O,
-- RAM output
A0 => A0,
-- RAM address[0] input
A1 => A1,
-- RAM address[1] input
A2 => A2,
-- RAM address[2] input
A3 => A3,
-- RAM address[3] input
D => D,
-- RAM data input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM16X1S_inst instantiation

Verilog Instantiation Template

// RAM16X1S: 16 x 1 posedge write distributed (LUT) RAM
//
All FPGA
// XilinxHDL Libraries Guide version 7.1i
RAM16X1S RAM16X1S_inst (
.O(O),
// RAM output
.A0(A0),
// RAM address[0] input
.A1(A1),
// RAM address[1] input
.A2(A2),
// RAM address[2] input
.A3(A3),
// RAM address[3] input
.D(D),
// RAM data input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
//
//
//
//

Edit the following defparam to change the inital contents of the RAM
to a non-zero value if desired. If the instance name to the RAM is
changed, that change needs to be reflected in the defpara
statements.
defparam RAM16X1S_inst.INIT = 16'h0000;

// End of RAM16X1S_inst instantiation

Commonly Used Constraints

BEL, BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM

930

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Libraries Guide
ISE 6.3i

RAM16X1S_1

RAM16X1S_1
16-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
Architectures Supported
RAM16X1S_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE RAM16X1S_1

D
WCLK
A0
A1
A2
A3

X9458

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous

write capability and negative-edge clock. When the write enable (WE) is Low,
transitions on the write clock (WCLK) are ignored and data stored in the RAM is not
affected. When WE is High, any negative transition on WCLK loads the data on the
data input (D) into the word selected by the 4-bit address (A3 A0). For predictable
performance, address and data inputs must be stable before a High-to-Low WCLK
transition. This RAM block assumes an active-Low WCLK. However, WCLK can be
active-High or active-Low. Any inverter placed on the WCLK input net is absorbed
into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at
the location defined by the values on the address pins.
You can initialize RAM16X1S_1 during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE(mode)

WCLK

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

1 (read)

Data

Data = word addressed by bits A3 A0

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

931

RAM16X1S_1

VHDL Instantiation Template

-- RAM16X1S_1: 16 x 1 negedge write distributed
-All FPGA
-- Xilinx HDL Language Template version 6.1i

=> LUT RAM

RAM16X1S_1_inst : RAM16X1S_1
-- Edit the following generic to change the inital contents
-- of the RAM.
generic map (
INIT => X"0000")
port map (
O => O,
-- RAM output
A0 => A0,
-- RAM address[0] input
A1 => A1,
-- RAM address[1] input
A2 => A2,
-- RAM address[2] input
A3 => A3,
-- RAM address[3] input
D => D,
-- RAM data input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM16X1S_1_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how toinclude INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM16X1S_1 RAM16X1S_1_inst (
.O(O),
// RAM output
.A0(A0),
// RAM address[0] input
.A1(A1),
// RAM address[1] input
.A2(A2),
// RAM address[2] input
.A3(A3),
// RAM address[3] input
.D(D),
// RAM data input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
//
//
//
//

Edit the following defparam to change the inital contents of the RAM
to a non-zero value if desired. If the instance name to the RAM is
changed, that change needs to be reflected in the defparam
statements.
defparam RAM16X1S_1_inst.INIT = 16'h0000;

// End of RAM16X1S_1_inst instantiation

Commonly Used Constraints

BEL, BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, XBLKNM

932

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Libraries Guide
ISE 6.3i

RAM16X2D

RAM16X2D
16-Deep by 2-Wide Static Dual Port Synchronous RAM
Architectures Supported
RAM16X2D
Spartan-II, Spartan-IIE

Macro

Spartan-3

No

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

WE

RAM16X2D

D0

SPO0
SPO1

D1
WCLK

DPO0

A0

DPO1

A1
A2
A3
DPRA0
DPRA1
DPRA2
DPRA3

X4951

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM16X2D is a 16-word by 2-bit static dual port random access memory with
synchronous write capability. The device has two separate address ports: the read
address (DPRA3 DPRA0) and the write address (A3 A0). These two address ports
are completely asynchronous. The read address controls the location of data driven
out of the output pin (DPO1 DPO0), and the write address controls the destination
of a valid write transaction.
When the write enable (WE) is Low, transitions on the write clock (WCLK) are
ignored and data stored in the RAM is not affected. When WE is High, any positive
transition on WCLK loads the data on the data input (D1 D0) into the word selected
by the 4-bit write address. For predictable performance, write address and data inputs
must be stable before a Low-to-High WCLK transition. This RAM block assumes an
active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter
placed on the WCLK input net is absorbed into the block.
The initial contents of RAM16X2D cannot be specified directly. See Specifying Initial
Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

D1-D0

SPO1-SPO0

DPO1-DPO0

0 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (write)

D1-D0

D1-D0

data_d

1 (read)

data_a

data_d

data_a = word addressed by bits A3-A0

data_d = word addressed by bits DPRA3-DPRA0

The SPO output reflects the data in the memory cell addressed by A3 A0. The DPO
output reflects the data in the memory cell addressed by DPRA3 DPRA0.
Note: The write process is not affected by the address on the read address port.

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933

RAM16X2D

Usage
For HDL, this design element is inferred. See the XST User Guide for details.

934

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Libraries Guide
ISE 6.3i

RAM16X2S

RAM16X2S
16-Deep by 2-Wide Static Synchronous RAM
Architectures Supported
RAM16X2S
Spartan-II, Spartan-IIE

Macro

Spartan-3

Primitive

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE

RAM16X2S O0

D0
D1

O1

WCLK
A0
A1
A2
A3

X4944

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM16X2S is a 16-word by 2-bit static random access memory with synchronous

write capability. When the write enable (WE) is Low, transitions on the write clock
(WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
any positive transition on WCLK loads the data on the data input (D1 D0) into the
word selected by the 4-bit address (A3 A0). For predictable performance, address
and data inputs must be stable before a Low-to-High WCLK transition. This RAM
block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pins (O1 O0) is the data that is stored in the
RAM at the location defined by the values on the address pins.
Except for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the initial contents of
RAM16X2S cannot be specified directly. See Specifying Initial Contents of a RAM in
the RAM16X1D section.
For Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, you can use the INIT_00 and
INIT_01 properties to specify the initial contents of RAM16X2S as described in
Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X
Wide RAM in this section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

D1-D0

O1-O0

0 (read)

Data

1(read)

Data

1(read)

Data

1(write)

D1-D0

D1-D0

1 (read)

Data

Data = word addressed by bits A3 A0

Libraries Guide
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935

RAM16X2S

Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and

Virtex-II Pro X Wide RAM
You can use the INIT_xx properties to specify the initial contents of a Spartan-3,
Virtex-II, Virtex-II Pro, and Virtex-II Pro X wide RAM. INIT_00 initializes the RAM
cells corresponding to the O0 output, INIT_01 initializes the cells corresponding to the
O1 output, etc. For example, a RAM16X2S instance is initialized by INIT_00 and
INIT_01 containing 4 hex characters each. A RAM16X8S instance is initialized by
eight properties INIT_00 through INIT_07 containing 4 hex characters each. A
RAM64x2S instance is completely initialized by two properties INIT_00 and INIT_01
containing 16 hex characters each. See the INIT_xx section of the Constraints Guide for
more information on the INIT_xx attribute.

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template

-- RAM16X2S: 16 x 2 posedge write distributed
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Language Template version 6.1i

=> LUT RAM

RAM16X2S_inst : RAM16X2S
-- Edit the following generic to change the inital contents
-- of the RAM.
generic map (
INIT_00 => X"0000", -- INIT for bit 0 of RAM
INIT_01 => X"0000", -- INIT for bit 1 of RAM")
port map (
O0 => O0,
-- RAM data[0] output
O1 => O1,
-- RAM data[1] output
A0 => A0,
-- RAM address[0] input
A1 => A1,
-- RAM address[1] input
A2 => A2,
-- RAM address[2] input
A3 => A3,
-- RAM address[3] input
D0 => D0,
-- RAM data[0] input
D1 => D1,
-- RAM data[1] input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM16X2S_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM16X2S RAM16X2S_inst
.O0(O0),
// RAM
.O1(O1),
// RAM
.A0(A0),
// RAM
.A1(A1),
// RAM

936

(
data[0] output
data[1] output
address[0] input
address[1] input

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Libraries Guide
ISE 6.3i

RAM16X2S

.A2(A2),
.A3(A3),
.D0(D0),
.D1(D1),
.WCLK(WCLK),
.WE(WE)

//
//
//
//
//
//

RAM address[2] input

RAM address[3] input
RAM data[0] input
RAM data[1] input
Write clock input
Write enable input

);
//
//
//
//

Edit the following defparam to change the inital contents of the RAM
to a non-zero value if desired. If the instance name to the RAM is
changed, that change needs to be reflected in the defparam
statements.
defparam RAM16X2S_inst.INIT_00 = 16'h0000; // INIT for bit 0 of RAM
defparam RAM16X2S_inst.INIT_01 = 16'h0000; // INIT for bit 1 of RAM

// End of RAM16X2S_inst instantiation

Commonly Used Constraints

BEL, INIT_xx, BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, XBLKNM

Libraries Guide
ISE 6.3i

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937

938

RAM16X2S

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Libraries Guide
ISE 6.3i

RAM16X4D

RAM16X4D
16-Deep by 4-Wide Static Dual Port Synchronous RAM
Architectures Supported
RAM16X4D
Spartan-II, Spartan-IIE

Macro

Spartan-3

No

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

WE

RAM16X4D

D0
D1
D2

SPO0
SPO1
SPO2
SPO3

D3
WCLK

DPO0

A0

DPO1

A1

DPO2

A2

DPO3

A3
DPRA0
DPRA1
DPRA2
DPRA3

X4952

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM16X4D is a 16-word by 4-bit static dual port random access memory with
synchronous write capability. The device has two separate address ports: the read
address (DPRA3 DPRA0) and the write address (A3 A0). These two address ports
are completely asynchronous. The read address controls the location of data driven
out of the output pin (DPO3 DPO0), and the write address controls the destination
of a valid write transaction.
When the write enable (WE) is Low, transitions on the write clock (WCLK) are
ignored and data stored in the RAM is not affected. When WE is High, any positive
transition on WCLK loads the data on the data input (D3 D0) into the word selected
by the 4-bit write address. For predictable performance, write address and data inputs
must be stable before a Low-to-High WCLK transition. This RAM block assumes an
active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter
placed on the WCLK input net is absorbed into the block.
The initial contents of RAM16X4D cannot be specified directly. See Specifying Initial
Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

D3-D0

SPO3-SPO0

DPO3-DPO0

0 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (write)

D3-D0

D3-D0

data_d

1 (read)

data_a

data_d

data_a = word addressed by bits A3-A0

data_d = word addressed by bits DPRA3-DPRA0

The SPO output reflects the data in the memory cell addressed by A3 A0. The DPO
output reflects the data in the memory cell addressed by DPRA3 DPRA0.
Note: The write process is not affected by the address on the read address port.

Libraries Guide
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939

RAM16X4D

Usage
For HDL, this design element must be inferred. For information on how to infer RAM,
see the XST User Guide.

940

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Libraries Guide
ISE 6.3i

RAM16X4S

RAM16X4S
16-Deep by 4-Wide Static Synchronous RAM
Architectures Supported
RAM16X4S
Spartan-II, Spartan-IIE

Macro

Spartan-3

Primitive

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE

RAM16X4S

D0

O0

D1

O1
O2

D2

O3

D3
WCLK
A0
A1
A2

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM16X4S is a 16-word by 4-bit static random access memory with synchronous

write capability. When the write enable (WE) is Low, transitions on the write clock
(WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
any positive transition on WCLK loads the data on the data input (D3 D0) into the
word selected by the 4-bit address (A3 A0). For predictable performance, address
and data inputs must be stable before a Low-to-High WCLK transition. This RAM
block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block.

A3
X4945

The signal output on the data output pins (O3 O0) is the data that is stored in the
RAM at the location defined by the values on the address pins.
Except for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the initial contents of
RAM16X4S cannot be specified directly. See Specifying Initial Contents of a RAM in
the RAM16X1D section.
For Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, you can use INIT_00
through INIT_03 to specify the initial contents of RAM16X4S as described in the
Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X
Wide RAMsection in the RAM16X2S section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

D3 D0

O3 O0

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

D3-D0

D3-D0

1 (read)

Data

Data = word addressed by bits A3 A0

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ISE 6.3i

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941

RAM16X4S

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template

-- RAM16X4S: 16 x 4 posedge write distributed
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Language Template version 6.1i

=> LUT RAM

RAM16X4S_inst : RAM16X4S
-- Edit the following generic to change the inital contents
-- of the RAM.
generic map (
INIT_00 => X"0000", -- INIT for bit 0 of RAM
INIT_01 => X"0000", -- INIT for bit 1 of RAM
INIT_02 => X"0000", -- INIT for bit 2 of RAM
INIT_03 => X"0000", -- INIT for bit 3 of RAM")
port map (
O0 => O0,
-- RAM data[0] output
O1 => O1,
-- RAM data[1] output
O2 => O2,
-- RAM data[2] output
O3 => O3,
-- RAM data[3] output
A0 => A0,
-- RAM address[0] input
A1 => A1,
-- RAM address[1] input
A2 => A2,
-- RAM address[2] input
A3 => A3,
-- RAM address[3] input
D0 => D0,
-- RAM data[0] input
D1 => D1,
-- RAM data[1] input
D2 => D2,
-- RAM data[2] input
D3 => D3,
-- RAM data[3] input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM16X4S_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM16X4S RAM16X4S_inst (
.O0(O0),
// RAM data[0] output
.O1(O1),
// RAM data[1] output
.O2(O2),
// RAM data[2] output
.O3(O3),
// RAM data[3] output
.A0(A0),
// RAM address[0] input
.A1(A1),
// RAM address[1] input
.A2(A2),
// RAM address[2] input
.A3(A3),
// RAM address[3] input
.D0(D0),
// RAM data[0] input
.D1(D1),
// RAM data[1] input
.D2(D2),
// RAM data[2] input
.D3(D3),
// RAM data[3] input
.WCLK(WCLK), // Write clock input

942

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Libraries Guide
ISE 6.3i

RAM16X4S

.WE(WE)

// Write enable input

);
//
//
//
//

Edit the following defparam to change the inital contents of the RAM
to a non-zero value if desired. If the instance name to the RAM is
changed, that change needs to be reflected in the defparam
statements.
defparam
defparam
defparam
defparam

RAM16X4S_inst.INIT_00
RAM16X4S_inst.INIT_01
RAM16X4S_inst.INIT_02
RAM16X4S_inst.INIT_03

=
=
=
=

16'h0000;
16'h0000;
16'h0000;
16'h0000;

//
//
//
//

INIT
INIT
INIT
INIT

for
for
for
for

bit
bit
bit
bit

0
1
2
3

of
of
of
of

RAM
RAM
RAM
RAM

// End of RAM16X4S_inst instantiation

Commonly Used Constraints

BEL, INIT_xx, BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, XBLKNM

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ISE 6.3i

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943

944

RAM16X4S

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Libraries Guide
ISE 6.3i

RAM16X8D

RAM16X8D
16-Deep by 8-Wide Static Dual Port Synchronous RAM
Architectures Supported
RAM16X8D
Spartan-II, Spartan-IIE

Macro

Spartan-3

No

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

D[7:0]

RAM16X8D

SPO[7:0]

WE
WCLK

DPO[7:0]

A0
A1
A2
A3
DPRA0
DPRA1
DPRA2
DPRA3

X9781

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM16X8D is a 16-word by 8-bit static dual port random access memory with
synchronous write capability. The device has two separate address ports: the read
address (DPRA3 DPRA0) and the write address (A3 A0). These two address ports
are completely asynchronous. The read address controls the location of data driven
out of the output pin (DPO7 DPO0), and the write address controls the destination
of a valid write transaction.
When the write enable (WE) is Low, transitions on the write clock (WCLK) are
ignored and data stored in the RAM is not affected. When WE is High, any positive
transition on WCLK loads the data on the data input (D7 D0) into the word selected
by the 4-bit write address (A3 A0). For predictable performance, write address and
data inputs must be stable before a Low-to-High WCLK transition. This RAM block
assumes an active-High WCLK. However, WCLK can be active-High or active-Low.
Any inverter placed on the WCLK input net is absorbed into the block.
The initial contents of RAM16X8D cannot be specified directly. See Specifying Initial
Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

D7-D0

SP7-SPO0

DPO7-DPO0

0 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (write)

D7-D0

D7-D0

data_d

1 (read)

data_a

data_d

data_a = word addressed by bits A3-A0

data_d = word addressed by bits DPRA3-DPRA0

The SPO output reflects the data in the memory cell addressed by A3 A0. The DPO
output reflects the data in the memory cell addressed by DPRA3 DPRA0.
The write process is not affected by the address on the read address port.

Libraries Guide
ISE 6.3i

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945

RAM16X8D

Usage
For HDL, this design element must be inferred. For information on how to infer RAM,
see the XST User Guide.

946

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

RAM16X8S

RAM16X8S
16-Deep by 8-Wide Static Synchronous RAM
Architectures Supported
RAM16X8S
Spartan-II, Spartan-IIE

Macro

Spartan-3

No

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

D[7:0]

RAM16X8S

O[7:0]

WE
WCLK
A0
A1
A2
A3
X9782

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM16X8S is a 16-word by 8-bit static random access memory with synchronous

write capability. When the write enable (WE) is Low, transitions on the write clock
(WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
any positive transition on WCLK loads the data on data inputs (D7 D0) into the
word selected by the 4-bit address (A3 A0). For predictable performance, address
and data inputs must be stable before a Low-to-High WCLK transition. This RAM
block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pins (O7 O0) is the data that is stored in the
RAM at the location defined by the values on the address pins.
Except for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the initial contents of
RAM16X8S cannot be specified directly. See Specifying Initial Contents of a RAM in
the RAM16X1D section.
For Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, you can use INIT_00
through INIT_07 to specify the initial contents of RAM16X8S as described in the
Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X
Wide RAM section in the RAM16X2S section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

D7-D0

O7-O0

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

D7-D0

D7-D0

1 (read)

Data

Data = word addressed by bits A3 A0

Libraries Guide
ISE 6.3i

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947

RAM16X8S

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template

-- RAM16X8S: 16 x 8 posedge write distributed
-Virtex-II/II-Pro
-- Xilinx HDL Language Template version 6.1i

=> LUT RAM

RAM16X8S_inst : RAM16X8S
-- Edit the following generic to change the inital contents
-- of the RAM.
generic map (
INIT_00 => X"0000", -- INIT for bit 0 of RAM
INIT_01 => X"0000", -- INIT for bit 1 of RAM
INIT_02 => X"0000", -- INIT for bit 2 of RAM
INIT_03 => X"0000", -- INIT for bit 3 of RAM
INIT_04 => X"0000", -- INIT for bit 4 of RAM
INIT_05 => X"0000", -- INIT for bit 5 of RAM
INIT_06 => X"0000", -- INIT for bit 6 of RAM
INIT_07 => X"0000", -- INIT for bit 7 of RAM")
port map (
O => O,
-- 8-bit RAM data output
A0 => A0,
-- RAM address[0] input
A1 => A1,
-- RAM address[1] input
A2 => A2,
-- RAM address[2] input
A3 => A3,
-- RAM address[3] input
D => D,
-- 8-bit RAM data input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM16X8S_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM16X8S RAM16X8S_inst (
.O(O),
// 8-bit RAM data output
.A0(A0),
// RAM address[0] input
.A1(A1),
// RAM address[1] input
.A2(A2),
// RAM address[2] input
.A3(A3),
// RAM address[3] input
.D(D),
// 8-bit RAM data input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
//
//
//
//

948

Edit the following defparam to change the inital contents of the RAM
to a non-zero value if desired. If the instance name to the RAM is
changed, that change needs to be reflected in the defparam
statements.

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Libraries Guide
ISE 6.3i

RAM16X8S

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAM16X8S_inst.INIT_00
RAM16X8S_inst.INIT_01
RAM16X8S_inst.INIT_02
RAM16X8S_inst.INIT_03
RAM16X8S_inst.INIT_04
RAM16X8S_inst.INIT_05
RAM16X8S_inst.INIT_06
RAM16X8S_inst.INIT_07

=
=
=
=
=
=
=
=

16'h0000;
16'h0000;
16'h0000;
16'h0000;
16'h0000;
16'h0000;
16'h0000;
16'h0000;

//
//
//
//
//
//
//
//

INIT
INIT
INIT
INIT
INIT
INIT
INIT
INIT

for
for
for
for
for
for
for
for

bit
bit
bit
bit
bit
bit
bit
bit

0
1
2
3
4
5
6
7

of
of
of
of
of
of
of
of

RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM

// End of RAM16X8S_inst instantiation

Commonly Used Constraints

BEL, INIT_xx, BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and
XBLKNM

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ISE 6.3i

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949

950

RAM16X8S

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Libraries Guide
ISE 6.3i

RAM32X1D

RAM32X1D
32-Deep by 1-Wide Static Dual Static Port Synchronous RAM
Architectures Supported
RAM32X1D
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE

RAM32x1D

SPO

WCLK
A0

DPO

A1
A2
A3
A4
DPRA0
DPRA1
DPRA2
DPRA3
DPRA4
X9261

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM32X1D is a 32-word by 1-bit static dual port random access memory with
synchronous write capability. The device has two separate address ports: the read
address (DPRA4 DPRA0) and the write address (A4 A0). These two address ports
are completely asynchronous. The read address controls the location of the data
driven out of the output pin (DPO), and the write address controls the destination of a
valid write transaction.
When the write enable (WE) is Low, transitions on the write clock (WCLK) are
ignored and data stored in the RAM is not affected. When WE is High, any positive
transition on WCLK loads the data on the data input (D) into the word selected by the
5-bit write address. For predictable performance, write address and data inputs must
be stable before a Low-to-High WCLK transition. This RAM block assumes an activeHigh WCLK. WCLK can be active-High or active-Low. Any inverter placed on the
WCLK input net is absorbed into the block.
You can initialize RAM32X1D during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

SPO

DPO

0 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (write)

data_d

1 (read)

data_a

data_d

data_a = word addressed by bits A4-A0

data_d = word addressed by bits DPRA4-DPRA0

The SPO output reflects the data in the memory cell addressed by A4 A0. The DPO
output reflects the data in the memory cell addressed by DPRA4 DPRA0.
Note: The write process is not affected by the address on the read address port.

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951

RAM32X1D

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template

-- RAM16X1D: 32 x 1 positive edge write, asynchronous read dual-port
distributed RAM
-Viretx-II/II-Pro
-- Xilinx HDL Language Template version 6.1i
RAM32X1D_inst : RAM32X1D
-- The following generic INIT declaration is only necessary
-- if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT => X"00000000")
port map (
DPO => DPO,
-- Port A 1-bit data output
SPO => SPO,
-- Port B 1-bit data output
A0 => A0,
-- Port A address[0] input bit
A1 => A1,
-- Port A address[1] input bit
A2 => A2,
-- Port A address[2] input bit
A3 => A3,
-- Port A address[3] input bit
A4 => A4,
-- Port A address[4] input bit
D => D,
-- Port A 1-bit data input
DPRA0 => DPRA0, -- Port B address[0] input bit
DPRA1 => DPRA1, -- Port B address[1] input bit
DPRA2 => DPRA2, -- Port B address[2] input bit
DPRA3 => DPRA3, -- Port B address[3] input bit
DPRA4 => DPRA4, -- Port B address[4] input bit
WCLK => WCLK,
-- Port A write clock input
WE => WE
-- Port A write enable input
);
-- End of RAM32X1D_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM32X1D RAM32X1D_inst (
.DPO(DPO),
// Port
.SPO(SPO),
// Port
.A0(A0),
// Port
.A1(A1),
// Port
.A2(A2),
// Port
.A3(A3),
// Port
.A4(A4),
// Port
.D(D),
// Port
.DPRA0(DPRA0), // Port
.DPRA1(DPRA1), // Port
.DPRA2(DPRA2), // Port
.DPRA3(DPRA3), // Port
.DPRA4(DPRA4), // Port

952

A
B
A
A
A
A
A
A
B
B
B
B
B

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1-bit data
1-bit data
address[0]
address[1]
address[2]
address[3]
address[4]
1-bit data
address[0]
address[1]
address[2]
address[3]
address[4]

output
output
input bit
input bit
input bit
input bit
input bit
input
input bit
input bit
input bit
input bit
input bit

Libraries Guide
ISE 6.3i

RAM32X1D

.WCLK(WCLK),
.WE(WE)

// Port A write clock input

// Port A write enable input

);
//
//
//
//

The following defparam INIT declaration is only necessary if you

wish to change the initial contents of the RAM to anything other
than all zero's. If the instance name for the RAM is is changes,
that change needs to be reflected in the defparam statement.

defparam RAM32X1D_inst.INIT = 32'h00000000;

// End of RAM32X1D_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, XBLKNM

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ISE 6.3i

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953

954

RAM32X1D

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Libraries Guide
ISE 6.3i

RAM32X1D_1

RAM32X1D_1
32-Deep by 1-Wide Static Dual Port Synchronous RAM with NegativeEdge Clock
Architectures Supported
RAM32X1D_1
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE RAM32x1D_1
SPO
D
WCLK
A0

DPO

A1
A2
A3

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM32X1D_1 is a 32-word by 1-bit static dual port random access memory with
synchronous write capability and a negative-edge clock. The device has two separate
address ports: the read address (DPRA4 DPRA0) and the write address (A4 A0).
These two address ports are completely asynchronous. The read address controls the
location of the data driven out of the output pin (DPO), and the write address controls
the destination of a valid write transaction.

A4
DPRA0
DPRA1
DPRA2
DPRA3
DPRA4
X9262

When the write enable (WE) is Low, transitions on the write clock (WCLK) are
ignored and data stored in the RAM is not affected. When WE is High, any negative
transition on WCLK loads the data on the data input (D) into the word selected by the
5-bit write address. For predictable performance, write address and data inputs must
be stable before a High-to-Low WCLK transition. This RAM block assumes an activeLow WCLK. WCLK can be active-High or active-Low. Any inverter placed on the
WCLK input net is absorbed into the block.
You can initialize RAM32X1D_1 during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

SPO

DPO

0 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (write)

data_d

1 (read)

data_a

data_d

data_a = word addressed by bits A4-A0

data_d = word addressed by bits DPRA4-DPRA0

The SPO output reflects the data in the memory cell addressed by A4 A0. The DPO
output reflects the data in the memory cell addressed by DPRA4 DPRA0.
Note: The write process is not affected by the address on the read address port.

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955

RAM32X1D_1

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template

-- RAM16X1D_1: 32 x 1 negative edge write, asynchronous read
-- dual-port distributed RAM
-Viretx-II/II-Pro
-- Xilinx HDL Language Template version 6.1i
RAM32X1D_1_inst : RAM32X1D_1
-- The following generic INIT declaration is only necessary
-- if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT => X"00000000")
port map (
DPO => DPO,
-- Port A 1-bit data output
SPO => SPO,
-- Port B 1-bit data output
A0 => A0,
-- Port A address[0] input bit
A1 => A1,
-- Port A address[1] input bit
A2 => A2,
-- Port A address[2] input bit
A3 => A3,
-- Port A address[3] input bit
A4 => A4,
-- Port A address[4] input bit
D => D,
-- Port A 1-bit data input
DPRA0 => DPRA0, -- Port B address[0] input bit
DPRA1 => DPRA1, -- Port B address[1] input bit
DPRA2 => DPRA2, -- Port B address[2] input bit
DPRA3 => DPRA3, -- Port B address[3] input bit
DPRA4 => DPRA4, -- Port B address[4] input bit
WCLK => WCLK,
-- Port A write clock input
WE => WE
-- Port A write enable input
);
-- End of RAM32X1D_1_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM32X1D_1 RAM32X1D_1_inst (
.DPO(DPO),
// Port A 1-bit data
.SPO(SPO),
// Port B 1-bit data
.A0(A0),
// Port A address[0]
.A1(A1),
// Port A address[1]
.A2(A2),
// Port A address[2]
.A3(A3),
// Port A address[3]
.A4(A4),
// Port A address[4]
.D(D),
// Port A 1-bit data
.DPRA0(DPRA0), // Port B address[0]
.DPRA1(DPRA1), // Port B address[1]
.DPRA2(DPRA2), // Port B address[2]
.DPRA3(DPRA3), // Port B address[3]
.DPRA4(DPRA4), // Port B address[4]

956

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output
output
input bit
input bit
input bit
input bit
input bit
input
input bit
input bit
input bit
input bit
input bit

Libraries Guide
ISE 6.3i

RAM32X1D_1

.WCLK(WCLK),
.WE(WE)

// Port A write clock input

// Port A write enable input

);
//
//
//
//

The following defparam INIT declaration is only necessary if you

wish to change the initial contents of the RAM to anything other
than all zero's. If the instance name for the RAM is is changes,
that change needs to be reflected in the defparam statement.

defparam RAM32X1D_1_inst.INIT = 32'h00000000;

// End of RAM32X1D_1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM

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ISE 6.3i

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957

958

RAM32X1D_1

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Libraries Guide
ISE 6.3i

RAM32X1S

RAM32X1S
32-Deep by 1-Wide Static Synchronous RAM
Architectures Supported
RAM32X1S
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE

RAM32X1S

D
WCLK
A0
A1
A2
A3
A4
X4943

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM32X1S is a 32-word by 1-bit static random access memory with synchronous

write capability. When the write enable is Low, transitions on the write clock (WCLK)
are ignored and data stored in the RAM is not affected. When WE is High, any
positive transition on WCLK loads the data on the data input (D) into the word
selected by the 5-bit address (A4 A0). For predictable performance, address and data
inputs must be stable before a Low-to-High WCLK transition. This RAM block
assumes an active-High WCLK. However, WCLK can be active-High or active-Low.
Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at
the location defined by the values on the address pins.
You can initialize RAM32X1S during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

1 (read)

Data

Data = word addressed by bits A4 A0

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

Libraries Guide
ISE 6.3i

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1-800-255-7778

959

RAM32X1S

VHDL Instantiation Template

-- RAM32X1S: 32 x 1 posedge write distributed
-All FPGA
-- Xilinx HDL Language Template version 6.1i

=> LUT RAM

RAM32X1S_inst : RAM32X1S
-- Edit the following generic to change the inital contents
-- of the RAM.
generic map (
INIT => X"00000000")
port map (
O => O,
-- RAM output
A0 => A0,
-- RAM address[0] input
A1 => A1,
-- RAM address[1] input
A2 => A2,
-- RAM address[2] input
A3 => A3,
-- RAM address[3] input
A4 => A4,
-- RAM address[4] input
D => D,
-- RAM data input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM32X1S_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM32X1S RAM32X1S_inst (
.O(O),
// RAM output
.A0(A0),
// RAM address[0] input
.A1(A1),
// RAM address[1] input
.A2(A2),
// RAM address[2] input
.A3(A3),
// RAM address[3] input
.A4(A4),
// RAM address[4] input
.D(D),
// RAM data input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
//
//
//
//

Edit the following defparam to change the inital contents of the RAM
to a non-zero value if desired. If the instance name to the RAM is
changed, that change needs to be reflected in the defparam
statements.
defparam RAM32X1S_inst.INIT = 32'h00000000;

// End of RAM32X1S_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM

960

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Libraries Guide
ISE 6.3i

RAM32X1S_1

RAM32X1S_1
32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
Architectures Supported
RAM32X1S_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE RAM32X1S_1

D
WCLK
A0
A1
A2
A3
A4

X8417

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM32X1S_1 is a 32-word by 1-bit static random access memory with synchronous

write capability. When the write enable is Low, transitions on the write clock (WCLK)
are ignored and data stored in the RAM is not affected. When WE is High, any
negative transition on WCLK loads the data on the data input (D) into the word
selected by the 5-bit address (A4 A0). For predictable performance, address and data
inputs must be stable before a High-to-Low WCLK transition. This RAM block
assumes an active-Low WCLK. However, WCLK can be active-High or active-Low.
Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at
the location defined by the values on the address pins.
You can initialize RAM32X1S_1 during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

1 (read)

Data

Data = word addressed by bits A4 A0

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

Libraries Guide
ISE 6.3i

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1-800-255-7778

961

RAM32X1S_1

VHDL Instantiation Template

-- RAM32X1S_1: 32 x 1 negedge write distributed
-All FPGA
-- Xilinx HDL Language Template version 6.1i

=> LUT RAM

RAM32X1S_1_inst : RAM32X1S_1
-- Edit the following generic to change the inital contents
-- of the RAM.
generic map (
INIT => X"00000000")
port map (
O => O,
-- RAM output
A0 => A0,
-- RAM address[0] input
A1 => A1,
-- RAM address[1] input
A2 => A2,
-- RAM address[2] input
A3 => A3,
-- RAM address[3] input
A4 => A4,
-- RAM address[4] input
D => D,
-- RAM data input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM32X1S_1_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM32X1S_1 RAM32X1S_1_inst (
.O(O),
// RAM output
.A0(A0),
// RAM address[0] input
.A1(A1),
// RAM address[1] input
.A2(A2),
// RAM address[2] input
.A3(A3),
// RAM address[3] input
.A4(A4),
// RAM address[4] input
.D(D),
// RAM data input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
//
//
//
//

Edit the following defparam to change the inital contents of the RAM
to a non-zero value if desired. If the instance name to the RAM is
changed, that change needs to be reflected in the defparam
statements.
defparam RAM32X1S_1_inst.INIT = 32'h00000000;

// End of RAM32X1S_1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM

962

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Libraries Guide
ISE 6.3i

RAM32X2S

RAM32X2S
32-Deep by 2-Wide Static Synchronous RAM
Architectures Supported
RAM32X2S
Spartan-II, Spartan-IIE

Macro

Spartan-3

Primitive

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE

RAM32X2S

D0

O0
O1

D1
WCLK
A0
A1
A2
A3
A4
X4947

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM32X2S is a 32-word by 2-bit static random access memory with synchronous

write capability. When the write enable (WE) is Low, transitions on the write clock
(WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
any positive transition on WCLK loads the data on the data input (D1 D0) into the
word selected by the 5-bit address (A4 A0). For predictable performance, address
and data inputs must be stable before a Low-to-High WCLK transition. This RAM
block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pins (O1 O0) is the data that is stored in the
RAM at the location defined by the values on the address pins.
Except for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the initial contents of
RAM32X2S cannot be specified directly. See Specifying Initial Contents of a RAM in
the RAM16X1D section.
For Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, you can use the INIT_00 and
INIT_01 properties to specify the initial contents of RAM32X2S as described in
Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X
Wide RAM in the RAM16X2S section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

D0-D1

O0-O1

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

D1-D0

D1-D0

1 (read)

Data

Data = word addressed by bits A4 A0

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963

RAM32X2S

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template

-- RAM32X2S: 32 x 2 posedge write distributed
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Language Template version 6.1i

=> LUT RAM

RAM32X2S_inst : RAM32X2S
-- Edit the following generic to change the inital contents
-- of the RAM.
generic map (
INIT_00 => X"00000000", -- INIT for bit 0 of RAM
INIT_01 => X"00000000", -- INIT for bit 1 of RAM")
port map (
O0 => O0,
-- RAM data[0] output
O1 => O1,
-- RAM data[1] output
A0 => A0,
-- RAM address[0] input
A1 => A1,
-- RAM address[1] input
A2 => A2,
-- RAM address[2] input
A3 => A3,
-- RAM address[3] input
A4 => A4,
-- RAM address[4] input
D0 => D0,
-- RAM data[0] input
D1 => D1,
-- RAM data[1] input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM32X2S_inst instantiation

Verilog Instantiation Template

Note that the use of INIT below is for simulation only. For examples of how to include
INIT as an implementation constraint, please refer to the Constraints Guide.
RAM32X2S RAM32X2S_inst (
.O0(O0),
// RAM data[0] output
.O1(O1),
// RAM data[1] output
.A0(A0),
// RAM address[0] input
.A1(A1),
// RAM address[1] input
.A2(A2),
// RAM address[2] input
.A3(A3),
// RAM address[3] input
.A4(A4),
// RAM address[4] input
.D0(D0),
// RAM data[0] input
.D1(D1),
// RAM data[1] input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
//
//
//
//

Edit the following defparam to change the inital contents of the RAM
to a non-zero value if desired. If the instance name to the RAM is
changed, that change needs to be reflected in the defparam
statements.

defparam RAM32X2S_inst.INIT_00 = 32'h00000000; // INIT for bit 0 of RAM

964

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ISE 6.3i

RAM32X2S

defparam RAM32X2S_inst.INIT_01 = 32'h00000000; // INIT for bit 1 of RAM

// End of RAM32X2S_inst instantiation

Commonly Used Constraints

INIT_xx, BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

965

966

RAM32X2S

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

RAM32X4S

RAM32X4S
32-Deep by 4-Wide Static Synchronous RAM
Architectures Supported
RAM32X4S
Spartan-II, Spartan-IIE

Macro

Spartan-3

No

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE

RAM32X4S

O0

D0

O1

D1

O2

D2

O3

D3
WCLK
A0
A1
A2
A3

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM32X4S is a 32-word by 4-bit static random access memory with synchronous

write capability. When the write enable (WE) is Low, transitions on the write clock
(WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
any positive transition on WCLK loads the data on the data inputs (D3 D0) into the
word selected by the 5-bit address (A4 A0). For predictable performance, address
and data inputs must be stable before a Low-to-High WCLK transition. This RAM
block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pins (O3 O0) is the data that is stored in the
RAM at the location defined by the values on the address pins.

A4

X4948

Except for Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the initial contents of
RAM32X4S cannot be specified directly. See Specifying Initial Contents of a RAM in
the RAM16X1D section.
For Virtex-II, Virtex-II Pro, and Virtex-II Pro X, you can use the INIT_00 through
INIT_03 properties to specify the initial contents of RAM32X4S as described in
Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X
Wide RAM in the RAM16X2S section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE

WCLK

D3-D0

O3-O0

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

D3-D0

D3-D0

1 (read)

Data

Data = word addressed by bits A4 A0

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ISE 6.3i

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967

RAM32X4S

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template

-- RAM32X4S: 32 x 4 posedge write distributed
-Virtex-II/II-Pro
-- Xilinx HDL Language Template version 6.1i
RAM32X4S_inst : RAM32X4S
-- Edit the following generic to change the
-- of the RAM.
generic map (
INIT_00 => X"00000000", -- INIT for bit
INIT_01 => X"00000000", -- INIT for bit
INIT_02 => X"00000000", -- INIT for bit
INIT_03 => X"00000000", -- INIT for bit
port map (
O0 => O0,
-- RAM data[0] output
O1 => O1,
-- RAM data[1] output
O2 => O2,
-- RAM data[2] output
O3 => O3,
-- RAM data[3] output
A0 => A0,
-- RAM address[0] input
A1 => A1,
-- RAM address[1] input
A2 => A2,
-- RAM address[2] input
A3 => A3,
-- RAM address[3] input
A4 => A4,
-- RAM address[4] input
D0 => D0,
-- RAM data[0] input
D1 => D1,
-- RAM data[1] input
D2 => D2,
-- RAM data[2] input
D3 => D3,
-- RAM data[3] input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);

=> LUT RAM

inital contents

0
1
2
3

of
of
of
of

RAM
RAM
RAM
RAM")

-- End of RAM32X4S_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM32X4S RAM32X4S_inst
.O0(O0),
// RAM
.O1(O1),
// RAM
.O2(O2),
// RAM
.O3(O3),
// RAM
.A0(A0),
// RAM
.A1(A1),
// RAM
.A2(A2),
// RAM
.A3(A3),
// RAM
.A4(A4),
// RAM
.D0(D0),
// RAM
.D1(D1),
// RAM
.D2(D2),
// RAM

968

(
data[0] output
data[1] output
data[2] output
data[3] output
address[0] input
address[1] input
address[2] input
address[3] input
address[4] input
data[0] input
data[1] input
data[2] input

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Libraries Guide
ISE 6.3i

RAM32X4S

.D3(D3),
// RAM data[3] input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
//
//
//
//

Edit the following defparam to change the inital contents of the RAM
to a non-zero value if desired. If the instance name to the RAM is
changed, that change needs to be reflected in the defparam
statements.

defparam
defparam
defparam
defparam

RAM32X4S_inst.INIT_00
RAM32X4S_inst.INIT_01
RAM32X4S_inst.INIT_02
RAM32X4S_inst.INIT_03

=
=
=
=

32'h00000000;
32'h00000000;
32'h00000000;
32'h00000000;

//
//
//
//

INIT
INIT
INIT
INIT

for
for
for
for

bit
bit
bit
bit

0
1
2
3

of
of
of
of

RAM
RAM
RAM
RAM

// End of RAM32X4S_inst instantiation

Commonly Used Constraints

INIT_xx, BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM

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ISE 6.3i

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969

970

RAM32X4S

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Libraries Guide
ISE 6.3i

RAM32X8S

RAM32X8S
32-Deep by 8-Wide Static Synchronous RAM
Architectures Supported
RAM32X8S
Spartan-II, Spartan-IIE

Macro

Spartan-3

No

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

D[7:0]

RAM32X8S

O[7:0]

WE
WCLK
A0
A1
A2
A3
A4

X9780

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM32X8S is a 32-word by 8-bit static random access memory with synchronous

write capability. When the write enable (WE) is Low, transitions on the write clock
(WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
any positive transition on WCLK loads the data on the data inputs (D7 D0) into the
word selected by the 5-bit address (A4 A0). For predictable performance, address
and data inputs must be stable before a Low-to-High WCLK transition. This RAM
block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pins (O7 O0) is the data that is stored in the
RAM at the location defined by the values on the address pins.
Except for Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the initial contents of
RAM32X8S cannot be specified directly. See Specifying Initial Contents of a RAM in
the RAM16X1D section.
For Virtex-II, Virtex-II Pro, and Virtex-II Pro X, you can use the INIT_00 through
INIT_07 properties to specify the initial contents of RAM32X8S as described in
Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X
Wide RAM in the RAM16X2S section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

D7-D0

O7-O0

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

D7-D0

D7-D0

1 (read)

Data

Data = word addressed by bits A4 A0

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ISE 6.3i

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971

RAM32X8S

O[7:0]

RAM32X1S
D0

WE
O
D
WCLK
A0
A1
A2
A3
A4
O0

RAM32X1S
O0
D4

RAM32X1S
D1

O
WE
D
WCLK
A0
A1
A2
A3
A4
O1

RAM32X1S
O1
D5

RAM32X1S
D2

O
WE
D
WCLK
A0
A1
A2
A3
A4
O2

D3

O5

WE
O
D
WCLK
A0
A1
A2
A3
A4
O5

RAM32X1S
O2
D6

RAM32X1S
O
WE
D
WCLK
A0
A1
A2
A3
A4
O3

O4

O
WE
D
WCLK
A0
A1
A2
A3
A4
O4

O6

O
WE
D
WCLK
A0
A1
A2
A3
A4
O6

RAM32X1S

O3
D7

O7

O
WE
D
WCLK
A0
A1
A2
A3
A4
O7

D[7:0]
WE
WCLK
A0
A1
A2
A3
A4

X6417

RAM32X8S Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template

-- RAM32X8S: 32 x 8 posedge write distributed
-Virtex-II/II-Pro
-- Xilinx HDL Language Template version 6.1i

=> LUT RAM

RAM32X8S_inst : RAM32X8S
-- Edit the following generic to change the inital contents
-- of the RAM.
generic map (
INIT_00 => X"00000000", -- INIT for bit 0 of RAM

972

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Libraries Guide
ISE 6.3i

RAM32X8S

INIT_01 => X"00000000", -- INIT for bit

INIT_02 => X"00000000", -- INIT for bit
INIT_03 => X"00000000", -- INIT for bit
INIT_04 => X"00000000", -- INIT for bit
INIT_05 => X"00000000", -- INIT for bit
INIT_06 => X"00000000", -- INIT for bit
INIT_07 => X"00000000", -- INIT for bit
port map (
O => O,
-- 8-bit RAM data output
A0 => A0,
-- RAM address[0] input
A1 => A1,
-- RAM address[1] input
A2 => A2,
-- RAM address[2] input
A3 => A3,
-- RAM address[3] input
A4 => A4,
-- RAM address[4] input
D => D,
-- 8-bit RAM data input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);

1
2
3
4
5
6
7

of
of
of
of
of
of
of

RAM
RAM
RAM
RAM
RAM
RAM
RAM")

-- End of RAM32X8S_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM32X8S RAM32X8S_inst (
.O(O),
// 8-bit RAM data output
.A0(A0),
// RAM address[0] input
.A1(A1),
// RAM address[1] input
.A2(A2),
// RAM address[2] input
.A3(A3),
// RAM address[3] input
.A4(A4),
// RAM address[4] input
.D(D),
// 8-bit RAM data input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
//
//
//
//

Edit the following defparam to change the inital contents of the RAM
to a non-zero value if desired. If the instance name to the RAM is
changed, that change needs to be reflected in the defparam
statements.

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAM32X8S_inst.INIT_00
RAM32X8S_inst.INIT_01
RAM32X8S_inst.INIT_02
RAM32X8S_inst.INIT_03
RAM32X8S_inst.INIT_04
RAM32X8S_inst.INIT_05
RAM32X8S_inst.INIT_06
RAM32X8S_inst.INIT_07

=
=
=
=
=
=
=
=

32'h00000000;
32'h00000000;
32'h00000000;
32'h00000000;
32'h00000000;
32'h00000000;
32'h00000000;
32'h00000000;

//
//
//
//
//
//
//
//

INIT
INIT
INIT
INIT
INIT
INIT
INIT
INIT

for
for
for
for
for
for
for
for

bit
bit
bit
bit
bit
bit
bit
bit

0
1
2
3
4
5
6
7

of
of
of
of
of
of
of
of

RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM

// End of RAM32X8S_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, INIT_xx, LOC, RLOC, U_SET, and XBLKNM

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

973

974

RAM32X8S

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Libraries Guide
ISE 6.3i

RAM64X1D

RAM64X1D
64-Deep by 1-Wide Dual Port Static Synchronous RAM
Architectures Supported
RAM64X1D
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE

RAM64x1D

SPO

WCLK
A0

DPO

A1
A2
A3

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM64X1D is a 64-word by 1-bit static dual port random access memory with
synchronous write capability. The device has two separate address ports: the read
address (DPRA5 DPRA0) and the write address (A5 A0). These two address ports
are completely asynchronous. The read address controls the location of the data
driven out of the output pin (DPO), and the write address controls the destination of a
valid write transaction.

A4
A5
DPRA0
DPRA1
DPRA2
DPRA3
DPRA4
DPRA5
X9263

When the write enable (WE) is Low, transitions on the write clock (WCLK) are
ignored and data stored in the RAM is not affected. When WE is High, any positive
transition on WCLK loads the data on the data input (D) into the word selected by the
6-bit (A0 - A5) write address. For predictable performance, write address and data
inputs must be stable before a Low-to-High WCLK transition. This RAM block
assumes an active-High WCLK. WCLK can be active-High or active-Low. Any
inverter placed on the WCLK input net is absorbed into the block.
You can initialize RAM64X1D during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

SPO

DPO

0 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (write)

data_d

1 (read)

data_a

data_d

data_a = word addressed by bits A5-A0

data_d = word addressed by bits DPRA5-DPRA0

The SPO output reflects the data in the memory cell addressed by A5 A0. The DPO
output reflects the data in the memory cell addressed by DPRA5 DPRA0.
Note: The write process is not affected by the address on the read address port.

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ISE 6.3i

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975

RAM64X1D

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template

-- RAM64X1D: 64 x 1 positive edge write, asynchronous read
-- dual-port distributed RAM
-Virtex-II/II-Pro
-- Xilinx HDL Language Template version 6.1i
RAM64X1D_inst : RAM64X1D
-- The following generic INIT declaration is only necessary
-- if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT => X"0000000000000000")
port map (
DPO => DPO,
-- Port A 1-bit data output
SPO => SPO,
-- Port B 1-bit data output
A0 => A0,
-- Port A address[0] input bit
A1 => A1,
-- Port A address[1] input bit
A2 => A2,
-- Port A address[2] input bit
A3 => A3,
-- Port A address[3] input bit
A4 => A4,
-- Port A address[4] input bit
A5 => A5,
-- Port A address[5] input bit
D => D,
-- Port A 1-bit data input
DPRA0 => DPRA0, -- Port B address[0] input bit
DPRA1 => DPRA1, -- Port B address[1] input bit
DPRA2 => DPRA2, -- Port B address[2] input bit
DPRA3 => DPRA3, -- Port B address[3] input bit
DPRA4 => DPRA4, -- Port B address[4] input bit
DPRA5 => DPRA5, -- Port B address[5] input bit
WCLK => WCLK,
-- Port A write clock input
WE => WE
-- Port A write enable input
);
-- End of RAM64X1D_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM64X1D RAM64X1D_inst (
.DPO(DPO),
// Port
.SPO(SPO),
// Port
.A0(A0),
// Port
.A1(A1),
// Port
.A2(A2),
// Port
.A3(A3),
// Port
.A4(A4),
// Port
.A5(A5),
// Port
.D(D),
// Port
.DPRA0(DPRA0), // Port
.DPRA1(DPRA1), // Port

976

A
B
A
A
A
A
A
A
A
B
B

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1-bit data
1-bit data
address[0]
address[1]
address[2]
address[3]
address[4]
address[5]
1-bit data
address[0]
address[1]

output
output
input bit
input bit
input bit
input bit
input bit
input bit
input
input bit
input bit

Libraries Guide
ISE 6.3i

RAM64X1D

.DPRA2(DPRA2),
.DPRA3(DPRA3),
.DPRA4(DPRA4),
.DPRA5(DPRA5),
.WCLK(WCLK),
.WE(WE)

//
//
//
//
//
//

Port
Port
Port
Port
Port
Port

B
B
B
B
A
A

address[2] input bit

address[3] input bit
address[4] input bit
address[5] input bit
write clock input
write enable input

);
//
//
//
//

The following defparam INIT declaration is only necessary if you

wish to change the initial contents of the RAM to anything other
than all zero's. If the instance name for the RAM is is changes,
that change needs to be reflected in the defparam statement.

defparam RAM64X1D_inst.INIT = 64'h0000000000000000;

// End of RAM64X1D_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, XBLKNM

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ISE 6.3i

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1-800-255-7778

977

978

RAM64X1D

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Libraries Guide
ISE 6.3i

RAM64X1D_1

RAM64X1D_1
64-Deep by 1-Wide Dual Port Static Synchronous RAM with NegativeEdge Clock
Architectures Supported
RAM64X1D_1
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE RAM64x1D_1
SPO
D
WCLK
A0

DPO

A1
A2
A3
A4
A5
DPRA0
DPRA1
DPRA2
DPRA3
DPRA4
DPRA5
X9264

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM64X1D_1 is a 64-word by 1-bit static dual port random access memory with
synchronous write capability and a negative-edge clock. The device has two separate
address ports: the read address (DPRA5 DPRA0) and the write address (A5 A0).
These two address ports are completely asynchronous. The read address controls the
location of the data driven out of the output pin (DPO), and the write address controls
the destination of a valid write transaction.
When the write enable (WE) is Low, transitions on the write clock (WCLK) are
ignored and data stored in the RAM is not affected. When WE is High, any negative
transition on WCLK loads the data on the data input (D) into the word selected by the
6-bit (A0 - A5) write address. For predictable performance, write address and data
inputs must be stable before a High-to-Low WCLK transition. This RAM block
assumes an active-Low WCLK. WCLK can be active-High or active-Low. Any inverter
placed on the WCLK input net is absorbed into the block.
You can initialize RAM64X1D_1 during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

SPO

DPO

0 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (read)

data_a

data_d

1 (write)

data_d

1 (read)

data_a

data_d

data_a = word addressed by bits A5-A0

data_d = word addressed by bits DPRA5-DPRA0

The SPO output reflects the data in the memory cell addressed by A5 A0. The DPO
output reflects the data in the memory cell addressed by DPRA5 DPRA0.
Note: The write process is not affected by the address on the read address port.

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979

RAM64X1D_1

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template

-- RAM64X1D_1: 64 x 1 negative edge write, asynchronous read
-- dual-port distributed RAM
-Virtex-II/II-Pro
-- Xilinx HDL Language Template version 6.1i
RAM64X1D_1_inst : RAM64X1D_1
-- The following generic INIT declaration is only necessary
-- if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT => X"0000000000000000")
port map (
DPO => DPO,
-- Port A 1-bit data output
SPO => SPO,
-- Port B 1-bit data output
A0 => A0,
-- Port A address[0] input bit
A1 => A1,
-- Port A address[1] input bit
A2 => A2,
-- Port A address[2] input bit
A3 => A3,
-- Port A address[3] input bit
A4 => A4,
-- Port A address[4] input bit
A5 => A5,
-- Port A address[5] input bit
D => D,
-- Port A 1-bit data input
DPRA0 => DPRA0, -- Port B address[0] input bit
DPRA1 => DPRA1, -- Port B address[1] input bit
DPRA2 => DPRA2, -- Port B address[2] input bit
DPRA3 => DPRA3, -- Port B address[3] input bit
DPRA4 => DPRA4, -- Port B address[4] input bit
DPRA5 => DPRA5, -- Port B address[5] input bit
WCLK => WCLK,
-- Port A write clock input
WE => WE
-- Port A write enable input
);
-- End of RAM64X1D_1_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM64X1D_1 RAM64X1D_1_inst (
.DPO(DPO),
// Port A 1-bit data
.SPO(SPO),
// Port B 1-bit data
.A0(A0),
// Port A address[0]
.A1(A1),
// Port A address[1]
.A2(A2),
// Port A address[2]
.A3(A3),
// Port A address[3]
.A4(A4),
// Port A address[4]
.A5(A5),
// Port A address[5]
.D(D),
// Port A 1-bit data
.DPRA0(DPRA0), // Port B address[0]
.DPRA1(DPRA1), // Port B address[1]

980

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output
output
input bit
input bit
input bit
input bit
input bit
input bit
input
input bit
input bit

Libraries Guide
ISE 6.3i

RAM64X1D_1

.DPRA2(DPRA2),
.DPRA3(DPRA3),
.DPRA4(DPRA4),
.DPRA5(DPRA5),
.WCLK(WCLK),
.WE(WE)

//
//
//
//
//
//

Port
Port
Port
Port
Port
Port

B
B
B
B
A
A

address[2] input bit

address[3] input bit
address[4] input bit
address[5] input bit
write clock input
write enable input

);
//
//
//
//

The following defparam INIT declaration is only necessary if you

wish to change the initial contents of the RAM to anything other
than all zero's. If the instance name for the RAM is is changes,
that change needs to be reflected in the defparam statement.

defparam RAM64X1D_1_inst.INIT = 64'h0000000000000000;

// End of RAM64X1D_1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, XBLKNM

Libraries Guide
ISE 6.3i

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1-800-255-7778

981

982

RAM64X1D_1

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

RAM64X1S

RAM64X1S
64-Deep by 1-Wide Static Synchronous RAM
Architectures Supported
RAM64X1S
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE

RAM64x1S

WCLK
A0
A1
A2
A3
A4
A5
X9265

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM64X1S is a 64-word by 1-bit static random access memory with synchronous

write capability. When the write enable is Low, transitions on the write clock (WCLK)
are ignored and data stored in the RAM is not affected. When WE is High, any
positive transition on WCLK loads the data on the data input (D) into the word
selected by the 6-bit address (A5 A0). For predictable performance, address and data
inputs must be stable before a Low-to-High WCLK transition. This RAM block
assumes an active-High WCLK. However, WCLK can be active-High or active-Low.
Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at
the location defined by the values on the address pins.
You can initialize RAM64X1S during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

1 (read)

Data

Data = word addressed by bits A5 A0

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

983

RAM64X1S

VHDL Instantiation Template

-- RAM64X1S: 64 x 1 positive edge write, asynchronous read
-- single-port distributed RAM
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Language Template version 6.1i
RAM64X1S_inst : RAM64X1S
-- The following generic INIT declaration is only necessary
-- if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT => X"0000000000000000")
port map (
O => O,
-- 1-bit data output
A0 => A0,
-- Address[0] input bit
A1 => A1,
-- Address[1] input bit
A2 => A2,
-- Address[2] input bit
A3 => A3,
-- Address[3] input bit
A4 => A4,
-- Address[4] input bit
A5 => A5,
-- Address[5] input bit
D => D,
-- 1-bit data input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM64X1S_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM64X1S RAM64X1S_inst (
.O(O),
// 1-bit data output
.A0(A0),
// Address[0] input bit
.A1(A1),
// Address[1] input bit
.A2(A2),
// Address[2] input bit
.A3(A3),
// Address[3] input bit
.A4(A4),
// Address[4] input bit
.A5(A5),
// Address[5] input bit
.D(D),
// 1-bit data input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
//
//
//
//

The following defparam INIT declaration is only necessary if you

wish to change the initial contents of the RAM to anything other
than all zero's. If the instance name for the RAM is is changes,
that change needs to be reflected in the defparam statement.

defparam RAM64X1S_inst.INIT = 64'h0000000000000000;

// End of RAM64X1S_inst instantiation

984

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Libraries Guide
ISE 6.3i

RAM64X1S

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

985

986

RAM64X1S

www.xilinx.com
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Libraries Guide
ISE 6.3i

RAM64X1S_1

RAM64X1S_1
64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
Architectures Supported
RAM64X1S_1
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE RAM64x1S_1
O
D
WCLK
A0
A1
A2
A3
A4
A5
X9266

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM64X1S_1 is a 64-word by 1-bit static random access memory with synchronous

write capability. When the write enable is Low, transitions on the write clock (WCLK)
are ignored and data stored in the RAM is not affected. When WE is High, any
negative transition on WCLK loads the data on the data input (D) into the word
selected by the 6-bit address (A5 A0). For predictable performance, address and data
inputs must be stable before a High-to-Low WCLK transition. This RAM block
assumes an active-Low WCLK. However, WCLK can be active-High or active-Low.
Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at
the location defined by the values on the address pins.
You can initialize RAM32X1S_1 during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

1 (read)

Data

Data = word addressed by bits A5 A0

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

987

RAM64X1S_1

VHDL Instantiation Template

-- RAM64X1S_1: 64 x 1 negative edge write, asynchronous read
-- single-port distributed RAM
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Language Template version 6.1i
RAM64X1S_1_inst : RAM64X1S_1
-- The following generic INIT declaration is only necessary
-- if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT => X"0000000000000000")
port map (
O => O,
-- 1-bit data output
A0 => A0,
-- Address[0] input bit
A1 => A1,
-- Address[1] input bit
A2 => A2,
-- Address[2] input bit
A3 => A3,
-- Address[3] input bit
A4 => A4,
-- Address[4] input bit
A5 => A5,
-- Address[5] input bit
D => D,
-- 1-bit data input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM64X1S_1_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.

RAM64X1S_1 RAM64X1S_1_inst (
.O(O),
// 1-bit data output
.A0(A0),
// Address[0] input bit
.A1(A1),
// Address[1] input bit
.A2(A2),
// Address[2] input bit
.A3(A3),
// Address[3] input bit
.A4(A4),
// Address[4] input bit
.A5(A5),
// Address[5] input bit
.D(D),
// 1-bit data input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
//
//
//
//

The following defparam INIT declaration is only necessary if you

wish to change the initial contents of the RAM to anything other
than all zero's. If the instance name for the RAM is is changes,
that change needs to be reflected in the defparam statement.

defparam RAM64X1S_1_inst.INIT = 64'h0000000000000000;

// End of RAM64X1S_1_inst instantiation

988

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Libraries Guide
ISE 6.3i

RAM64X1S_1

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM

Libraries Guide
ISE 6.3i

www.xilinx.com
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989

990

RAM64X1S_1

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Libraries Guide
ISE 6.3i

RAM64X2S

RAM64X2S
64-Deep by 2-Wide Static Synchronous RAM
Architectures Supported
RAM64X2S
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE

RAM64x2S

D0

O0

D1

O1

WCLK
A0
A1
A2
A3
A4
A5
X9410

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM64X2S is a 64-word by 2-bit static random access memory with synchronous

write capability. When the write enable (WE) is Low, transitions on the write clock
(WCLK) are ignored and data stored in the RAM is not affected. When WE is High,
any positive transition on WCLK loads the data on the data input (D1 D0) into the
word selected by the 6-bit address (A5 A0). For predictable performance, address
and data inputs must be stable before a Low-to-High WCLK transition. This RAM
block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pins (O1 O0) is the data that is stored in the
RAM at the location defined by the values on the address pins.
You can use the INIT_00 and INIT_01 properties to specify the initial contents of
RAM64X2S as described in Specifying Initial Contents of a Spartan-3, Virtex-II,
Virtex-II Pro, and Virtex-II Pro X Wide RAM in the RAM16X2S section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

D0-D1

O0-O1

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

D1-D0

D1-D0

1 (read)

Data

Data = word addressed by bits A5 A0

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

991

RAM64X2S

VHDL Instantiation Template

-- RAM64X1S: 64 x 2 positive edge write, asynchronous read
-- single-port distributed RAM
-Virtex-II/II-Pro
-- Xilinx HDL Language Template version 6.1i
RAM64X2S_inst : RAM64X2S
-- The following generic INIT declaration is only necessary
-- if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT => X"0000000000000000")
port map (
O0 => O0,
-- Data[0] output
O1 => O1,
-- Data[1] output bit
A0 => A0,
-- Address[0] input bit
A1 => A1,
-- Address[1] input bit
A2 => A2,
-- Address[2] input bit
A3 => A3,
-- Address[3] input bit
A4 => A4,
-- Address[4] input bit
A5 => A5,
-- Address[5] input bit
D0 => D0,
-- Data[0] input
D1 => D1,
-- Data[1] input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM64X2S_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAM64X2S RAM64X2S_inst (
.O0(O0),
// Data[0] output
.O1(O1),
// Data[1] output bit
.A0(A0),
// Address[0] input bit
.A1(A1),
// Address[1] input bit
.A2(A2),
// Address[2] input bit
.A3(A3),
// Address[3] input bit
.A4(A4),
// Address[4] input bit
.A5(A5),
// Address[5] input bit
.D0(D0),
// Data[0] input
.D1(D1),
// Data[1] input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
//
//
//
//

The following defparam INIT declaration is only necessary if you

wish to change the initial contents of the RAM to anything other
than all zero's. If the instance name for the RAM is is changes,
that change needs to be reflected in the defparam statement.

defparam RAM64X2S_inst.INIT = 64'h0000000000000000;

// End of RAM64X2S_inst instantiation

992

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Libraries Guide
ISE 6.3i

RAM64X2S

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM

Libraries Guide
ISE 6.3i

www.xilinx.com
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993

994

RAM64X2S

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Libraries Guide
ISE 6.3i

RAM128X1S

RAM128X1S
128-Deep by 1-Wide Static Synchronous RAM
Architectures Supported
RAM128X1S
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE

RAM128x1S

WCLK
A0
A1
A2
A3
A4
A5
A6
X9267

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM128X1S is a 128-word by 1-bit static random access memory with synchronous

write capability. When the write enable is Low, transitions on the write clock (WCLK)
are ignored and data stored in the RAM is not affected. When WE is High, any
positive transition on WCLK loads the data on the data input (D) into the word
selected by the 7-bit address (A6 A0). For predictable performance, address and data
inputs must be stable before a Low-to-High WCLK transition. This RAM block
assumes an active-High WCLK. However, WCLK can be active-High or active-Low.
Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at
the location defined by the values on the address pins.
You can initialize RAM128X1S during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

1 (read)

Data

Data = word addressed by bits A6 A0

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

995

RAM128X1S

VHDL Instantiation Template

-- RAM128X1S: 128 x 1 positive edge write, asynchronous read
-- single-port distributed RAM
-Virtex-II/II-Pro
-- Xilinx HDL Language Template version 6.1i
RAM128X1S_inst : RAM128X1S
-- The following generic INIT declaration is only necessary
-- if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT => X"00000000000000000000000000000000")
port map (
O => O,
-- 1-bit data output
A0 => A0,
-- Address[0] input bit
A1 => A1,
-- Address[1] input bit
A2 => A2,
-- Address[2] input bit
A3 => A3,
-- Address[3] input bit
A4 => A4,
-- Address[4] input bit
A5 => A5,
-- Address[5] input bit
A6 => A6,
-- Address[6] input bit
D => D,
-- 1-bit data input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM128X1S_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.

// RAM128X1S: 128 x 1 positive edge write, asynchronous read

// single-port
//
distributed RAM. Virtex-II/II-Pro
// Xilinx HDL Libraries Guide version 7.1i
RAM128X1S RAM128X1S_inst (
.O(O),
// 1-bit data output
.A0(A0),
// Address[0] input bit
.A1(A1),
// Address[1] input bit
.A2(A2),
// Address[2] input bit
.A3(A3),
// Address[3] input bit
.A4(A4),
// Address[4] input bit
.A5(A5),
// Address[5] input bit
.A6(A6),
// Address[6] input bit
.D(D),
// 1-bit data input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
// The following defparam INIT declaration is only necessary if you
// wish to change the initial contents of the RAM to anything other
// than all zero's. If the instance name for the RAM is is changes,

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ISE 6.3i

RAM128X1S

// that change needs to be reflected in the defparam statement.

defparam RAM128X1S_inst.INIT = 128'h00000000000000000000000000000000;
// End of RAM128X1S_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

997

998

RAM128X1S

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Libraries Guide
ISE 6.3i

RAM128X1S_1

RAM128X1S_1
128-Deep by 1-Wide Static Synchronous RAM with Negative-Edge
Clock
Architectures Supported
RAM128X1S_1
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

WE RAM128x1S_1
O
D
WCLK
A0
A1
A2
A3
A4
A5

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAM128X1S_1 is a 128-word by 1-bit static random access memory with synchronous

write capability. When the write enable is Low, transitions on the write clock (WCLK)
are ignored and data stored in the RAM is not affected. When WE is High, any
negative transition on WCLK loads the data on the data input (D) into the word
selected by the 7-bit address (A6 A0). For predictable performance, address and data
inputs must be stable before a High-to-Low WCLK transition. This RAM block
assumes an active-Low WCLK. However, WCLK can be active-High or active-Low.
Any inverter placed on the WCLK input net is absorbed into the block.

A6
X9268

The signal output on the data output pin (O) is the data that is stored in the RAM at
the location defined by the values on the address pins.
You can initialize RAM128X1S_1 during configuration using the INIT attribute. See
Specifying Initial Contents of a RAM in the RAM16X1D section.
Mode selection is shown in the following truth table.
Inputs

Outputs

WE (mode)

WCLK

0 (read)

Data

1 (read)

Data

1 (read)

Data

1 (write)

1 (read)

Data

Data = word addressed by bits A6 A0

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

999

RAM128X1S_1

VHDL Instantiation Template

-- RAM128X1S_1: 128 x 1 negative edge write, asynchronous
-- read single-port distributed RAM
-Virtex-II/II-Pro
-- Xilinx HDL Language Template version 6.1i
RAM128X1S_1_inst : RAM128X1S_1
-- The following generic INIT declaration is only necessary
-- if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT => X"00000000000000000000000000000000")
port map (
O => O,
-- 1-bit data output
A0 => A0,
-- Address[0] input bit
A1 => A1,
-- Address[1] input bit
A2 => A2,
-- Address[2] input bit
A3 => A3,
-- Address[3] input bit
A4 => A4,
-- Address[4] input bit
A5 => A5,
-- Address[5] input bit
A6 => A6,
-- Address[6] input bit
D => D,
-- 1-bit data input
WCLK => WCLK, -- Write clock input
WE => WE
-- Write enable input
);
-- End of RAM128X1S_1_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.

// RAM128X1S_1: 128 x 1 negative edge write, asynch. read

//
single-port distributed RAM.
Virtex-II/II-Pro
// Xilinx HDL Libraries Guide version 7.1i
RAM128X1S_1 RAM128X1S_1_inst (
.O(O),
// 1-bit data output
.A0(A0),
// Address[0] input bit
.A1(A1),
// Address[1] input bit
.A2(A2),
// Address[2] input bit
.A3(A3),
// Address[3] input bit
.A4(A4),
// Address[4] input bit
.A5(A5),
// Address[5] input bit
.A6(A6),
// Address[6] input bit
.D(D),
// 1-bit data input
.WCLK(WCLK), // Write clock input
.WE(WE)
// Write enable input
);
//
//
//
//

1000

The following defparam INIT declaration is only necessary if you

wish to change the initial contents of the RAM to anything other
than all zero's. If the instance name for the RAM is is changes,
that change needs to be reflected in the defparam statement.

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Libraries Guide
ISE 6.3i

RAM128X1S_1

defparam RAM128X1S_1_inst.INIT =
128'h00000000000000000000000000000000;
// End of RAM128X1S_1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM

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ISE 6.3i

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1001

1002

RAM128X1S_1

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Libraries Guide
ISE 6.3i

RAMB4_Sn

RAMB4_Sn
4096-Bit Single-Port Synchronous Block RAM with Port Width (n)
Configured to 1, 2, 4, 8, or 16 Bits
RAMB4_Sn
Spartan-II, Spartan-IIE

Primitive

Spartan-3

No

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

WE

RAMB4_S1

DO[0]

EN
RST
CLK
ADDR[11:0]
DI[0]

No

CoolRunner XPLA3

No

CoolRunner-II

No

RAMB4_S1, RAMB4_S2, RAMB4_S4, RAMB4_S8, and RAMB4_S16 are dedicated

random access memory blocks with synchronous write capability. They provide the
capability for fast, discrete, large blocks of RAM in each Virtex, Virtex-E, Spartan-II,
and Spartan-IIE device.The RAMB4_Sn cell configurations are listed in the following
table.

X8416

Component
WE

RAMB4_S2 DO[1:0]

EN
RST
CLK
ADDR[10:0]
DI[1:0]

X8415

WE

RAMB4_S4 DO[3:0]

EN
RST
CLK
ADDR[9:0]
DI[3:0]

X8414

Depth

Width

Address Bus

Data Bus

RAMB4_S1

4096

(11:0)

(0:0)

RAMB4_S2

2048

(10:0)

(1:0)

RAMB4_S4

1024

(9:0)

(3:0)

RAMB4_S8

512

(8:0)

(7:0)

RAMB4_S16

256

16

(7:0)

(15:0)

The enable (EN) pin controls read, write, and reset. When EN is Low, no data is
written and the output (DO) retains the last state. When EN is High and reset (RST) is
High, DO is cleared during the Low-to-High clock (CLK) transition; if write enable
(WE) is High, the memory contents reflect the data at DI. When EN is High and WE is
Low, the data stored in the RAM address (ADDR) is read during the Low-to-High
clock transition. When EN and WE are High, the data on the data input (DI) is loaded
into the word selected by the write address (ADDR) during the Low-to-High clock
transition and the data output (DO) reflects the selected (addressed) word.
The above description assumes an active High EN, WE, RST, and CLK. However, the
active level can be changed by placing an inverter on the port. Any inverter placed on
a RAMB4 port is absorbed into the block and does not use a CLB resource.
RAMB4_Sn's may be initialized during configuration. See Specifying Initial
Contents of a Block RAM below.
Block RAM output registers are asynchronously cleared, output Low, when power is
applied. The initial contents of the block RAM are not altered.
Virtex, Virtex-E, Spartan-II, and Spartan-IIE simulate power-on when global set/reset
(GSR) is active.

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ISE 6.3i

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1003

RAMB4_Sn

GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Mode selection is shown in the following truth table.

Inputs

Outputs

EN

RST

WE

CLK

ADDR

DI

DO

RAM Contents

No Chg

No Chg

No Chg

addr

data

RAM(addr) =>data

addr

RAM(addr)

No Chg

addr

data

data

RAM(addr) =>data

addr=RAM address
RAM(addr)=RAM contents at address ADDR
data=RAM input data

Specifying Initial Contents of a Block RAM

You can use the INIT_xx attributes to specify an initial value during device
configuration. The initialization of each RAMB4_Sn is set by 16 initialization
attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. See the
INIT_xx section of the Constraints Guide for more information on these attributes.
If any INIT_0x attribute is not specified, it is configured as zeros. Partial initialization
strings are padded with zeros to the left.

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template for RAMB4_Sn

-- RAMB4_S1: Virtex/E, Spartan-II/IIE 4k x 1 Single-Port RAM
-- Xilinx HDL Language Template version 6.1i
RAMB4_S1_inst : RAMB4_S1
-- The following generic INIT_xx declarations are only necessary
-- if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT_00
INIT_01
INIT_02
INIT_03
INIT_04
INIT_05
INIT_06
INIT_07
INIT_08
INIT_09
INIT_0A

1004

=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>

X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",

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Libraries Guide
ISE 6.3i

RAMB4_Sn

INIT_0B
INIT_0C
INIT_0D
INIT_0E
INIT_0F

=>
=>
=>
=>
=>

X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000")

port map (
DO => DO,
ADDR => ADDR,
CLK => CLK,
DI => DI,
EN => EN,
RST => RST,
WE => WE
);

--------

1-bit data output

12-bit address input
Clock input
1-bit data input
RAM enable input
Synchronous reset input
RAM write enable input

-- End of RAMB4_S1_inst instantiation

Verilog Instantiation Template for RAMB4_Sn

-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
ALL RAMB4_Sn TEMPLATES ARE LISTED BELOW. FIND AND CUT THE SPECFIC
CONFIGURATION YOU NEED FOR YOUR DESIGN:
// RAMB4_S1: Virtex/E, Spartan-II/IIE 4k x 1 Single-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S1 RAMB4_S1_inst (
.DO(DO),
// 1-bit data output
.ADDR(ADDR), // 12-bit address input
.CLK(CLK),
// Clock input
.DI(DI),
// 1-bit data input
.EN(EN),
// RAM enable input
.RST(RST),
// Synchronous reset input
.WE(WE)
// RAM write enable input
);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S1_inst.INIT_00
RAMB4_S1_inst.INIT_01
RAMB4_S1_inst.INIT_02
RAMB4_S1_inst.INIT_03
RAMB4_S1_inst.INIT_04
RAMB4_S1_inst.INIT_05
RAMB4_S1_inst.INIT_06
RAMB4_S1_inst.INIT_07
RAMB4_S1_inst.INIT_08
RAMB4_S1_inst.INIT_09
RAMB4_S1_inst.INIT_0A
RAMB4_S1_inst.INIT_0B
RAMB4_S1_inst.INIT_0C
RAMB4_S1_inst.INIT_0D
RAMB4_S1_inst.INIT_0E
RAMB4_S1_inst.INIT_0F

Libraries Guide
ISE 6.3i

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

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1-800-255-7778

1005

RAMB4_Sn

// End of RAMB4_S1_inst instantiation

// RAMB4_S2: Virtex/E, Spartan-II/IIE 2k x 2 Single-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S2 RAMB4_S2_inst (
.DO(DO),
// 2-bit data output
.ADDR(ADDR), // 11-bit address input
.CLK(CLK),
// Clock input
.DI(DI),
// 2-bit data input
.EN(EN),
// RAM enable input
.RST(RST),
// Synchronous reset input
.WE(WE)
// RAM write enable input
);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S2_inst.INIT_00
RAMB4_S2_inst.INIT_01
RAMB4_S2_inst.INIT_02
RAMB4_S2_inst.INIT_03
RAMB4_S2_inst.INIT_04
RAMB4_S2_inst.INIT_05
RAMB4_S2_inst.INIT_06
RAMB4_S2_inst.INIT_07
RAMB4_S2_inst.INIT_08
RAMB4_S2_inst.INIT_09
RAMB4_S2_inst.INIT_0A
RAMB4_S2_inst.INIT_0B
RAMB4_S2_inst.INIT_0C
RAMB4_S2_inst.INIT_0D
RAMB4_S2_inst.INIT_0E
RAMB4_S2_inst.INIT_0F

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S2_inst instantiation

// RAMB4_S4: Virtex/E, Spartan-II/IIE 1k x 4 Single-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S4 RAMB4_S4_inst (
.DO(DO),
// 4-bit data output
.ADDR(ADDR), // 10-bit address input
.CLK(CLK),
// Clock input
.DI(DI),
// 4-bit data input
.EN(EN),
// RAM enable input
.RST(RST),
// Synchronous reset input
.WE(WE)
// RAM write enable input
);
//
//
//
//

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

defparam RAMB4_S4_inst.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4_S4_inst.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S4_inst.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S4_inst.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1006

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Libraries Guide
ISE 6.3i

RAMB4_Sn

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB4_S4_inst.INIT_04
RAMB4_S4_inst.INIT_05
RAMB4_S4_inst.INIT_06
RAMB4_S4_inst.INIT_07
RAMB4_S4_inst.INIT_08
RAMB4_S4_inst.INIT_09
RAMB4_S4_inst.INIT_0A
RAMB4_S4_inst.INIT_0B
RAMB4_S4_inst.INIT_0C
RAMB4_S4_inst.INIT_0D
RAMB4_S4_inst.INIT_0E
RAMB4_S4_inst.INIT_0F

=
=
=
=
=
=
=
=
=
=
=
=

256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB4_S8_inst.INIT_00
RAMB4_S8_inst.INIT_01
RAMB4_S8_inst.INIT_02
RAMB4_S8_inst.INIT_03
RAMB4_S8_inst.INIT_04
RAMB4_S8_inst.INIT_05
RAMB4_S8_inst.INIT_06
RAMB4_S8_inst.INIT_07
RAMB4_S8_inst.INIT_08
RAMB4_S8_inst.INIT_09
RAMB4_S8_inst.INIT_0A
RAMB4_S8_inst.INIT_0B
RAMB4_S8_inst.INIT_0C
RAMB4_S8_inst.INIT_0D
RAMB4_S8_inst.INIT_0E
RAMB4_S8_inst.INIT_0F

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S8_inst instantiation

// RAMB4_S16: Virtex/E, Spartan-II/IIE 256 x 16 Single-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S16 RAMB4_S16_inst (
.DO(DO),
// 16-bit data output
.ADDR(ADDR), // 8-bit address input
.CLK(CLK),
// Clock input
.DI(DI),
// 16-bit data input
.EN(EN),
// RAM enable input
.RST(RST),
// Synchronous reset input
.WE(WE)
// RAM write enable input
);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S16_inst.INIT_00
RAMB4_S16_inst.INIT_01
RAMB4_S16_inst.INIT_02
RAMB4_S16_inst.INIT_03
RAMB4_S16_inst.INIT_04
RAMB4_S16_inst.INIT_05
RAMB4_S16_inst.INIT_06
RAMB4_S16_inst.INIT_07
RAMB4_S16_inst.INIT_08
RAMB4_S16_inst.INIT_09
RAMB4_S16_inst.INIT_0A

Libraries Guide
ISE 6.3i

=
=
=
=
=
=
=
=
=
=
=

256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

www.xilinx.com
1-800-255-7778

1007

RAMB4_Sn

defparam RAMB4_S16_inst.INIT_0B =

Commonly Used Constraints

INIT_xx

1008

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Libraries Guide
ISE 6.3i

RAMB4_Sm_Sn

RAMB4_Sm_Sn
4096-Bit Dual-Port Synchronous Block RAM with Port Width (m or n)
Configured to 1, 2, 4, 8, or 16 Bits
Architectures Supported
RAMB4_Sm_Sn
Spartan-II, Spartan-IIE

Primitive

Spartan-3

No

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

Libraries Guide
ISE 6.3i

No

CoolRunner XPLA3

No

CoolRunner-II

No

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1-800-255-7778

1009

WEA

RAMB4_Sm_Sn

WEA

RAMB4_S1_S1

ENA

WEA

RAMB4_S1_S2

RSTA

RSTA

DOA[0]

WEA

RAMB4_S1_S4

ENA

ENA

RSTA

DOA[0]

WEA

RAMB4_S1_S8

RSTA

DOA[0]

RSTA

DOA[0]

DOA[0]

CLKA

CLKA

CLKA

CLKA

CLKA

ADDRA[11:0]

ADDRA[11:0]

ADDRA[11:0]

ADDRA[11:0]

ADDRA[11:0]

DIA[0]

DIA[0]

DIA[0]

DIA[0]

DIA[0]

WEB

WEB

WEB

WEB

WEB

ENB

ENB

ENB

ENB

RSTB

RSTB

DOB[0]

RSTB

DOB[1:0]

ENB

RSTB

DOB[3:0]

RSTB

DOB[7:0]

CLKB

CLKB

CLKB

CLKB

CLKB

ADDRB[11:0]

ADDRB[10:0]

ADDRB[9:0]

ADDRB[8:0]

ADDRB[7:0]

DIB[0]

DIB[1:0]

DIB[3:0]

DIB[7:0]

DIB[15:0]

X8359

WEA

X8390

WEA

RAMB4_S2_S2

ENA

X8391

WEA

RAMB4_S2_S4

ENA

RSTA

DOA[1:0]

WEA

RAMB4_S2_S8

X8393

WEA

RAMB4_S2_S16

DOA[1:0]

RSTA

RSTA

DOA[1:0]

CLKA

CLKA

CLKA

CLKA

CLKA

ADDRA[10:0]

ADDRA[10:0]

ADDRA[10:0]

ADDRA[10:0]

ADDRA[9:0]

DIA[1:0]

DIA[1:0]

DIA[1:0]

DIA[1:0]

DIA[3:0]

WEB

WEB

WEB

WEB

WEB

ENB

ENB

ENB

ENB

RSTB

DOB[1:0]

RSTB

RSTB

DOB[3:0]

DOB[7:0]

DOB[15:0]

RSTB

CLKB

CLKB

CLKB

CLKB

CLKB

ADDRB[9:0]

ADDRB[8:0]

ADDRB[7:0]

ADDRB[9:0]

DIB[3:0]

DIB[7:0]

X8394

WEA

WEA

RAMB4_S4_S8

ENA
RSTA

X8396

WEA

RAMB4_S4_S16

ENA
DOA[3:0]

RSTA

WEA

RAMB4_S8_S16

ENA

RSTA

DOA[3:0]

DOA[7:0]

X8398

X8397

WEA

RAMB4_S8_S8

ENA

RSTA

RSTA
DOA[7:0]

DOA[15:0]

CLKA

CLKA

CLKA

CLKA

ADDRA[9:0]

ADDRA[9:0]

ADDRA[8:0]

ADDRA[8:0]

ADDRA[7:0]

DIA[3:0]

DIA[3:0]

DIA[7:0]

DIA[7:0]

DIA[15:0]

WEB

WEB

WEB

WEB

WEB

ENB

ENB

ENB

ENB

DOB[7:0]

RSTB

RSTB

DOB[7:0]

DOB[15:0]

RSTB

ENB
DOB[15:0]

RSTB

CLKB

CLKB

CLKB

CLKB

CLKB

ADDRB[8:0]

ADDRB[7:0]

ADDRB[8:0]

ADDRB[7:0]

ADDRB[7:0]

DIB[7:0]

DIB[15:0]

DIB[7:0]

DIB[15:0]

DIB[15:0]

X8399

X8400

X8401

RAMB4_S16_S16

ENA

CLKA

RSTB

DOB[3:0]

DIB[3:0]

DIB[15:0]

X8395

DOA[3:0]

ENB

RSTB

ADDRB[10:0]
DIB[1:0]

RAMB4_S4_S4

ENA

ENA

RSTA

DOA[1:0]

DOB[15:0]

X8392

ENA

RSTA

RAMB4_S1_S16

ENA

ENA

X8402

DOB[15:0]

X8403

X8727

RAMB4_Sm_Sn Representations

1010

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Libraries Guide
ISE 6.3i

RAMB4_Sm_Sn

The RAMB4_Sm_Sn components listed in the following table are 4096-bit dual-ported
dedicated random access memory blocks with synchronous write capability. Each
port is independent of the other while accessing the same set of 4096 memory cells.
Each port is independently configured to a specific data width.
Port A
Depth

Port A
Width

Port A
ADDR

Port A
DI

Port B
Depth

Port B
Width

Port B
ADDR

Port B
DI

RAMB4_S1_S1

4096

(11:0)

(0:0)

4096

(11:0)

(0:0)

RAMB4_S1_S2

4096

(11:0)

(0:0)

2048

(10:0)

(1:0)

RAMB4_S1_S4

4096

(11:0)

(0:0)

1024

(9:0)

(3:0)

RAMB4_S1_S8

4096

(11:0)

(0:0)

512

(8:0)

(7:0)

RAMB4_S1_S16

4096

(11:0)

(0:0)

256

16

(7:0)

(15:0)

RAMB4_S2_S2

2048

(10:0)

(1:0)

2048

(10:0)

(1:0)

RAMB4_S2_S4

2048

(10:0)

(1:0)

1024

(9:0)

(3:0)

RAMB4_S2_S8

2048

(10:0)

(1:0)

512

(8:0)

(7:0)

RAMB4_S2_S16

2048

(10:0)

(1:0)

256

16

(7:0)

(15:0)

RAMB4_S4_S4

1024

(9:0)

(3:0)

1024

(9:0)

(3:0)

RAMB4_S4_S8

1024

(9:0)

(3:0)

512

(8:0)

(7:0)

RAMB4_S4_S16

1024

(9:0)

(3:0)

256

16

(7:0)

(15:0)

RAMB4_S8_S8

512

(8:0)

(7:0)

512

(8:0)

(7:0)

Component

RAMB4_S8_S16

512

(8:0)

(7:0)

256

16

(7:0)

(15:0)

RAMB4_S16_S16

256

16

(7:0)

(15:0)

256

16

(7:0)

(15:0)

ADDR=address bus for the port

DI=data input bus for the port

Each port is fully synchronous with independent clock pins. All port A input pins
have setup time referenced to the CLKA pin and its data output bus DOA has a clockto-out time referenced to the CLKA. All port B input pins have setup time referenced
to the CLKB pin and its data output bus DOB has a clock-to-out time referenced to the
CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no
data is written and the output (DOA) retains the last state. When ENA is High and
reset (RSTA) is High, DOA is cleared during the Low-to-High clock (CLKA)
transition; if write enable (WEA) is High, the memory contents reflect the data at DIA.
When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is
read during the Low-to-High clock transition. When ENA and WEA are High, the
data on the data input (DIA) is loaded into the word selected by the write address
(ADDRA) during the Low-to-High clock transition and the data output (DOA)
reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no
data is written and the output (DOB) retains the last state. When ENB is High and
reset (RSTB) is High, DOB is cleared during the Low-to-High clock (CLKB) transition;
if write enable (WEB) is High, the memory contents reflect the data at DIB. When ENB
is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during
the Low-to-High clock transition. When ENB and WEB are High, the data on the data
input (DIB) is loaded into the word selected by the write address (ADDRB) during the
Low-to-High clock transition and the data output (DOB) reflects the selected
(addressed) word.

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1011

RAMB4_Sm_Sn

The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA,
ENB, WEB, RSTB, and CLKB). However, the active level can be changed by placing an
inverter on the port. Any inverter placed on a RAMB4 port is absorbed into the block
and does not use a CLB resource.
RAMB_Sm_Sn's may be initialized during configuration. See the following truth
table.
Block RAM output registers are asynchronously cleared, output Low, when power is
applied. The initial contents of the block RAM are not altered.
Virtex, Virtex-E, Spartan-II, and Spartan-IIE simulate power-on when global set/reset
(GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Mode selection is shown in the following truth table.
Inputs

Outputs

EN(A/B)

RST(A/B)

WE(A/B)

CLK(A/B)

ADDR(A/B)

DI(A/B)

DO(A/B)

RAM Contents

No Chg

No Chg

No Chg

addr

data

RAM(addr) =>data

addr

RAM(addr)

No Chg

addr

data

data

RAM(addr) =>data

addr=RAM address of port A/B

RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB

Address Mapping
Each port accesses the same set of 4096 memory cells using an addressing scheme that
is dependent on the width of the port. The physical RAM location that is addressed
for a particular width is determined from the following formula.
Start=((ADDR port+1)*(Widthport)) -1
End=(ADDRport)*(Widthport)

The following table shows address mapping for each port width.
Port Address Mapping
Port Width

1012

Port Addresses

4096

<-----

2048

<-----

1024

<-----

512

<-----

16

256

<-----

15

14

13

07

12

11

06

10

09

05

03

08

07

04

06

05

03

02

04

03

02

01

01

01

01

02

00
00

00
00

00

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ISE 6.3i

RAMB4_Sm_Sn

Port A and Port B Conflict Resolution

A RAMB4_Sm_Sn component is a true dual-ported RAM in that it allows
simultaneous reads of the same memory cell. When one port is performing a write to
a given memory cell, the other port should not address that memory cell (for a write
or a read) within the clock-to-clock setup window.
If both ports write to the same memory cell simultaneously, violating the clock-tosetup requirement, the data stored will be invalid.
If one port attempts to read from the same memory cell that the other is
simultaneously writing to, violating the clock setup requirement, the write will be
successful but the data read will be invalid.

Specifying Initial Contents of a Block RAM

You can use the INIT_0x attributes to specify an initial value during device
configuration. The initialization of each RAMB4_Sm_Sn is set by 16 initialization
attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. See the
INIT_xx section of the Constraints Guide for more information on these attributes.
If any INIT_0x attribute is not specified, it is configured as zeros. Partial initialization
strings are padded with zeros to the left.

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template for RAMB4_Sm_Sn

-- RAMB4_S1_S1: Virtex/E, Spartan-II/IIE 4k x 1 Dual-Port RAM
-- Xilinx HDL Language Template version 6.1i
RAMB4_S1_S1_inst : RAMB4_S1_S1
-- The following generic INIT_xx declarations are only necessary if you
-- wish to change the initial
-- contents of the RAM to anything other than all zero's.
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"")

port map (
DOA => DOA,
-- Port A 1-bit data output
DOB => DOB,
-- Port B 1-bit data output
ADDRA => ADDRA, -- Port A 12-bit address input

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1013

RAMB4_Sm_Sn

ADDRB => ADDRB,

CLKA => CLKA,
CLKB => CLKB,
DIA => DIA,
DIB => DIB,
ENA => ENA,
ENB => ENB,
RSTA => RSTA,
RSTB => RSTB,
WEA => WEA,
WEB => WEB

------------

Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port

B
A
B
A
B
A
B
A
B
A
B

12-bit address input

clock input
clock input
1-bit data input
1-bit data input
RAM enable input
RAM enable input
Synchronous reset input
Synchronous reset input
RAM write enable input
RAM write enable input

);
-- End of RAMB4_S1_S1_inst instantiation

Verilog Instantiation Template for RAMB4_Sm_Sn

All RAMB4_Sm_Sn templates are listed below. Find and cut the specific
configuration you need for your design.
---//
//

Note that the use of INIT below is for simulation only. For examples
of how to include INIT as an implementation constraint,
please refer to the Constraints Guide.
RAMB4_S1_S1: Virtex/E, Spartan-II/IIE 4k x 1 Dual-Port RAM
Xilinx HDL Language Template version 6.1i
RAMB4_S1_S1 RAMB4_S1_S1_inst (
.DOA(DOA),
// Port A 1-bit data output
.DOB(DOB),
// Port B 1-bit data output
.ADDRA(ADDRA), // Port A 12-bit address input
.ADDRB(ADDRB), // Port B 12-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 1-bit data input
.DIB(DIB),
// Port B 1-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input
.RSTB(RSTB),
// Port B Synchronous reset input
.WEA(WEA),
// Port A RAM write enable input
.WEB(WEB)
// Port B RAM write enable input
);

//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

1014

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S1_S1_inst.INIT_00
RAMB4_S1_S1_inst.INIT_01
RAMB4_S1_S1_inst.INIT_02
RAMB4_S1_S1_inst.INIT_03
RAMB4_S1_S1_inst.INIT_04
RAMB4_S1_S1_inst.INIT_05
RAMB4_S1_S1_inst.INIT_06
RAMB4_S1_S1_inst.INIT_07
RAMB4_S1_S1_inst.INIT_08
RAMB4_S1_S1_inst.INIT_09
RAMB4_S1_S1_inst.INIT_0A

=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;

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ISE 6.3i

defparam
defparam
defparam
defparam
defparam

RAMB4_Sm_Sn

RAMB4_S1_S1_inst.INIT_0B
RAMB4_S1_S1_inst.INIT_0C
RAMB4_S1_S1_inst.INIT_0D
RAMB4_S1_S1_inst.INIT_0E
RAMB4_S1_S1_inst.INIT_0F

=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S1_S1_inst instantiation

// RAMB4_S1_S2: Virtex/E, Spartan-II/IIE 4k/2k x 1/2 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S1_S2 RAMB4_S1_S2_inst (
.DOA(DOA),
// Port A 1-bit data output
.DOB(DOB),
// Port B 2-bit data output
.ADDRA(ADDRA), // Port A 12-bit address input
.ADDRB(ADDRB), // Port B 11-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 1-bit data input
.DIB(DIB),
// Port B 2-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input
.RSTB(RSTB),
// Port B Synchronous reset input
.WEA(WEA),
// Port A RAM write enable input
.WEB(WEB)
// Port B RAM write enable input
);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S1_S2_inst.INIT_00
RAMB4_S1_S2_inst.INIT_01
RAMB4_S1_S2_inst.INIT_02
RAMB4_S1_S2_inst.INIT_03
RAMB4_S1_S2_inst.INIT_04
RAMB4_S1_S2_inst.INIT_05
RAMB4_S1_S2_inst.INIT_06
RAMB4_S1_S2_inst.INIT_07
RAMB4_S1_S2_inst.INIT_08
RAMB4_S1_S2_inst.INIT_09
RAMB4_S1_S2_inst.INIT_0A
RAMB4_S1_S2_inst.INIT_0B
RAMB4_S1_S2_inst.INIT_0C
RAMB4_S1_S2_inst.INIT_0D
RAMB4_S1_S2_inst.INIT_0E
RAMB4_S1_S2_inst.INIT_0F

=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S1_S2_inst instantiation

// RAMB4_S1_S4: Virtex/E, Spartan-II/IIE 4k/1k x 1/4 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S1_S4 RAMB4_S1_S4_inst (
.DOA(DOA),
// Port A 1-bit data output
.DOB(DOB),
// Port B 4-bit data output
.ADDRA(ADDRA), // Port A 12-bit address input
.ADDRB(ADDRB), // Port B 10-bit address input

1015

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Libraries Guide
ISE 6.3i

RAMB4_Sm_Sn

.CLKA(CLKA),
.CLKB(CLKB),
.DIA(DIA),
.DIB(DIB),
.ENA(ENA),
.ENB(ENB),
.RSTA(RSTA),
.RSTB(RSTB),
.WEA(WEA),
.WEB(WEB)

//
//
//
//
//
//
//
//
//
//

Port
Port
Port
Port
Port
Port
Port
Port
Port
Port

A
B
A
B
A
B
A
B
A
B

clock input
clock input
1-bit data input
4-bit data input
RAM enable input
RAM enable input
Synchronous reset input
Synchronous reset input
RAM write enable input
RAM write enable input

);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S1_S4_inst.INIT_00
RAMB4_S1_S4_inst.INIT_01
RAMB4_S1_S4_inst.INIT_02
RAMB4_S1_S4_inst.INIT_03
RAMB4_S1_S4_inst.INIT_04
RAMB4_S1_S4_inst.INIT_05
RAMB4_S1_S4_inst.INIT_06
RAMB4_S1_S4_inst.INIT_07
RAMB4_S1_S4_inst.INIT_08
RAMB4_S1_S4_inst.INIT_09
RAMB4_S1_S4_inst.INIT_0A
RAMB4_S1_S4_inst.INIT_0B
RAMB4_S1_S4_inst.INIT_0C
RAMB4_S1_S4_inst.INIT_0D
RAMB4_S1_S4_inst.INIT_0E
RAMB4_S1_S4_inst.INIT_0F

=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S1_S4_inst instantiation

// RAMB4_S1_S8: Virtex/E, Spartan-II/IIE 4k/512 x 1/8 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S1_S8 RAMB4_S1_S8_inst (
.DOA(DOA),
// Port A 1-bit data output
.DOB(DOB),
// Port B 8-bit data output
.ADDRA(ADDRA), // Port A 12-bit address input
.ADDRB(ADDRB), // Port B 9-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 1-bit data input
.DIB(DIB),
// Port B 8-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input
.RSTB(RSTB),
// Port B Synchronous reset input
.WEA(WEA),
// Port A RAM write enable input
.WEB(WEB)
// Port B RAM write enable input
);
// The following defparam INIT_xx declarations are only necessary if
// you wish to change the initial contents of the RAM to anything
// other than all zero's. If the instance name to the RAM is changed,

1016

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ISE 6.3i

RAMB4_Sm_Sn

// that change needs to be reflected in the defparam statements.

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB4_S1_S8_inst.INIT_00
RAMB4_S1_S8_inst.INIT_01
RAMB4_S1_S8_inst.INIT_02
RAMB4_S1_S8_inst.INIT_03
RAMB4_S1_S8_inst.INIT_04
RAMB4_S1_S8_inst.INIT_05
RAMB4_S1_S8_inst.INIT_06
RAMB4_S1_S8_inst.INIT_07
RAMB4_S1_S8_inst.INIT_08
RAMB4_S1_S8_inst.INIT_09
RAMB4_S1_S8_inst.INIT_0A
RAMB4_S1_S8_inst.INIT_0B
RAMB4_S1_S8_inst.INIT_0C
RAMB4_S1_S8_inst.INIT_0D
RAMB4_S1_S8_inst.INIT_0E
RAMB4_S1_S8_inst.INIT_0F

=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S1_S8_inst instantiation

// RAMB4_S1_S16: Virtex/E, Spartan-II/IIE 4k/256 x 1/16 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S1_S16 RAMB4_S1_S16_inst (
.DOA(DOA),
// Port A 1-bit data output
.DOB(DOB),
// Port B 16-bit data output
.ADDRA(ADDRA), // Port A 12-bit address input
.ADDRB(ADDRB), // Port B 8-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 1-bit data input
.DIB(DIB),
// Port B 16-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input
.RSTB(RSTB),
// Port B Synchronous reset input
.WEA(WEA),
// Port A RAM write enable input
.WEB(WEB)
// Port B RAM write enable input
);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S1_S16_inst.INIT_00=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_01=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_02=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_03=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_04=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_05=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_06=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_07=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_08=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_09=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_0A=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_0B=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_0C=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_0D=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S1_S16_inst.INIT_0E=256'h0000000000000000000000000000000000000000000000000000000000000000;

Libraries Guide
ISE 6.3i

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1017

RAMB4_Sm_Sn

defparam RAMB4_S1_S16_inst.INIT_0F=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S1_S16_inst instantiation

// RAMB4_S2_S2: Virtex/E, Spartan-II/IIE 2k x 2 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S2_S2 RAMB4_S2_S2_inst (
.DOA(DOA),
// Port A 2-bit data output
.DOB(DOB),
// Port B 2-bit data output
.ADDRA(ADDRA), // Port A 11-bit address input
.ADDRB(ADDRB), // Port B 11-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 2-bit data input
.DIB(DIB),
// Port B 2-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input
.RSTB(RSTB),
// Port B Synchronous reset input
.WEA(WEA),
// Port A RAM write enable input
.WEB(WEB)
// Port B RAM write enable input
);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S2_S2_inst.INIT_00
RAMB4_S2_S2_inst.INIT_01
RAMB4_S2_S2_inst.INIT_02
RAMB4_S2_S2_inst.INIT_03
RAMB4_S2_S2_inst.INIT_04
RAMB4_S2_S2_inst.INIT_05
RAMB4_S2_S2_inst.INIT_06
RAMB4_S2_S2_inst.INIT_07
RAMB4_S2_S2_inst.INIT_08
RAMB4_S2_S2_inst.INIT_09
RAMB4_S2_S2_inst.INIT_0A
RAMB4_S2_S2_inst.INIT_0B
RAMB4_S2_S2_inst.INIT_0C
RAMB4_S2_S2_inst.INIT_0D
RAMB4_S2_S2_inst.INIT_0E
RAMB4_S2_S2_inst.INIT_0F

=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S2_S2_inst instantiation

// RAMB4_S2_S4: Virtex/E, Spartan-II/IIE 2k/1k x 2/4 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S2_S4 RAMB4_S2_S4_inst (
.DOA(DOA),
// Port A 2-bit data output
.DOB(DOB),
// Port B 4-bit data output
.ADDRA(ADDRA), // Port A 11-bit address input
.ADDRB(ADDRB), // Port B 10-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 2-bit data input

1018

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Libraries Guide
ISE 6.3i

RAMB4_Sm_Sn

.DIB(DIB),
.ENA(ENA),
.ENB(ENB),
.RSTA(RSTA),
.RSTB(RSTB),
.WEA(WEA),
.WEB(WEB)

//
//
//
//
//
//
//

Port
Port
Port
Port
Port
Port
Port

B
A
B
A
B
A
B

4-bit data input

RAM enable input
RAM enable input
Synchronous reset input
Synchronous reset input
RAM write enable input
RAM write enable input

);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S2_S4_inst.INIT_00
RAMB4_S2_S4_inst.INIT_01
RAMB4_S2_S4_inst.INIT_02
RAMB4_S2_S4_inst.INIT_03
RAMB4_S2_S4_inst.INIT_04
RAMB4_S2_S4_inst.INIT_05
RAMB4_S2_S4_inst.INIT_06
RAMB4_S2_S4_inst.INIT_07
RAMB4_S2_S4_inst.INIT_08
RAMB4_S2_S4_inst.INIT_09
RAMB4_S2_S4_inst.INIT_0A
RAMB4_S2_S4_inst.INIT_0B
RAMB4_S2_S4_inst.INIT_0C
RAMB4_S2_S4_inst.INIT_0D
RAMB4_S2_S4_inst.INIT_0E
RAMB4_S2_S4_inst.INIT_0F

=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S2_S4_inst instantiation

// RAMB4_S2_S8: Virtex/E, Spartan-II/IIE 2k/512 x 2/8 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S2_S8 RAMB4_S2_S8_inst (
.DOA(DOA),
// Port A 2-bit data output
.DOB(DOB),
// Port B 8-bit data output
.ADDRA(ADDRA), // Port A 11-bit address input
.ADDRB(ADDRB), // Port B 9-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 2-bit data input
.DIB(DIB),
// Port B 8-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input
.RSTB(RSTB),
// Port B Synchronous reset input
.WEA(WEA),
// Port A RAM write enable input
.WEB(WEB)
// Port B RAM write enable input
);
//
//
//
//

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

defparam RAMB4_S2_S8_inst.INIT_00 =256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB4_S2_S8_inst.INIT_01 =256'h0000000000000000000000000000000000000000000000000000000000000000;

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1019

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB4_Sm_Sn

RAMB4_S2_S8_inst.INIT_02
RAMB4_S2_S8_inst.INIT_03
RAMB4_S2_S8_inst.INIT_04
RAMB4_S2_S8_inst.INIT_05
RAMB4_S2_S8_inst.INIT_06
RAMB4_S2_S8_inst.INIT_07
RAMB4_S2_S8_inst.INIT_08
RAMB4_S2_S8_inst.INIT_09
RAMB4_S2_S8_inst.INIT_0A
RAMB4_S2_S8_inst.INIT_0B
RAMB4_S2_S8_inst.INIT_0C
RAMB4_S2_S8_inst.INIT_0D
RAMB4_S2_S8_inst.INIT_0E
RAMB4_S2_S8_inst.INIT_0F

=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S2_S8_inst instantiation

// RAMB4_S2_S16: Virtex/E, Spartan-II/IIE 2k/256 x 2/16 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S2_S16 RAMB4_S2_S16_inst (
.DOA(DOA),
// Port A 2-bit data output
.DOB(DOB),
// Port B 16-bit data output
.ADDRA(ADDRA), // Port A 11-bit address input
.ADDRB(ADDRB), // Port B 8-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 2-bit data input
.DIB(DIB),
// Port B 16-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input
.RSTB(RSTB),
// Port B Synchronous reset input
.WEA(WEA),
// Port A RAM write enable input
.WEB(WEB)
// Port B RAM write enable input
);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S2_S16_inst.INIT_00=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_01=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_02=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_03=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_04=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_05=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_06=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_07=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_08=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_09=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_0A=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_0B=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_0C=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_0D=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_0E=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S2_S16_inst.INIT_0F=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S2_S16_inst instantiation

1020

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Libraries Guide
ISE 6.3i

RAMB4_Sm_Sn

// RAMB4_S4_S4: Virtex/E, Spartan-II/IIE 1k x 4 Dual-Port RAM

// Xilinx HDL Language Template version 6.1i
RAMB4_S4_S4 RAMB4_S4_S4_inst (
.DOA(DOA),
// Port A 4-bit data output
.DOB(DOB),
// Port B 4-bit data output
.ADDRA(ADDRA), // Port A 10-bit address input
.ADDRB(ADDRB), // Port B 10-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 4-bit data input
.DIB(DIB),
// Port B 4-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input
.RSTB(RSTB),
// Port B Synchronous reset input
.WEA(WEA),
// Port A RAM write enable input
.WEB(WEB)
// Port B RAM write enable input
);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S4_S4_inst.INIT_00
RAMB4_S4_S4_inst.INIT_01
RAMB4_S4_S4_inst.INIT_02
RAMB4_S4_S4_inst.INIT_03
RAMB4_S4_S4_inst.INIT_04
RAMB4_S4_S4_inst.INIT_05
RAMB4_S4_S4_inst.INIT_06
RAMB4_S4_S4_inst.INIT_07
RAMB4_S4_S4_inst.INIT_08
RAMB4_S4_S4_inst.INIT_09
RAMB4_S4_S4_inst.INIT_0A
RAMB4_S4_S4_inst.INIT_0B
RAMB4_S4_S4_inst.INIT_0C
RAMB4_S4_S4_inst.INIT_0D
RAMB4_S4_S4_inst.INIT_0E
RAMB4_S4_S4_inst.INIT_0F

=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S4_S4_inst instantiation

// RAMB4_S4_S8: Virtex/E, Spartan-II/IIE 1k/512 x 4/8 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S4_S8 RAMB4_S4_S8_inst (
.DOA(DOA),
// Port A 4-bit data output
.DOB(DOB),
// Port B 8-bit data output
.ADDRA(ADDRA), // Port A 10-bit address input
.ADDRB(ADDRB), // Port B 9-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 4-bit data input
.DIB(DIB),
// Port B 8-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input

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1021

RAMB4_Sm_Sn

.RSTB(RSTB),
.WEA(WEA),
.WEB(WEB)

// Port B Synchronous reset input

// Port A RAM write enable input
// Port B RAM write enable input

);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S4_S8_inst.INIT_00
RAMB4_S4_S8_inst.INIT_01
RAMB4_S4_S8_inst.INIT_02
RAMB4_S4_S8_inst.INIT_03
RAMB4_S4_S8_inst.INIT_04
RAMB4_S4_S8_inst.INIT_05
RAMB4_S4_S8_inst.INIT_06
RAMB4_S4_S8_inst.INIT_07
RAMB4_S4_S8_inst.INIT_08
RAMB4_S4_S8_inst.INIT_09
RAMB4_S4_S8_inst.INIT_0A
RAMB4_S4_S8_inst.INIT_0B
RAMB4_S4_S8_inst.INIT_0C
RAMB4_S4_S8_inst.INIT_0D
RAMB4_S4_S8_inst.INIT_0E
RAMB4_S4_S8_inst.INIT_0F

=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S4_S8_inst instantiation

// RAMB4_S4_S16: Virtex/E, Spartan-II/IIE 1k/256 x 4/16 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S4_S16 RAMB4_S4_S16_inst (
.DOA(DOA),
// Port A 4-bit data output
.DOB(DOB),
// Port B 16-bit data output
.ADDRA(ADDRA), // Port A 10-bit address input
.ADDRB(ADDRB), // Port B 8-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 4-bit data input
.DIB(DIB),
// Port B 16-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input
.RSTB(RSTB),
// Port B Synchronous reset input
.WEA(WEA),
// Port A RAM write enable input
.WEB(WEB)
// Port B RAM write enable input
);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam

1022

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S4_S16_inst.INIT_00=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_01=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_02=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_03=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_04=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_05=256'h0000000000000000000000000000000000000000000000000000000000000000;

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ISE 6.3i

RAMB4_Sm_Sn

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB4_S4_S16_inst.INIT_06=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_07=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_08=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_09=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_0A=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_0B=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_0C=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_0D=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_0E=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S4_S16_inst.INIT_0F=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S4_S16_inst instantiation

// RAMB4_S8_S8: Virtex/E, Spartan-II/IIE 512 x 8 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S8_S8 RAMB4_S8_S8_inst (
.DOA(DOA),
// Port A 8-bit data output
.DOB(DOB),
// Port B 8-bit data output
.ADDRA(ADDRA), // Port A 9-bit address input
.ADDRB(ADDRB), // Port B 9-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 8-bit data input
.DIB(DIB),
// Port B 8-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input
.RSTB(RSTB),
// Port B Synchronous reset input
.WEA(WEA),
// Port A RAM write enable input
.WEB(WEB)
// Port B RAM write enable input
);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S8_S8_inst.INIT_00
RAMB4_S8_S8_inst.INIT_01
RAMB4_S8_S8_inst.INIT_02
RAMB4_S8_S8_inst.INIT_03
RAMB4_S8_S8_inst.INIT_04
RAMB4_S8_S8_inst.INIT_05
RAMB4_S8_S8_inst.INIT_06
RAMB4_S8_S8_inst.INIT_07
RAMB4_S8_S8_inst.INIT_08
RAMB4_S8_S8_inst.INIT_09
RAMB4_S8_S8_inst.INIT_0A
RAMB4_S8_S8_inst.INIT_0B
RAMB4_S8_S8_inst.INIT_0C
RAMB4_S8_S8_inst.INIT_0D
RAMB4_S8_S8_inst.INIT_0E
RAMB4_S8_S8_inst.INIT_0F

=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;
=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S8_S8_inst instantiation

// RAMB4_S8_S16: Virtex/E, Spartan-II/IIE 512/256 x 8/16 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i

Libraries Guide
ISE 6.3i

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1023

RAMB4_Sm_Sn

RAMB4_S8_S16 RAMB4_S8_S16_inst (
.DOA(DOA),
// Port A 8-bit data output
.DOB(DOB),
// Port B 16-bit data output
.ADDRA(ADDRA), // Port A 9-bit address input
.ADDRB(ADDRB), // Port B 8-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 8-bit data input
.DIB(DIB),
// Port B 16-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input
.RSTB(RSTB),
// Port B Synchronous reset input
.WEA(WEA),
// Port A RAM write enable input
.WEB(WEB)
// Port B RAM write enable input
);
//
//
//
//
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

RAMB4_S8_S16_inst.INIT_00=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_01=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_02=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_03=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_04=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_05=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_06=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_07=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_08=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_09=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_0A=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_0B=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_0C=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_0D=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_0E=256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB4_S8_S16_inst.INIT_0F=256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S8_S16_inst instantiation

// RAMB4_S16_S16: Virtex/E, Spartan-II/IIE 256 x 16 Dual-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB4_S16_S16 RAMB4_S16_S16_inst (
.DOA(DOA),
// Port A 16-bit data output
.DOB(DOB),
// Port B 16-bit data output
.ADDRA(ADDRA), // Port A 8-bit address input
.ADDRB(ADDRB), // Port B 8-bit address input
.CLKA(CLKA),
// Port A clock input
.CLKB(CLKB),
// Port B clock input
.DIA(DIA),
// Port A 16-bit data input
.DIB(DIB),
// Port B 16-bit data input
.ENA(ENA),
// Port A RAM enable input
.ENB(ENB),
// Port B RAM enable input
.RSTA(RSTA),
// Port A Synchronous reset input
.RSTB(RSTB),
// Port B Synchronous reset input
.WEA(WEA),
// Port A RAM write enable input
.WEB(WEB)
// Port B RAM write enable input

1024

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Libraries Guide
ISE 6.3i

RAMB4_Sm_Sn

);
//
//
//
//

The following defparam INIT_xx declarations are only necessary if

you wish to change the initial contents of the RAM to anything
other than all zero's. If the instance name to the RAM is changed,
that change needs to be reflected in the defparam statements.

defparam RAMB4_S16_S16_inst.INIT_00
=256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_01 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_02 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_03 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_04 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_05 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_06 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_07 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_08 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_09 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_0A =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_0B =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_0C =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_0D =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_0E =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAMB4_S16_S16_inst.INIT_0F =
256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB4_S16_S16_inst instantiation

Commonly Used Constraints

INIT_xx

Libraries Guide
ISE 6.3i

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1025

1026

RAMB4_Sm_Sn

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ISE 6.3i

RAMB16_Sn

RAMB16_Sn
16384-Bit Data Memory and 2048-Bit Parity Memory, Single-Port
Synchronous Block RAM with Port Width (n) Configured to 1, 2, 4, 9,
18, or 36 Bits
Architectures Supported
RAMB16_Sn
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

WE

WE

RAMB16_S1

WE

RAMB16_S2

EN

EN
SSR

DO [0:0]

SSR

DO [1:0]

SSR

CLK

CLK

CLK

ADDR [13:0]

ADDR [12:0]

ADDR [11:0]

DI [0:0]

DI [1:0]

DI [3:0]

WE
EN
SSR

RAMB16_S9

WE
DOP [0:0]
DO [7:0]

EN
SSR

RAMB16_S4

EN

RAMB16_S18

WE
DOP [1:0]
DO [15:0]

EN
SSR

CLK

CLK

CLK

ADDR [10:0]

ADDR [9:0]

ADDR [8:0]

DI [7:0]

DI [15:0]

DI [31:0]

DIP [0:0]

DIP [1:0]

DIP [3:0]

DO [3:0]

RAMB16_S36
DOP [3:0]
DO [31:0]

X9465

RAMB16_S1 through RAMB16_S36 Representations

RAMB16_S1, RAMB16_S2, RAMB16_S4, RAMB16_S9, RAMB16_S18, and
RAMB16_S36 are dedicated random access memory blocks with synchronous write
capability. The block RAM port has 16384 bits of data memory. RAMB16_S9,
RAMB16_S18, and RAMB16_S36 have an additional 2048 bits of parity memory. The
RAMB16_Sn cell configurations are listed in the following table.

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1027

RAMB16_Sn

The enable (EN) pin controls read, write, and reset. When EN is Low, no data is
Component

Data Cells

Parity Cells

Address Bus

Data Bus

Parity Bus

Depth

Width

Depth

Width

16384

(13:0)

(0:0)

RAMB16_S2

8192

(12:0)

(1:0)

RAMB16_S4

4096

(11:0)

(3:0)

RAMB16_S9

2048

2048

(10:0)

(7:0)

(0:0)

RAMB16_S18

1024

16

1024

(9:0)

(15:0)

(1:0)

RAMB16_S36

512

32

512

(8:0)

(31:0)

(3:0)

RAMB16_S1

written and the outputs (DO and DOP) retain the last state. When EN is High and
reset (SSR) is High, DO and DOP are set to SRVAL during the Low-to-High clock
(CLK) transition; if write enable (WE) is High, the memory contents reflect the data at
DI and DIP. When SSR is Low, EN is High, and WE is Low, the data stored in the RAM
address (ADDR) is read during the Low-to-High clock transition. The output value
depends on the mode. By default WRITE_MODE=WRITE_FIRST, when EN and WE
are High and SSR is Low, the data on the data inputs (DI and DIP) is loaded into the
word selected by the write address (ADDR) during the Low-to-High clock transition.
See Write Mode Selection for information on setting the WRITE_MODE.
The above description assumes an active High EN, WE, SSR, and CLK. However, the
active level can be changed by placing an inverter on the port. Any inverter placed on
a RAMB16 port is absorbed into the block and does not use a CLB resource.
Inputs
GS
R

EN

SSR WE CLK

Outputs
ADD
R

DI

DIP

DO

DOP

RAM Contents
Data RAM

Parity RAM

INIT

INIT

No Chg

No Chg

No Chg

No Chg

No Chg

No Chg

SRVAL

SRVAL

No Chg

No Chg

addr

data

pdata SRVAL

SRVAL

RAM(addr)
=>data

RAM(addr) =>pdata

addr

RAM(addr)

No Chg

No Chg

1028

RAM(addr)

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Libraries Guide
ISE 6.3i

RAMB16_Sn

Inputs
GS
R
0

EN
1

Outputs

SSR WE CLK
0

ADD
R

DI

addr

data

DIP

DO

DOP

RAM Contents

pdata No Chga
No Chga
RAM(addr)
RAM (addr)b RAM(addr)b =>data
datac
pdatac

RAM(addr) =>pdata

GSR=Global Set Reset signal

INIT=Value specified by the INIT attribute for data memory. Default is all zeros.
SRVAL=Value after assertion of SSR as specified by the SRVAL attribute.
addr=RAM address
RAM(addr)=RAM contents at address ADDR
data=RAM input data
pdata=RAM parity data
aWRITE_MODE=NO_CHANGE
bWRITE_MODE=READ_FIRST
cWRITE_MODE=WRITE_FIRST

Initializing Memory Contents of a Single-Port RAMB16

You can use the INIT_xx attributes to specify an initialization value for the memory
contents of a RAMB16 during device configuration. The initialization of each
RAMB16_Sn is set by 64 initialization attributes (INIT_00 through INIT_3F) of 64 hex
values for a total of 16384 bits.
You can use the INITP_xx attributes to specify an initial value for the parity memory
during device configuration or assertion. The initialization of the parity memory for
ports configured for 9, 18, or 36 bits is set by 8 initialization attributes (INITP_00
through INITP_07) of 64 hex values for a total of 2048 bits.
If any INIT_xx or INITP_xx attribute is not specified, it is configured as zeros. Partial
strings are padded with zeros to the left.
See the Constraints Guide for more information on these attributes.

Initializing the Output Register of a Single-Port RAMB16

In Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, each bit in the output register
can be initialized at power on to either a 0 or 1. In addition, the initial state specified
for power on can be different than the state that results from assertion of a set/reset.
Two types of properties control initialization of the output register for a single-port
RAMB16: INIT and SRVAL. The INIT attribute specifies the output register value at
power on. You can use the SRVAL attribute to define the state resulting from assertion
of the SSR (set/reset) input.
The INIT and SRVAL attributes specify the initialization value as a hexadecimal
string. The value is dependent upon the port width. For example, for a RAMB16_S1
with port width equal to 1, the output register contains 1 bit. Therefore, the INIT or
SRVAL value can only be specified as a 1 or 0. For RAMB16_S4 with port width equal
to 4, the output register contains 4 bits. In this case, you can specify a hexadecimal
value from 0 through F to initialize the 4 bits of the output register.

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ISE 6.3i

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1029

RAMB16_Sn

For those ports that include parity bits, the parity portion of the output register is
specified in the high order bit position of the INIT or SRVAL value.
The INIT and SRVAL attributes default to zero if they are not set by the user.
See the Constraints Guide for more information on these attributes.

Write Mode Selection

The WRITE_MODE attribute controls RAMB16 memory and output contents. By
default, the WRITE_MODE is set to WRITE_FIRST. This means that input is read,
written to memory, and then passed to output. You can set the WRITE_MODE to
READ_FIRST to read the memory contents, pass the memory contents to the outputs,
and then write the input to memory. Or, you can set the WRITE_MODE to
NO_CHANGE to have the input written to memory without changing the output.

Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is
shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template for RAMB16_S1, S2, and S4

RAMB16_S4
-- RAMB16_S4: Virtex-II/II-Pro, Spartan-3 4k x 4 Single-Port RAM
-- Xilinx HDL Language Template version 6.1i
RAMB16_S4_inst : RAMB16_S4
generic map (
-- The following generics are only necessary if you
-- wish to change the default behavior.
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
NO_CHANGE
-- The following generic INIT_xx declarations are only
-- necessary if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",

1030

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Libraries Guide
ISE 6.3i

RAMB16_Sn

INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DOA => DOA,
-- Port A 4-bit Data Output
DOB => DOB,
-- Port B 16-bit Data Output
DOPB => DOPB,
-- Port B 2-bit Parity Output
ADDRA => ADDRA, -- Port A 12-bit Address Input
ADDRB => ADDRB, -- Port B 10-bit Address Input
CLKA => CLKA,
-- Port A Clock
CLKB => CLKB,
-- Port B Clock
DIA => DIA,
-- Port A 4-bit Data Input
DIB => DIB,
-- Port B 16-bit Data Input
DIPB => DIPB,
-- Port-B 2-bit parity Input
ENA => ENA,
-- Port A RAM Enable Input

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ISE 6.3i

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1031

ENB => ENB,

SSRA => SSRA,
SSRB => SSRB,
WEA => WEA,
WEB => WEB

RAMB16_Sn

------

PortB RAM Enable Input

Port A Synchronous Set/Reset Input
Port B Synchronous Set/Reset Input
Port A Write Enable Input
Port B Write Enable Input

);

-- End of RAMB16_S4_S18_inst instantiation

RAMB16_S4_S36

-------------

RAMB16_S4_S36 : In order to incorporate this function into the

-- design,
VHDL : the following instance declaration needs to be placed
instance
: in the architecture body of the design code. The
declaration : (RAMB16_S4_S36_inst) and/or the port declarations
code
: after the "=>" assignment maybe changed to properly
: reference and connect this function to the design.
: All inputs and outputs must be connected.
Library
-- use
declaration
-- to be
for
Xilinx
primitives
-- used

----

: In addition to adding the instance declaration, a

: statement for the UNISIM.vcomponents library needs
: added before the entity declaration. This library
: contains the component declarations for all Xilinx
: primitives and points to the models that will be
: for simulation.

Copy the following two statements and paste them before the
Entity declaration, unless they already exists.

-- Library UNISIM; use UNISIM.vcomponents.all;

RAMB16_S4_S36

-- RAMB16_S4_S36: Virtex-II/II-Pro, Spartan-3 4k/512 x 4/32 + 0/4

Parity bits Dual-Port RAM
-- Xilinx HDL Language Template version 6.1i
RAMB16_S4_S36_inst : RAMB16_S4_S36
generic map (
-- The following generics are only necessary if you wish to change the default behavior.
INIT_A => X"0", -- Value of output RAM registers on Port A at startup
INIT_B => X"000000000", -- Value of output RAM registers on Port B at startup
SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
SRVAL_B => X"000000000", -- Port B ouput value upon SSR assertion
WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following generic INIT_xx declarations are only necessary if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",

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Libraries Guide
ISE 6.3i

RAMB16_Sn

INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")

Libraries Guide
ISE 6.3i

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1033

RAMB16_Sn

port map (
DOA => DOA,
DOB => DOB,
DOPB => DOPB,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA,
DIB => DIB,
DIPB => DIPB,
ENA => ENA,
ENB => ENB,
SSRA => SSRA,
SSRB => SSRB,
WEA => WEA,
WEB => WEB
);

-----------------

Port A 4-bit Data Output

Port B 32-bit Data Output
Port B 4-bit Parity Output
Port A 12-bit Address Input
Port B 9-bit Address Input
Port A Clock
Port B Clock
Port A 4-bit Data Input
Port B 32-bit Data Input
Port-B 4-bit parity Input
Port A RAM Enable Input
PortB RAM Enable Input
Port A Synchronous Set/Reset Input
Port B Synchronous Set/Reset Input
Port A Write Enable Input
Port B Write Enable Input

-- End of RAMB16_S4_S36_inst instantiation

Verilog Instantiation Template for RAMB16_Sn

All RAMB16_Sn templates are listed below. Find and cut the specific configuration
you need for your design.

RAMB16_S1
-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.

// RAMB16_S1: Virtex-II/II-Pro,
// Spartan-3 16kx1 Single-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB16_S1 RAMB16_S1_inst (
.DO(DO),
// 1-bit Data Output
.ADDR(ADDR), // 14-bit Address Input
.CLK(CLK),
// Clock
.DI(DI),
// 1-bit Data Input
.EN(EN),
// RAM Enable Input
.SSR(SSR),
// Synchronous Set/Reset Input
.WE(WE)
// Write Enable Input
);
// The following defparam declarations are only necessary if you
// wish to change the default behavior of the RAM. If the instance
// name is changed, these defparams need to be updated accordingly.
defparam RAMB16_S1_inst.INIT = 1'h0;
// Value of output RAM registers at startup
defparam RAMB16_S1_inst.SRVAL = 1'h0;
// Ouput value upon SSR assertion
defparam RAMB16_S1_inst.WRITE_MODE = "WRITE_FIRST";
// WRITE_FIRST, READ_FIRST or NO_CHANGE
// The following defparam INIT_xx declarations are only
// necessary if you wish to change the initial

1034

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Libraries Guide
ISE 6.3i

RAMB16_Sn

// contents of the RAM to anything other than all zero's.

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB16_S1_inst.INIT_00
RAMB16_S1_inst.INIT_01
RAMB16_S1_inst.INIT_02
RAMB16_S1_inst.INIT_03
RAMB16_S1_inst.INIT_04
RAMB16_S1_inst.INIT_05
RAMB16_S1_inst.INIT_06
RAMB16_S1_inst.INIT_07
RAMB16_S1_inst.INIT_08
RAMB16_S1_inst.INIT_09
RAMB16_S1_inst.INIT_0A
RAMB16_S1_inst.INIT_0B
RAMB16_S1_inst.INIT_0C
RAMB16_S1_inst.INIT_0D
RAMB16_S1_inst.INIT_0E
RAMB16_S1_inst.INIT_0F
RAMB16_S1_inst.INIT_10
RAMB16_S1_inst.INIT_11
RAMB16_S1_inst.INIT_12
RAMB16_S1_inst.INIT_13
RAMB16_S1_inst.INIT_14
RAMB16_S1_inst.INIT_15
RAMB16_S1_inst.INIT_16
RAMB16_S1_inst.INIT_17
RAMB16_S1_inst.INIT_18
RAMB16_S1_inst.INIT_19
RAMB16_S1_inst.INIT_1A
RAMB16_S1_inst.INIT_1B
RAMB16_S1_inst.INIT_1C
RAMB16_S1_inst.INIT_1D
RAMB16_S1_inst.INIT_1E
RAMB16_S1_inst.INIT_1F
RAMB16_S1_inst.INIT_20
RAMB16_S1_inst.INIT_21
RAMB16_S1_inst.INIT_22
RAMB16_S1_inst.INIT_23
RAMB16_S1_inst.INIT_24
RAMB16_S1_inst.INIT_25
RAMB16_S1_inst.INIT_26
RAMB16_S1_inst.INIT_27
RAMB16_S1_inst.INIT_28
RAMB16_S1_inst.INIT_29
RAMB16_S1_inst.INIT_2A
RAMB16_S1_inst.INIT_2B
RAMB16_S1_inst.INIT_2C
RAMB16_S1_inst.INIT_2D
RAMB16_S1_inst.INIT_2E
RAMB16_S1_inst.INIT_2F
RAMB16_S1_inst.INIT_30
RAMB16_S1_inst.INIT_31
RAMB16_S1_inst.INIT_32
RAMB16_S1_inst.INIT_33
RAMB16_S1_inst.INIT_34
RAMB16_S1_inst.INIT_35
RAMB16_S1_inst.INIT_36
RAMB16_S1_inst.INIT_37
RAMB16_S1_inst.INIT_38
RAMB16_S1_inst.INIT_39
RAMB16_S1_inst.INIT_3A
RAMB16_S1_inst.INIT_3B
RAMB16_S1_inst.INIT_3C
RAMB16_S1_inst.INIT_3D

Libraries Guide
ISE 6.3i

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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

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1-800-255-7778

1035

RAMB16_Sn

defparam RAMB16_S1_inst.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAMB16_S1_inst.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB16_S1_inst instantiation

RAMB16_S2
// RAMB16_S2: Virtex-II/II-Pro,
// Spartan-3 8k x 2 Single-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB16_S2 RAMB16_S2_inst (
.DO(DO),
// 2-bit Data Output
.ADDR(ADDR), // 13-bit Address Input
.CLK(CLK),
// Clock
.DI(DI),
// 2-bit Data Input
.EN(EN),
// RAM Enable Input
.SSR(SSR),
// Synchronous Set/Reset Input
.WE(WE)
// Write Enable Input
);
// The following defparam declarations are only necessary if you
// wish to change the default behavior of the RAM. If the instance
// name is changed, these defparams need to be updated accordingly.
defparam RAMB16_S2_inst.INIT = 1'h0;
// Value of output RAM registers at startup
defparam RAMB16_S2_inst.SRVAL = 1'h0;
// Ouput value upon SSR assertion
defparam RAMB16_S2_inst.WRITE_MODE = "WRITE_FIRST";
// WRITE_FIRST, READ_FIRST or NO_CHANGE
// The following defparam INIT_xx declarations are only
// necessary if you wish to change the initial
// contents of the RAM to anything other than all zero's.
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

1036

RAMB16_S2_inst.INIT_00
RAMB16_S2_inst.INIT_01
RAMB16_S2_inst.INIT_02
RAMB16_S2_inst.INIT_03
RAMB16_S2_inst.INIT_04
RAMB16_S2_inst.INIT_05
RAMB16_S2_inst.INIT_06
RAMB16_S2_inst.INIT_07
RAMB16_S2_inst.INIT_08
RAMB16_S2_inst.INIT_09
RAMB16_S2_inst.INIT_0A
RAMB16_S2_inst.INIT_0B
RAMB16_S2_inst.INIT_0C
RAMB16_S2_inst.INIT_0D
RAMB16_S2_inst.INIT_0E
RAMB16_S2_inst.INIT_0F
RAMB16_S2_inst.INIT_10
RAMB16_S2_inst.INIT_11
RAMB16_S2_inst.INIT_12
RAMB16_S2_inst.INIT_13
RAMB16_S2_inst.INIT_14
RAMB16_S2_inst.INIT_15
RAMB16_S2_inst.INIT_16
RAMB16_S2_inst.INIT_17
RAMB16_S2_inst.INIT_18
RAMB16_S2_inst.INIT_19
RAMB16_S2_inst.INIT_1A

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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sn

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
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defparam
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defparam
defparam

RAMB16_S2_inst.INIT_1B
RAMB16_S2_inst.INIT_1C
RAMB16_S2_inst.INIT_1D
RAMB16_S2_inst.INIT_1E
RAMB16_S2_inst.INIT_1F
RAMB16_S2_inst.INIT_20
RAMB16_S2_inst.INIT_21
RAMB16_S2_inst.INIT_22
RAMB16_S2_inst.INIT_23
RAMB16_S2_inst.INIT_24
RAMB16_S2_inst.INIT_25
RAMB16_S2_inst.INIT_26
RAMB16_S2_inst.INIT_27
RAMB16_S2_inst.INIT_28
RAMB16_S2_inst.INIT_29
RAMB16_S2_inst.INIT_2A
RAMB16_S2_inst.INIT_2B
RAMB16_S2_inst.INIT_2C
RAMB16_S2_inst.INIT_2D
RAMB16_S2_inst.INIT_2E
RAMB16_S2_inst.INIT_2F
RAMB16_S2_inst.INIT_30
RAMB16_S2_inst.INIT_31
RAMB16_S2_inst.INIT_32
RAMB16_S2_inst.INIT_33
RAMB16_S2_inst.INIT_34
RAMB16_S2_inst.INIT_35
RAMB16_S2_inst.INIT_36
RAMB16_S2_inst.INIT_37
RAMB16_S2_inst.INIT_38
RAMB16_S2_inst.INIT_39
RAMB16_S2_inst.INIT_3A
RAMB16_S2_inst.INIT_3B
RAMB16_S2_inst.INIT_3C
RAMB16_S2_inst.INIT_3D
RAMB16_S2_inst.INIT_3E
RAMB16_S2_inst.INIT_3F

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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB16_S2_inst instantiation

RAMB16_S4
// RAMB16_S4: Virtex-II/II-Pro,
// Spartan-3 4k x 4 Single-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB16_S4 RAMB16_S4_inst (
.DO(DO),
// 4-bit Data Output
.ADDR(ADDR), // 12-bit Address Input
.CLK(CLK),
// Clock
.DI(DI),
// 4-bit Data Input
.EN(EN),
// RAM Enable Input
.SSR(SSR),
// Synchronous Set/Reset Input
.WE(WE)
// Write Enable Input
);
// The following defparam declarations are only necessary if you
// wish to change the default behavior of the RAM. If the instance
// name is changed, these defparams need to be updated accordingly.
defparam RAMB16_S4_inst.INIT = 1'h0;
// Value of output RAM registers at startup
defparam RAMB16_S4_inst.SRVAL = 1'h0;

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1037

RAMB16_Sn

// Ouput value upon SSR assertion

defparam RAMB16_S4_inst.WRITE_MODE = "WRITE_FIRST";
// WRITE_FIRST, READ_FIRST or NO_CHANGE
// The following defparam INIT_xx declarations are only
// necessary if you wish to change the initial
// contents of the RAM to anything other than all zero's.
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
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defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

1038

RAMB16_S4_inst.INIT_00
RAMB16_S4_inst.INIT_01
RAMB16_S4_inst.INIT_02
RAMB16_S4_inst.INIT_03
RAMB16_S4_inst.INIT_04
RAMB16_S4_inst.INIT_05
RAMB16_S4_inst.INIT_06
RAMB16_S4_inst.INIT_07
RAMB16_S4_inst.INIT_08
RAMB16_S4_inst.INIT_09
RAMB16_S4_inst.INIT_0A
RAMB16_S4_inst.INIT_0B
RAMB16_S4_inst.INIT_0C
RAMB16_S4_inst.INIT_0D
RAMB16_S4_inst.INIT_0E
RAMB16_S4_inst.INIT_0F
RAMB16_S4_inst.INIT_10
RAMB16_S4_inst.INIT_11
RAMB16_S4_inst.INIT_12
RAMB16_S4_inst.INIT_13
RAMB16_S4_inst.INIT_14
RAMB16_S4_inst.INIT_15
RAMB16_S4_inst.INIT_16
RAMB16_S4_inst.INIT_17
RAMB16_S4_inst.INIT_18
RAMB16_S4_inst.INIT_19
RAMB16_S4_inst.INIT_1A
RAMB16_S4_inst.INIT_1B
RAMB16_S4_inst.INIT_1C
RAMB16_S4_inst.INIT_1D
RAMB16_S4_inst.INIT_1E
RAMB16_S4_inst.INIT_1F
RAMB16_S4_inst.INIT_20
RAMB16_S4_inst.INIT_21
RAMB16_S4_inst.INIT_22
RAMB16_S4_inst.INIT_23
RAMB16_S4_inst.INIT_24
RAMB16_S4_inst.INIT_25
RAMB16_S4_inst.INIT_26
RAMB16_S4_inst.INIT_27
RAMB16_S4_inst.INIT_28
RAMB16_S4_inst.INIT_29
RAMB16_S4_inst.INIT_2A
RAMB16_S4_inst.INIT_2B
RAMB16_S4_inst.INIT_2C
RAMB16_S4_inst.INIT_2D
RAMB16_S4_inst.INIT_2E
RAMB16_S4_inst.INIT_2F
RAMB16_S4_inst.INIT_30
RAMB16_S4_inst.INIT_31
RAMB16_S4_inst.INIT_32
RAMB16_S4_inst.INIT_33
RAMB16_S4_inst.INIT_34
RAMB16_S4_inst.INIT_35
RAMB16_S4_inst.INIT_36
RAMB16_S4_inst.INIT_37

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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sn

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB16_S4_inst.INIT_38
RAMB16_S4_inst.INIT_39
RAMB16_S4_inst.INIT_3A
RAMB16_S4_inst.INIT_3B
RAMB16_S4_inst.INIT_3C
RAMB16_S4_inst.INIT_3D
RAMB16_S4_inst.INIT_3E
RAMB16_S4_inst.INIT_3F

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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB16_S4_inst instantiation

RAMB16_S9
// RAMB16_S9: Virtex-II/II-Pro,
// Spartan-3 2k x 8 + 1 Parity bit Single-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB16_S9 RAMB16_S9_inst (
.DO(DO),
// 8-bit Data Output
.DOP(DOP),
// 1-bit parity Output
.ADDR(ADDR), // 11-bit Address Input
.CLK(CLK),
// Clock
.DI(DI),
// 8-bit Data Input
.DIP(DIP),
// 1-bit parity Input
.EN(EN),
// RAM Enable Input
.SSR(SSR),
// Synchronous Set/Reset Input
.WE(WE)
// Write Enable Input
);
// The following defparam declarations are only necessary if you
// wish to change the default behavior of the RAM. If the instance
// name is changed, these defparams need to be updated accordingly.
defparam RAMB16_S9_inst.INIT = 1'h0;
// Value of output RAM registers at startup
defparam RAMB16_S9_inst.SRVAL = 1'h0;
// Ouput value upon SSR assertion
defparam RAMB16_S9_inst.WRITE_MODE = "WRITE_FIRST";
// WRITE_FIRST, READ_FIRST or NO_CHANGE
// The following defparam INIT_xx declarations are only
// necessary if you wish to change the initial
// contents of the RAM to anything other than all zero's.
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB16_S9_inst.INIT_00
RAMB16_S9_inst.INIT_01
RAMB16_S9_inst.INIT_02
RAMB16_S9_inst.INIT_03
RAMB16_S9_inst.INIT_04
RAMB16_S9_inst.INIT_05
RAMB16_S9_inst.INIT_06
RAMB16_S9_inst.INIT_07
RAMB16_S9_inst.INIT_08
RAMB16_S9_inst.INIT_09
RAMB16_S9_inst.INIT_0A
RAMB16_S9_inst.INIT_0B
RAMB16_S9_inst.INIT_0C
RAMB16_S9_inst.INIT_0D
RAMB16_S9_inst.INIT_0E
RAMB16_S9_inst.INIT_0F
RAMB16_S9_inst.INIT_10
RAMB16_S9_inst.INIT_11
RAMB16_S9_inst.INIT_12

Libraries Guide
ISE 6.3i

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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

www.xilinx.com
1-800-255-7778

1039

RAMB16_Sn

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
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defparam
defparam
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defparam
defparam
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defparam
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defparam
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defparam
defparam
defparam
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defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB16_S9_inst.INIT_13
RAMB16_S9_inst.INIT_14
RAMB16_S9_inst.INIT_15
RAMB16_S9_inst.INIT_16
RAMB16_S9_inst.INIT_17
RAMB16_S9_inst.INIT_18
RAMB16_S9_inst.INIT_19
RAMB16_S9_inst.INIT_1A
RAMB16_S9_inst.INIT_1B
RAMB16_S9_inst.INIT_1C
RAMB16_S9_inst.INIT_1D
RAMB16_S9_inst.INIT_1E
RAMB16_S9_inst.INIT_1F
RAMB16_S9_inst.INIT_20
RAMB16_S9_inst.INIT_21
RAMB16_S9_inst.INIT_22
RAMB16_S9_inst.INIT_23
RAMB16_S9_inst.INIT_24
RAMB16_S9_inst.INIT_25
RAMB16_S9_inst.INIT_26
RAMB16_S9_inst.INIT_27
RAMB16_S9_inst.INIT_28
RAMB16_S9_inst.INIT_29
RAMB16_S9_inst.INIT_2A
RAMB16_S9_inst.INIT_2B
RAMB16_S9_inst.INIT_2C
RAMB16_S9_inst.INIT_2D
RAMB16_S9_inst.INIT_2E
RAMB16_S9_inst.INIT_2F
RAMB16_S9_inst.INIT_30
RAMB16_S9_inst.INIT_31
RAMB16_S9_inst.INIT_32
RAMB16_S9_inst.INIT_33
RAMB16_S9_inst.INIT_34
RAMB16_S9_inst.INIT_35
RAMB16_S9_inst.INIT_36
RAMB16_S9_inst.INIT_37
RAMB16_S9_inst.INIT_38
RAMB16_S9_inst.INIT_39
RAMB16_S9_inst.INIT_3A
RAMB16_S9_inst.INIT_3B
RAMB16_S9_inst.INIT_3C
RAMB16_S9_inst.INIT_3D
RAMB16_S9_inst.INIT_3E
RAMB16_S9_inst.INIT_3F

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB16_S9_inst.INITP_00
RAMB16_S9_inst.INITP_01
RAMB16_S9_inst.INITP_02
RAMB16_S9_inst.INITP_03
RAMB16_S9_inst.INITP_04
RAMB16_S9_inst.INITP_05
RAMB16_S9_inst.INITP_06
RAMB16_S9_inst.INITP_07

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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

// The next set of INITP_xx are for the parity bits

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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB16_S9_inst instantiation

RAMB16_S18
// RAMB16_S18: Virtex-II/II-Pro,
// Spartan-3 1k x 16 + 2 Parity bits Single-Port RAM
// Xilinx HDL Language Template version 6.1i

1040

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sn

RAMB16_S18 RAMB16_S18_inst (
.DO(DO),
// 16-bit Data Output
.DOP(DOP),
// 2-bit parity Output
.ADDR(ADDR), // 10-bit Address Input
.CLK(CLK),
// Clock
.DI(DI),
// 16-bit Data Input
.DIP(DIP),
// 2-bit parity Input
.EN(EN),
// RAM Enable Input
.SSR(SSR),
// Synchronous Set/Reset Input
.WE(WE)
// Write Enable Input
);
// The following defparam declarations are only necessary if you
// wish to change the default behavior of the RAM. If the instance
// name is changed, these defparams need to be updated accordingly.
defparam RAMB16_S18_inst.INIT = 1'h0;
// Value of output RAM registers at startup
defparam RAMB16_S18_inst.SRVAL = 1'h0;
// Ouput value upon SSR assertion
defparam RAMB16_S18_inst.WRITE_MODE = "WRITE_FIRST";
// WRITE_FIRST, READ_FIRST or NO_CHANGE
// The following defparam INIT_xx declarations are only
// necessary if you wish to change the initial
// contents of the RAM to anything other than all zero's.
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB16_S18_inst.INIT_00
RAMB16_S18_inst.INIT_01
RAMB16_S18_inst.INIT_02
RAMB16_S18_inst.INIT_03
RAMB16_S18_inst.INIT_04
RAMB16_S18_inst.INIT_05
RAMB16_S18_inst.INIT_06
RAMB16_S18_inst.INIT_07
RAMB16_S18_inst.INIT_08
RAMB16_S18_inst.INIT_09
RAMB16_S18_inst.INIT_0A
RAMB16_S18_inst.INIT_0B
RAMB16_S18_inst.INIT_0C
RAMB16_S18_inst.INIT_0D
RAMB16_S18_inst.INIT_0E
RAMB16_S18_inst.INIT_0F
RAMB16_S18_inst.INIT_10
RAMB16_S18_inst.INIT_11
RAMB16_S18_inst.INIT_12
RAMB16_S18_inst.INIT_13
RAMB16_S18_inst.INIT_14
RAMB16_S18_inst.INIT_15
RAMB16_S18_inst.INIT_16
RAMB16_S18_inst.INIT_17
RAMB16_S18_inst.INIT_18
RAMB16_S18_inst.INIT_19
RAMB16_S18_inst.INIT_1A
RAMB16_S18_inst.INIT_1B
RAMB16_S18_inst.INIT_1C
RAMB16_S18_inst.INIT_1D
RAMB16_S18_inst.INIT_1E
RAMB16_S18_inst.INIT_1F
RAMB16_S18_inst.INIT_20
RAMB16_S18_inst.INIT_21
RAMB16_S18_inst.INIT_22
RAMB16_S18_inst.INIT_23
RAMB16_S18_inst.INIT_24

Libraries Guide
ISE 6.3i

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256'h0000000000000000000000000000000000000000000000000000000000000000;
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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

www.xilinx.com
1-800-255-7778

1041

RAMB16_Sn

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB16_S18_inst.INIT_25
RAMB16_S18_inst.INIT_26
RAMB16_S18_inst.INIT_27
RAMB16_S18_inst.INIT_28
RAMB16_S18_inst.INIT_29
RAMB16_S18_inst.INIT_2A
RAMB16_S18_inst.INIT_2B
RAMB16_S18_inst.INIT_2C
RAMB16_S18_inst.INIT_2D
RAMB16_S18_inst.INIT_2E
RAMB16_S18_inst.INIT_2F
RAMB16_S18_inst.INIT_30
RAMB16_S18_inst.INIT_31
RAMB16_S18_inst.INIT_32
RAMB16_S18_inst.INIT_33
RAMB16_S18_inst.INIT_34
RAMB16_S18_inst.INIT_35
RAMB16_S18_inst.INIT_36
RAMB16_S18_inst.INIT_37
RAMB16_S18_inst.INIT_38
RAMB16_S18_inst.INIT_39
RAMB16_S18_inst.INIT_3A
RAMB16_S18_inst.INIT_3B
RAMB16_S18_inst.INIT_3C
RAMB16_S18_inst.INIT_3D
RAMB16_S18_inst.INIT_3E
RAMB16_S18_inst.INIT_3F

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defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB16_S18_inst.INITP_00=
RAMB16_S18_inst.INITP_01=
RAMB16_S18_inst.INITP_02=
RAMB16_S18_inst.INITP_03=
RAMB16_S18_inst.INITP_04=
RAMB16_S18_inst.INITP_05=
RAMB16_S18_inst.INITP_06=
RAMB16_S18_inst.INITP_07=

256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

// The next set of INITP_xx are for the parity bits

256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB16_S18_inst instantiation

RAMB16_S36
// RAMB16_S36: Virtex-II/II-Pro,
// Spartan-3 512 x 32 + 4 Parity bits Single-Port RAM
// Xilinx HDL Language Template version 6.1i
RAMB16_S36 RAMB16_S36_inst (
.DO(DO),
// 32-bit Data Output
.DOP(DOP),
// 4-bit parity Output
.ADDR(ADDR), // 9-bit Address Input
.CLK(CLK),
// Clock
.DI(DI),
// 32-bit Data Input
.DIP(DIP),
// 4-bit parity Input
.EN(EN),
// RAM Enable Input
.SSR(SSR),
// Synchronous Set/Reset Input
.WE(WE)
// Write Enable Input
);
// The following defparam declarations are only necessary if you
// wish to change the default behavior of the RAM. If the instance
// name is changed, these defparams need to be updated accordingly.
defparam RAMB16_S36_inst.INIT = 1'h0;
// Value of output RAM registers at startup

1042

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1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sn

defparam RAMB16_S36_inst.SRVAL = 1'h0;

// Ouput value upon SSR assertion
defparam RAMB16_S36_inst.WRITE_MODE = "WRITE_FIRST";
// WRITE_FIRST, READ_FIRST or NO_CHANGE
// The following defparam INIT_xx declarations are only
// necessary if you wish to change the initial
// contents of the RAM to anything other than all zero's.
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

1043

RAMB16_S36_inst.INIT_00
RAMB16_S36_inst.INIT_01
RAMB16_S36_inst.INIT_02
RAMB16_S36_inst.INIT_03
RAMB16_S36_inst.INIT_04
RAMB16_S36_inst.INIT_05
RAMB16_S36_inst.INIT_06
RAMB16_S36_inst.INIT_07
RAMB16_S36_inst.INIT_08
RAMB16_S36_inst.INIT_09
RAMB16_S36_inst.INIT_0A
RAMB16_S36_inst.INIT_0B
RAMB16_S36_inst.INIT_0C
RAMB16_S36_inst.INIT_0D
RAMB16_S36_inst.INIT_0E
RAMB16_S36_inst.INIT_0F
RAMB16_S36_inst.INIT_10
RAMB16_S36_inst.INIT_11
RAMB16_S36_inst.INIT_12
RAMB16_S36_inst.INIT_13
RAMB16_S36_inst.INIT_14
RAMB16_S36_inst.INIT_15
RAMB16_S36_inst.INIT_16
RAMB16_S36_inst.INIT_17
RAMB16_S36_inst.INIT_18
RAMB16_S36_inst.INIT_19
RAMB16_S36_inst.INIT_1A
RAMB16_S36_inst.INIT_1B
RAMB16_S36_inst.INIT_1C
RAMB16_S36_inst.INIT_1D
RAMB16_S36_inst.INIT_1E
RAMB16_S36_inst.INIT_1F
RAMB16_S36_inst.INIT_20
RAMB16_S36_inst.INIT_21
RAMB16_S36_inst.INIT_22
RAMB16_S36_inst.INIT_23
RAMB16_S36_inst.INIT_24
RAMB16_S36_inst.INIT_25
RAMB16_S36_inst.INIT_26
RAMB16_S36_inst.INIT_27
RAMB16_S36_inst.INIT_28
RAMB16_S36_inst.INIT_29
RAMB16_S36_inst.INIT_2A
RAMB16_S36_inst.INIT_2B
RAMB16_S36_inst.INIT_2C
RAMB16_S36_inst.INIT_2D
RAMB16_S36_inst.INIT_2E
RAMB16_S36_inst.INIT_2F
RAMB16_S36_inst.INIT_30
RAMB16_S36_inst.INIT_31
RAMB16_S36_inst.INIT_32
RAMB16_S36_inst.INIT_33
RAMB16_S36_inst.INIT_34
RAMB16_S36_inst.INIT_35
RAMB16_S36_inst.INIT_36

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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
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256'h0000000000000000000000000000000000000000000000000000000000000000;
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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
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256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sn

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB16_S36_inst.INIT_37
RAMB16_S36_inst.INIT_38
RAMB16_S36_inst.INIT_39
RAMB16_S36_inst.INIT_3A
RAMB16_S36_inst.INIT_3B
RAMB16_S36_inst.INIT_3C
RAMB16_S36_inst.INIT_3D
RAMB16_S36_inst.INIT_3E
RAMB16_S36_inst.INIT_3F

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defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

RAMB16_S36_inst.INITP_00=
RAMB16_S36_inst.INITP_01=
RAMB16_S36_inst.INITP_02=
RAMB16_S36_inst.INITP_03=
RAMB16_S36_inst.INITP_04=
RAMB16_S36_inst.INITP_05=
RAMB16_S36_inst.INITP_06=
RAMB16_S36_inst.INITP_07=

256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

// The next set of INITP_xx are for the parity bits

256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;
256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of RAMB16_S36_inst instantiation

VHDL Instantiation Template for RAMB16_S9, S18 and S36

-- Component Declaration for RAMB16_{S9 | S18 | S36} should be placed
-- after architecture statement but before begin keyword
-- Note that the use of INIT below is for simulation only
-- For examples on how to include INIT as an implementation
-- constraint,please refer to the Constraints Guide

component RAMB16_{S9 | S18 | S36}

-- synthesis translate_off
generic (
INIT : bit_vector
:= X"0";
INIT_00
INIT_01
INIT_02
INIT_03
INIT_04
INIT_05
INIT_06
INIT_07
INIT_08
INIT_09
INIT_0A
INIT_0B
INIT_0C
INIT_0D
INIT_0E
INIT_0F
INIT_10
INIT_11
INIT_12
INIT_13
INIT_14
INIT_15
INIT_16
INIT_17
INIT_18
INIT_19
INIT_1A
INIT_1B

1044

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bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector

:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=

X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sn

INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
);

-- synthesis translate_on
port (DO : out STD_LOGIC_VECTOR (0 downto 0);
DOP : out STD_LOGIC_VECTOR (1 downto 0);
ADDR : in STD_LOGIC_VECTOR (13 downto 0);
CLK : in STD_ULOGIC;
DI : in STD_LOGIC_VECTOR (0 downto 0);
DIP : in STD_LOGIC_VECTOR (0 downto 0);
EN : in STD_ULOGIC;
SSR : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- Component Attribute specification for RAMB16_{S9 | S18 | S36}

1045

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1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sn

-- should be placed after architecture declaration but

-- before the begin keyword
Enter attributes here
-- Component Instantiation for RAMB16_{S9 | S18 | S36} should be placed
-- in architecture after the begin keyword
-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAMB16_{S9 | S18 | S36}_INSTANCE_NAME : RAMB16_S1
-- synthesis translate_off
generic map (
INIT => bit_value,
INIT_00 => vector_value,
INIT_01 => vector_value,
INIT_02 => vector_value,
INIT_03 => vector_value,
INIT_04 => vector_value,
INIT_05 => vector_value,
INIT_06 => vector_value,
INIT_07 => vector_value,
INIT_08 => vector_value,
INIT_09 => vector_value,
INIT_0A => vector_value,
INIT_0B => vector_value,
INIT_0C => vector_value,
INIT_0D => vector_value,
INIT_0E => vector_value,
INIT_0F => vector_value,
INIT_10 => vector_value,
INIT_11 => vector_value,
INIT_12 => vector_value,
INIT_13 => vector_value,
INIT_14 => vector_value,
INIT_15 => vector_value,
INIT_16 => vector_value,
INIT_17 => vector_value,
INIT_18 => vector_value,
INIT_19 => vector_value,
INIT_1A => vector_value,
INIT_1B => vector_value,
INIT_1C => vector_value,
INIT_1D => vector_value,
INIT_1E => vector_value,
INIT_1F => vector_value,
INIT_20 => vector_value,
INIT_21 => vector_value,
INIT_22 => vector_value,
INIT_23 => vector_value,
INIT_24 => vector_value,
INIT_25 => vector_value,
INIT_26 => vector_value,
INIT_27 => vector_value,
INIT_28 => vector_value,
INIT_3A => vector_value,

1046

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sn

INIT_3B => vector_value,

INIT_3C => vector_value,
INIT_3D => vector_value,
INIT_3E => vector_value,
INIT_3F => vector_value,
INITP_00 => vector_value,
INITP_01 => vector_value,
INITP_02 => vector_value,
INITP_03 => vector_value,
INITP_04 => vector_value,
INITP_05 => vector_value,
INITP_06 => vector_value,
INITP_07 => vector_value
SRVAL => bit_value,
WRITE_MODE => user_WRITE_MODE)
-- synopsys translate_on
port map (DO => user_DO,
DOP => user_DOP,
ADDR => user_ADDR,
CLK => user_CLK,
DI => user_DI,
DIP => user_DIP,
EN => user_EN,
SSR => user_SSR,
WE => user_WE);

Commonly Used Constraints

INIT, INIT_xx, SRVAL, WRITE_MODE, HU_SET, INITP_xx, SRVAL,
WRITE_MODE

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1047

1048

RAMB16_Sn

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sm_Sn

RAMB16_Sm_Sn
16384-Bit Data Memory and 2048-Bit Parity Memory, Dual-Port
Synchronous Block RAM with Port Width (m or n) Configured to 1, 2, 4,
9, 18, or 36 Bits
Architectures Supported
RAMB16_Sm_Sn
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Libraries Guide
ISE 6.3i

No

CoolRunner XPLA3

No

CoolRunner-II

No

www.xilinx.com
1-800-255-7778

1049

WEA

RAMB16_Sm_Sn

RAMB16_S1_S1

WEA

ENA

RAMB16_S1_S2

WEA

ENA

SSRA

DOA [0:0]

SSRA

DOA [0:0]

SSRA

CLKA

CLKA

CLKA

ADDRA [13:0]

ADDRA [13:0]

ADDRA [13:0]

DIA [0:0]

DIA [0:0]

DIA [0:0]

WEB

WEB

WEB

ENB

ENB

SSRB

DOB [0:0]

DOB [1:0]

SSRB

CLKB

CLKB

ADDRB [13:0]

ADDRB [12:0]

ADDRB [11:0]

DIB [0:0]

DIB [1:0]

DIB [3:0]

RAMB16_S1_S9

WEA

ENA
SSRA

RAMB16_S1_S18

WEA

SSRA

DOA [0:0]

CLKA

CLKA

ADDRA [13:0]

ADDRA [13:0]

ADDRA [13:0]

DIA [0:0]

DIA [0:0]

DIA [0:0]

WEB

WEB

WEB

ENB

ENB

ENB

SSRB

SSRB

SSRB

DOPB [0:0]
DOB [7:0]

CLKB

RAMB16_S1_S36

SSRA

CLKA

CLKB

DOB [3:0]

ENA

ENA
DOA [0:0]

DOA [0:0]

ENB

SSRB

CLKB

WEA

RAMB16_S1_S4

ENA

DOPB [1:0]
DOB [15:0]

CLKB

ADDRB [10:0]

ADDRB [9:0]

ADDRB [8:0]

DIB [7:0]

DIB [15:0]

DIB [31:0]

DIPB [0:0]

DIPB [1:0]

DIPB [3:0]

DOA [0:0]

DOPB [3:0]
DOB [31:0]

X9466

RAMB16_S1_S1 through RAMB16_S1_S36 Representations

1050

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1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sm_Sn

WEA
RAMB16_S2_S2

WEA

WEA

ENA

ENA

SSRA

SSRA

DOA [1:0]

CLKA

CLKA

ADDRA [12:0]

ADDRA [12:0]

DIA [1:0]

DIA [1:0]

RAMB16_S2_S9

ENA

RAMB16_S2_S4

SSRA
DOA [1:0]

DOA [1:0]

CLKA
ADDRA [12:0]
DIA [1:0]

WEB
WEB

WEB

ENB

ENB

SSRB

DOB [1:0]

ENB
SSRB

SSRB

DOB [3:0]

CLKB
ADDRB [11:0]

DIB [7:0]

DIB [3:0]

DIPB [0:0]

WEA

RAMB16_S2_S18

WEA

ENA

RAMB16_S2_S36

ENA

SSRA

DOA [1:0]

WEA

SSRA

CLKA

CLKA

ADDRA [12:0]

ADDRA [12:0]

DIA [1:0]

DIA [1:0]

DOB [7:0]

ADDRB [10:0]

CLKB
ADDRB [12:0]
DIB [1:0]

DOPB [0:0]

CLKB

DOA [1:0]

RAMB16_S4_S4

ENA
SSRA

DOA [3:0]

CLKA
ADDRA [11:0]
DIA [3:0]

WEB

WEB

ENB

ENB

SSRB

DOPB [1:0]

CLKB

DOB [15:0]

ADDRB [9:0]

WEB

SSRB
CLKB

DOPB [3:0]

ENB

DOB [31:0]

SSRB

ADDRB [8:0]

DIB [15:0]

DIB [31:0]

ADDRB [11:0]

DIPB [1:0]

DIPB [3:0]

DIB [3:0]

WEA

RAMB16_S4_S9

WEA

ENA
SSRA

RAMB16_S4_S18

WEA

ENA
DOA [3:0]

SSRA

DOA [3:0]

SSRA

CLKA

CLKA

ADDRA [11:0]

ADDRA [11:0]

ADDRA [11:0]

DIA [3:0]

DIA [3:0]

DIA [3:0]

WEB

WEB

WEB

ENB

ENB

ENB

SSRB

SSRB

SSRB

ADDRB [10:0]

DOPB [0:0]
DOB [7:0]

CLKB
ADDRB [9:0]

RAMB16_S4_S36

ENA

CLKA

CLKB

DOB [3:0]

CLKB

DOPB [1:0]
DOB [15:0]

CLKB

DOA [3:0]

DOPB [3:0]
DOB [31:0]

ADDRB [8:0]

DIB [7:0]

DIB [15:0]

DIB [31:0]

DIPB [0:0]

DIPB [1:0]

DIPB [3:0]
X9467

RAMB16_S2_S2 through RAMB16_S4_S36 Representations

Libraries Guide
ISE 6.3i

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1051

WEA

RAMB16_Sm_Sn

RAMB16_S9_S9

WEA

SSRA

DOPA [0:0]

SSRA
CLKA

CLKA
ADDRA [10:0]

RAMB16_S9_S18

WEA

DOA [7:0]

DOPA [0:0]
DOA [7:0]

SSRA

DIA [7:0]

DIPA [0:0]

DIPA [0:0]

WEB

WEB

WEB

ENB

ENB

CLKB

DOPB [0:0]
DOB [7:0]

SSRB
CLKB

ENB
DOPB [1:0]
DOB [15:0]

ADDRB [9:0]

ADDRB [10:0]

DOA [7:0]

ADDRA [10:0]

ADDRA [10:0]

DIPA [0:0]

SSRB

DOPA [0:0]

CLKA

DIA [7:0]

DIA [7:0]

RAMB16_S9_S36

ENA

ENA

ENA

SSRB

DOPB [3:0]

CLKB

DOB [31:0]

ADDRB [8:0]

DIB [7:0]

DIB [15:0]

DIB [31:0]

DIPB [0:0]

DIPB [1:0]

DIPB [3:0]

WEA RAMB16_S18_S18

WEA RAMB16_S18_S36

ENA

ENA

ENA

DOPA [1:0]

SSRA

SSRA

DOPA [3:0]

DOA [15:0]

CLKA

CLKA

DOA [31:0]

SSRA
CLKA

WEA RAMB16_S36_S36

DOPA [1:0]
DOA [15:0]

ADDRA [9:0]

ADDRA [9:0]

ADDRA [8:0]

DIA [15:0]

DIA [15:0]

DIA [31:0]

DIPA [1:0]

DIPA [1:0]

DIPA [3:0]

WEB

WEB

WEB

ENB

ENB

SSRB
CLKB
ADDRB [9:0]

DOPB [1:0]
DOB [15:0]

SSRB
CLKB
ADDRB [8:0]

ENB
DOPB [3:0]
DOB [31:0]

SSRB
CLKB

DOPB [3:0]
DOB [31:0]

ADDRB [8:0]

DIB [15:0]

DIB [31:0]

DIB [31:0]

DIPB [1:0]

DIPB [3:0]

DIPB [3:0]
X9468

RAMB16_S9_S9 through RAMB16_S36_S36 Representations

The RAMB16_Sm_Sn components listed in the following table are dual-ported
dedicated random access memory blocks with synchronous write capability. Each
block RAM port has 16384 bits of data memory. Ports configured as 9, 18, or 36-bits
wide have an additional 2048 bits of parity memory. Each port is independent of the
other while accessing the same set of 16384 data memory cells. Each port is
independently configured to a specific data width. The possible port and cell
configurations are listed in the following table.

1052

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ISE 6.3i

RAMB16_Sm_Sn

Port A
Component

Data Cellsa

Port B
Data Bus

Cellsa

Address
Bus

Parity
Bus

Data Cellsa

Parity

Parity
Cellsa

Address
Bus

Data Bus

Parity
Bus

RAMB16_S1_
S1

16384 x 1

(13:0)

(0:0)

16384 x 1

(13:0)

(0:0)

RAMB16_S1_
S2

16384 x 1

(13:0)

(0:0)

8192 x 2

(12:0)

(1:0)

RAMB16_S1_
S4

16384 x 1

(13:0)

(0:0)

4096 x 4

(11:0)

(3:0)

RAMB16_S1_
S9

16384 x 1

(13:0)

(0:0)

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

RAMB16_S1_
S18

16384 x 1

(13:0)

(0:0)

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

RAMB16_S1_
S36

16384 x 1

(13:0)

(0:0)

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

RAMB16_S2_
S2

8192 x 2

(12:0)

(1:0)

8192 x 2

(12:0)

(1:0)

RAMB16_S2_
S4

8192 x 2

(12:0)

(1:0)

4096 x 4

(11:0)

(3:0)

RAMB16_S2_
S9

8192 x 2

(12:0)

(1:0)

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

RAMB16_S2_
S18

8192 x 2

(12:0)

(1:0)

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

RAMB16_S2_
S36

8192 x 2

(12:0)

(1:0)

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

RAMB16_S4_
S4

4096 x 4

(11:0)

(3:0)

4096 x 4

(11:0)

(3:0)

RAMB16_S4_
S9

4096 x 4

(11:0)

(3:0)

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

RAMB16_S4_
S18

4096 x 4

(11:0)

(3:0)

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

RAMB16_S4_
S36

4096 x 4

(11:0)

(3:0)

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

RAMB16_S9_
S9

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

RAMB16_S9_
S18

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

RAMB16_S9_
S36

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

RAMB16_S18
_S18

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

RAMB16_S18
_S36

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

RAMB16_S36
_S36

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

aDepth x Width

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ISE 6.3i

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1053

RAMB16_Sm_Sn

Each port is fully synchronous with independent clock pins. All port A input pins
have setup time referenced to the CLKA pin and its data output bus DOA has a clockto-out time referenced to the CLKA. All port B input pins have setup time referenced
to the CLKB pin and its data output bus DOB has a clock-to-out time referenced to the
CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no
data is written and the outputs (DOA and DOPA) retain the last state. When ENA is
High and reset (SSRA) is High, DOA and DOPA are set to SRVAL_A during the Lowto-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents
reflect the data at DIA and DIPA. When ENA is High and WEA is Low, the data stored
in the RAM address (ADDRA) is read during the Low-to-High clock transition. By
default, WRITE_MODE_A=WRITE_FIRST, when ENA and WEA are High, the data
on the data inputs (DIA and DIPA) is loaded into the word selected by the write
address (ADDRA) during the Low-to-High clock transition and the data outputs
(DOA and DOPA) reflect the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no
data is written and the outputs (DOB and DOPB) retain the last state. When ENB is
High and reset (SSRB) is High, DOB and DOPB are set to SRVAL_B during the Lowto-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents
reflect the data at DIB and DIPB. When ENB is High and WEB is Low, the data stored
in the RAM address (ADDRB) is read during the Low-to-High clock transition. By
default, WRITE_MODE_B=WRITE_FIRST, when ENB and WEB are High, the data on
the data inputs (DIB and PB) are loaded into the word selected by the write address
(ADDRB) during the Low-to-High clock transition and the data outputs (DOB and
DOPB) reflect the selected (addressed) word.
The above descriptions assume active High control pins (ENA, WEA, SSRA, CLKA,
ENB, WEB, SSRB, and CLKB). However, the active level can be changed by placing an
inverter on the port. Any inverter placed on a RAMB16 port is absorbed into the block
and does not use a CLB resource.
Port A Truth Table
Inputs
GS
R

ENA

Outputs

SSR WE CLK ADD

A
A
A
RA

DIA

DIPA

DOA

DOPA

RAM Contents
Data RAM

Parity RAM

INIT_A

INIT_A

No Chg

No Chg

No Chg

No Chg

No Chg

No Chg

SRVAL_A

SRVAL_A

No Chg

No Chg

addr

data

pdata SRVAL_A

SRVAL_A

RAM(addr)
=>data

RAM(addr) =>pdata

addr

RAM(addr)

No Chg

No Chg

1054

RAM(addr)

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ISE 6.3i

RAMB16_Sm_Sn

Port A Truth Table

Inputs
GS
R
0

ENA
1

Outputs

SSR WE CLK ADD

A
A
A
RA
0

addr

DIA

DIPA

DOA

DOPA

RAM Contents

data

pdata No Chg1
No Chg1
RAM(addr)
RAM (addr)2 RAM(addr)2 =>data
data3
pdata3

RAM(addr) =>pdata

GSR=Global Set Reset

INIT_A=Value specified by the INIT_A attribute for output register. Default is all zeros.
SRVAL_A=register value
addr=RAM address
RAM(addr)=RAM contents at address ADDR
data=RAM input data
pdata=RAM parity data
1WRITE_MODE_A=NO_CHANGE
2WRITE_MODE_A=READ_FIRST
3WRITE_MODE_A=WRITE_FIRST

Port B Truth Table

Inputs
GS
R

ENB

Outputs

SSR WE CLK ADD

B
B
B
RB

DIB

DIPB

DOB

DOPB

RAM Contents
Data RAM

Parity RAM

INIT_B

INIT_B

No Chg

No Chg

No Chg

No Chg

No Chg

No Chg

SRVAL_B

SRVAL_B

No Chg

No Chg

addr

data

pdata SRVAL_B

SRVAL_B

RAM(addr)
=>data

RAM(addr) =>pdata

addr

RAM(addr)

RAM(addr)

No Chg

No Chg

Chg1

Chg1

addr

data

No
RAM(addr)
pdata No
RAM (addr)2 RAM(addr)2 =>data
data3
pdata3

RAM(addr) =>pdata

GSR=Global Set Reset

INIT_B=Value specified by the INIT_B attribute for output registers. Default is all zeros.
SRVAL_B=register value
addr=RAM address
RAM(addr)=RAM contents at address ADDR
data=RAM input data
pdata=RAM parity data
1WRITE_MODE_B=NO_CHANGE
2WRITE_MODE_B=READ_FIRST
3WRITE_MODE_B=WRITE_FIRST

Libraries Guide
ISE 6.3i

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1055

RAMB16_Sm_Sn

Address Mapping
Each port accesses the same set of 18432 memory cells using an addressing scheme
that is dependent on the width of the port. For all port widths, 16384 memory cells are
available for data as shown in the Port Address Mapping for Data table. For 9-, 18-,
and 36-bit wide ports, 2408 parity memory cells are also available as shown in Port
Address Mapping for Parity table. The physical RAM location that is addressed for a
particular width is determined from the following formula.
Start=((ADDR port+1)*(Widthport)) -1
End=(ADDRport)*(Widthport)

The following tables shows address mapping for each port width.
Port Address Mapping for Data
Data
Width

Port Data Addresses

16384

8192

4096

2048

16

1024

32

512

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
15

14

13

07

12

11

06

10

09

05

08

07

04

03

06

05

03

02

11 10 09 08 07 06 05 04 03 02 01 00
04

03

02

02

01

01

01

00
00

00

01

00
00

Port Address Mapping for Parity

Parity Width

Port Parity Addresses

2048

1024

512

03

02

01

01

00
00

00

Initializing Memory Contents of a Dual-Port RAMB16

You can use the INIT_xx attributes to specify an initialization value for the memory
contents of a RAMB16 during device configuration. The initialization of each
RAMB16_Sm_Sn is set by 64 initialization attributes (INIT_00 through INIT_3F) of 64
hex values for a total of 16384 bits.
You can use the INITP_xx attributes to specify an initial value for the parity memory
during device configuration or assertion. The initialization of the parity memory for
ports configured for 9, 18, or 36 bits is set by 8 initialization attributes (INITP_00
through INITP_07) of 64 hex values for a total of 2048 bits.
If any INIT_xx or INITP_xx attribute is not specified, it is configured as zeros. Partial
strings are padded with zeros to the left.
See the Constraints Guide for more information on these attributes.

1056

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ISE 6.3i

RAMB16_Sm_Sn

Initializing the Output Register of a Dual-Port RAMB16

In Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, each bit in an output register
can be initialized at power on (when GSR is high) to either a 0 or 1. In addition, the
initial state specified for power on can be different than the state that results from
assertion of a set/reset. Four properties control initialization of the output register for
a dual-port RAMB16: INIT_A, INIT_B, SRVAL_A, and SRVAL_B. The INIT_A
attribute specifies the output register value at power on for port A and the INIT_B
attribute specifies the value for port B. You can use the SRVAL_A attribute to define
the state resulting from assertion of the SSR (set/reset) input on port A. You can use
the SRVAL_B attribute to define the state resulting from assertion of the SSR input on
port B.
The INIT_A, INIT_B, SRVAL_A, and SRVAL_B attributes specify the initialization
value as a hexadecimal string. The value is dependent upon the port width. For
example, for a RAMB16_S1_S4 with port A width equal to 1 and port B width equal to
4, the port A output register contains 1 bit and the port B output register contains 4
bits. Therefore, the INIT_A or SRVAL_A value can only be specified as a 1 or 0. For
port B, the output register contains 4 bits. In this case, you can use INIT_B or
SRVAL_B to specify a hexadecimal value from 0 through F to initialize the 4 bits of the
output register.
For those ports that include parity bits, the parity portion of the output register is
specified in the high order bit position of the INIT_A, INIT_B, SRVAL_A, or SRVAL_B
value.
The INIT and SRVAL attributes default to zero if they are not set by the user.
See the Constraints Guide for more information on these attributes.

Write Mode Selection

The WRITE_MODE_A attribute controls the memory and output contents of port A
for a dual-port RAMB16. The WRITE_MODE_B attribute does the same for port B. By
default, both WRITE_MODE_A and WRITE_MODE_B are set to WRITE_FIRST. This
means that input is read, written to memory, and then passed to output. You can set
the write mode for port A and/or port B to READ_FIRST to read the memory
contents, pass the memory contents to the outputs, and then write the input to
memory. Or, you can set the write mode to NO_CHANGE to have the input written to
memory without changing the output. The Port A and Port B Conflict Resolution
section describes how read/write conflicts are resolved when both port A and port B
are attempting to read/write to the same memory cells.

Port A and Port B Conflict Resolution

Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X block SelectRAM is True DualPort RAM that allows both ports to simultaneously access the same memory cell.
When one port writes to a given memory cell, the other port must not address that
memory cell (for a write or a read) within the clock-to-clock setup window. For a list
of specifics of conflict resolution for port and memory cell write operations that have
either a clock common to both ports or synchronous clocks on each port, see Virtex-II
Handbook, Chapter 2, Design Considerations, Using BlockSelectRAM Memory, Conflict
Resolution.
The following tables summarize the collision detection behavior of the dual-port
RAMB16 based on the WRITE_MODE_A and WRITE_MODE_B settings.

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1057

RAMB16_Sm_Sn

WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=NO_CHANGE

WEA WEB CLKA CLKB
0

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

Data
RAM

Parity
Ram

No Chg No Chg

DIA

DIB

DIPA

DIPB

No Chg

No Chg

DIA

DIPA

DIA

DIB

DIPA

DIPB

No Chg

No Chg

DIB

DIPB

DIA

DIB

DIPA

DIPB

No Chg No Chg No Chg No Chg

WRITE_MODE_A=READ_FIRST and WRITE_MODE_B=READ_FIRST

Data
RAM

Parity
Ram

WEA

WEB

CLKA

CLKB

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIA

DIPA

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIB

DIPB

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

No Chg No Chg

WRITE_MODE_A= WRITE_FIRST and WRITE_MODE_B=WRITE_FIRST

Data
RAM

Parity
Ram

WEA

WEB

CLKA

CLKB

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIA

DIB

DIPA

DIPB

DIA

DIPA

DIA

DIPA

DIA

DIB

DIPA

DIPB

DIB

DIPB

DIB

DIPB

DIA

DIB

DIPA

DIPB

No Chg No Chg

WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=READ_FIRST

Data
RAM

Parity
Ram

WEA

WEB

CLKA

CLKB

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIA

DIB

DIPA

DIPB

No Chg

No Chg

DIA

DIPA

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIB

DIPB

DIA

DIB

DIPA

DIPB

No Chg

No Chg

DIB

DIPB

No Chg No Chg

WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=WRITE_FIRST

WEA

WEB

CLKA

CLKB

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIA

DIB

DIPA

DIPB

No Chg

No Chg

1058

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Data
RAM

Parity
Ram

No Chg No Chg
DIA

DIPA

Libraries Guide
ISE 6.3i

RAMB16_Sm_Sn

WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=WRITE_FIRST

WEA

WEB

CLKA

CLKB

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

Data
RAM

Parity
Ram

DIA

DIB

DIPA

DIPB

DIB

DIPB

DIB

DIPB

DIA

DIB

DIPA

DIPB

No Chg

No Chg

WRITE_MODE_A=READ_FIRST and WRITE_MODE_B=WRITE_FIRST

Data
RAM

Parity
Ram

WEA

WEB

CLKA

CLKB

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIA

DIPA

DIA

DIB

DIPA

DIPB

DIB

DIPB

DIB

DIPB

DIA

DIB

DIPA

DIPB

DIB

DIPB

DIA

DIPA

No Chg No Chg

Usage
For HDL, these design elements can be inferred or instantiated. The instantiation code
is shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template for RAMB16_S1_S1, RAMB16_S1_S2,

RAMB16_S1_S4, RAMB16_S2_S2, RAMB16_S2_S4, and
RAMB16_S4_S4
-- RAMB16_S1: Virtex-II/II-Pro, Spartan-3 16kx1 Single-Port RAM
-- Xilinx HDL Language Template version 6.1i
RAMB16_S1_inst : RAMB16_S1
generic map (
-- The following generics are only necessary if you wish to
change the default behavior.
INIT => "0", -- Value of output RAM registers at startup
SRVAL => "0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
NO_CHANGE
-- The following generic INIT_xx declarations are only necessary
if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
INIT_00
INIT_01
INIT_02
INIT_03
INIT_04
INIT_05
INIT_06
INIT_07
INIT_08
INIT_09
INIT_0A
INIT_0B
INIT_0C
INIT_0D
INIT_0E

Libraries Guide
ISE 6.3i

=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>

X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",

www.xilinx.com
1-800-255-7778

1059

INIT_0F
INIT_10
INIT_11
INIT_12
INIT_13
INIT_14
INIT_15
INIT_16
INIT_17
INIT_18
INIT_19
INIT_1A
INIT_1B
INIT_1C
INIT_1D
INIT_1E
INIT_1F
INIT_20
INIT_21
INIT_22
INIT_23
INIT_24
INIT_25
INIT_26
INIT_27
INIT_28
INIT_29
INIT_2A
INIT_2B
INIT_2C
INIT_2D
INIT_2E
INIT_2F
INIT_30
INIT_31
INIT_32
INIT_33
INIT_34
INIT_35
INIT_36
INIT_37
INIT_38
INIT_39
INIT_3A
INIT_3B
INIT_3C
INIT_3D
INIT_3E
INIT_3F

RAMB16_Sm_Sn

=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>

X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000",
X"0000000000000000000000000000000000000000000000000000000000000000")

port map (
DO => DO,
-- 1-bit
ADDR => ADDR, -CLK => CLK,
-DI => DI,
-EN => EN,
-SSR => SSR,
-WE => WE
-);

Data Output
14-bit Address Input
Clock
1-bit Data Input
RAM Enable Input
Synchronous Set/Reset Input
Write Enable Input

-- End of RAMB16_S1_inst instantiation

1060

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Libraries Guide
ISE 6.3i

RAMB16_Sm_Sn

-- Component Attribute specification for RAM16X1D

-- should be placed after architecture declaration but
-- before the begin keyword
Put attributes if necessary
-- Component Instantiation for RAMB16_Sm_Sn should be placed
-- in architecture after the begin keyword
-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.

RAMB16_Sm_Sn INSTANCE_NAME : RAMB16_Sm_Sn

-- synthesis translate_off
generic map (
INIT_00 => vector_value,
INIT_01 => vector_value,
INIT_02 => vector_value,
INIT_03 => vector_value,
INIT_04 => vector_value,
INIT_05 => vector_value,
INIT_06 => vector_value,
INIT_07 => vector_value,
INIT_08 => vector_value,
INIT_09 => vector_value,
INIT_0A => vector_value,
INIT_0B => vector_value,
INIT_0C => vector_value,
INIT_0D => vector_value,
INIT_0E => vector_value,
INIT_0F => vector_value,
INIT_10 => vector_value,
INIT_11 => vector_value,
INIT_12 => vector_value,
INIT_13 => vector_value,
INIT_14 => vector_value,
INIT_15 => vector_value,
INIT_16 => vector_value,
INIT_17 => vector_value,
INIT_18 => vector_value,
INIT_19 => vector_value,
INIT_1A => vector_value,
INIT_1B => vector_value,
INIT_1C => vector_value,
INIT_1D => vector_value,
INIT_1E => vector_value,
INIT_1F => vector_value,
INIT_20 => vector_value,
INIT_21 => vector_value,
INIT_22 => vector_value,
INIT_23 => vector_value,
INIT_24 => vector_value,
INIT_25 => vector_value,
INIT_26 => vector_value,
INIT_27 => vector_value,
INIT_28 => vector_value,
INIT_29 => vector_value,

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1061

RAMB16_Sm_Sn

INIT_2A => vector_value,

INIT_2B => vector_value,
INIT_2C => vector_value,
INIT_2D => vector_value,
INIT_2E => vector_value,
INIT_2F => vector_value,
INIT_30 => vector_value,
INIT_31 => vector_value,
INIT_32 => vector_value,
INIT_33 => vector_value,
INIT_34 => vector_value,
INIT_35 => vector_value,
INIT_36 => vector_value,
INIT_37 => vector_value,
INIT_38 => vector_value,
INIT_39 => vector_value,
INIT_3A => vector_value,
INIT_3B => vector_value,
INIT_3C => vector_value,
INIT_3D => vector_value,
INIT_3E => vector_value,
INIT_3F => vector_value,
INIT_A => bit_value,
INIT_B => bit_value,
INITP_00 => vector_value,
INITP_01 => vector_value,
INITP_02 => vector_value,
INITP_03 => vector_value,
INITP_04 => vector_value,
INITP_05 => vector_value,
INITP_06 => vector_value,
INITP_07 => vector_value,
SRVAL_A => bit_value,
SRVAL_B => bit_value,
WRITE_MODE_A => string_value,
WRITE_MODE_B => string_value)
-- synopsys translate_on
port map (DOA => user_DOA,
DOB => user_DOB,
ADDRA => user_ADDRA,
ADDRB => user_ADDRB,
CLKA => user_CLKA,
CLKB => user_CLKB,
DIA => user_DIA,
DIB => user_DIB,
ENA => user_ENA,
ENB => user_ENB,
SSRA => user_SSRA,
SSRB => user_SSRB,
WEA => user_WEA,
WEB => user_WEB);

Verilog Instantiation Template for RAMB16_S1_S1,

RAMB16_S1_S2, RAMB16_S1_S4, RAMB16_S2_S2,
RAMB16_S2_S4, and RAMB16_S4_S4
-- Note that the use of INIT below is for simulation only. For examples

1062

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Libraries Guide
ISE 6.3i

RAMB16_Sm_Sn

-- of how to include INIT as an implementation constraint,

-- please refer to the Constraints Guide.
RAMB16_Sm_Sn user_instance_name (.DOA (user_DOA),
.DOB (user_DOB),
.ADDRA (user_ADDRA),
.ADDRB (user_ADDRB),
.CLKA (user_CLKA),
.CLKB (user_CLKB),
.DIA (user_DIA),
.DIB (user_DIB),
.ENA (user_ENA),
.ENB (user_ENB),
.SSRA (user_SSRA),
.SSRB (user_SSRB),
.WEA (user_WEA),
.WEB (user_WEB));
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

Libraries Guide
ISE 6.3i

user_instance_name.INIT_00
user_instance_name.INIT_01
user_instance_name.INIT_02
user_instance_name.INIT_03
user_instance_name.INIT_04
user_instance_name.INIT_05
user_instance_name.INIT_06
user_instance_name.INIT_07
user_instance_name.INIT_08
user_instance_name.INIT_09
user_instance_name.INIT_0A
user_instance_name.INIT_0B
user_instance_name.INIT_0C
user_instance_name.INIT_0D
user_instance_name.INIT_0E
user_instance_name.INIT_0F
user_instance_name.INIT_10
user_instance_name.INIT_11
user_instance_name.INIT_12
user_instance_name.INIT_13
user_instance_name.INIT_14
user_instance_name.INIT_15
user_instance_name.INIT_16
user_instance_name.INIT_17
user_instance_name.INIT_18
user_instance_name.INIT_19
user_instance_name.INIT_1A
user_instance_name.INIT_1B
user_instance_name.INIT_1C
user_instance_name.INIT_1D
user_instance_name.INIT_1E
user_instance_name.INIT_1F
user_instance_name.INIT_20
user_instance_name.INIT_21
user_instance_name.INIT_22
user_instance_name.INIT_23
user_instance_name.INIT_24
user_instance_name.INIT_25
user_instance_name.INIT_26
user_instance_name.INIT_27

www.xilinx.com
1-800-255-7778

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;

1063

RAMB16_Sm_Sn

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

user_instance_name.INIT_28 = 256_bit_hex_value;
user_instance_name.INIT_29 = 256_bit_hex_value;
user_instance_name.INIT_2A = 256_bit_hex_value;
user_instance_name.INIT_2B = 256_bit_hex_value;
user_instance_name.INIT_2C = 256_bit_hex_value;
user_instance_name.INIT_2D = 256_bit_hex_value;
user_instance_name.INIT_2E = 256_bit_hex_value;
user_instance_name.INIT_2F = 256_bit_hex_value;
user_instance_name.INIT_30 = 256_bit_hex_value;
user_instance_name.INIT_31 = 256_bit_hex_value;
user_instance_name.INIT_32 = 256_bit_hex_value;
user_instance_name.INIT_33 = 256_bit_hex_value;
user_instance_name.INIT_34 = 256_bit_hex_value;
user_instance_name.INIT_35 = 256_bit_hex_value;
user_instance_name.INIT_36 = 256_bit_hex_value;
user_instance_name.INIT_37 = 256_bit_hex_value;
user_instance_name.INIT_38 = 256_bit_hex_value;
user_instance_name.INIT_39 = 256_bit_hex_value;
user_instance_name.INIT_3A = 256_bit_hex_value;
user_instance_name.INIT_3B = 256_bit_hex_value;
user_instance_name.INIT_3C = 256_bit_hex_value;
user_instance_name.INIT_3D = 256_bit_hex_value;
user_instance_name.INIT_3E = 256_bit_hex_value;
user_instance_name.INIT_3F = 256_bit_hex_value;
user_instance_name.INIT_A = bit_value;
user_instance_name.INIT_B = bit_value;
user_instance_name.INITP_00 = 256_bit_hex_value;
user_instance_name.INITP_01 = 256_bit_hex_value;
user_instance_name.INITP_02 = 256_bit_hex_value;
user_instance_name.INITP_03 = 256_bit_hex_value;
user_instance_name.INITP_04 = 256_bit_hex_value;
user_instance_name.INITP_05 = 256_bit_hex_value;
user_instance_name.INITP_06 = 256_bit_hex_value;
user_instance_name.INITP_07 = 256_bit_hex_value;
user_instance_name.SRVAL_A = bit_value;
user_instance_name.SRVAL_B = bit_value;
user_instance_name.WRITE_MODE_A = string_value;
user_instance_name.WRITE_MODE_B = string_value;

VHDL Instantiation Template for RAMB16_S1_S9,

RAMB16_S1_S18, RAMB16_S1_S36, RAMB16_S2_S9,
RAMB16_S2_S18, RAMB16_S2_S36, RAMB16_S4_S9,
RAMB16_S4_S18, and RAMB16_S4_S36
-- Component Declaration for RAMB16_S1_{S9 | S18 | S36}, RAMB16_S2_{S9 |
S18 | S36}, or RAMB16_S4_{S9 | S18 | S36} should be placed
-- after architecture statement but before begin keyword
-- Note that the use of INIT below is for simulation only
-- For examples on how to include INIT as an implementation
-- constraint,please refer to the Constraints Guide
component RAMB16_Sm_Sn
-- synthesis translate_off
generic (
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

1064

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Libraries Guide
ISE 6.3i

RAMB16_Sm_Sn

INIT_02 : bit_vector
INIT_03 : bit_vector
INIT_04 : bit_vector
INIT_05 : bit_vector
INIT_06 : bit_vector
INIT_07 : bit_vector
INIT_08 : bit_vector
INIT_09 : bit_vector
INIT_0A : bit_vector
INIT_0B : bit_vector
INIT_0C : bit_vector
INIT_0D : bit_vector
INIT_0E : bit_vector
INIT_0F : bit_vector
INIT_10 : bit_vector
INIT_11 : bit_vector
INIT_12 : bit_vector
INIT_13 : bit_vector
INIT_14 : bit_vector
INIT_15 : bit_vector
INIT_16 : bit_vector
INIT_17 : bit_vector
INIT_18 : bit_vector
INIT_19 : bit_vector
INIT_1A : bit_vector
INIT_1B : bit_vector
INIT_1C : bit_vector
INIT_1D : bit_vector
INIT_1E : bit_vector
INIT_1F : bit_vector
INIT_20 : bit_vector
INIT_21 : bit_vector
INIT_22 : bit_vector
INIT_23 : bit_vector
INIT_24 : bit_vector
INIT_25 : bit_vector
INIT_26 : bit_vector
INIT_27 : bit_vector
INIT_28 : bit_vector
INIT_29 : bit_vector
INIT_2A : bit_vector
INIT_2B : bit_vector
INIT_2C : bit_vector
INIT_2D : bit_vector
INIT_2E : bit_vector
INIT_2F : bit_vector
INIT_30 : bit_vector
INIT_31 : bit_vector
INIT_32 : bit_vector
INIT_33 : bit_vector
INIT_34 : bit_vector
INIT_35 : bit_vector
INIT_36 : bit_vector
INIT_37 : bit_vector
INIT_38 : bit_vector
INIT_39 : bit_vector
INIT_3A : bit_vector
INIT_3B : bit_vector
INIT_3C : bit_vector
INIT_3D : bit_vector
INIT_3E : bit_vector
INIT_3F : bit_vector
INIT_A : bit_vector
INIT_B : bit_vector

Libraries Guide
ISE 6.3i

:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0000000000000000000000000000000000000000000000000000000000000000";
:= X"0";
:= X"0";

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1-800-255-7778

1065

INITP_00
INITP_01
INITP_02
INITP_03
INITP_04
INITP_05
INITP_06
INITP_07

RAMB16_Sm_Sn

:
:
:
:
:
:
:
:

bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector
bit_vector

:=
:=
:=
:=
:=
:=
:=
:=

X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";
X"0000000000000000000000000000000000000000000000000000000000000000";

SRVAL_A : bit_vector
:= X"0";
SRVAL_B : bit_vector
:= X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
);
-- synthesis translate_on
port (DOA : out STD_LOGIC_VECTOR (n downto 0);
DOB : out STD_LOGIC_VECTOR (n downto 0);
DOPB : out STD_LOGIC_VECTOR (n downto 0);
ADDRA : in STD_LOGIC_VECTOR (n downto 0);
ADDRB : in STD_LOGIC_VECTOR (n downto 0);
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
DIA : in STD_LOGIC_VECTOR (n downto 0);
DIB : in STD_LOGIC_VECTOR (n downto 0);
DIPB : in STD_LOGIC_VECTOR (n downto 0);
ENA : in STD_ULOGIC;
ENB : in STD_ULOGIC;
SSRA : in STD_ULOGIC;
SSRB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC);
end component;

-- Component Attribute specification for RAMB16_Sm_Sn

-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here
-- Component Instantiation for RAMB16_Sm_Sn should be placed
-- in architecture after the begin keyword
-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.

RAMB16_Sm_Sn INSTANCE_NAME : RAMB16_Sm_Sn

-- synthesis translate_off
generic map (
INIT_00 => vector_value,
INIT_01 => vector_value,
INIT_02 => vector_value,
INIT_03 => vector_value,
INIT_04 => vector_value,
INIT_05 => vector_value,
INIT_06 => vector_value,

1066

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Libraries Guide
ISE 6.3i

RAMB16_Sm_Sn

INIT_07 => vector_value,

INIT_08 => vector_value,
INIT_09 => vector_value,
INIT_0A => vector_value,
INIT_0B => vector_value,
INIT_0C => vector_value,
INIT_0D => vector_value,
INIT_0E => vector_value,
INIT_0F => vector_value,
INIT_10 => vector_value,
INIT_11 => vector_value,
INIT_12 => vector_value,
INIT_13 => vector_value,
INIT_14 => vector_value,
INIT_15 => vector_value,
INIT_16 => vector_value,
INIT_17 => vector_value,
INIT_18 => vector_value,
INIT_19 => vector_value,
INIT_1A => vector_value,
INIT_1B => vector_value,
INIT_1C => vector_value,
INIT_1D => vector_value,
INIT_1E => vector_value,
INIT_1F => vector_value,
INIT_20 => vector_value,
INIT_21 => vector_value,
INIT_22 => vector_value,
INIT_23 => vector_value,
INIT_24 => vector_value,
INIT_25 => vector_value,
INIT_26 => vector_value,
INIT_27 => vector_value,
INIT_28 => vector_value,
INIT_29 => vector_value,
INIT_2A => vector_value,
INIT_2B => vector_value,
INIT_2C => vector_value,
INIT_2D => vector_value,
INIT_2E => vector_value,
INIT_2F => vector_value,
INIT_30 => vector_value,
INIT_31 => vector_value,
INIT_32 => vector_value,
INIT_33 => vector_value,
INIT_34 => vector_value,
INIT_35 => vector_value,
INIT_36 => vector_value,
INIT_37 => vector_value,
INIT_38 => vector_value,
INIT_39 => vector_value,
INIT_3A => vector_value,
INIT_3B => vector_value,
INIT_3C => vector_value,
INIT_3D => vector_value,
INIT_3E => vector_value,
INIT_3F => vector_value,
INIT_A => bit_value,

Libraries Guide
ISE 6.3i

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1-800-255-7778

1067

RAMB16_Sm_Sn

INIT_B => bit_value,

INITP_00 => vector_value,
INITP_01 => vector_value,
INITP_02 => vector_value,
INITP_03 => vector_value,
INITP_04 => vector_value,
INITP_05 => vector_value,
INITP_06 => vector_value,
INITP_07 => vector_value,
SRVAL_A => bit_value,
SRVAL_B => bit_value,
WRITE_MODE_A => string_value,
WRITE_MODE_B => string_value)
-- synopsys translate_on
port map (DOA => user_DOA,
DOB => user_DOB,
DOPB => user_DOPB,
ADDRA => user_ADDRA,
ADDRB => user_ADDRB,
CLKA => user_CLKA,
CLKB => user_CLKB,
DIA => user_DIA,
DIB => user_DIB,
DIPB => user_DIPB,
ENA => user_ENA,
ENB => user_ENB,
SSRA => user_SSRA,
SSRB => user_SSRB,
WEA => user_WEA,
WEB => user_WEB);

Verilog Instantiation Template for RAMB16_S1_S9,

RAMB16_S1_S18, RAMB16_S1_S36, RAMB16_S2_S9,
RAMB16_S2_S18, RAMB16_S2_S36, RAMB16_S4_S9,
RAMB16_S4_S18, and RAMB16_S4_S36
-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.

RAMB16_Sm_Sn user_instance_name (.DOA (user_DOA),

.DOB (user_DOB),
.DOPB (user_DOPB),
.ADDRA (user_ADDRA),
.ADDRB (user_ADDRB),
.CLKA (user_CLKA),
.CLKB (user_CLKB),
.DIA (user_DIA),
.DIB (user_DIB),
.DIPB (user_DIB),
.ENA (user_ENA),
.ENB (user_ENB),
.SSRA (user_SSRA),
.SSRB (user_SSRB),
.WEA (user_WEA),

1068

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1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sm_Sn

.WEB (user_WEB));
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
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defparam
defparam
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defparam
defparam
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defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

Libraries Guide
ISE 6.3i

user_instance_name.INIT_00
user_instance_name.INIT_01
user_instance_name.INIT_02
user_instance_name.INIT_03
user_instance_name.INIT_04
user_instance_name.INIT_05
user_instance_name.INIT_06
user_instance_name.INIT_07
user_instance_name.INIT_08
user_instance_name.INIT_09
user_instance_name.INIT_0A
user_instance_name.INIT_0B
user_instance_name.INIT_0C
user_instance_name.INIT_0D
user_instance_name.INIT_0E
user_instance_name.INIT_0F
user_instance_name.INIT_10
user_instance_name.INIT_11
user_instance_name.INIT_12
user_instance_name.INIT_13
user_instance_name.INIT_14
user_instance_name.INIT_15
user_instance_name.INIT_16
user_instance_name.INIT_17
user_instance_name.INIT_18
user_instance_name.INIT_19
user_instance_name.INIT_1A
user_instance_name.INIT_1B
user_instance_name.INIT_1C
user_instance_name.INIT_1D
user_instance_name.INIT_1E
user_instance_name.INIT_1F
user_instance_name.INIT_20
user_instance_name.INIT_21
user_instance_name.INIT_22
user_instance_name.INIT_23
user_instance_name.INIT_24
user_instance_name.INIT_25
user_instance_name.INIT_26
user_instance_name.INIT_27
user_instance_name.INIT_28
user_instance_name.INIT_29
user_instance_name.INIT_2A
user_instance_name.INIT_2B
user_instance_name.INIT_2C
user_instance_name.INIT_2D
user_instance_name.INIT_2E
user_instance_name.INIT_2F
user_instance_name.INIT_30
user_instance_name.INIT_31
user_instance_name.INIT_32
user_instance_name.INIT_33
user_instance_name.INIT_34
user_instance_name.INIT_35
user_instance_name.INIT_36
user_instance_name.INIT_37

www.xilinx.com
1-800-255-7778

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256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;

1069

RAMB16_Sm_Sn

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

user_instance_name.INIT_38 = 256_bit_hex_value;
user_instance_name.INIT_39 = 256_bit_hex_value;
user_instance_name.INIT_3A = 256_bit_hex_value;
user_instance_name.INIT_3B = 256_bit_hex_value;
user_instance_name.INIT_3C = 256_bit_hex_value;
user_instance_name.INIT_3D = 256_bit_hex_value;
user_instance_name.INIT_3E = 256_bit_hex_value;
user_instance_name.INIT_3F = 256_bit_hex_value;
user_instance_name.INIT_A = bit_value;
user_instance_name.INIT_B = bit_value;
user_instance_name.INITP_00 = 256_bit_hex_value;
user_instance_name.INITP_01 = 256_bit_hex_value;
user_instance_name.INITP_02 = 256_bit_hex_value;
user_instance_name.INITP_03 = 256_bit_hex_value;
user_instance_name.INITP_04 = 256_bit_hex_value;
user_instance_name.INITP_05 = 256_bit_hex_value;
user_instance_name.INITP_06 = 256_bit_hex_value;
user_instance_name.INITP_07 = 256_bit_hex_value;
user_instance_name.SRVAL_A = bit_value;
user_instance_name.SRVAL_B = bit_value;
user_instance_name.WRITE_MODE_A = string_value;
user_instance_name.WRITE_MODE_B = string_value;

VHDL Instantiation Template RAMB16_S9_S9, RAMB16_S9_S18,

RAMB16_S9_S36, RAMB16_S18_S18, RAMB16_S18_S36, and
RAMB16_S36_S36
-- RAMB16_S18: Virtex-II/II-Pro, Spartan-3 1k x 16 + 2 Parity bits
Single-Port RAM
-- Xilinx HDL Language Template version 6.1i
RAMB16_S18_inst : RAMB16_S18
generic map (
-- The following generics are only necessary if you wish to
change the default behavior.
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
NO_CHANGE
-- The following generic INIT_xx declarations are only necessary
if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",

1070

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1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sm_Sn

INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")

port map (
DOA => DOA,
DOB => DOB,
DOPA => DOPA,
DOPB => DOPB,
ADDRA => ADDRA,
ADDRB => ADDRB,

Libraries Guide
ISE 6.3i

-------

Port
Port
Port
Port
Port
Port

www.xilinx.com
1-800-255-7778

A
B
A
B
A
B

16-bit Data Output

16-bit Data Output
2-bit Parity Output
2-bit Parity Output
10-bit Address Input
10-bit Address Input

1071

RAMB16_Sm_Sn

CLKA => CLKA,

CLKB => CLKB,
DIA => DIA,
DIB => DIB,
DIPA => DIPA,
DIPB => DIPB,
ENA => ENA,
ENB => ENB,
SSRA => SSRA,
SSRB => SSRB,
WEA => WEA,
WEB => WEB
);

-- Port A Clock
-- Port B Clock
-- Port A 16-bit Data Input
-- Port B 16-bit Data Input
-- Port A 2-bit parity Input
-- Port-B 2-bit parity Input
-- Port A RAM Enable Input
-- PortB RAM Enable Input
-- Port A Synchronous Set/Reset Input
-- Port B Synchronous Set/Reset Input
-- Port A Write Enable Input
-- Port B Write Enable Input

-- End of RAMB16_S18_S18_inst instantiation

-- RAMB16_S18_S36: Virtex-II/II-Pro, Spartan-3 1k/512 x 16/32 + 2/4

Parity bits Dual-Port RAM
-- Xilinx HDL Language Template version 6.1i
RAMB16_S18_S36_inst : RAMB16_S18_S36
generic map (
-- The following generics are only necessary if you wish to
change the default behavior.
INIT_A => X"00000", -- Value of output RAM registers on Port A
at startup
INIT_B => X"000000000", -- Value of output RAM registers on Port
B at startup
SRVAL_A => X"00000", -- Port A ouput value upon SSR assertion
SRVAL_B => X"000000000", -- Port B ouput value upon SSR
assertion
WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
NO_CHANGE
WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
NO_CHANGE
-- The following generic INIT_xx declarations are only necessary
if you wish to change the initial
-- contents of the RAM to anything other than all zero's.
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",

1072

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1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sm_Sn

INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")

port map (
DOA => DOA,
DOB => DOB,
DOPA => DOPA,
DOPB => DOPB,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA,
DIB => DIB,

Libraries Guide
ISE 6.3i

-----------

Port
Port
Port
Port
Port
Port
Port
Port
Port
Port

www.xilinx.com
1-800-255-7778

A
B
A
B
A
B
A
B
A
B

16-bit Data Output

32-bit Data Output
2-bit Parity Output
4-bit Parity Output
10-bit Address Input
9-bit Address Input
Clock
Clock
16-bit Data Input
32-bit Data Input

1073

RAMB16_Sm_Sn

DIPA => DIPA,

DIPB => DIPB,
ENA => ENA,
ENB => ENB,
SSRA => SSRA,
SSRB => SSRB,
WEA => WEA,
WEB => WEB
);

-- Port A 2-bit parity Input

-- Port-B 4-bit parity Input
-- Port A RAM Enable Input
-- PortB RAM Enable Input
-- Port A Synchronous Set/Reset Input
-- Port B Synchronous Set/Reset Input
-- Port A Write Enable Input
-- Port B Write Enable Input

-- End of RAMB16_S18_S36_inst instantiation

-- Component Attribute specification for RAM16X1D

-- should be placed after architecture declaration but
-- before the begin keyword
Put attributes if necessary
-- Component Instantiation for RAMB16_Sm_Sn should be placed
-- in architecture after the begin keyword
-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.

RAMB16_Sm_Sn INSTANCE_NAME : RAMB16_Sm_Sn

-- synthesis translate_off
generic map (
INIT_00 => vector_value,
INIT_01 => vector_value,
INIT_02 => vector_value,
INIT_03 => vector_value,
INIT_04 => vector_value,
INIT_05 => vector_value,
INIT_06 => vector_value,
INIT_07 => vector_value,
INIT_08 => vector_value,
INIT_09 => vector_value,
INIT_0A => vector_value,
INIT_0B => vector_value,
INIT_0C => vector_value,
INIT_0D => vector_value,
INIT_0E => vector_value,
INIT_0F => vector_value,
INIT_10 => vector_value,
INIT_11 => vector_value,
INIT_12 => vector_value,
INIT_13 => vector_value,
INIT_14 => vector_value,
INIT_15 => vector_value,
INIT_16 => vector_value,
INIT_17 => vector_value,
INIT_18 => vector_value,
INIT_19 => vector_value,
INIT_1A => vector_value,
INIT_1B => vector_value,

1074

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

RAMB16_Sm_Sn

INIT_1C => vector_value,

INIT_1D => vector_value,
INIT_1E => vector_value,
INIT_1F => vector_value,
INIT_20 => vector_value,
INIT_21 => vector_value,
INIT_22 => vector_value,
INIT_23 => vector_value,
INIT_24 => vector_value,
INIT_25 => vector_value,
INIT_26 => vector_value,
INIT_27 => vector_value,
INIT_28 => vector_value,
INIT_29 => vector_value,
INIT_2A => vector_value,
INIT_2B => vector_value,
INIT_2C => vector_value,
INIT_2D => vector_value,
INIT_2E => vector_value,
INIT_2F => vector_value,
INIT_30 => vector_value,
INIT_31 => vector_value,
INIT_32 => vector_value,
INIT_33 => vector_value,
INIT_34 => vector_value,
INIT_35 => vector_value,
INIT_36 => vector_value,
INIT_37 => vector_value,
INIT_38 => vector_value,
INIT_39 => vector_value,
INIT_3A => vector_value,
INIT_3B => vector_value,
INIT_3C => vector_value,
INIT_3D => vector_value,
INIT_3E => vector_value,
INIT_3F => vector_value,
INIT_A => bit_value,
INIT_B => bit_value,
INITP_00 => vector_value,
INITP_01 => vector_value,
INITP_02 => vector_value,
INITP_03 => vector_value,
INITP_04 => vector_value,
INITP_05 => vector_value,
INITP_06 => vector_value,
INITP_07 => vector_value,
SRVAL_A => bit_value,
SRVAL_B => bit_value,
WRITE_MODE_A => string_value,
WRITE_MODE_B => string_value)
-- synopsys translate_on
port map (DOA => user_DOA,
DOB => user_DOB,
DOPA => user_DOPA,
DOPB => user_DOPB,
ADDRA => user_ADDRA,
ADDRB => user_ADDRB,
CLKA => user_CLKA,

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1075

RAMB16_Sm_Sn

CLKB => user_CLKB,

DIA => user_DIA,
DIB => user_DIB,
DIPA => user_DIPA,
DIPB => user_DIPB,
ENA => user_ENA,
ENB => user_ENB,
SSRA => user_SSRA,
SSRB => user_SSRB,
WEA => user_WEA,
WEB => user_WEB);

Verilog Instantiation Template for RAMB16_S9_S9,

RAMB16_S9_S18, RAMB16_S9_S36, RAMB16_S18_S18,
RAMB16_S18_S36, and RAMB16_S36_S36
-- Note that the use of INIT below is for simulation only. For examples
-- of how to include INIT as an implementation constraint,
-- please refer to the Constraints Guide.
RAMB16_Sm_Sn user_instance_name (.DOA (user_DOA),
.DOB (user_DOB),
.DOPA (user_DOPA),
.DOPB (user_DOPB),
.ADDRA (user_ADDRA),
.ADDRB (user_ADDRB),
.CLKA (user_CLKA),
.CLKB (user_CLKB),
.DIA (user_DIA),
.DIB (user_DIB),
.DIPA (user_DIPA),
.DIPB (user_DIB),
.ENA (user_ENA),
.ENB (user_ENB),
.SSRA (user_SSRA),
.SSRB (user_SSRB),
.WEA (user_WEA),
.WEB (user_WEB));
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

1076

user_instance_name.INIT_00
user_instance_name.INIT_01
user_instance_name.INIT_02
user_instance_name.INIT_03
user_instance_name.INIT_04
user_instance_name.INIT_05
user_instance_name.INIT_06
user_instance_name.INIT_07
user_instance_name.INIT_08
user_instance_name.INIT_09
user_instance_name.INIT_0A
user_instance_name.INIT_0B
user_instance_name.INIT_0C
user_instance_name.INIT_0D
user_instance_name.INIT_0E
user_instance_name.INIT_0F
user_instance_name.INIT_10
user_instance_name.INIT_11

www.xilinx.com
1-800-255-7778

=
=
=
=
=
=
=
=
=
=
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256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;
256_bit_hex_value;

Libraries Guide
ISE 6.3i

RAMB16_Sm_Sn

defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam
defparam

Libraries Guide
ISE 6.3i

user_instance_name.INIT_12 = 256_bit_hex_value;
user_instance_name.INIT_13 = 256_bit_hex_value;
user_instance_name.INIT_14 = 256_bit_hex_value;
user_instance_name.INIT_15 = 256_bit_hex_value;
user_instance_name.INIT_16 = 256_bit_hex_value;
user_instance_name.INIT_17 = 256_bit_hex_value;
user_instance_name.INIT_18 = 256_bit_hex_value;
user_instance_name.INIT_19 = 256_bit_hex_value;
user_instance_name.INIT_1A = 256_bit_hex_value;
user_instance_name.INIT_1B = 256_bit_hex_value;
user_instance_name.INIT_1C = 256_bit_hex_value;
user_instance_name.INIT_1D = 256_bit_hex_value;
user_instance_name.INIT_1E = 256_bit_hex_value;
user_instance_name.INIT_1F = 256_bit_hex_value;
user_instance_name.INIT_20 = 256_bit_hex_value;
user_instance_name.INIT_21 = 256_bit_hex_value;
user_instance_name.INIT_22 = 256_bit_hex_value;
user_instance_name.INIT_23 = 256_bit_hex_value;
user_instance_name.INIT_24 = 256_bit_hex_value;
user_instance_name.INIT_25 = 256_bit_hex_value;
user_instance_name.INIT_26 = 256_bit_hex_value;
user_instance_name.INIT_27 = 256_bit_hex_value;
user_instance_name.INIT_28 = 256_bit_hex_value;
user_instance_name.INIT_29 = 256_bit_hex_value;
user_instance_name.INIT_2A = 256_bit_hex_value;
user_instance_name.INIT_2B = 256_bit_hex_value;
user_instance_name.INIT_2C = 256_bit_hex_value;
user_instance_name.INIT_2D = 256_bit_hex_value;
user_instance_name.INIT_2E = 256_bit_hex_value;
user_instance_name.INIT_2F = 256_bit_hex_value;
user_instance_name.INIT_30 = 256_bit_hex_value;
user_instance_name.INIT_31 = 256_bit_hex_value;
user_instance_name.INIT_32 = 256_bit_hex_value;
user_instance_name.INIT_33 = 256_bit_hex_value;
user_instance_name.INIT_34 = 256_bit_hex_value;
user_instance_name.INIT_35 = 256_bit_hex_value;
user_instance_name.INIT_36 = 256_bit_hex_value;
user_instance_name.INIT_37 = 256_bit_hex_value;
user_instance_name.INIT_38 = 256_bit_hex_value;
user_instance_name.INIT_39 = 256_bit_hex_value;
user_instance_name.INIT_3A = 256_bit_hex_value;
user_instance_name.INIT_3B = 256_bit_hex_value;
user_instance_name.INIT_3C = 256_bit_hex_value;
user_instance_name.INIT_3D = 256_bit_hex_value;
user_instance_name.INIT_3E = 256_bit_hex_value;
user_instance_name.INIT_3F = 256_bit_hex_value;
user_instance_name.INIT_A = bit_value;
user_instance_name.INIT_B = bit_value;
user_instance_name.INITP_00 = 256_bit_hex_value;
user_instance_name.INITP_01 = 256_bit_hex_value;
user_instance_name.INITP_02 = 256_bit_hex_value;
user_instance_name.INITP_03 = 256_bit_hex_value;
user_instance_name.INITP_04 = 256_bit_hex_value;
user_instance_name.INITP_05 = 256_bit_hex_value;
user_instance_name.INITP_06 = 256_bit_hex_value;
user_instance_name.INITP_07 = 256_bit_hex_value;
user_instance_name.SRVAL_A = bit_value;
user_instance_name.SRVAL_B = bit_value;

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1077

RAMB16_Sm_Sn

defparam user_instance_name.WRITE_MODE_A = string_value;

defparam user_instance_name.WRITE_MODE_B = string_value;

1078

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Libraries Guide
ISE 6.3i

ROC

ROC
Reset On Configuration
Architectures Supported
ROC
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

The ROC is a component used for VHDL simulation of FPGA designs. This
component should not be used for Verilog or schematic entry. The ROC's function is to
mimic the function of the internal reset signal during the FPGA configuration process.
In order to use ROC, it must be connected to the reset/preset signal for all inferred
and instantiated registers in the design. During synthesis and implementation, this
reset signal will use the dedicated global set/reset network and will not use local
routing resources. During simulation, ROC will emit a one-shot pulse for the amount
of time specified by the WIDTH generic (default is 100 ns). This one-shot pulse is
intended to reset all registers so that at the beginning of operation, all registers are at a
known value as would happen in the real silicon during configuration of the device.
For more information, see the Xilinx Synthesis and Verification Design Guide.
Port O will be high at simulation time 0 for the amount of time specified by the
WIDTH generic attribute. After that time, it will be 0. This will not affect
implementation in any way.

VHDL Instantiation Code

component ROC
-- synthesis translate_off
generic (WIDTH : Time := 100 ns);
-- synthesis translate_on
port (O : out std_ulogic := '1');
end component;

Commonly Used Constraints

For simulation, the WIDTH generic can be modified to change the amount of time the
one-shot pulse is applied for.
There are no supported constraints for this component for implementation.

Libraries Guide
ISE 6.3i

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1079

1080

ROC

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Libraries Guide
ISE 6.3i

ROCBUF

ROCBUF
Reset On Configuration Buffer
Architectures Supported
ROCBUF
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

The ROCBUF is a component used for VHDL simulation of FPGA designs that is
similar to the ROC component except that it contains an input for controlling the
global set/reset function rather than a one-shot. This component should not be used
for Verilog or schematic entry. The ROCBUF's function allows user control of the
function of the global set/reset signal as done during the FPGA configuration process.
In order to use the ROCBUF, the input should be connected to a top-level port in the
design and the output must be connected to the reset/preset signal for all inferred and
instantiated registers in the design.
During simulation, the input to the ROCBUF can be toggled by the testbench in order
to activate the global set/reset signal in the design. This should be done at the
beginning of the simulation as is done in the real silicon after configuration to get the
design in a known state. The signal may also be pulsed during simulation to simulate
a reconfiguration (ProG pin high) of the device. During synthesis and
implementation, this reset signal will use the dedicated global set/reset network and
will not use local routing resources. The port connected to this component will be
optimized out of the design and not use any pin resources.
If you want to have the port implemented in the design, a STARTBUF_architecture
should be used. In order to replace this port during back-end simulation the -gp
switch should be used when invoking the netgen. If using the ISE GUI, use the "Bring
Out Global Set/Reset Net as a Port" option in the Simulation Model Properties
window.
For more information, see the Xilinx Synthesis and Verification Design Guide.
The value at port O will always be the value at port I (it is a buffer).

VHDL Instantiation Code

component ROCBUF
port( I : in std_ulogic;
O : out std_ulogic);
end component;

Libraries Guide
ISE 6.3i

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1081

1082

ROCBUF

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Libraries Guide
ISE 6.3i

ROM16X1

ROM16X1
16-Deep by 1-Wide ROM
Architectures Supported
ROM16X1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

A0

ROM16X1

A1
A2
A3

X4137

No

CoolRunner XPLA3

No

CoolRunner-II

No

ROM16X1 is a 16-word by 1-bit read-only memory. The data output (O) reflects the
word selected by the 4-bit address (A3 A0). The ROM is initialized to a known value
during configuration with the INIT=value parameter. The value consists of four
hexadecimal digits that are written into the ROM from the most-significant digit
A=FH to the least-significant digit A=0H. For example, the INIT=10A7 parameter
produces the data stream:
0001 0000 1010 0111

An error occurs if the INIT=value is not specified. See the appropriate CAE tool
interface user guide for details.

Usage
For HDL, the ROM16X1 design element should be instantiated rather than inferred.

VHDL Instantiation Template

-- ROM16X1: 16 x 1 Asynchronous Distributed => LUT ROM
-- Xilinx HDL Language Template version 6.1i
ROM16X1_inst : ROM16X1
-- Edit the following generic to define the contents of the ROM.
generic map (
INIT => X"0000")
port map (
O => O,
-- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3 -- ROM address[3]
);
-- End of ROM16X1_inst instantiation

Libraries Guide
ISE 6.3i

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1083

ROM16X1

Verilog Instantiation Template

ROM16X1 ROM16X1_inst (
.O(O),
// ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3) // ROM address[3]
);
// Edit the following defparam to define the contents of the ROM.
// If the instance name to the ROM is changed, that change needs to
// be reflected in the defparam statements.
defparam ROM16X1_inst.INIT = 16'h0000;
// End of ROM16X1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, ROM_EXTRACT, U_SET, XBLKNM

1084

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Libraries Guide
ISE 6.3i

ROM32X1

ROM32X1
32-Deep by 1-Wide ROM
Architectures Supported
ROM32X1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

A0

ROM32X1

A1
A2
A3
A4

X4130

No

CoolRunner XPLA3

No

CoolRunner-II

No

ROM32X1 is a 32-word by 1-bit read-only memory. The data output (O) reflects the
word selected by the 5-bit address (A4 A0). The ROM is initialized to a known value
during configuration with the INIT=value parameter. The value consists of eight
hexadecimal digits that are written into the ROM from the most-significant digit
A=1FH to the least-significant digit A=00H. For example, the INIT=10A78F39
parameter produces the data stream:
0001 0000 1010 0111 1000 1111 0011 1001

An error occurs if the INIT=value is not specified. See the appropriate CAE tool
interface user guide for details.

Usage
For HDL, the ROM32X1 design element should be instantiated rather than inferred.

VHDL Instantiation Template

-- ROM32X1: 32 x 1 Asynchronous Distributed => LUT ROM
-- Xilinx HDL Language Template version 6.1i
ROM32X1_inst : ROM32X1
-- Edit the following generic to define the contents of the ROM.
generic map (
INIT => X"00000000")
port map (
O => O,
-- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3, -- ROM address[3]
A4 => A4 -- ROM address[4]
);
-- End of ROM32X1_inst instantiation

Libraries Guide
ISE 6.3i

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1085

ROM32X1

Verilog Instantiation Template

ROM32X1 ROM32X1_inst (
.O(O),
// ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3), // ROM address[3]
.A4(A4) // ROM address[4]
);
// Edit the following defparam to define the contents of the ROM.
// If the instance name to the ROM is changed, that change needs to
// be reflected in the defparam statements.
defparam ROM32X1_inst.INIT = 32'h00000000;
// End of ROM32X1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, ROM_EXTRACT, U_SET, XBLKNM

1086

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Libraries Guide
ISE 6.3i

ROM64X1

ROM64X1
64-Deep by 1-Wide ROM
Architectures Supported
ROM64X1
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

A0

ROM64X1

A1
A2
A3
A4
A5
X9730

No

CoolRunner XPLA3

No

CoolRunner-II

No

ROM64X1 is a 64-word by 1-bit read-only memory. The data output (O) reflects the
word selected by the 6-bit address (A5 A0). The ROM is initialized to a known value
during configuration with the INIT=value parameter. The value consists of 16
hexadecimal digits that are written into the ROM from the most-significant digit
A=FH to the least-significant digit A=0H.
An error occurs if the INIT=value is not specified. See the appropriate CAE tool
interface user guide for details.

Usage
For HDL, the ROM64X1 design element should be instantiated rather than inferred.

VHDL Instantiation Template

-- ROM64X1: 64 x 1 Asynchronous Distributed => LUT ROM
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Language Template version 6.1i
ROM64X1_inst : ROM64X1
-- Edit the following generic to define the contents of the ROM.
generic map (
INIT => X"0000000000000000")
port map (
O => O,
-- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3, -- ROM address[3]
A4 => A4, -- ROM address[4]
A5 => A5 -- ROM address[5]
);
-- End of ROM64X1_inst instantiation

Libraries Guide
ISE 6.3i

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1087

ROM64X1

Verilog Instantiation Template

ROM64X1 ROM64X1_inst (
.O(O),
// ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3), // ROM address[3]
.A4(A4), // ROM address[4]
.A5(A5) // ROM address[5]
);
// Edit the following defparam to define the contents of the ROM.
// If the instance name to the ROM is changed, that change needs to
// be reflected in the defparam statements.
defparam ROM64X1_inst.INIT = 64'h0000000000000000;
// End of ROM64X1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, ROM_EXTRACT, U_SET, XBLKNM

1088

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Libraries Guide
ISE 6.3i

ROM128X1

ROM128X1
128-Deep by 1-Wide ROM
Architectures Supported
ROM128X1
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

A0

ROM128X1

A1
A2
A3
A4
A5
A6
X9731

No

CoolRunner XPLA3

No

CoolRunner-II

No

ROM128X1 is a 128-word by 1-bit read-only memory. The data output (O) reflects the
word selected by the 7-bit address (A6 A0). The ROM is initialized to a known value
during configuration with the INIT=value parameter. The value consists of 32
hexadecimal digits that are written into the ROM from the most-significant digit
A=FH to the least-significant digit A=0H.
An error occurs if the INIT=value is not specified. See the appropriate CAE tool
interface user guide for details.

Usage
For HDL, the ROM128X1 design element should be instantiated rather than inferred.

VHDL Instantiation Template

-- ROM128X1: 128 x 1 Asynchronous Distributed
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Language Template version 6.1i

=> LUT ROM

ROM128X1_inst : ROM128X1
-- Edit the following generic to define the contents of the ROM.
generic map (
INIT => X"00000000000000000000000000000000")
port map (
O => O,
-- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3, -- ROM address[3]
A4 => A4, -- ROM address[4]
A5 => A5, -- ROM address[5]
A6 => A6 -- ROM address[6]
);
-- End of ROM128X1_inst instantiation

Libraries Guide
ISE 6.3i

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1-800-255-7778

1089

ROM128X1

Verilog Instantiation Template

ROM128X1 ROM128X1_inst (
.O(O),
// ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3), // ROM address[3]
.A4(A4), // ROM address[4]
.A5(A5), // ROM address[5]
.A6(A6) // ROM address[6]
);
// Edit the following defparam to define the contents of the ROM.
// If the instance name to the ROM is changed, that change needs to
// be reflected in the defparam statements.
defparam ROM128X1_inst.INIT =
128'h00000000000000000000000000000000;
// End of ROM128X1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, ROM_EXTRACT, U_SET, XBLKNM

1090

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Libraries Guide
ISE 6.3i

ROM256X1

ROM256X1
256-Deep by 1-Wide ROM
Architectures Supported
ROM256X1
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

A0

ROM256X1

A1
A2
A3
A4
A5
A6

No

CoolRunner XPLA3

No

CoolRunner-II

No

ROM256X1 is a 256-word by 1-bit read-only memory. The data output (O) reflects the
word selected by the 8-bit address (A7 A0). The ROM is initialized to a known value
during configuration with the INIT=value parameter. The value consists of 64
hexadecimal digits that are written into the ROM from the most-significant digit
A=FH to the least-significant digit A=0H.

A7
X9732

An error occurs if the INIT=value is not specified. See the appropriate CAE tool
interface user guide for details.

Usage
For HDL, the ROM256X1 design element should be instantiated rather than inferred.

VHDL Instantiation Template

-- ROM256X1: 256 x 1 Asynchronous Distributed
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Language Template version 6.1i

=> LUT ROM

ROM256X1_inst : ROM256X1
-- Edit the following generic to define the contents of the ROM.
generic map (
INIT =>
X"0000000000000000000000000000000000000000000000000000000000000000
")
port map (
O => O,
-- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3, -- ROM address[3]
A4 => A4, -- ROM address[4]
A5 => A5, -- ROM address[5]
A6 => A6 -- ROM address[6]
A7 => A7 -- ROM address[7]
);
-- End of ROM256X1_inst instantiation

Libraries Guide
ISE 6.3i

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1091

ROM256X1

Verilog Instantiation Template

ROM256X1 ROM256X1_inst (
.O(O),
// ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3), // ROM address[3]
.A4(A4), // ROM address[4]
.A5(A5), // ROM address[5]
.A6(A6) // ROM address[6]
.A7(A7) // ROM address[7]
);
// Edit the following defparam to define the contents of the ROM.
// If the instance name to the ROM is changed, that change needs to
// be reflected in the defparam statements.
defparam ROM256X1_inst.INIT =
256'h0000000000000000000000000000000000000000000000000000000000000000;

// End of ROM256X1_inst instantiation

Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, ROM_EXTRACT, U_SET, XBLKNM

1092

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Libraries Guide
ISE 6.3i

SOP3-4

SOP3-4
Sum of Products
Architectures Supported
SOP3, SOP3B1A, SOP3B1B, SOP3B2A,
SOP3B2B, SOP3B3 SOP4, SOP4B1, SOP4B2A,
SOP4B2B, SOP4B3, SOP4B4
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Macro

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No
I3
I2

I2
O
I1

I2

O
I1

I0

I3

I2
I1

I0
SOP3

I1

I0
SOP3B2A

I0
SOP4

SOP4B2B

I3
I2
O

I2

O
I1

I0

I3

I2

I2

I1

O
I0

SOP3B2B

I0
SOP4B1

SOP4B3

I3

I1

SOP3B1B

I0

I0
SOP3B3

O
I1

I1

I0

I0

I2
O

O
I1

I3

I2

I2

I2

O
I1

I1

I0
SOP3B1A

SOP4B2A

SOP4B4

X9421

SOP Gate Representations

Sum Of Products (SOP) macros provide common logic functions by OR gating the
outputs of two AND functions or the output of one AND function with one direct
input. Variations of inverting and non-inverting inputs are available.
I2
I1

I01

I0
AND2

OR2
X8111

SOP3 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide
ISE 6.3i

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1093

SOP3-4

I3
I2

I2B3
AND2
O
OR2

I1
I0

I0B1B
AND2
X8112

SOP4 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II,

Spartan-II, Spartan-IIE, Virtex, Virtex-E
I3

I23

I2

AND2
I1

I01

I0
AND2

OR2
X9374

SOP4 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

1094

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Libraries Guide
ISE 6.3i

SR4CE, SR8CE, SR16CE

SR4CE, SR8CE, SR16CE

4-, 8-, 16-Bit Serial-In Parallel-Out Shift Registers with Clock Enable
and Asynchronous Clear
Architectures Supported
SR4CE, SR8CE, SR16CE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

SLI

SR4CE

Q0

CE

Q1
Q2

Q3

CLR
X4145

SLI

SR8CE

Q[7:0]

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

SR4CE, SR8CE, and SR16CE are 4-, 8-, and 16-bit shift registers, respectively, with a
shift-left serial input (SLI), parallel outputs (Q), and clock enable (CE) and
asynchronous clear (CLR) inputs. The CLR input, when High, overrides all other
inputs and resets the data outputs (Q) Low. When CE is High and CLR is Low, the
data on the SLI input is loaded into the first bit of the shift register during the Low-toHigh clock (C) transition and appears on the Q0 output. During subsequent Low-toHigh clock transitions, when CE is High and CLR is Low, data is shifted to the next
highest bit position as new data is loaded into Q0 (SLIQ0, Q0Q1, Q1Q2, and so
forth). The register ignores clock transitions when CE is Low.
Registers can be cascaded by connecting the last Q output (Q3 for SR4CE, Q7 for
SR8CE, or Q15 for SR16CE) of one stage to the SLI input of the next stage and
connecting clock, CE, and CLR in parallel.

CE
C

CLR
X4151

SLI

Macro

SR16CE

The register is asynchronously cleared, outputs Low, when power is applied.

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.

Q[15:0]

CE
C

CLR
X4157

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Outputs

CLR

CE

SLI

Q0

Qz Q1

No Chg

No Chg

qn-1

qn-1

z = 3 for SR4CE; z = 7for SR8CE; z = 15 for SR16CE

qn-1 = state of referenced output one setup time prior to active clock transition

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1095

SR4CE, SR8CE, SR16CE

Q[7:0]

FDCE
FDCE
SLI

D
CE
C

CE

Q3
Q

Q0

D
CE
C

Q4

CLR
CLR

Q4
Q0

FDCE
FDCE
D
CE
C

Q1

D
CE
C

Q5

CLR

CLR

Q5
Q1

FDCE
FDCE
D
CE
C

Q2

D
CE
C

Q6

CLR

CLR

Q6
Q2

FDCE
FDCE
D
CE
C

Q3

D
CE
C

CLR

Q7

CLR
Q7

Q3

C
CLR

X7868

SR8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

1096

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

SR4CLE, SR8CLE, SR16CLE

SR4CLE, SR8CLE, SR16CLE

4-, 8-, 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers
with Clock Enable and Asynchronous Clear
Architectures Supported
SR4CLE, SR8CLE, SR16CLE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

SLI

SR4CLE
Q0
Q1

D0
D1

Q2
Q3

D2
D3
L
CE
C

CLR
X4147

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

SR4CLE, SR8CLE, and SR16CLE are 4-, 8-, and 16-bit shift registers, respectively, with
a shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q), and three control
inputs: clock enable (CE), load enable (L), and asynchronous clear (CLR).The register
ignores clock transitions when L and CE are Low. The asynchronous CLR, when High,
overrides all other inputs and resets the data outputs (Q) Low. When L is High and
CLR is Low, data on the Dn D0 inputs is loaded into the corresponding Qn Q0 bits
of the register. When CE is High and L and CLR are Low, data on the SLI input is
loaded into the first bit of the shift register during the Low-to-High clock (C)
transition and appears on the Q0 output. During subsequent clock transitions, when
CE is High and L and CLR are Low, the data is shifted to the next highest bit position
as new data is loaded into Q0 (SLIQ0, Q0Q1, Q1Q2, and so forth).
Registers can be cascaded by connecting the last Q output (Q3 for SR4CLE, Q7 for
SR8CLE, or Q15 for SR16CLE) of one stage to the SLI input of the next stage and
connecting clock, CE, L, and CLR inputs in parallel.
The register is asynchronously cleared, outputs Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

SLI
D[15:0]

SR16CLE

Inputs

Outputs

Q[15:0]
L
CE
C

CLR

CE

SLI

Dn D0

Q0

Qz Q1

Dn D0

D0

Dn

SLI

SLI

qn-1

CLR
X4159

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1097

SR4CLE, SR8CLE, SR16CLE

Inputs

Outputs

CLR

CE

SLI

Dn D0

Q0

Qz Q1

No Chg

No Chg

z = 3 for SR4CLE; z = 7 for SR8CLE; z = 15 for SR16CLE

qn-1 = state of referenced output one setup time prior to active clock transition
Q[7:0]
CE

L_OR_CE
OR2

M2_1

SLI

D0
D0

D1
S0

M2_1

FDCE
O

MD0

D0
Q

Q0

D4

CE

MQ0

D1
S0

FDCE
O

MD4

CLR

CLR

Q4

Q0

M2_1
D1

D0
D1
S0

M2_1

FDCE
O

MD1

Q1

D5

CE

MQ1

D0
D1
S0

FDCE
O

MD5

C
CLR

CLR

Q5

Q1

M2_1
D0
D1
S0

M2_1

FDCE
O

MD2

MQ2

Q2

D6

CE

D0
D1
S0

FDCE
O

MD6

MQ6

C
CLR

CLR

Q6

Q2

M2_1
D3

M2_1

FDCE
O

MQ3

MD3

Q6

CE

D0
D1
S0

Q5

CE

MQ5

D2

Q4

CE

MQ4

Q3

D7

CE

D0
D1
S0

FDCE
O

MQ7

MD7

Q7

CE
C

CLR

CLR

Q7

Q3
CLR
C
D[7:0]

X7869

SR8CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

1098

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1-800-255-7778

Libraries Guide
ISE 6.3i

SR4CLED, SR8CLED, SR16CLED

SR4CLED, SR8CLED, SR16CLED

4-, 8-, 16-Bit Shift Registers with Clock Enable and Asynchronous Clear
Architectures Supported
SR4CLED, SR8CLED, SR16CLED
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

SLI

SR4CLED

D0

Q0

D1

Q1

D2

Q2

D3

Q3

SRI
L
LEFT
CE
C

CLR
X4149

SLI SR8CLED
D[7:0]
SRI
Q[7:0]

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

SR4CLED, SR8CLED, and SR16CLED are 4-, 8-, and 16-bit shift registers, respectively,
with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D), parallel
outputs (Q), and four control inputs: clock enable (CE), load enable (L), shift left/right
(LEFT), and asynchronous clear (CLR). The register ignores clock transitions when CE
and L are Low. The asynchronous clear, when High, overrides all other inputs and
resets the data outputs (Qn) Low. When L is High and CLR is Low, the data on the D
inputs is loaded into the corresponding Q bits of the register. When CE is High and L
and CLR are Low, data is shifted right or left, depending on the state of the LEFT
input. If LEFT is High, data on the SLI is loaded into Q0 during the Low-to-High clock
transition and shifted left (to Q1, Q2, and so forth) during subsequent clock
transitions. If LEFT is Low, data on the SRI is loaded into the last Q output (Q3 for
SR4CLED, Q7 for SR8CLED, or Q15 for SR16CLED) during the Low-to-High clock
transition and shifted right (to Q2, Q1,... for SR4CLED; to Q6, Q5,... for SR8CLED; and
to Q14, Q13,... for SR16CLED) during subsequent clock transitions. The truth tables
for SR4CLED, SR8CLED, and SR16CLED indicate the state of the Q outputs under all
input conditions for SR4CLED, SR8CLED, and SR16CLED.

The register is asynchronously cleared, outputs Low, when power is applied.

LEFT
CE

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.

CLR
X4155

GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

SLI SR16CLED
D[15:0]
SRI

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

Q[15:0]

L
LEFT

SR4CLED Truth Table

Inputs

CE
C

CLR
X4161

Libraries Guide
ISE 6.3i

Outputs

CLR

CE

LEFT

SLI

SRI

D3 D0

Q0

Q3

Q2 Q1

D3 D0

D0

D3

Dn

No Chg

No Chg

No Chg

www.xilinx.com
1-800-255-7778

1099

SR4CLED, SR8CLED, SR16CLED

SR4CLED Truth Table

Inputs

Outputs

CLR

CE

LEFT

SLI

SRI

D3 D0

Q0

Q3

Q2 Q1

SLI

SLI

q2

qn-1

SRI

q1

SRI

qn+1

qn-1 and qn+1 = state of referenced output one setup time prior to active clock transition

SR8CLED Truth Table

Inputs

Outputs

CLR

CE

LEFT

SLI

SRI

D7 D0

Q0

Q7

Q6 Q1

D7 D0

D0

D7

Dn

No Chg

No Chg

No Chg

SLI

SLI

q6

qn-1

SRI

q1

SRI

qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

SR16CLED Truth Table

Inputs
CLR

CE

LEFT

SLI

Outputs
SRI

D15 D0

Q0

Q15

Q14 Q1

D15 D0

D0

D15

Dn

No Chg

No Chg

No Chg

SLI

SLI

q14

qn-1

SRI

q1

SRI

qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

1100

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1-800-255-7778

Libraries Guide
ISE 6.3i

SR4CLED, SR8CLED, SR16CLED

CE

L_OR_CE
OR2

SLI

D0
D0

M2_1

D1
S0

D0
MDL0

S0

MDL0

M2_1

FDCE
O

D1

MDR0

D
CE
C

MDR0

Q[7:0]

Q0

CLR
Q0

D1

D0
D1
S0

M2_1

D0
O

MDL1

S0

MDL1

M2_1

FDCE
O

D1

MDR1

D
CE
C

MDR1

Q1

CLR
Q1

D2

D0
D1
S0

M2_1
MDL2

D0
D1
S0

MDL2

M2_1

FDCE
O

MDR2

D
CE
C

MDR2

Q2

CLR
Q2

D3

D0
D1
S0

M2_1
O

MDL3

D0
D1
S0

MDL3

M2_1

FDCE
O

MDR3

D
CE
C

MDR3

Q3

CLR
Q3

M2_1
D4

D0
D1
S0

MDL4

D0
D1
S0

MDL4

M2_1

FDCE
O

MDR4

D
CE
C

MDR4

Q4

CLR
Q4

D5

D0
D1
S0

M2_1
MDL5

D0
D1
S0

MDL5

M2_1

FDCE
O

MDR5

D
CE
C

MDR5

Q5

CLR
Q5

D6

D0
D1
S0

M2_1
MDL6

D0
D1
S0

MDL6

M2_1

FDCE
O

MDR6

D
CE
C

MDR6

Q6

CLR
Q6

D[7:0]
L
SRI

D7

D0
D1
S0

M2_1
MDL7

O
MDL7

D0
D1
S0

M2_1

FDCE
O

MDR7

MDR7

D
CE
C

Q7

CLR
Q7

L_LEFT

LEFT
CLR
C

OR2
X7870

SR8CLED Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1101

SR4CLED, SR8CLED, SR16CLED

VCC
5
L_OR_CE

CE
AND2

SLI

OR2
D0

D0

M2_1

S0

D0
MDL0

D1

S0

MDL0

M2_1

FDCE
O

D1

MDR0

D
CE
C

MDR0

Q0

Q[7:0]

CLR
Q0

D0
D1

D1

S0

M2_1

D0
O

MDL1

S0

MDL1

M2_1

FDCE
O

D1

MDR1

D
CE
C

MDR1

Q1

CLR
Q1

D0
D2

D1
S0

M2_1

D0
MDL2

S0

MDL2

M2_1

FDCE
O

D1

MDR2

D
CE
C

MDR2

Q2

CLR
Q2

D0
D1

D3

S0

M2_1
O

MDL3

D0
D1
S0

MDL3

M2_1

FDCE
O

MDR3

D
CE
C

MDR3

Q3

CLR
Q3

M2_1
D0
D1
S0

D4

MDL4

D0
D1
S0

MDL4

M2_1

FDCE
O

MDR4

D
CE
C

MDR4

Q4

CLR
Q4

D0
D1

D5

S0

M2_1
MDL5

D0
D1
S0

MDL5

M2_1

FDCE
O

MDR5

D
CE
C

MDR5

Q5

CLR
Q5

D0
D1

D6

S0

M2_1
MDL6

D0
D1
S0

MDL6

M2_1

FDCE
O

MDR6

D
CE
C

MDR6

Q6

CLR
Q6

D0

D[7:0]

D7

M2_1

S0

MDL7

D1

MDL7

L
OR2

LEFT

OR2

L_LEFT

D0
D1
S0

M2_1

FDCE
O

MDR7

MDR7

D
CE
C

Q7

CLR
Q7

OR2

GND
SRI
CLR

X8108

SR8CLED Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

1102

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1-800-255-7778

Libraries Guide
ISE 6.3i

SR4RE, SR8RE, SR16RE

SR4RE, SR8RE, SR16RE

4-, 8-, 16-Bit Serial-In Parallel-Out Shift Registers with Clock Enable
and Synchronous Reset
Architectures Supported
SR4RE, SR8RE, SR16RE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

SLI

SR4RE

Q0
Q1

CE

Q2

Q3

R
X4144

SLI

SR8RE
Q[7:0]

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

SR4RE, SR8RE, and SR16RE are 4-, 8-, and 16-bit shift registers, respectively, with
shift-left serial input (SLI), parallel outputs (Qn), clock enable (CE), and synchronous
reset (R) inputs. The R input, when High, overrides all other inputs during the Lowto-High clock (C) transition and resets the data outputs (Q) Low. When CE is High
and R is Low, the data on the SLI is loaded into the first bit of the shift register during
the Low-to-High clock (C) transition and appears on the Q0 output. During
subsequent Low-to-High clock transitions, when CE is High and R is Low, data is
shifted to the next highest bit position as new data is loaded into Q0 (SLIQ0,
Q0Q1, Q1Q2, and so forth). The register ignores clock transitions when CE is
Low.

CE
C

R
X4150

Registers can be cascaded by connecting the last Q output (Q3 for SR4RE, Q7 for
SR8RE, or Q15 for SR16RE) of one stage to the SLI input of the next stage and
connecting clock, CE, and R in parallel.
The register is asynchronously cleared, outputs Low, when power is applied.

SLI

SR16RE

Q[15:0]

CE

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

R
X4156

GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Inputs

Libraries Guide
ISE 6.3i

Outputs

CE

SLI

Q0

Qz Q1

No Chg

No Chg

qn-1

www.xilinx.com
1-800-255-7778

1103

SR4RE, SR8RE, SR16RE

Inputs

Outputs

CE

SLI

Q0

Qz Q1

qn-1

z = 3 for SR4RE; z = 7 for SR8RE; z = 15 for SR16RE

qn-1 = state of referenced output one setup time prior to active clock transition
Q[7:0]

FDRE
FDRE
SLI

D
CE
C

CE

Q3
Q

Q0

D
CE
C

Q4

R
R

Q4
Q0

FDRE
FDRE
D
CE
C

Q1

D
CE
C

Q5

Q5
Q1

FDRE
FDRE
D
CE
C

Q2

D
CE
C

Q6

Q6
Q2

FDRE
FDRE
D
CE
C

Q3

D
CE
C

Q7

R
Q7

Q3

C
R

X7871

SR8RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

1104

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Libraries Guide
ISE 6.3i

SR4RLE, SR8RLE, SR16RLE

SR4RLE, SR8RLE, SR16RLE

4-, 8-, 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers
with Clock Enable and Synchronous Reset
Architectures Supported
SR4RLE, SR8RLE, SR16RLE
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

SLI

SR4RLE

D0

Q0

D1
D2

Q1

D3

Q3

Q2

L
CE
C

R
X4146

SLI
D[7:0]

SR8RLE

Q[7:0]

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

SR4RLE, SR8RLE, and SR16RLE are 4-, 8-, and 16-bit shift registers, respectively, with
shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q), and three control
inputs: clock enable (CE), load enable (L), and synchronous reset (R). The register
ignores clock transitions when L and CE are Low. The synchronous R, when High,
overrides all other inputs during the Low-to-High clock (C) transition and resets the
data outputs (Q) Low. When L is High and R is Low during the Low-to-High clock
transition, data on the D inputs is loaded into the corresponding Q bits of the register.
When CE is High and L and R are Low, data on the SLI input is loaded into the first bit
of the shift register during the Low-to-High clock (C) transition and appears on the
Q0 output. During subsequent clock transitions, when CE is High and L and R are
Low, the data is shifted to the next highest bit position as new data is loaded into Q0
(SLIQ0, Q0Q1, Q1Q2, and so forth).
Registers can be cascaded by connecting the last Q output (Q3 for SR4RLE, Q7 for
SR8RLE, or 15 for SR16RLE) of one stage to the SLI input of the next stage and
connecting clock, CE, L, and R inputs in parallel.

The register is asynchronously cleared, outputs Low, when power is applied.

CE

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.

R
X4152

SLI
D[15:0]

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

SR16RLE

Q[15:0]

Inputs

L
CE

Outputs

CE

SLI

Dz D0

Q0

Qz Q1

Dz D0

D0

Dn

SLI

SLI

qn-1

R
X4158

Libraries Guide
ISE 6.3i

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1-800-255-7778

1105

SR4RLE, SR8RLE, SR16RLE

Inputs

Outputs

CE

SLI

Dz D0

Q0

Qz Q1

No Chg

No Chg

z = 3 for SR4RLE; z = 7 for SR8RLE; z = 15 for SR16RLE

qn-1 = state of referenced output one setup time prior to active clock transition

Q[7:0]
CE

L_OR_CE
OR2

M2_1

SLI
D0

D0
D1
S0

FDRE
O

MD0

M2_1

Q3
Q

Q0

D4

CE

MQ0

D0
D1
S0

FDRE
O

MD4

Q4

Q0

M2_1
D1

D0
D1
S0

M2_1

FDRE
O

MD1

Q1

D5

CE

MQ1

D0
D1
S0

FDRE
O

MD5

C
R

Q5

Q1

M2_1
D0
D1
S0

M2_1

FDRE
O

MD2

MQ2

Q2

D6

CE

D0
D1
S0

FDRE
O

MD6

MQ6

C
R

Q6

Q2

M2_1
D0
D1
S0

M2_1

FDRE
O

MQ3

MD3

Q6

CE

D3

Q5

CE

MQ5

D2

Q4

CE

MQ4

Q3

D7

CE

D0
D1
S0

FDRE
O

MQ7

MD7

Q7

CE
C

Q7

Q3
R
C
D[7:0]

X7872

SR8RLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

1106

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1-800-255-7778

Libraries Guide
ISE 6.3i

SR4RLED, SR8RLED, SR16RLED

SR4RLED, SR8RLED, SR16RLED

4-, 8-, 16-Bit Shift Registers with Clock Enable and Synchronous Reset
Architectures Supported
SR4RLED, SR8RLED, SR16RLED
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

SLI

SR4RLED

D0

Q0

D1
D2

Q1
Q2

D3

Q3

SRI
L
LEFT
CE
C

R
X4148

SLI SR8RLED
D[7:0]
SRI
Q[7:0]

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

SR4RLED, SR8RLED, and SR16RLED are 4-, 8-, and 16-bit shift registers, respectively,
with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D), parallel
outputs (Q) and four control inputs clock enable (CE), load enable (L), shift
left/right (LEFT), and synchronous reset (R). The register ignores clock transitions
when CE and L are Low. The synchronous R, when High, overrides all other inputs
during the Low-to-High clock (C) transition and resets the data outputs (Q) Low.
When L is High and R is Low during the Low-to-High clock transition, the data on the
D inputs is loaded into the corresponding Q bits of the register. When CE is High and
L and R are Low, data is shifted right or left, depending on the state of the LEFT input.
If LEFT is High, data on SLI is loaded into Q0 during the Low-to-High clock transition
and shifted left (to Q1, Q2, and so forth) during subsequent clock transitions. If LEFT
is Low, data on the SRI is loaded into the last Q output (Q3 for SR4RLED, Q7 for
SR8RLED, or Q15 for SR16RLED) during the Low-to-High clock transition and shifted
right (to Q2, Q1,... for SR4RLED; to Q6, Q5,... for SR8RLED; or to Q14, Q13,... for
SR16RLED) during subsequent clock transitions. The truth table indicates the state of
the Q outputs under all input conditions.
The register is asynchronously cleared, outputs Low, when power is applied.

L
LEFT
CE

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on

condition can be simulated by applying a High-level pulse on the PRLD global net.

R
X4154

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.

SLI SR16RLED
D[15:0]
SRI
Q[15:0]

SR4RLED Truth Table

Inputs

LEFT
CE
C

R
X4160

Libraries Guide
ISE 6.3i

Macro

Outputs

CE

LEFT

SLI

SRI

D3 D0

Q0

Q3

Q2 Q1

D3 D0

D0

D3

Dn

No Chg

No Chg

No Chg

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1107

SR4RLED, SR8RLED, SR16RLED

SR4RLED Truth Table

Inputs

Outputs

CE

LEFT

SLI

SRI

D3 D0

Q0

Q3

Q2 Q1

SLI

SLI

q2

qn-1

SRI

q1

SRI

qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

SR8RLED Truth Table

Inputs

Outputs

CE

LEFT

SLI

SRI

D7 D0

Q0

Q7

Q6 Q1

D7 D0

D0

D7

Dn

No Chg

No Chg

No Chg

SLI

SLI

q6

qn-1

SRI

q1

SRI

qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

SR16RLED Truth Table

Inputs

Outputs

CE

LEFT

SLI

SRI

D15 D0

Q0

Q15

Q14 Q1

D15 D0

D0

D15

Dn

No Chg

No Chg

No Chg

SLI

SLI

q14

qn-1

SRI

q1

SRI

qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

1108

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Libraries Guide
ISE 6.3i

SR4RLED, SR8RLED, SR16RLED

CE

L_OR_CE

OR2
D0

D0

D1
S0

FDRE

M2_1

M2_1

SLI

D0
O MDL0

MDLO

D1
S0

MDR0

MDR0

D
CE
C

Q0

Q[7:0]

Q0

D1
S0

FDRE

M2_1

M2_1
D0

D1

D0
O MDL1

MDL1

D1
S0

MDR1

MDR1

D
CE
C

Q1

Q1

D1
S0

FDRE

M2_1

M2_1
D0

D2

D0
O MDL2

MDL2

D1
S0

MDR2

MDR2

D
CE

Q2

C
R

Q2

D1
S0

FDRE

M2_1

M2_1
D0

D3

D0
O MDL3

MDL3

D1
S0

MDR3

MDR3

D
CE

Q3

C
R

Q3

D4

D1
S0

FDRE

M2_1

M2_1
D0

D0
O MDL4

MDL4

D1
S0

MDR4

MDR4

D
CE
C

Q4

Q4

D5

D1
S0

FDRE

M2_1

M2_1
D0

D0
O MDL5

MDL5

D1
S0

MDR5

MDR5

D
CE

Q5

C
R

Q5

D1
S0

FDRE

M2_1

M2_1
D0

D6

D0
O MDL6

MDL6

D1
S0

MDR6

MDR6

D
CE

Q6

C
R

Q6

D0

D7

D1
S0

D0
O MDL7

MDL7

D1
S0

O
MDR7

MDR7

D
CE
C

Q7

SRI

Q7
L_LEFT

LEFT
R
C

FDRE

M2_1

M2_1
D[7:0]

OR2

X8688

SR8RLED Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II,

Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1109

SR4RLED, SR8RLED, SR16RLED

Usage
For HDL, these design elements are inferred rather than instantiated.

1110

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Libraries Guide
ISE 6.3i

SRD4CE, SRD8CE, SRD16CE

SRD4CE, SRD8CE, SRD16CE

4-, 8-, 16-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Registers
with Clock Enable and Asynchronous Clear
Architectures Supported
SRD4CE, SRD8CE, SRD16CE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

SLI

Q0

SRD4CE

Q1
CE

Q2

Q3

CLR
X9700

SLI

SRD8CE

Q[7:0]

CE
C

SRD16CE

CoolRunner XPLA3

No

CoolRunner-II

Macro

SRD4CE, SRD8CE, and SRD16CE are 4-, 8-, and 16-bit dual edge triggered shift
registers, respectively, with a shift-left serial input (SLI), parallel outputs (Q), clock
enable (CE) and asynchronous clear (CLR) inputs. The CLR input, when High,
overrides all other inputs and resets the data outputs (Q) Low. When CE is High and
CLR is Low, the data on the SLI input is loaded into the first bit of the shift register
during the Low-to-High (or High-to-Low) clock (C) transition and appears on the Q0
output. During subsequent clock transitions, when CE is High and CLR is Low, data
is shifted to the next highest bit position as new data is loaded into Q0 (SLIQ0,
Q0Q1, Q1Q2, and so forth). The register ignores clock transitions when CE is
Low.

X9701

Registers can be cascaded by connecting the last Q output (Q3 for SRD4CE, Q7 for
SRD8CE, or Q15 for SRD16CE) of one stage to the SLI input of the next stage and
connecting clock, CE, and CLR in parallel.

Q[15:0]

The register is asynchronously cleared, outputs Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

CLR

SLI

No

CE

Inputs

CLR
X9702

Outputs

CLR

CE

SLI

Q0

Qz Q1

No Chg

No Chg

qn-1

qn-1

qn-1

qn-1

z = 3 for SRD4CE; z = 7for SRD8CE; z = 15 for SRD16CE

qn-1 = state of referenced output one setup time prior to active clock transition

Libraries Guide
ISE 6.3i

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1-800-255-7778

1111

SRD4CE, SRD8CE, SRD16CE

Q[7:0]

FDDCE
FDDCE
SLI
CE

D
CE
C

Q3
Q0

D
CE
C

Q4

CLR
CLR

Q4
Q0

FDDCE
FDDCE
D
CE
C

Q1

D
CE
C

Q5

CLR

CLR

Q5
Q1

FDDCE
FDDCE
D
CE
C

Q2

D
CE
C

Q6

CLR

CLR

Q6
Q2

FDDCE
FDDCE
D
CE
C

Q3

D
CE
C

CLR

Q7

CLR
Q7

Q3

C
CLR

X9703

SRD8CE Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

1112

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1-800-255-7778

Libraries Guide
ISE 6.3i

SRD4CLE, SRD8CLE, SRD16CLE

SRD4CLE, SRD8CLE, SRD16CLE

4-, 8-, 16-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge
Triggered Shift Registers with Clock Enable and Asynchronous Clear
Architectures Supported
SRD4CLE, SRD8CLE, SRD16CLE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

SLI

SRD4CLE
Q0
Q1

D0
D1
D2

Q2
Q3

D3
L
CE
C

CLR
X9704

SLI
D[7:0]

SRD8CLE

Q[7:0]
L

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

SRD4CLE, SRD8CLE, and SRD16CLE are 4-, 8-, and 16-bit dual edge triggered shift
registers, respectively, with a shift-left serial input (SLI), parallel inputs (D), parallel
outputs (Q), and three control inputs: clock enable (CE), load enable (L), and
asynchronous clear (CLR). The register ignores clock transitions when L and CE are
Low. The asynchronous CLR, when High, overrides all other inputs and resets the
data outputs (Q) Low. When L is High and CLR is Low, data on the Dn D0 inputs is
loaded into the corresponding Qn Q0 bits of the register. When CE is High and L
and CLR are Low, data on the SLI input is loaded into the first bit of the shift register
during the Low-to-High (or High-to-Low) clock (C) transition and appears on the Q0
output. During subsequent clock transitions, when CE is High and L and CLR are
Low, the data is shifted to the next highest bit position as new data is loaded into Q0
(SLIQ0, Q0Q1, Q1Q2, and so forth).
Registers can be cascaded by connecting the last Q output (Q3 for SRD4CLE, Q7 for
SRD8CLE, or Q15 for SRD16CLE) of one stage to the SLI input of the next stage and
connecting clock, CE, L, and CLR inputs in parallel.
The register is asynchronously cleared, outputs Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

CE
C

CLR

Inputs

X9705

SLI SRD16CLE
D[15:0]

Outputs

CLR

CE

SLI

Dn D0

Q0

Qz Q1

Dn D0

D0

Dn

Dn D0

D0

Dn

SLI

SLI

qn-1

CE

SLI

SLI

qn-1

No Chg

No Chg

Q[15:0]

CLR
X9706

z = 3 for SRD4CLE; z = 7 for SRD8CLE; z = 15 for SRD16CLE

qn-1 = state of referenced output one setup time prior to active clock transition

Libraries Guide
ISE 6.3i

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1-800-255-7778

1113

SRD4CLE, SRD8CLE, SRD16CLE

Q[7:0]
CE

L_OR_CE
OR2

D0
D0

D1
S0

MD0

D0
Q

Q0

D4

CE

MQ0

FDDCE

M2_1

FDDCE

M2_1

SLI

D1
S0

MD4

CLR

CLR

Q4

Q0

D1
S0

MD1

D0
Q

Q1

D5

CE

MQ1

FDDCE

M2_1

FDDCE

M2_1
D0
D1

D1
S0

MD5

C
CLR

CLR

Q5

Q1

D1
S0

MD2

MQ2

FDDCE

M2_1

FDDCE

M2_1
D0

D0
Q

Q2

D6

CE

D1
S0

MD6

MQ6

C
CLR

CLR

Q6

Q2

D1
S0

MD3

MQ3

FDDCE

M2_1

FDDCE

M2_1
D0

Q6

CE

D3

Q5

CE

MQ5

D2

Q4

CE

MQ4

D0
Q

Q3

D7

CE

D1
S0

O
MQ7

MD7

Q7

CE
C

CLR

CLR

Q7

Q3
CLR
C
D[7:0]

X9707

SRD8CLE Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

1114

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1-800-255-7778

Libraries Guide
ISE 6.3i

SRD4CLED, SRD8CLED, SRD16CLED

SRD4CLED, SRD8CLED, SRD16CLED

4-, 8-, 16-Bit Dual Edge Triggered Shift Registers with Clock Enable and
Asynchronous Clear
Architectures Supported
SRD4CLED, SRD8CLED, SRD16CLED
Spartan-II, Spartan-IIE

SLI

SRD4CLED

D0

Q0

D1

Q1

D2

Q2

D3

Q3

SRI
L
LEFT
CE
C

CLR
X9708

SLI SRD8CLED
D[7:0]
SRI
Q[7:0]
L

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

SRD4CLED, SRD8CLED, and SRD16CLED are 4-, 8-, and 16-bit dual edge triggered
shift registers, respectively, with shift-left (SLI) and shift-right (SRI) serial inputs,
parallel inputs (D), parallel outputs (Q), and four control inputs: clock enable (CE),
load enable (L), shift left/right (LEFT), and asynchronous clear (CLR). The register
ignores clock transitions when CE and L are Low. The asynchronous clear, when
High, overrides all other inputs and resets the data outputs (Qn) Low. When L is High
and CLR is Low, the data on the D inputs is loaded into the corresponding Q bits of
the register. When CE is High and L and CLR are Low, data is shifted right or left,
depending on the state of the LEFT input. If LEFT is High, data on the SLI is loaded
into Q0 during the Low-to-High or High-to-Low clock transition and shifted left (to
Q1, Q2, and so forth) during subsequent clock transitions. If LEFT is Low, data on the
SRI is loaded into the last Q output (Q3 for SRD4CLED, Q7 for SRD8CLED, or Q15 for
SRD16CLED) during the Low-to-High or High-to-Low clock transition and shifted
right (to Q2, Q1,... for SRD4CLED; to Q6, Q5,... for SRD8CLED; and to Q14, Q13,... for
SRD16CLED) during subsequent clock transitions. The truth tables for SRD4CLED,
SRD8CLED, and SRD16CLED indicate the state of the Q outputs under all input
conditions for SRD4CLED, SRD8CLED, and SRD16CLED.

LEFT

The register is asynchronously cleared, outputs Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

CE
C

CLR
X9709

SRD4CLED Truth Table

Inputs

SLI SRD16CLED
D[15:0]

CLR

CE

LEFT

SLI

CE

SRI

Q[15:0]

L
LEFT

CLR
X9710

Libraries Guide
ISE 6.3i

Outputs
SRI

D3 D0

Q0

Q3

Q2 Q1

D3 D0

D0

D3

Dn

D3 D0

D0

D3

Dn

No Chg

No Chg

No Chg

SLI

SLI

q2

qn-1

SLI

SLI

q2

qn-1

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1115

SRD4CLED, SRD8CLED, SRD16CLED

SRD4CLED Truth Table

Inputs

Outputs

CLR

CE

LEFT

SLI

SRI

D3 D0

Q0

Q3

Q2 Q1

SRI

q1

SRI

qn+1

SRI

q1

SRI

qn+1

qn-1 and qn+1 = state of referenced output one setup time prior to active clock transition

SRD8CLED Truth Table

Inputs

Outputs

CLR

CE

LEFT

SLI

SRI

D7 D0

Q0

Q7

Q6 Q1

D7 D0

D0

D7

Dn

D7 D0

D0

D7

Dn

No Chg

No Chg

No Chg

SLI

SLI

q6

qn-1

SLI

SLI

q6

qn-1

SRI

q1

SRI

qn+1

SRI

q1

SRI

qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

SRD16CLED Truth Table

Inputs

Outputs

CLR

CE

LEFT

SLI

SRI

D15 D0

Q0

Q15

Q14 Q1

D15 D0

D0

D15

Dn

D15 D0

D0

D15

Dn

No Chg

No Chg

No Chg

SLI

SLI

q14

qn-1

SLI

SLI

q14

qn-1

SRI

q1

SRI

qn+1

SRI

q1

SRI

qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

1116

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Libraries Guide
ISE 6.3i

SRD4CLED, SRD8CLED, SRD16CLED

VCC
5
L_OR_CE

CE
AND2

SLI

OR2
D0
D1
S0

D0

M2_1
MDL0

D0
D1
S0

MDL0

FDDCE

M2_1
O

MDR0

CE
C

MDR0

Q0

Q[7:0]

CLR
Q0

D0
D1

D1

S0

M2_1
O

MDL1

D0
D1
S0

MDL1

FDDCE

M2_1
O

MDR1

CE
C

MDR1

Q1

CLR
Q1

D0
D1
S0

D2

M2_1
MDL2

D0
D1
S0

MDL2

FDDCE

M2_1
O

MDR2

CE
C

MDR2

Q2

CLR
Q2

D0
D1

D3

S0

M2_1
O

MDL3

D0
D1
S0

MDL3

FDDCE

M2_1
O

MDR3

CE
C

MDR3

Q3

CLR
Q3

M2_1
D0
D1
S0

D4

MDL4

D0
D1
S0

MDL4

FDDCE

M2_1
O

MDR4

CE
C

MDR4

Q4

CLR
Q4

D0
D1

D5

S0

M2_1
MDL5

D0
D1
S0

MDL5

FDDCE

M2_1
O

MDR5

CE
C

MDR5

Q5

CLR
Q5

D0
D1

D6

S0

M2_1
MDL6

D0
D1
S0

MDL6

FDDCE

M2_1
O

MDR6

CE
C

MDR6

Q6

CLR
Q6

D[7:0]

D0
D1

D7

S0

M2_1
MDL7

O
MDL7

D0
D1
S0

FDDCE

M2_1
O
MDR7

L
OR2

LEFT

OR2

L_LEFT

MDR7

D
CE
C

Q7

CLR
Q7

OR2

GND
SRI
CLR
C

X9711

SRD8CLED Implementation CoolRunner-II

Libraries Guide
ISE 6.3i

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1-800-255-7778

1117

SRD4CLED, SRD8CLED, SRD16CLED

Usage
For HDL, these design elements are inferred rather than instantiated.

1118

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Libraries Guide
ISE 6.3i

SRD4RE, SRD8RE, SRD16RE

SRD4RE, SRD8RE, SRD16RE

4-, 8-, 16-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Registers
with Clock Enable and Synchronous Reset
Architectures Supported
SRD4RE, SRD8RE, SRD16RE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

SLI

SRD4RE

Q0
Q1

CE

Q2

Q3

R
X9712

SLI

SRD8RE
Q[7:0]

CE

CoolRunner XPLA3

No

CoolRunner-II

Macro

SRD4RE, SRD8RE, and SRD16RE are 4-, 8-, and 16-bit dual edge triggered shift
registers, respectively, with shift-left serial input (SLI), parallel outputs (Qn), clock
enable (CE), and synchronous reset (R) inputs. The R input, when High, overrides all
other inputs during the Low-to-High or High-to-Low clock (C) transition and resets
the data outputs (Q) Low. When CE is High and R is Low, the data on the SLI is
loaded into the first bit of the shift register during the Low-to-High clock or High-toLow (C) transition and appears on the Q0 output. During subsequent clock
transitions, when CE is High and R is Low, data is shifted to the next highest bit
position as new data is loaded into Q0 (SLIQ0, Q0Q1, Q1Q2, and so forth). The
register ignores clock transitions when CE is Low.
Registers can be cascaded by connecting the last Q output (Q3 for SRD4RE, Q7 for
SRD8RE, or Q15 for SRD16RE) of one stage to the SLI input of the next stage and
connecting clock, CE, and R in parallel.

R
X9713

SLI

No

SRD16RE

Q[15:0]

The register is asynchronously cleared, outputs Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
Inputs

CE

Outputs

R
X9714

CE

SLI

Q0

Qz Q1

No Chg

No Chg

qn-1

qn-1

qn-1

qn-1

z = 3 for SRD4RE; z = 7 for SRD8RE; z = 15 for SRD16RE

qn-1 = state of referenced output one setup time prior to active clock transition

Libraries Guide
ISE 6.3i

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1119

SRD4RE, SRD8RE, SRD16RE

Q[7:0]

FDDRE
FDDRE
SLI
CE

D
CE
C

Q3
Q0

D
CE
C

Q4

R
R

Q4
Q0

FDDRE
FDDRE
D
CE
C

Q1

D
CE
C

Q5

Q5
Q1

FDDRE
FDDRE
D
CE
C

Q2

D
CE
C

Q6

Q6
Q2

FDDRE
FDDRE
D
CE
C

Q3

D
CE
C

Q7

R
Q7

Q3

C
R

X9715

SRD8RE Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

1120

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Libraries Guide
ISE 6.3i

SRD4RLE, SRD8RLE, SRD16RLE

SRD4RLE, SRD8RLE, SRD16RLE

4-, 8-, 16-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge
Triggered Shift Registers with Clock Enable and Synchronous Reset
Architectures Supported
SRD4RLE, SRD8RLE, SRD16RLE
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

SLI

SRD4RLE

D0

Q0

D1
D2

Q1

D3

Q3

Q2

L
CE
C

R
X9716

SLI
D[7:0]

SRD8RLE

Q[7:0]

CoolRunner XPLA3

No

CoolRunner-II

Macro

SRD4RLE, SRD8RLE, and SRD16RLE are 4-, 8-, and 16-bit dual edge triggered shift
registers, respectively, with shift-left serial input (SLI), parallel inputs (D), parallel
outputs (Q), and three control inputs: clock enable (CE), load enable (L), and
synchronous reset (R). The register ignores clock transitions when L and CE are Low.
The synchronous R, when High, overrides all other inputs during the Low-to-High or
High-to-Low clock (C) transition and resets the data outputs (Q) Low. When L is High
and R is Low, data on the D inputs is loaded into the corresponding Q bits of the
register. When CE is High and L and R are Low, data on the SLI input is loaded into
the first bit of the shift register during the Low-to-High or High-to-Low clock (C)
transition and appears on the Q0 output. During subsequent clock transitions, when
CE is High and L and R are Low, the data is shifted to the next highest bit position as
new data is loaded into Q0 (SLIQ0, Q0Q1, Q1Q2, and so forth).
Registers can be cascaded by connecting the last Q output (Q3 for SRD4RLE, Q7 for
SRD8RLE, or 15 for SRD16RLE) of one stage to the SLI input of the next stage and
connecting clock, CE, L, and R inputs in parallel.
The register is asynchronously cleared, outputs Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

L
CE
C

Inputs

R
X9717

SLI
D[15:0]

No

SRD16RLE

Outputs

CE

SLI

Dz D0

Q0

Qz Q1

Dz D0

D0

Dn

Dz D0

D0

Dn

CE

SLI

SLI

qn-1

SLI

SLI

qn-1

Q[15:0]

R
X9718

Libraries Guide
ISE 6.3i

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1121

SRD4RLE, SRD8RLE, SRD16RLE

Inputs

Outputs

CE

SLI

Dz D0

Q0

Qz Q1

No Chg

No Chg

z = 3 for SRD4RLE; z = 7 for SRD8RLE; z = 15 for SRD16RLE

qn-1 = state of referenced output one setup time prior to active clock transition
Q[7:0]
CE

L_OR_CE
OR2

FDDRE

M2_1

SLI
D0

D0
D1
S0

MD0

Q0

D0
D4

CE

MQ0

FDDRE

M2_1

Q3
Q

D1
S0

MD4

Q4

Q0

D0
D1
S0

MD1

Q1

D5

CE

MQ1

FDDRE

M2_1

FDDRE

M2_1
D1

D0
D1
S0

MD5

C
R

Q5

Q1

MD2

MQ2

FDDRE

M2_1

FDDRE

M2_1
D0
D1
S0

Q2

D6

CE

D0
D1
S0

MD6

MQ6

C
R

Q6

Q2

D1
S0

O
MQ3

MD3

FDDRE

M2_1

FDDRE

M2_1
D0

Q6

CE

D3

Q5

CE

MQ5

D2

Q4

CE

MQ4

CE

Q3

D7

D0
D1
S0

MD7

MQ7

Q7

CE
C

Q7

Q3
R
C
D[7:0]

X9719

SRD8RLE Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

1122

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Libraries Guide
ISE 6.3i

SRD4RLED, SRD8RLED, SRD16RLED

SRD4RLED, SRD8RLED, SRD16RLED

4-, 8-, 16-Bit Dual Edge Triggered Shift Registers with Clock Enable and
Synchronous Reset
Architectures Supported
SRD4RLED, SRD8RLED, SRD16RLED
Spartan-II, Spartan-IIE

SLI SRD4RLED
D0

Q0

D1
D2

Q1

D3

Q3

Q2

SRDI
L
LEFT
CE
C

R
X9844

SLI SRD8RLED
D[7:0]
SRDI
Q[7:0]
L
LEFT

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

Macro

SRD4RLED, SRD8RLED, and SRD16RLED are 4-, 8-, and 16-bit dual edge triggered
shift registers, respectively, with shift-left (SLI) and shift-right (SRDI) serial inputs,
parallel inputs (D), parallel outputs (Q), and four control inputs clock enable (CE),
load enable (L), shift left/right (LEFT), and synchronous reset (R). The register ignores
clock transitions when CE and L are Low. The synchronous R, when High, overrides
all other inputs during the Low-to-High or High-to-Low clock (C) transition and
resets the data outputs (Q) Low. When L is High and R is Low, the data on the D
inputs is loaded into the corresponding Q bits of the register. When CE is High and L
and R are Low, data is shifted right or left, depending on the state of the LEFT input. If
LEFT is High, data on SLI is loaded into Q0 during the Low-to-High or High-to-Low
clock transition and shifted left (to Q1, Q2, and so forth) during subsequent clock
transitions. If LEFT is Low, data on the SRDI is loaded into the last Q output (Q3 for
SRD4RLED, Q7 for SRD8RLED, or Q15 for SRD16RLED) during the Low-to-High or
High-to-Low clock transition and shifted right (to Q2, Q1,... for SRD4RLED; to Q6,
Q5,... for SRD8RLED; or to Q14, Q13,... for SRD16RLED) during subsequent clock
transitions. The truth table indicates the state of the Q outputs under all input
conditions.
The register is asynchronously cleared, outputs Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.

CE
C

R
X9845

SRD4RLED Truth Table

Inputs

SLI SRD16RLED
D[15:0]
SRDI
Q[15:0]
L
LEFT

Outputs

CE

LEFT

SLI

SRDI

D3 D0

Q0

Q3

Q2 Q1

D3 D0

D0

D3

Dn

D3 D0

D0

D3

Dn

No Chg

No Chg

No Chg

SLI

SLI

q2

qn-1

CE
C

R
X9846

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1123

SRD4RLED, SRD8RLED, SRD16RLED

SRD4RLED Truth Table

Inputs

Outputs

CE

LEFT

SLI

SRDI

D3 D0

Q0

Q3

Q2 Q1

SLI

SLI

q2

qn-1

SRDI

q1

SRDI

qn+1

SRDI

q1

SRDI

qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

SRD8RLED Truth Table

Inputs

Outputs

CE

LEFT

SLI

SRDI

D7 D0

Q0

Q7

Q6 Q1

D7 D0

D0

D7

Dn

D7 D0

D0

D7

Dn

No Chg

No Chg

No Chg

SLI

SLI

q6

qn-1

SLI

SLI

q6

qn-1

SRDI

q1

SRDI

qn+1

SRDI

q1

SRDI

qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

SRD16RLED Truth Table

Inputs

Outputs

CE

LEFT

SLI

SRDI

D15 D0

Q0

Q15

Q14 Q1

D15 D0

D0

D15

Dn

D15 D0

D0

D15

Dn

No Chg

No Chg

No Chg

SLI

SLI

q14

qn-1

SLI

SLI

q14

qn-1

SRDI

q1

SRDI

qn+1

SRDI

q1

SRDI

qn+1

qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition

1124

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Libraries Guide
ISE 6.3i

SRD4RLED, SRD8RLED, SRD16RLED

CE

L_OR_CE
OR2

D0
D0

D0
O MDL0

D1
S0

FDDRE

M2_1

M2_1

SLI

MDLO

D1
S0

MDR0

MDR0

D
CE
C

Q0

Q[7:0]

R
Q0

D0
O MDL1

D1
S0

FDDRE

M2_1

M2_1
D0
D1

MDL1

D1
S0

MDR1

MDR1

D
CE
C

Q1

R
Q1

D0
O MDL2

D1
S0

FDDRE

M2_1

M2_1
D0
D2

MDL2

D1
S0

MDR2

MDR2

D
CE

Q2

C
R
Q2

D0
O MDL3

D1
S0

FDDRE

M2_1

M2_1
D0
D3

MDL3

D1
S0

MDR3

MDR3

D
CE

Q3

C
R
Q3

D4

D0
O MDL4

D1
S0

FDDRE

M2_1

M2_1
D0

MDL4

D1
S0

MDR4

MDR4

D
CE
C

Q4

R
Q4

D0
O MDL5

D1
S0

FDDRE

M2_1

M2_1
D0
D5

MDL5

D1
S0

MDR5

MDR5

D
CE

Q5

C
R
Q5

D6

D0
O MDL6

D1
S0

FDDRE

M2_1

M2_1
D0

MDL6

D1
S0

MDR6

MDR6

D
CE

Q6

C
R
Q6

D7

D1
S0

FDDRE

M2_1

M2_1
D0
D[7:0]

D0
O MDL7

MDL7

D1
S0

O
MDR7

MDR7

D
CE
C

Q7

SRI

Q7
L_LEFT

LEFT
R

OR2

X9723

SRD8RLED Implementation CoolRunner-II

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1125

1126

SRD4RLED, SRD8RLED, SRD16RLED

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Libraries Guide
ISE 6.3i

SRL16

SRL16
16-Bit Shift Register Look-Up-Table (LUT)
Architectures Supported
SRL16
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

SRL16 is a shift register look up table (LUT). The inputs A3, A2, A1, and A0 select the
output length of the shift register. The shift register may be of a fixed, static length or
it may be dynamically adjusted.
The shift register LUT contents are initialized by assigning a four-digit hexadecimal
number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most
significant bit. If an INIT value is not specified, it defaults to a value of four zeros
(0000) so that the shift register LUT is cleared during configuration.
The data (D) is loaded into the first bit of the shift register during the Low-to-High
clock (CLK) transition. During subsequent Low-to-High clock transitions data is
shifted to the next highest bit position as new data is loaded. The data appears on the
Q output when the shift register length determined by the address inputs is reached.

Static Length Mode

To get a fixed length shift register, drive the A3 through A0 inputs with static values.
The length of the shift register can vary from 1 bit to 16 bits as determined from the
following formula:
Length = (8*A3) +(4*A2) + (2*A1) + A0 +1
If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. If they are
all ones (1111), it is 16 bits long.

Dynamic Length Mode

The length of the shift register can be changed dynamically by changing the values
driving the A3 through A0 inputs. For example, if A2, A1, and A0 are all ones (111)
and A3 toggles between a one (1) and a zero (0), the length of the shift register changes
from 16 bits to 8 bits.

Libraries Guide
ISE 6.3i

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1127

SRL16

Internally, the length of the shift register is always 16 bits and the input lines A3
through A0 select which of the 16 bits reach the output.
Inputs

Output

Am

CLK

Am

Q(Am)

Am

Q(Am-1)

m= 0, 1, 2, 3

Usage
Below are example templates for instantiating this component into a design. These
templates can be cut and pasteddirectly into the users source code.

VHDL Instantiation Templates

-- SRL16: 16-bit shift register LUT operating on posedge of clock
-All FPGAs
-- Xilinx HDL Libraries Guide version 7.1i
SRL16_inst : SRL16
-- The following generic declaration is only necessary if you wish to
-- change the initial contents of the SRL to anything other than all
-- zero's.
generic map (
INIT => X"0000")
port map (
Q => Q,
-- SRL data output
A0 => A0,
-- Select[0] input
A1 => A1,
-- Select[1] input
A2 => A2,
-- Select[2] input
A3 => A3,
-- Select[3] input
CLK => CLK,
-- Clock input
D => D
-- SRL data input
);
-- End of SRL16_inst instantiation

Verilog Instantiation Template

-- SRL16: 16-bit shift register LUT operating on posedge of clock
-All FPGAs
-- Xilinx HDL Libraries Guide version 7.1i
SSRL16 SRL16_inst (
.Q(Q),
// SRL data output
.A0(A0),
// Select[0] input
.A1(A1),
// Select[1] input
.A2(A2),
// Select[2] input
.A3(A3),
// Select[3] input
.CLK(CLK),
// Clock input
.D(D)
// SRL data input
);
// The following defparam declaration is only necessary if you wish to

1128

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Libraries Guide
ISE 6.3i

SRL16

// change the initial contents of the SRL to anything other than all
// zero's. If the instance name to the SRL is changed, that change
// needs to be reflected in the defparam statements.
defparam SRL16_inst.INIT = 16'h0000;
// End of SRL16_inst instantiation

Commonly Used Constraints

BEL, U_SET, INIT

Libraries Guide
ISE 6.3i

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1129

1130

SRL16

www.xilinx.com
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Libraries Guide
ISE 6.3i

SRL16_1

SRL16_1
16-Bit Shift Register Look-Up-Table (LUT) with Negative-Edge Clock
Architectures Supported
SRL16_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

D
CLK
A0

SRL16_1

A1
A2
A3

X8422

No

CoolRunner XPLA3

No

CoolRunner-II

No

SRL16_1 is a shift register look up table (LUT). The inputs A3, A2, A1, and A0 select
the output length of the shift register. The shift register may be of a fixed, static length
or it may be dynamically adjusted. See Static Length Mode and Dynamic Length
Mode in SRL16.
The shift register LUT contents are initialized by assigning a four-digit hexadecimal
number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most
significant bit. If an INIT value is not specified, it defaults to a value of four zeros
(0000) so that the shift register LUT is cleared during configuration.
The data (D) is loaded into the first bit of the shift register during the High-to-Low
clock (CLK) transition. During subsequent High-to-Low clock transitions data is
shifted to the next highest bit position as new data is loaded. The data appears on the
Q output when the shift register length determined by the address inputs is reached.
Inputs

Output

Am

CLK

Am

Q(Am)

Am

Q(Am-1)

m= 0, 1, 2, 3

Usage
For HDL, this design element can be inferred or instantiated.

VHDL Instantiation Template

-- SRL16_1: 16-bit shift register LUT operating on negedge of clock
-All FPGAs
-- Xilinx HDL Language Template version 6.1i
SRL16_1_inst : SRL16_1
-- The following generic declaration is only necessary if
-- you wish to change the initial.
-- contents of the SRL to anything other than all zero's.
generic map (

Libraries Guide
ISE 6.3i

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1131

SRL16_1

INIT => X"0000")

port map (
Q => Q,
-- SRL data output
A0 => A0,
-- Select[0] input
A1 => A1,
-- Select[1] input
A2 => A2,
-- Select[2] input
A3 => A3,
-- Select[3] input
CLK => CLK,
-- Clock input
D => D
-- SRL data input
);
-- End of SRL16_1_inst instantiation

Verilog Instantiation Template

SRL16_1 SRL16_1_inst (
.Q(Q),
// SRL data output
.A0(A0),
// Select[0] input
.A1(A1),
// Select[1] input
.A2(A2),
// Select[2] input
.A3(A3),
// Select[3] input
.CLK(CLK),
// Clock input
.D(D)
// SRL data input
);
//
//
//
//

The following defparam declaration is only necessary if you wish to

change the initial contents of the SRL to anything other than all
zero's. If the instance name to the SRL is changed, that change
needs to be reflected in the defparam statements.
defparam SRL16_1_inst.INIT = 16'h0000;

// End of SRL16_1_inst instantiation

Commonly Used Constraints

BEL, U_SET, INIT

1132

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Libraries Guide
ISE 6.3i

SRL16E

SRL16E
16-Bit Shift Register Look-Up-Table (LUT) with Clock Enable
Architectures Supported
SRL16E
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

SRL16E

CE
CLK
A0
A1
A2
A3

X8423

No

CoolRunner XPLA3

No

CoolRunner-II

No

SRL16E is a shift register look up table (LUT). The inputs A3, A2, A1, and A0 select
the output length of the shift register. The shift register may be of a fixed, static length
or dynamically adjusted. See Static Length Mode and Dynamic Length Mode in
SRL16.
The shift register LUT contents are initialized by assigning a four-digit hexadecimal
number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most
significant bit. If an INIT value is not specified, it defaults to a value of four zeros
(0000) so that the shift register LUT is cleared during configuration.
When CE is High, the data (D) is loaded into the first bit of the shift register during the
Low-to-High clock (CLK) transition. During subsequent Low-to-High clock
transitions, when CE is High, data is shifted to the next highest bit position as new
data is loaded. The data appears on the Q output when the shift register length
determined by the address inputs is reached.
When CE is Low, the register ignores clock transitions.
Inputs

Output

Am

CE

CLK

Am

Q(Am)

Am

Q(Am-1)

m= 0, 1, 2, 3

Usage
For HDL, this design element can be inferred or instantiated.

VHDL Instantiation Template

-- SRL16E: 16-bit shift register LUT with clock enable operating
-- on posedge of clock
-All FPGAs
-- Xilinx HDL Language Template version 6.1i
SRL16E_inst : SRL16E

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1133

SRL16E

-- The following generic declaration is only necessary if

-- you wish to change the initial.
-- contents of the SRL to anything other than all zero's.
generic map (
INIT => X"0000")
port map (
Q => Q,
-- SRL data output
A0 => A0,
-- Select[0] input
A1 => A1,
-- Select[1] input
A2 => A2,
-- Select[2] input
A3 => A3,
-- Select[3] input
CE => CE,
-- Clock enable input
CLK => CLK,
-- Clock input
D => D
-- SRL data input
);
-- End of SRL16E_inst instantiation

Verilog Instantiation Template

SRL16E SRL16E_inst
.Q(Q),
//
.A0(A0),
//
.A1(A1),
//
.A2(A2),
//
.A3(A3),
//
.CE(CE),
//
.CLK(CLK),
//
.D(D)
//
);
//
//
//
//

(
SRL data output
Select[0] input
Select[1] input
Select[2] input
Select[3] input
Clock enable input
Clock input
SRL data input

The following defparam declaration is only necessary if you wish to

change the initial contents of the SRL to anything other than all
zero's. If the instance name to the SRL is changed, that change
needs to be reflected in the defparam statements.
defparam SRL16E_inst.INIT = 16'h0000;

// End of SRL16E_inst instantiation

Commonly Used Constraints

BEL, U_SET, INIT

1134

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Libraries Guide
ISE 6.3i

SRL16E_1

SRL16E_1
16-Bit Shift Register Look-Up-Table (LUT) with Negative-Edge Clock
and Clock Enable
Architectures Supported
SRLC16E_1
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

SRL16E_1

CE
CLK
A0
A1
A2
A3

X8421

No

CoolRunner XPLA3

No

CoolRunner-II

No

SRL16E_1 is a shift register look up table (LUT) with clock enable (CE). The inputs A3,
A2, A1, and A0 select the output length of the shift register. The shift register may be
of a fixed, static length or dynamically adjusted. See Static Length Mode and
Dynamic Length Mode in the SRL16.
The shift register LUT contents are initialized by assigning a four-digit hexadecimal
number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most
significant bit. If an INIT value is not specified, it defaults to a value of four zeros
(0000) so that the shift register LUT is cleared during configuration.
When CE is High, the data (D) is loaded into the first bit of the shift register during the
High-to-Low clock (CLK) transition. During subsequent High-to-Low clock
transitions, when CE is High, data is shifted to the next highest bit position as new
data is loaded. The data appears on the Q output when the shift register length
determined by the address inputs is reached.
When CE is Low, the register ignores clock transitions.
Inputs

Output

Am

CE

CLK

Am

Q(Am)

Am

Q(Am-1)

m= 0, 1, 2, 3

Usage
For HDL, this design element can be inferred or instantiated.

VHDL Instantiation Template

-- SRL16E_1: 16-bit shift register LUT with clock enable
-- operating on negedge of clock
-All FPGAs
-- Xilinx HDL Language Template version 6.1i

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1135

SRL16E_1

SRL16E_1_inst : SRL16E_1
-- The following generic declaration is only necessary if
-- you wish to change the initial.
-- contents of the SRL to anything other than all zero's.
generic map (
INIT => X"0000")
port map (
Q => Q,
-- SRL data output
A0 => A0,
-- Select[0] input
A1 => A1,
-- Select[1] input
A2 => A2,
-- Select[2] input
A3 => A3,
-- Select[3] input
CE => CE,
-- Clock enable input
CLK => CLK,
-- Clock input
D => D
-- SRL data input
);
-- End of SRL16E_1_inst instantiation

Verilog Instantiation Template

SRL16E_1 SRL16E_1_inst (
.Q(Q),
// SRL data output
.A0(A0),
// Select[0] input
.A1(A1),
// Select[1] input
.A2(A2),
// Select[2] input
.A3(A3),
// Select[3] input
.CE(CE),
// Clock enable input
.CLK(CLK),
// Clock input
.D(D)
// SRL data input
);
//
//
//
//

The following defparam declaration is only necessary if you wish to

change the initial contents of the SRL to anything other than all
zero's. If the instance name to the SRL is changed, that change
needs to be reflected in the defparam statements.
defparam SRL16E_1_inst.INIT = 16'h0000;

// End of SRL16E_1_inst instantiation

Commonly Used Constraints

BEL, U_SET, and INIT

1136

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Libraries Guide
ISE 6.3i

SRLC16

SRLC16
16-Bit Shift Register Look-Up-Table (LUT) with Carry
Architectures Supported
SRLC16
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

SRLC16
Q

CLK

No

CoolRunner XPLA3

No

CoolRunner-II

No

SRLC16 is a shift register look up table (LUT) with Carry. The inputs A3, A2, A1, and
A0 select the output length of the shift register. The shift register may be of a fixed,
static length, or it may be dynamically adjusted.

Q15

The shift register LUT contents are initialized by assigning a four-digit hexadecimal
number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most
significant bit. If an INIT value is not specified, it defaults to a value of four zeros
(0000) so that the shift register LUT is cleared during configuration.

A0
A1
A2
A3

X9296

The data (D) is loaded into the first bit of the shift register during the Low-to-High
clock (CLK) transition. During subsequent Low-to-High clock transitions data is
shifted to the next highest bit position as new data is loaded. The data appears on the
Q output when the shift register length determined by the address inputs is reached.
The Q15 output is available for the user to cascade multiple shift register LUTs to
create larger shift registers.
For information about the static length mode, see Static Length Mode in SRL16.
For information about the dynamic length mode, see Dynamic Length Mode in
SRL16.
Inputs

Output

Am

CLK

Am

Q(Am)

Am

Q(Am-1)

m= 0, 1, 2, 3

Usage
For HDL, this design element can be inferred or instantiated.

VHDL Instantiation Template

-- SRLC16: 16-bit cascadable shift register LUT operating on
-- posedge of clock
-Virtex-II/II-Pro, Spartan-3

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1137

SRLC16

-- Xilinx

HDL Language Template version 6.1i

SRLC16_inst : SRLC16
-- The following generic declaration is only necessary if
-- you wish to change the initial.
-- contents of the SRL to anything other than all zero's.
generic map (
INIT => X"0000")
port map (
Q => Q,
-- SRL data output
Q15 => Q15,
-- Carry output (connect to next SRL)
A0 => A0,
-- Select[0] input
A1 => A1,
-- Select[1] input
A2 => A2,
-- Select[2] input
A3 => A3,
-- Select[3] input
CLK => CLK,
-- Clock input
D => D
-- SRL data input
);
-- End of SRLC16_inst instantiation

Verilog Instantiation Template

SRLC16 SRLC16_inst
.Q(Q),
//
.Q15(Q15),
//
.A0(A0),
//
.A1(A1),
//
.A2(A2),
//
.A3(A3),
//
.CLK(CLK),
//
.D(D)
//
);
//
//
//
//

(
SRL data output
Carry output (connect to next SRL)
Select[0] input
Select[1] input
Select[2] input
Select[3] input
Clock input
SRL data input

The following defparam declaration is only necessary if you wish to

change the initial contents of the SRL to anything other than all
zero's. If the instance name to the SRL is changed, that change
needs to be reflected in the defparam statements.
defparam SRLC16_inst.INIT = 16'h0000;

// End of SRLC16_inst instantiation

Commonly Used Constraints

INIT

1138

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Libraries Guide
ISE 6.3i

SRLC16_1

SRLC16_1
16-Bit Shift Register Look-Up-Table (LUT) with Carry and NegativeEdge Clock
Architectures Supported
SRLC16_1
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

SRLC16_1
Q

CLK

Q15

A0
A1
A2
A3

X9297

No

CoolRunner XPLA3

No

CoolRunner-II

No

SRLC16_1 is a shift register look up table (LUT) with carry and a negative-edge clock.
The inputs A3, A2, A1, and A0 select the output length of the shift register. The shift
register may be of a fixed, static length or it may be dynamically adjusted. See Static
Length Mode and Dynamic Length Mode in SRL16.
The shift register LUT contents are initialized by assigning a four-digit hexadecimal
number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most
significant bit. If an INIT value is not specified, it defaults to a value of four zeros
(0000) so that the shift register LUT is cleared during configuration.
The data (D) is loaded into the first bit of the shift register during the High-to-Low
clock (CLK) transition. During subsequent High-to-Low clock transitions data is
shifted to the next highest bit position as new data is loaded. The data appears on the
Q output when the shift register length determined by the address inputs is reached.
The Q15 output is available for the user to cascade multiple shift register LUTs to
create larger shift registers.
Inputs

Output

Am

CLK

Q15

Am

Q(Am)

No Chg

Am

Q(Am-1)

Q14

m= 0, 1, 2, 3

Usage
For HDL, this design element can inferred.

Verilog Instantiation Template

-- SRLC16_1: 16-bit cascadable shift register LUT operating
-- on negedge of clock
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Language Template version 6.1i

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1139

SRLC16_1

SRLC16_1_inst : SRLC16_1
-- The following generic declaration is only necessary if you
-- wish to change the initial.
-- contents of the SRL to anything other than all zero's.
generic map (
INIT => X"0000")
port map (
Q => Q,
-- SRL data output
Q15 => Q15,
-- Carry output (connect to next SRL)
A0 => A0,
-- Select[0] input
A1 => A1,
-- Select[1] input
A2 => A2,
-- Select[2] input
A3 => A3,
-- Select[3] input
CLK => CLK,
-- Clock input
D => D
-- SRL data input
);
-- End of SRLC16_1_inst instantiation

Commonly Used Constraints

BEL, U_SET, INIT

1140

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Libraries Guide
ISE 6.3i

SRLC16E

SRLC16E
16-Bit Shift Register Look-Up-Table (LUT) with Carry and Clock Enable
Architectures Supported
SRLC16E
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

SRLC16E

CE
CLK

No

CoolRunner XPLA3

No

CoolRunner-II

No

SRLC16E is a shift register look up table (LUT) with carry and clock enable. The
inputs A3, A2, A1, and A0 select the output length of the shift register. The shift
register may be of a fixed, static length or it may be dynamically adjusted.

Q15

The shift register LUT contents are initialized by assigning a four-digit hexadecimal
number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most
significant bit. If an INIT value is not specified, it defaults to a value of four zeros
(0000) so that the shift register LUT is cleared during configuration.

A0
A1
A2
A3

X9298

The data (D) is loaded into the first bit of the shift register during the Low-to-High
clock (CLK) transition. When CE is High, during subsequent Low-to-High clock
transitions, data is shifted to the next highest bit position as new data is loaded. The
data appears on the Q output when the shift register length determined by the
address inputs is reached.
The Q15 output is available for the user to cascade multiple shift register LUTs to
create larger shift registers.
For information about the static length mode, see Static Length Mode in SRL16.
For information about the dynamic length mode, see Dynamic Length Mode in
SRL16.
Inputs

Output

Am

CLK

CE

Q15

Am

Q(Am)

Q(15)

Am

Q(Am)

Q(15)

Am

Q(Am-1)

Q15

m= 0, 1, 2, 3

Usage
For HDL, this design element can be inferred or instantiated.

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1141

SRLC16E

VHDL Instantiation Template

-- SRLC16E: 16-bit cascable shift register LUT with clock
-- enable operating on posedge of clock
-Virtex-II/II-Pro, Spartan-3
-- Xilinx HDL Language Template version 6.1i
SRLC16E_inst : SRLC16E
-- The following generic declaration is only necessary if you
-- wish to change the initial.
-- contents of the SRL to anything other than all zero's.
generic map (
INIT => X"0000")
port map (
Q => Q,
-- SRL data output
Q15 => Q15,
-- Carry output (connect to next SRL)
A0 => A0,
-- Select[0] input
A1 => A1,
-- Select[1] input
A2 => A2,
-- Select[2] input
A3 => A3,
-- Select[3] input
CE => CE,
-- Clock enable input
CLK => CLK,
-- Clock input
D => D
-- SRL data input
);
-- End of SRLC16E_inst instantiation

Verilog Instantiation Template

SRLC16E SRLC16E_inst (
.Q(Q),
// SRL data output
.Q15(Q15),
// Carry output (connect to next SRL)
.A0(A0),
// Select[0] input
.A1(A1),
// Select[1] input
.A2(A2),
// Select[2] input
.A3(A3),
// Select[3] input
.CE(CE),
// Clock enable input
.CLK(CLK),
// Clock input
.D(D)
// SRL data input
);
//
//
//
//

The following defparam declaration is only necessary if you wish to

change the initial contents of the SRL to anything other than all
zero's. If the instance name to the SRL is changed, that change
needs to be reflected in the defparam statements.
defparam SRLC16E_inst.INIT = 16'h0000;

// End of SRLC16E_inst instantiation

Commonly Used Constraints

INIT

1142

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Libraries Guide
ISE 6.3i

SRLC16E_1

SRLC16E_1
16-Bit Shift Register Look-Up-Table (LUT) with Carry, Negative-Edge
Clock, and Clock Enable
Architectures Supported
SRLC16E_1
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

SRLC16E_1

CE
CLK

Q
Q15

A0
A1
A2
A3

X9299

No

CoolRunner XPLA3

No

CoolRunner-II

No

SRLC16E_1 is a shift register look up table (LUT) with carry, clock enable, and
negative-edge clock. The inputs A3, A2, A1, and A0 select the output length of the
shift register. The shift register may be of a fixed, static length or it may be
dynamically adjusted. See SRLC16 and Dynamic Length Mode in SRL16.
The shift register LUT contents are initialized by assigning a four-digit hexadecimal
number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most
significant bit. If an INIT value is not specified, it defaults to a value of four zeros
(0000) so that the shift register LUT is cleared during configuration.
When CE is High, the data (D) is loaded into the first bit of the shift register during the
High-to-Low clock (CLK) transition. During subsequent High-to-Low clock
transitions data is shifted to the next highest bit position as new data is loaded when
CE is HIgh. The data appears on the Q output when the shift register length
determined by the address inputs is reached.
The Q15 output is available for the user to cascade multiple shift register LUTs to
create larger shift registers.
Inputs

Output

Am

CE

CLK

Q15

Am

Q(Am)

No Chg

Am

Q(Am)

No Chg

Am

Q(Am-1)

Q14

m= 0, 1, 2, 3

Usage
For HDL, this design element can be inferred or instantiated.

VHDL Instantiation Template

-- SRLC16E_1: 16-bit shift register LUT with clock enable
-- operating on negedge of clock

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1143

SRLC16E_1

--- Xilinx

Virtex-II/II-Pro, Spartan-3
HDL Language Template version 6.1i

SRLC16_1_inst : SRLC16_1
-- The following generic declaration is only necessary if you
-- wish to change the initial.
-- contents of the SRL to anything other than all zero's.
generic map (
INIT => X"0000")
port map (
Q => Q,
-- SRL data output
Q15 => Q15,
-- Carry output (connect to next SRL)
A0 => A0,
-- Select[0] input
A1 => A1,
-- Select[1] input
A2 => A2,
-- Select[2] input
A3 => A3,
-- Select[3] input
CE => CE,
-- Clock enable input
CLK => CLK,
-- Clock input
D => D
-- SRL data input
);
-- End of SRLC16E_1_inst instantiation

Verilog Instantiation Template

SRLC16E_1 SRLC16E_1_inst (
.Q(Q),
// SRL data output
.Q15(Q15),
// Carry output (connect to next SRL)
.A0(A0),
// Select[0] input
.A1(A1),
// Select[1] input
.A2(A2),
// Select[2] input
.A3(A3),
// Select[3] input
.CE(CE),
// Clock enable input
.CLK(CLK),
// Clock input
.D(D)
// SRL data input
);
//
//
//
//

The following defparam declaration is only necessary if you wish to

change the initial contents of the SRL to anything other than all
zero's. If the instance name to the SRL is changed, that change
needs to be reflected in the defparam statements.
defparam SRLC16E_1_inst.INIT = 16'h0000;

// End of SRLC16E_1_inst instantiation

Commonly Used Constraints

INIT

1144

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Libraries Guide
ISE 6.3i

STARTBUF_architecture

STARTBUF_architecture
VHDL Simulation of FPGA Designs
Architectures Supported
STARTBUF_architecture
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

STARTBUF_architecture is used for VHDL simulation of FPGA designs that require the
use of the STARTUP block. The difference between the STARTBUF_architecture and
the STARTUP block is that the STARTBUF_architecture contains output ports which
may be connected to all register set/resets in the design (GSROUT) or to all
I/O three-state controls (GTSOUT) so that these functions may be functionally
simulated. This design element should not be used for Verilog or schematic entry. In
order to use the STARTBUF_architecture, the desired input(s) should be connected to a
top-level port in the design and the corresponding output(s) must be connected to
either the three-state control signal for all inferred and instantiated output buffers in
the design (GTSOUT) or all inferred or instantiated register set/resets in the design.
During simulation, the inputs to the STARTBUF_architecture can be toggled by the
testbench in order to activate the global three-state or global set/reset signal in the
design. This should be done at the beginning of the simulation to simulate the
behavior of the registers and I/O during configuration. It may also be applied during
simulation to simulate a reconfiguration (ProG pin high) of the device. During
synthesis and implementation, this component will be treated as a STARTUP block.
The connected input ports to this component should remain in the design and be
connected to the correct corresponding global resource.
For more information, see the Xilinx Synthesis and Verification Design Guide.
The value at port GSROUT will be always the be value at port GSRIN. The value at
port GTSOUT will always be the value at port GTSIN. CLKIN has no effect on
simulation.

VHDL Instantiation Code

Following are four examples:
component STARTBUF_SPARTAN2
port (GSROUT
: out std_ulogic;
GTSOUT
: out std_ulogic;
CLKIN
: in std_ulogic;
GSRIN
: in std_ulogic;
GTSIN
: in std_ulogic);
end component;

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ISE 6.3i

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1145

STARTBUF_architecture

component STARTBUF_VIRTEX
port (GTSOUT
: out std_ulogic;
GSROUT
: out std_ulogic;
CLKIN
: in std_ulogic;
GSRIN
: in std_ulogic;
GTSIN
: in std_ulogic);
end component;
component STARTBUF_VIRTEX2
port (GSROUT
: out std_ulogic;
GTSOUT
: out std_ulogic;
CLKIN
: in std_ulogic;
GSRIN
: in std_ulogic;
GTSIN
: in std_ulogic);
end component;
component STARTBUF_VIRTEX4
port(
EOSOUT : out std_ulogic;
GSROUT : out std_ulogic;
GTSOUT : out std_ulogic;
CLKIN : in
GSRIN : in
GTSIN : in
);
end component;

1146

std_ulogic := 'X';
std_ulogic := 'X';
std_ulogic := 'X'

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Libraries Guide
ISE 6.3i

STARTUP_SPARTAN2

STARTUP_SPARTAN2
Spartan-II User Interface to Global Clock, Reset, and 3-State Controls
Architectures Supported
STARTUP_SPARTAN2
Spartan-II, Spartan-IIE

Primitive*

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X

No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

* Supported for Spartan-II but not for Spartan-IIE,

which is supported by STARTUP_VIRTEX.

STARTUP_SPARTAN2
GSR
GTS

CLK

The STARTUP_SPARTAN2 primitive is used for Global Set/Reset, global 3-state

control, and the user configuration clock. The Global Set/Reset (GSR) input, when
High, sets or resets all flip-flops, all latches, and every block RAM (RAMB4) output
register in the device, depending on the initialization state (S or R) of the component.
Note: Block RAMB4 content, LUT RAMs, delay locked loop elements (CLKDLL, CLKDLLHF,
BUFGDLL), and shift register LUTs (SRL16, SRL16_1, SRL16E, SRL16E_1) are not set/reset.

X8896

Following configuration, the global 3-state control (GTS), when Highand BSCAN is
not enabled and executing an EXTEST instructionforces all the IOB outputs into
high impedance mode, which isolates the device outputs from the circuit but leaves
the inputs active.
Note: GTS= Global 3-State
Including the STARTUP_SPARTAN2 symbol in a design is optional. You must include
the symbol under the following conditions.

To exert external control over global set/reset, connect the GSR pin to a top level
port and an IBUF, as shown here.
STARTUP_SPARTAN2
GSR
GTS

CLK

X8904

To exert external control over global 3-state, connect the GTS pin to a top level
port and IBUF, as shown here.
STARTUP_SPARTAN2
GSR
GTS

CLK

X8905

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1147

STARTUP_SPARTAN2

To synchronize startup to a user clock, connect the user clock signal to the CLK
input, as shown here. Furthermore, user clock must be selected in the BitGen
program.
STARTUP_SPARTAN2
GSR
GTS

CLK

X8906

You can use location constraints to specify the pin from which GSR or GTS (or both) is
accessed.

Usage
For HDL, this design element typically is instantiated rather than inferred.

VHDL Instantiation Template

-- STARTUP_SPARTAN2: Startup primitve for GSR, GTS or
-- startup sequence
-control. Spartan-II
-- Xilinx HDL Language Template version 6.1i
STARTUP_SPARTAN2_inst : STARTUP_SPARTAN2
port map (
CLK => CLK,
-- Clock input for start-up sequence
GSR => GSR,
-- Global Set/Reset input
GTS => GTS
-- Global 3-state input
);
-- End of STARTUP_SPARTAN2_inst instantiation

Verilog Instantiation Template

STARTUP_SPARTAN2 STARTUP_SPARTAN2_inst (
.CLK(CLK),
// Clock input for start-up sequence
.GSR(GSR),
// Global Set/Reset input
.GTS(GTS)
// Global 3-state input
);
// End of STARTUP_SPARTAN2_inst instantiation

1148

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Libraries Guide
ISE 6.3i

STARTUP_SPARTAN3

STARTUP_SPARTAN3
Spartan-3 User Interface to Global Clock, Reset, and 3-State Controls
Architectures Supported
STARTUP_SPARTAN3
Spartan-II, Spartan-IIE

No

Spartan-3

Primitive

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

STARTUP_SPARTAN3
GSR

The STARTUP_SPARTAN3 primitive is used for Global Set/Reset, global 3-state

control, and the user configuration clock. The Global Set/Reset (GSR) input, when
High, sets or resets all flip-flops, all latches, and every block RAMB16 output register
in the device, depending on the initialization state (INIT=1 or 0) of the component.

GTS
CLK

X9932

Note: Block RAM content, LUT RAMs, the Digital Clock Manager (DCM), and shift register
LUTs (SRL16, SRL16_1, SRL16E, SRL16E_1, SRLC16, SRLC16_1, SRLC16E, and
SRLC16E_1) are not set/reset.
Following configuration, the global 3-state control (GTS), when Highand BSCAN is
not enabled and executing an EXTEST instructionforces all the IOB outputs into
high impedance mode, which isolates the device outputs from the circuit but leaves
the inputs active.
Note: GTS= Global 3-State
Including the STARTUP_SPARTAN3 symbol in a design is optional. You must include
the symbol under the following conditions.

To exert external control over global set/reset, connect the GSR pin to a top level
port and an IBUF, as shown here.
GSR
GTS

CLK

X9391

Libraries Guide
ISE 6.3i

To exert external control over global 3-state, connect the GTS pin to a top level
port and IBUF, as shown here.

www.xilinx.com
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1149

STARTUP_SPARTAN3

GSR
GTS

CLK

X9392

To synchronize startup to a user clock, connect the user clock signal to the CLK
input, as shown here. Furthermore, user clock must be selected in the BitGen
program.
GSR
GTS

CLK

X9393

You can use location constraints to specify the pin from which GSR or GTS (or both) is
accessed.

Usage
For HDL, this design element typically is instantiated rather than inferred.

VHDL Instantiation Template

-- STARTUP_SPARTAN3: Startup primitve for GSR, GTS or startup sequence
-control. Virtex-II/II-Pro
-- Xilinx HDL Language Template version 6.1i
STARTUP_SPARTAN3_inst : STARTUP_SPARTAN3
port map (
CLK => CLK,
-- Clock input for start-up sequence
GSR => GSR,
-- Global Set/Reset input
GTS => GTS
-- Global 3-state input
);
-- End of STARTUP_SPARTAN3_inst instantiation

Verilog Instantiation Template

STARTUP_SPARTAN3 STARTUP_SPARTAN3_inst (
.CLK(CLK),
// Clock input for start-up sequence
.GSR(GSR),
// Global Set/Reset input
.GTS(GTS)
// Global 3-state input
);
// End of STARTUP_SPARTAN3_inst instantiation

1150

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Libraries Guide
ISE 6.3i

STARTUP_VIRTEX

STARTUP_VIRTEX
Virtex and Virtex-E User Interface to Global Clock, Reset, and 3-State
Controls
Architectures Supported
STARTUP_VIRTEX
Spartan-II, Spartan-IIE

Primitive*

Spartan-3

No

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

* Supported for Spartan-IIE but not for Spartan-II

which is supported by STARTUP_SPARTAN2..

STARTUP_VIRTEX
GSR
GTS

CLK

X8682

The STARTUP_VIRTEX primitive is used for Global Set/Reset, global 3-state control,
and the user configuration clock. The Global Set/Reset (GSR) input, when High, sets
or resets all flip-flops, all latches, and every block RAM (RAMB4) output register in
the device, depending on the initialization state (S or R) of the component. For VirtexII, Virtex-II Pro, and Virtex-II Pro X, see STARTUP_VIRTEX2.
Note: Block RAMB4 content, LUT RAMs, delay locked loop elements (CLKDLL, CLKDLLHF,
BUFGDLL), and shift register LUTs (SRL16, SRL16_1, SRL16E, SRL16E_1) are not set/reset.
Following configuration, the global 3-state control (GTS), when Highand BSCAN is
not enabled and executing an EXTEST instructionforces all the IOB outputs into
high impedance mode, which isolates the device outputs from the circuit but leaves
the inputs active.
Note: GTS= Global 3-State
Including the STARTUP_VIRTEX symbol in a design is optional. You must include the
symbol under the following conditions.

To exert external control over global set/reset, connect the GSR pin to a top level
port and an IBUF, as shown here.
STARTUP_VIRTEX
GSR
GTS

CLK

X8683

Libraries Guide
ISE 6.3i

To exert external control over global 3-state, connect the GTS pin to a top level
port and IBUF, as shown here.

www.xilinx.com
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1151

STARTUP_VIRTEX

STARTUP_VIRTEX
GSR
GTS

CLK

X8684

To synchronize startup to a user clock, connect the user clock signal to the CLK
input, as shown here. Furthermore, user clock must be selected in the BitGen
program.
STARTUP_VIRTEX
GSR
GTS

CLK

X8685

You can use location constraints to specify the pin from which GSR or GTS (or both) is
accessed.

Usage
For HDL, this design element typically is instantiated rather than inferred.

VHDL Instantiation Template

-- STARTUP_VIRTEX: Startup primitve for GSR, GTS or startup sequence
-control. Virtex/E, Spartan-IIE
-- Xilinx HDL Language Template version 6.1i
STARTUP_VIRTEX_inst
port map (
CLK => CLK,
-GSR => GSR,
-GTS => GTS
-);

: STARTUP_VIRTEX
Clock input for start-up sequence
Global Set/Reset input
Global 3-state input

-- End of STARTUP_VIRTEX_inst instantiation

Verilog Instantiation Template

STARTUP_VIRTEX STARTUP_VIRTEX_inst (
.CLK(CLK),
// Clock input for start-up sequence
.GSR(GSR),
// Global Set/Reset input
.GTS(GTS)
// Global 3-state input
);
// End of STARTUP_VIRTEX_inst instantiation

1152

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Libraries Guide
ISE 6.3i

STARTUP_VIRTEX2

STARTUP_VIRTEX2
Virtex-II, Virtex-II Pro, and Virtex-II Pro X User Interface to Global
Clock, Reset, and 3-State Controls
Architectures Supported
STARTUP_VIRTEX2
Spartan-II, Spartan-IIE

No

Spartan-3

No

Virtex, Virtex-E

No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

STARTUP_VIRTEX2
GSR
GTS
CLK
X9300

No

CoolRunner XPLA3

No

CoolRunner-II

No

The STARTUP_VIRTEX2 primitive is used for Global Set/Reset, global 3-state control,
and the user configuration clock. The Global Set/Reset (GSR) input, when High, sets
or resets all flip-flops, all latches, and every block RAMB16 output register in the
device, depending on the initialization state (INIT=1 or 0) of the component. For
Virtex and Virtex-E, see STARTUP_VIRTEX.
Note: Block RAM content, LUT RAMs, the Digital Clock Manager (DCM), and shift register
LUTs (SRL16, SRL16_1, SRL16E, SRL16E_1, SRLC16, SRLC16_1, SRLC16E, and
SRLC16E_1) are not set/reset.
Following configuration, the global 3-state control (GTS), when Highand BSCAN is
not enabled and executing an EXTEST instructionforces all the IOB outputs into
high impedance mode, which isolates the device outputs from the circuit but leaves
the inputs active.
Note: GTS= Global 3-State
Including the STARTUP_VIRTEX2 symbol in a design is optional. You must include
the symbol under the following conditions.

To exert external control over global set/reset, connect the GSR pin to a top level
port and an IBUF, as shown here.
GSR
GTS

CLK

X9391

Libraries Guide
ISE 6.3i

To exert external control over global 3-state, connect the GTS pin to a top level
port and IBUF, as shown here.

www.xilinx.com
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1153

STARTUP_VIRTEX2

GSR
GTS

CLK

X9392

To synchronize startup to a user clock, connect the user clock signal to the CLK
input, as shown here. Furthermore, user clock must be selected in the BitGen
program.
GSR
GTS

CLK

X9393

You can use location constraints to specify the pin from which GSR or GTS (or both) is
accessed.

Usage
For HDL, this design element typically is instantiated rather than inferred.

VHDL Instantiation Template

-- STARTUP_VIRTEX2: Startup primitve for GSR, GTS or startup sequence
-control. Virtex-II/II-Pro
-- Xilinx HDL Language Template version 6.1i
STARTUP_VIRTEX2_inst : STARTUP_VIRTEX2
port map (
CLK => CLK,
-- Clock input for start-up sequence
GSR => GSR,
-- Global Set/Reset input
GTS => GTS
-- Global 3-state input
);
-- End of STARTUP_VIRTEX2_inst instantiation

Verilog Instantiation Template

STARTUP_VIRTEX2 STARTUP_VIRTEX2_inst (
.CLK(CLK),
// Clock input for start-up sequence
.GSR(GSR),
// Global Set/Reset input
.GTS(GTS)
// Global 3-state input
);
// End of STARTUP_VIRTEX2_inst instantiation

1154

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Libraries Guide
ISE 6.3i

TOC

TOC
Three-State On Configuration
Architectures Supported
TOC
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

The TOC is a component used for VHDL simulation of FPGA designs. This
component should not be used for Verilog or schematic entry. The TOC's function is to
mimic the function of the internal three-state signal during the FPGA configuration
process. In order to use TOC, it must be connected to the three-state signal for all
inferred and instantiated output buffers in the design. During synthesis and
implementation, this three-state signal will use the dedicated global three-state
network and will not use local routing resources. During simulation, TOC will emit a
one-shot pulse for the amount of time specified by the WIDTH generic (default is 100
ns). This one-shot pulse is intended to three-state all outputs so that at the beginning
of operation, all outputs are not being driven as would happen in the real silicon
during configuration of the device.
For more information, see the Xilinx Synthesis and Verification Design Guide.
Port O will be high at simulation time 0 for the amount of time specified by the
WIDTH generic attribute. After that time, it will be 0. This will not affect
implementation in any way.

VHDL Instantiation Code

component TOC
-- synthesis translate_off
generic (WIDTH : Time := 100 ns);
-- synthesis translate_on
port (O : out std_ulogic := '0');
end component;

Commonly Used Constraints

For simulation, the WIDTH generic can be modified to change the amount of time the
one-shot pulse is applied for.
There are no supported constraints for this component for implementation.

Libraries Guide
ISE 6.3i

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1155

1156

TOC

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Libraries Guide
ISE 6.3i

TOCBUF

TOCBUF
Three-State On Configuration Buffer
Architectures Supported
TOCBUF
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

No

CoolRunner XPLA3

No

CoolRunner-II

No

The TOCBUF is a component used for VHDL simulation of FPGA designs. It is similar
to the TOC component except that it contains an input for controlling the global I/O
three-state function rather than a one-shot. This component should not be used for
Verilog or schematic entry. The TOCBUF's function allows user control of the function
of the global I/O three-state signal as done during the FPGA configuration process. In
order to use the TOCBUF, the input should be connected to a top-level port in the
design and the output must be connected to the three-state control signal for all
inferred and instantiated output buffers in the design.
During simulation, the input to the TOCBUF can be toggled by the testbench in order
to activate the global three-state signal in the design. This should be done at the
beginning of the simulation to simulate the behavior of the I/O during configuration.
It may also be applied during simulation to simulate a reconfiguration (ProG pin
high) of the device. During synthesis and implementation, this three-state signal uses
the dedicated global three-state network and does not use local routing resources. The
port connected to this component is optimized out of the design and does not use any
pin resources. If you want to have the port implemented in the design, a
STARTBUF_architecture should be used. In order to replace this port during back-end
simulation, the -tp switch should be used when invoking the NGD2VER or
NGD2VHDL netlister. If using the ISE GUI, use the Bring Out Global Three-state Net
as a Port option in the Simulation Model Properties window.
For more information, see the Xilinx Synthesis and Verification Design Guide.
The value at port O will be always be the value at port I (it is a buffer).

VHDL Instantiation Code

component TOCBUF
port (I : in std_ulogic;
O : out std_ulogic);
end component;

Commonly Used Constraints

None

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1157

1158

TOCBUF

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

UPAD

UPAD
Connects the I/O Node of an IOB to the Internal PLD Circuit
Architectures Supported
UPAD
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

UPAD

No

CoolRunner XPLA3

No

CoolRunner-II

No

A UPAD allows the use of any unbonded IOBs in a device. It is used the same way as
an IOPAD except that the signal output is not visible on any external device pins.

X3843

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1159

1160

UPAD

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

VCC

VCC
VCC-Connection Signal Tag
Architectures Supported
VCC
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

VCC
X8721

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

The VCC signal tag or parameter forces a net or input function to a logic High level. A
net tied to VCC cannot have any other source.
When the placement and routing software encounters a net or input function tied to
VCC, it removes any logic that is disabled by the VCC signal. The VCC signal is only
implemented when the disabled logic cannot be removed.

Usage
VHDL Instantiation Template
-- Component Declaration for VCC should be placed
-- after architecture statement but before begin keyword
component VCC
port (P : out STD_ULOGIC);
end component;
-- Component Attribute specification for VCC
-- should be placed after architecture declaration but
-- before the begin keyword
-- Enter attributes here

-- Component Instantiation for VCC should be placed

-- in architecture after the begin keyword
VCC_INSTANCE_NAME : VCC
port map (P => user_P);

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1161

VCC

Verilog Instantiation Template

VCC instance_name (.P (user_P));

1162

www.xilinx.com
1-800-255-7778

Libraries Guide
ISE 6.3i

XNOR2-9

XNOR2-9
2- to 9-Input XNOR Gates with Non-Inverted Inputs
Architectures Supported
XNOR2, XNOR3, XNOR4
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive
XNOR5

Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

XNOR6, XNOR7, XNOR8

Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro
XNOR9

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

Libraries Guide
ISE 6.3i

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

www.xilinx.com
1-800-255-7778

1163

XNOR2-9

I1
I0

I6
I5

I4
I2
I1
I0

I2
O

I1

I3

XNOR2

I0

XNOR7
XNOR3

I7

I3

I6

I2
I1

I5

I4
I3

I0

I2

XNOR4

I1

I4
I3

I0

I2

XNOR8

I1
I0

I5

IA
I7
I6
I5

I4

I4

I3
I2

I3
I2
I1
I0

XNOR5

I1
I0

XNOR9

XNOR6

X9439

XNOR Gate Representations

XNOR functions of up to nine inputs are available. All inputs are non-inverting.
Because each input uses a CLB resource, replace functions with unused inputs with
functions having the necessary number of inputs.
I0
I1
I2

XOR3
I3
I4

XNOR2
XOR2
X7836

XNOR5 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

I0
I1
I2
XOR3
I3
I4
I5

O
XNOR2

XOR3

X7876

XNOR6 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

1164

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Libraries Guide
ISE 6.3i

XNOR2-9

I0
I1
I2
I3
O

XOR4
I4
I5

XNOR2

I6
XOR3
X8205

XNOR7 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

FMAP

I6

I6

I5

I36

I4

I5

I4

I3

I4
I3

I3
XOR4

I2

I36

I1
RLOC=R0C0.S1

I2

FMAP
XNOR4

I36

I4

I2
I1

I3

I1
I0

I0

I2

I1

X8699

RLOC=R0C0.S1

XNOR7 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I6

I6

I5

I5

I36

I4
I3

I4
I3

XOR4
O

I2
I1

I4
I3
I2

I36

I1
RLOC=X0Y0

XNOR4

I0

FMAP
I36
I2
I1
I0

I4
I3
I2

I1
RLOC=X0Y0

X9375

XNOR7 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

I0
I1
I2
I3
I4

XOR4

I5
I6

XNOR2

I7
XOR4
X7877

XNOR8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Libraries Guide
ISE 6.3i

www.xilinx.com
1-800-255-7778

1165

XNOR2-9

FMAP
I4
I3
S1
S2

I2
I1

I7
I6

RLOC=R0C0.S0

S1

I5

I4

FMAP

XOR4

I7

I4

I6

I3

I5
I4

XNOR2

I2

S1

I1

I3

RLOC=R0C0.S1

I2

S0

I1

FMAP

I0
I3

XOR4

I4

I2

I3

I1
I0

I2

S0

I1

X8697

RLOC=R0C0.S1

XNOR8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I4
I7

I3

I6

S1

S1

I5
I4

S0

I2

I1

XOR4
RLOC=X0Y1
O

FMAP

XNOR2

I3
I2

I7
I6

S0

I1
I0

I5
XOR4

I4

I4
I3
I2

S1

I1
RLOC=X0Y0

FMAP
I3
I2
I1
I0

I4
I3
I2

S0

I1
RLOC=X0Y0

X9376

XNOR8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

I0
I1
I2
XOR3
I3
I4

XOR2

I5

O
XOR3
XNOR2

I6
I7
I8
XOR3

X7878

XNOR9 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

1166

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Libraries Guide
ISE 6.3i

XNOR2-9

FMAP
I4

S1

I8

I3

S0
I8

I2

I1

FMAP
I7

I7
I6

S1

I5
I4

I4

I6

I3

I5
I4

I2

S1

I1

XNOR3

XOR4

FMAP
I3

I3

I2

I2

S0

I1

I4
I3

I1
I0

I0

I2

S0

I1

XOR4
X8696

XNOR9 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I4
S1
S0
I8
I8

I3
I2

I1
RLOC=X0Y1

FMAP
I7

I7

I6

I6

S1

I5
I4

I5
I4

XNOR3

XOR4

I3
I2

S1

I1
RLOC=X0Y0

I3
I2

FMAP

S0

I1
I0

I4

I3
XOR4

I2
I1
I0

I4
I3
I2

S0

I1
RLOC=X0Y0
X9377

XNOR9 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements can be inferred or instantiated.

VHDL Instantiation Template for XNOR5

Following is the VHDL code for XNOR5. To instantiate XNOR2, remove I2, I3, and I4.
To instantiate XNOR3, remove I3 and I4, For XNOR4, remove I4. XNOR2B1, and
XNOR2B2 have the same code as XNOR2. XNOR3B1, 3B2, and 3B3 have the same
code as XNOR3 and so forth.
-- Component Declaration for XNOR5 should be placed
-- after architecture statement but before begin keyword
component XNOR5
port (O : out STD_ULOGIC;
I0 : in STD_ULOGIC;
I1 : in STD_ULOGIC;

Libraries Guide
ISE 6.3i

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1167

XNOR2-9

I2 : in STD_ULOGIC;
I3 : in STD_ULOGIC;
I4 : in STD_ULOGIC);
end component;
-- Component Attribute specification for XNOR5
-- should be placed after architecture declaration but
-- before the begin keyword
-- Attributes should be placed here
-- Component Instantiation for XNOR5 should be placed
-- in architecture after the begin keyword
XNOR5_INSTANCE_NAME : XNOR5
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2,
I3 => user_I3,
I4 => user_I4);

Verilog Instantiation Template for XNOR5

XNOR5 XNOR5_instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.I2 (user_I2),
.I3 (user_I3),
.I4 (user_I4));

1168

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Libraries Guide
ISE 6.3i

XOR2-9

XOR2-9
2- to 9-Input XOR Gates with Non-Inverted Inputs
Architectures Supported
XOR2, XOR3
Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive
XOR4

Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive
XOR5

Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Primitive

CoolRunner XPLA3

Primitive

CoolRunner-II

Primitive

XOR6, XOR7, XOR9

Spartan-II, Spartan-IIE

Macro

Spartan-3

Macro

Virtex, Virtex-E

Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

Libraries Guide
ISE 6.3i

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro

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1169

XOR2-9

XOR8
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

Macro

CoolRunner XPLA3

Macro

CoolRunner-II

Macro
XOR5

XOR2
I1

I0

I3

I6

I2
XOR3
I2
I1

I0

I4
I3

I2
XOR6

I1
I0

I4
I3

I3

I1

I5

I0

I5
XOR4

I2

I1

I0

XOR8
I7

I4

I2
O

IA

I1

I7

I0

I6

XOR9

I5
XOR7

I4

I6

I3

I5

I2
I1

I4
I3

I0

I2
I1
I0
x9441

XOR Gate Representations

XOR functions of up to nine inputs are available. All inputs are non-inverting.
Because each input uses a CLB resource, replace functions with unused inputs with
functions having the necessary number of inputs.
I0
I1
I2
XOR3
I3
I4

O
XOR2

XOR2
X7882

XOR5 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

1170

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ISE 6.3i

XOR2-9

I0
I1
I2
XOR3

I3
I4
I5

XOR2

XOR3
X7883

XOR6 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

I0
I1
I2
I3
O

XOR4
I4
XOR2

I5
I6
XOR3

X7884

XOR7 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

I0
I1
I2
I3
O

XOR4

I4
I5
I6

XOR2

I7
XOR4
X7885

XOR8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

FMAP
I4
I3
S1
S2
I7
I6

I1
RLOC=R0C0.S0

S1

I5

I2

I4

FMAP

XOR4

I7
O
XOR2

I6
I5
I4

I3

I4
I3
I2

S1

I1
RLOC=R0C0.S1

I2

S0

I1

FMAP

I0
I3

XOR4

I2
I1
I0
X8695

I4
I3
I2

S2

I1
RLOC=R0C0.S1

XOR8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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ISE 6.3i

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1171

XOR2-9

FMAP
I4
I3

I7
S1

I6

S1

I5
I4

S0

XOR4

I2

I1
RLOC=X0Y1

FMAP

I3

XOR2

I2

S0

I1
I0

I7
I6
I5

XOR4

I4

I4
I3
I2

S1

I1
RLOC=X0Y0

FMAP
I3
I2
I1
I0

I4
I3
I2

S0

I1
RLOC=X0Y0

X9378

XOR8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

I0
I1
I2
XOR3
I3
I4

XOR2

I5

O
XOR3
XOR2

I6
I7
I8
XOR3

X7886

XOR9 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements can be inferred or instantiated.

VHDL Instantiation Template for XOR5

Following is the VHDL code for XOR5. To instantiate XOR2, remove I2, I3, and I4. To
instantiate XOR3, remove I3 and I4, For XOR4, remove I4. XOR2B1, and XOR2B2 have
the same code as XOR2. XOR3B1, 3B2, and 3B3 have the same code as XOR3 and so
forth.
-- Component Declaration for XOR5 should be placed
-- after architecture statement but before begin keyword
component XOR5
port (O : out
I0 : in
I1 : in
I2 : in
I3 : in
I4 : in
end component;

STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC;
STD_ULOGIC);

-- Component Attribute specification for XOR5

-- should be placed after architecture declaration but

1172

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ISE 6.3i

XOR2-9

-- before the begin keyword

-- Attributes should be placed here
-- Component Instantiation for XOR5 should be placed
-- in architecture after the begin keyword
XOR5_INSTANCE_NAME : XOR5
port map (O => user_O,
I0 => user_I0,
I1 => user_I1,
I2 => user_I2,
I3 => user_I3,
I4 => user_I4);

Verilog Instantiation Template for XOR5

XOR5 XOR5_instance_name (.O (user_O),
.I0 (user_I0),
.I1 (user_I1),
.I2 (user_I2),
.I3 (user_I3),
.I4 (user_I4));

1173

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Libraries Guide
ISE 6.3i

1174

XOR2-9

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Libraries Guide
ISE 6.3i

XORCY

XORCY
XOR for Carry Logic with General Output
Architectures Supported
XORCY
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LI

No

CoolRunner XPLA3

No

CoolRunner-II

No

CI

X8410

XORCY is a special XOR with general O output used for generating faster and smaller
arithmetic functions.
Its O output is a general interconnect. See also XORCY_D and XORCY_L.

Commonly Used Constraints

BEL

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ISE 6.3i

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1175

1176

XORCY

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Libraries Guide
ISE 6.3i

XORCY_D

XORCY_D
XOR for Carry Logic with Dual Output
Architectures Supported
XORCY_D
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LO
LI

CI

X8409

No

CoolRunner XPLA3

No

CoolRunner-II

No

XORCY_D is a special XOR used for generating faster and smaller arithmetic
functions.
XORCY_D has two functionally identical outputs, O and LO. The O output is a
general interconnect. The LO output is used to connect to another output within the
same CLB slice.
See also XORCY and XORCY_L.

Commonly Used Constraints

BEL

Libraries Guide
ISE 6.3i

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1177

1178

XORCY_D

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Libraries Guide
ISE 6.3i

XORCY_L

XORCY_L
XOR for Carry Logic with Local Output
Architectures Supported
XORCY_L
Spartan-II, Spartan-IIE

Primitive

Spartan-3

Primitive

Virtex, Virtex-E

Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL

LO
LI
CI

No

CoolRunner XPLA3

No

CoolRunner-II

No

XORCY_L is a special XOR with local LO output used for generating faster and
smaller arithmetic functions. The LO output is used to connect to another output
within the same CLB slice.
See also XORCY and XORCY_D.

X8404

Commonly Used Constraints

BEL

Libraries Guide
ISE 6.3i

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1179

1180

XORCY_L

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Libraries Guide
ISE 6.3i