Seminar Report’06

Digital Visual Interface

Introduction

The Digital Visual Interface (hereinafter DVI) specification provides a high-speed digital
connection for visual data types that is display technology independent. The interface is primarily
focused at providing a connection between a computer and its display device. The DVI
specification meets the needs of all segments of the PC industry (workstation, desktop, laptop, etc)
and will enable these different segments to unite around one monitor interface specification.

The DVI interface enables:

1. Content to remain in the lossless digital domain from creation to consumption
2. Display technology independence
3. Plug and play through hot plug detection, EDID and DDC2B
4. Digital and Analog support in a single connector

Some new DVD players, TV sets (including HDTV sets) and video projectors have DVI/HDCP
(High band width digital content protector) connectors; these are physically the same as DVI
connectors but transmit an encrypted signal using the HDCP protocol for copyright protection.
Computers with DVI video connectors can use many DVI-equipped HDTV sets as display.

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Digital Visual Interface

1. 1 Scope and Motivation

The purpose of this interface specification is to provide an industry specification for a digital
interface between a personal computing device and a display device. This specification provides
for a simple low-cost implementation on both the host and monitor while allowing for monitor
manufacturers and system providers to add feature rich values as appropriate for their specific
application.

The DDWG has worked to address the various business models and requirements of the
industry by delivering a transition methodology that addresses the needs of those various
requirements. This is accomplished by specifying two connectors with identical mechanical
characteristics: one that is digital only and one that is digital and analog. The combined digital
and analog connector is designed to meet the needs of systems with special form factor or
performance requirements. Having support for the analog and digital interfaces for the
computer to monitor interconnect will allow the end user to simply plug the display into the
DVI connector regardless of the display technology. The digital only DVI connector is designed
to coexist with the standard VGA connector. With the combined connector or the digital only
connector the opportunity exists for the removal of the legacy VGA connector. The removal of
the legacy VGA connector is anticipated to be driven strictly by business demands.

A digital interface for the computer to monitor interconnect has several benefits over the
standard VGA connector. A digital interface ensures all content transferred over this interface
remains in the lossless digital domain from creation to consumption. The digital interface is
developed with no assumption made as to the attached display technology. This specification
completely describes the interface so that one could implement a complete transmission and
interconnect solution or any portion of the interface. The T.M.D.S. protocol and associated
electrical signaling as developed by Silicon Image is described in detail. The mechanical
specification of the connector and the signal placement within the connector are described.

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Digital Visual Interface
A device that is compliant with this specification is should be interoperable with other
compliant devices through the plug and play configuration and implementation provided for in
this specification. The plug and play interface provides for hot plug detection and monitor
feature detection. Additionally, this specification describes the number of T.M.D.S. links
available to the display device and the method for configuring the T.M.D.S. links. Additionally
the DVI specification provides for alternate media implementations.

Power management and plug and play configuration management are both fully described. To
ensure baseline functionality, low-pixel format requirements are included. As appropriate, this
interface makes use of existing Video Electronics Standards Association (VESA) specifications
to allow for simple low-cost implementations. Specifically VESA Extended Display
Identification Data (EDID) and Display Data Channel (DDC) specifications are referenced for
monitor identification and the VESA Monitor Timing Specification (DMT) is referenced for the
monitor timings.

Architectural Requirements

2.1. T.M.D.S. Overview

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Digital Visual Interface
The Digital Visual Interface uses transition minimized differential signaling for the base
electrical interconnection. The T.M.D.S. link is used to send graphics data to the monitor. The
transition minimization is achieved by implementing an advanced encoding algorithm that
converts 8 bits of data into a 10-bit transition minimized, DC balanced character. This interface
specification allows for two T.M.D.S. links enabling large pixel format digital display devices, see
Figure 2-1. One or two T.M.D.S. links are available depending on the pixel format and timings
desired. The two T.M.D.S. links share the same clock allowing the bandwidth to be evenly
divided between the two links. As the capabilities of the monitor are determined the system will
choose to enable one or both T.M.D.S. links.

The transmitter incorporates an advanced coding algorithm to enable T.M.D.S. signaling for
reduced EMI across copper cables and DC-balancing for data transmission over fiber optic cables.
In addition, the advanced coding algorithm enables robust clock recovery at the receiver to achieve
high-skew tolerance for driving longer cable lengths as well as shorter low cost cables.

2.2. Plug and Play Specification

2.2.1 Overview

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Digital Visual Interface
On initial system boot a VGA compliant device might be assumed by the graphics controller. To
accommodate system boot modes and debug modes, the DVI compliant monitor must
support the low pixel format mode defined in section 2.2.4.2. Both BIOS POST and the
operating system are likely to query the monitor using the DDC2B protocol to determine
what pixel formats and interface is supported. DVI makes use of the EDID data structure for
the identification of the monitor type and capabilities. The combination of pixel formats
supported by the monitor, pixel formats supported by the graphics subsystem, and user input
will determine what pixel format to display.

If the DVI compliant monitor was not present during the boot process, the Hot Plug Detection
mechanism exists to allow the system to determine when a DVI compliant monitor has
beenplugged in. After the Hot Plug-In event the system will query the monitor using the DDC2B
interface and enable the T.M.D.S. link if required.

After the pixel format and timings have been determined there are two more parameters that effect
the user perception of the picture quality, gamma and scaling. The gamma characteristic of a
monitor is display technology dependent. In the past a CRT has been assumed as the primary
display technology to be used. To ensure display independence, no assumption is made of display
technology. The DVI requires a gamma characteristic of the data at the interface allowing monitors
of varying display technologies to compensate for their specific display transfer characteristic.

If the monitor is identified in the EDID data structure as a fixed pixel format device that supports
more than a single pixel format, then a monitor scalar is assumed to exist. A monitor scalar allows
monitor vendors the ability to ensure the quality of the displayed image.

2.2.2. T.M.D.S. Link Usage Model

The two-link monitor plugged into the one link system still boots and displays images. The images
are pixel format limited by the graphics driver to the maximum system single link frequency of up

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Digital Visual Interface
to 165MHz T.M.D.S clock operation. A configuration utility may optionally report to the user the
nature of the system limitations. A message only stating there is a system limitation is OK, ideally
a message should be displayed by the operating system or a display utility to inform the user
specifically the issue is the graphics sub-system does not support the larger pixel format.

T.M.D.S. Link System Requirements

A DVI compliant system must implement a minimum of a single T.M.D.S. link, link #0. The
minimum low pixel format mode must be supported. The maximum pixel format supported is
implementation specific. If the system supports pixel formats and timings that require greater than
a 165MHz T.M.D.S. clock then implementation of the second T.M.D.S. link is required. There is
no specified maximum for the dual link implementations. A system supporting dual T.M.D.S. links
must be able to dynamically switch between supported pixel formats including switching between
pixel formats that require single and dual link configurations. When a dual T.M.D.S. link capable
system is driving only a single link, the secondary link must be inactive.

T.M.D.S. Link Monitor Requirements

A DVI compliant monitor must implement a minimum of a single T.M.D.S. link, link #0. The
minimum low pixel format mode must be supported. The maximum pixel format supported is
implementation specific. If the monitor supports pixel formats and timings that require greater than
a 165MHz T.M.D.S. clock then implementation of the second T.M.D.S. link is required. A dual
link T.M.D.S. monitor must be able to detect the activity of each link and dynamically switch
between supported pixel formats including switching between pixel formats that
require single and dual link configurations.

2.2.3. High Color Depth Support

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Digital Visual Interface
Color depths requiring greater than 24-bit per pixel are allowed to be supported via the second
link. Future versions of this specification reserve the right to require different implementations of
high color depth support that are not backwards compatible with this version of the specification.
The colors per pel are logically concatenated with the most significant bits provided over the
primary T.M.D.S. link (link #0) and the least significant bits provided over the secondary
T.M.D.S. link (link #1). If implemented, the data format on the secondary T.M.D.S. links must the
same 24-bit MSB aligned RGB TFT data format as defined for the primary link. The system must
identify the capability exists in the monitor before the high color depth is enabled. If the monitor
does not support the high color depth, the system must be able to operate in the required 24-bit
format.

2.2.4. Low Pixel Format Support

Low-pixel format modes are supported to allow a default operation mode. This default operation
mode enables the user to view a legible display of BIOS messages and progress as well as
Operating System initial loading messages. A legible picture does not require the image to be
scaled to full screen or centered. Once the Operating System loads the graphics controller driver
the driver may switch into a different pixel format and timing mode. The video BIOS is required to
respond to all legacy VESA BIOS calls and INT 10 BIOS (IBM PS/2 Legacy BIOS) calls,
however it is acceptable for the hardware to emulate the legacy mode.

System Low Pixel Format Support Requirement

Industry Standard Timings for 640x480 pixel format at 60 Hz Refresh with a pixel clock of
25.175MHz and Horizontal Frequency of 31.5 kHz. To insure compatibility the system must re-
map int10 mode 3 BIOS calls to required low pixel format support mode.

Monitor Low Pixel Format Support Requirement

Industry Standard Timings for 640x480 pixel format at 60 Hz Refresh with a pixel clock of 25.175
MHz and Horizontal Frequency of 31.5 kHz.

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Digital Visual Interface

2.2.5. EDID

The EDID 1.3 data structure specification that is under development purportedly addresses several
of the display technology independent issues germane to the DVI specification. It is anticipated
that the DVI specification will require support for the EDID 1.3 data structure support within 12
months of VESA adoption.

EDID System Requirements

A DVI compliant system must support the EDID data structure. EDID 1.2 and 2.0 are
recommended for interim support for systems. No assumption above the low pixel format
requirement (640x480) pixel format can be made about monitor support. The system is required to
read the EDID data structure to determine the capabilities supported by the monitor. Current digital
monitors based on the T.M.D.S. electrical specification use both the EDID 1.2 data structure and
the EDID 2.0 data structure. Any system desiring to support both groups of existing monitors must
support both EDID data structures.
EDID Monitor Requirements
A DVI compliant monitor must support the EDID data structure. EDID 1.2 and 2.0 are
recommended for interim support for systems. The DVI low-pixel format requirement does not
have to be listed in the EDID data structure but the monitor must present a legible image. If the
monitor is a fixed pixel format monitor then the EDID "Preferred Timing Mode" bit monitors
should make every effort to provide a quality scalar thus allowing the end-user experience to
match that of the typical analog multi-sync monitors.

2.2.6. Hot Plugging

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Hot Plug Detection(HPD) is a system level function requiring industry specifications at both
hardware and software levels. It is beyond the scope of this specification to define a complete
system solution. This section is therefore limited to the specification of the hot plug signal that
provides the hardware underpinning for a complete system solution. The operation of the hot plug
pin, as described below, is required by this specification. Any specific system response to the hot
plug pin is optional. Future software specifications are anticipated, which should provide the
complete system solution. In the interim, the graphics driver is free to generate its own application
based on the hot plug signal.
Hot Plug Events:
• Monitor Attachment: When a "Monitor Attach" Hot Plug event is detected the graphics
ubsystem must generate a system level event (OS dependent) to allow the operating system
to read the monitor’s EDID data. If the graphics subsystem and monitor support compatible
pixel formats the operating system should enable the monitor and the T.M.D.S. link if
required.
• Monitor Removal: When a "Monitor Removal" Hot Plug event is detected the graphics
subsystem must generate a system level event (OS dependent) to notify the operating
system of the event. Additionally, if the DVI complaint monitor is a digital monitor, when
"Monitor Removal" is detected the graphics subsystem must disable the T.M.D.S.
transmitter within 1 second.

System Hot Plugging Requirements

Any specific system response to Hot Plug Detection is future OS dependent. It is anticipated this
functionality will be required in the future, as Operating System API’s become available to take
advantage of this feature. When the host detects a transition above +2.0 volts or below +0.8 volts
the graphics subsystem must generate a system level event (OS dependent) to inform the Operating
System of the event. Additionally, if the DVI complaint monitor is a digital monitor, when
"MonitorRemoval" is detected the graphics subsystem must disable the T.M.D.S. transmitter
within 1 second.

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Digital Visual Interface
Note: The VESA Plug and Display specification allows for up to +20 volts to be applied to its
Charge/Hot Plug Detect Pin, although no such implementations are known to exist. To ensure the
safety of the transmitter and to enable compatibility with a P&D monitor, it is required that any
adapter connecting a P&D monitor to a DVI compliant system leaves the HPD pin unconnected, or
otherwise insures that +5 volts is not exceeded. +20 volt tolerance is not required of a DVI
compliant host.

Monitor Hot Plugging Requirements

The monitor must provide a voltage of greater than +2.4 volts on the Hot Plug Detect (HPD) pin of
the connector only when the EDID data structure is available to be read by the host. When the
EDID data structure can not be read then voltage on the HPD pin must be below +0.4 volts.
Implementation Note: As an example for hot plug support, a simple monitor implementation of
HPD support could be a pull up resistor to the EDID power supply.

2.2.7. HSync, VSync and Data Enable Required

It is expected that digital CRT monitors will become available to connect to the DVI Interface. To
ensure display independence, the digital host is required to separately encode HSync and VSync in
the T.M.D.S. channel. The digital host is required to encode Data Enable (hereinafter DE) in the
T.M.D.S. channel.DE must be an active high signal.

2.2.8. Data Formats

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System Data Format Support

The system must support the 24-bit MSB aligned RGB TFT data format as a minimum. The 24-bit
MSB aligned RGB TFT data format is defined in the VESA EDID specification version 3.0. Note
that lower color depths are also defined there. If the monitor implements the EDID 1.2 data
structure the system must assume the monitor supports the 24-bit MSB aligned RGB TFT data
format.

Monitor Data Format Support

If the monitor chooses to implement the EDID 1.2 data structure then the monitor must accept the
24-bit MSB aligned RGB TFT data format as defined in the VESA EDID specification version 3.0.
If the monitor implements the EDID 2.0, 1.3 or newer data structure the monitor may specify any
data format that is definable within the EDID data structure used. In all cases the monitor must
support the 24-bit MSB aligned RGB TFT data format as a minimum.

2.2.9. Interoperability with Other T.M.D.S. Based Specifications

The DVI specification is based on a T.M.D.S. electrical layer. Every effort has been made to
ensure interoperability with existing products that support similar T.M.D.S. signaling. DC coupled
implementations of VESA DFP or VESA P&D specification should connect to the DVI
specification through a cable adapter. While every effort is being made to ensure the
interoperability of the T.M.D.S. link, the accessory functions available in other specifications will
not function. For example the IEEE- 1394 interface potentially in the P&D connector will not have
a connection point in the DVI interface and as such will not function. Likewise, USB does not
have a connection in the DVI connector. Any interface with USB on the monitor side will have to
use an alternative means of connecting USB to the system. The DVI compliant system may have
two T.M.D.S. links. Any non-DVI compliant monitor that was based on T.M.D.S. electrical would
not be able to take advantage of the bandwidth available from the second link. To ensure the safety

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Digital Visual Interface
of the transmitter and to enable compatibility with a P&D monitor, it is required that any adapter
connecting a P&D monitor to a DVI compliant system complies with requirements in section
2.2.4.

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Digital Visual Interface

2.3. Bandwidth

2.3.1. Minimum Frequency Supported

The minimum frequency supported is specified to allow the link to differentiate between an active
low-pixel format link and a power managed state (inactive link). The lowest pixel format required
by the DVI specification is 640x480@60 Hz (clock timing of 25.175 MHz). The DVI link can be
considered inactive if the T. M. D.S. clock transitions at less than 22.5 MHz for more than one
second.

2.3.2. Alternate Media

The T.M.D.S. transmission protocol is DC balanced and capable of being transmitted over fiber
optic cable. Specific details of a fiber optic implementation are not covered in this specification,
but left to the designer. Fiber optic implementations can be DVI compliant as long as the plug and
play ability of the interconnect is still supported. For example, the system must be able to read
EDID data and detect a hot plug event. For alternative media to be DVI compliant it is envisioned
that the alternate media will serve as a connector to connector adapter.

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Digital Visual Interface

2.4. Digital Monitor Power Management

The following digital monitor power management (hereinafter DMPM) definition is for power
management as applied over the T.M.D.S. link for any monitor type. Power management applied
over the analog link is defined in section 2.5.4. Four monitor power states are defined to provide
programmatic control of monitor power and ensure the availability of the monitor identification
data. For completeness, the monitor power states include states entered via the power switch.

• Monitor On Power State. T.M.D.S. link is active. Transmitter powered and active.
Receiver powered and active. This power state is equivalent to the DPMS "On" power
state. EDID data is guaranteed to be available. DDC +5 volt signal is present, monitor
drawing less than 10 mA current from DDC + 5 volt pin. The monitor can leave this state if
1. The link becomes inactive as defined in 2.4.1, 2. The DDC +5 volt signal is removed, or
3. The monitor power switch is toggled.

• Intermediate Power State. T.M.D.S. link is inactive. Transmitter should be powered

down. Receiver remains powered with receiver outputs optionally disabled. The receiver
must be able to detect the activation of the link and return the monitor to the "On" Power
State. A timer controls the duration of the Intermediate Power State. This power state is
similar to the DPMS "Suspend" power state allowing for the controller circuitry in the
monitor to be powered as necessary to enable a quick recovery while dissipating less power
than the "On" Power State. EDID data is guaranteed to be available. DDC +5 volt signal is
present, monitor drawing less than 10 mA current from DDC + 5 volt pin. The monitor can
leave this state if 1. The link becomes active, 2. The DDC +5 volt signal is removed 3. The
monitor power switch is toggled or 4. Monitor timer expires.

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Digital Visual Interface
• Active-Off Power State. T.M.D.S. link is inactive. Transmitter should be powered down.
Receiver remains powered with receiver outputs optionally disabled. The receiver must be
able to detect the activation of the link and return the monitor to the "On" Power State. This
power state is equivalent to the DPMS "Off" state ("Active Off" in EDID 2.0 data
structure). EDID data is guaranteed to be available. DDC +5 volt signal is present, monitor
drawing less than 50 mA current from DDC + 5 volt pin. The monitor can leave this state if
1. The link becomes active, 2. The DDC +5 volt signal is removed, or 3. The monitor
power switch is toggled.
• Non-Link Recoverable Off Power State. T.M.D.S. link is inactive. Transmitter should be
powered off. Receiver should be powered off. The Non-Link Recoverable Off Power State
is entered when the DDC +5 volt signal has been removed from the monitor.

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Digital Visual Interface

2.5 Decoder Specification

Clock Recovery
A T.M.D.S. receiver must be capable of phase lock with a transmit clock from 25 MHz up to the
stated maximum frequency of the receiver. Phase lock to the input clock must occur within 100 ms
from the time that the input clock meets the electrical specifications of chapter
four.

Data Synchronization
The receiver is required to establish synchronization with the data streams during any blanking
period greater than 128 characters in length. Prior to synchronization detection, and during periods
of lost synchronization, the receiver shall not update the signals of the recovered stream.

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Digital Visual Interface

2.6. Signal List

There are mainly three types of connectors.

The DVI connector may also incorporate pins to pass through the legacy analog signals using the
VGA standard. This feature was included in order to make DVI universal, as it allows either type
of monitor (analog or digital) to be operated from the same connector. The DVI connector on a
device is therefore given one of three names, depending on which signals it implements:

• DVI-D (digital only)

• DVI-A (analog only)
• DVI-I (digital & analog)

Types of connectors

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Digital Visual Interface

Pin numbers (looking at socket): (DVI-I, dual link)

Pin number description (DVI-I, dual link)

Pin assignments
Pin Name Function

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Digital Visual Interface

1 TMDS Data 2- Digital red - (Link 1)

2 TMDS Data 2+ Digital red + (Link 1)
3 TMDS Data 2/4 shield
4 TMDS Data 4− Digital green − (Link 2)
5 TMDS Data 4+ Digital green + (Link 2)
6 DDC clock
7 DDC data
8 Analog Vertical Sync
9 TMDS Data 1− Digital green − (Link 1)
10 TMDS Data 1+ Digital green + (Link 1)
11 TMDS Data 1/3 shield
12 TMDS Data 3− Digital blue − (Link 2)
13 TMDS Data 3+ Digital blue + (Link 2)
14 +5V Power for monitor when in standby
15 Ground Return for pin 14 and analog sync
16 Hot Plug Detect
17 TMDS data 0− Digital blue − (Link 1) and digital sync
18 TMDS data 0+ Digital blue + (Link 1) and digital sync
19 TMDS data 0/5 shield
20 TMDS data 5− Digital red − (Link 2)
21 TMDS data 5+ Digital red + (Link 2)
22 TMDS clock shield
23 TMDS clock+ Digital clock + (Links 1 and 2)
24 TMDS clock− Digital clock − (Links 1 and 2)
C1 Analog Red
C2 Analog Green
C3 Analog Blue
C4 Analog Horizontal Sync
C5 Analog Ground Return for R, G and B signals

T.M.D.S. Electrical Specification

Some timing parameter values in this specification are based on the clock rate of the link while
others are based on absolute values. For scalable timing parameters based on the clock rate, the

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Digital Visual Interface
time period of the clock is denoted as pixel time, or Tpixel. One tenth of the ‘pixel time’ is called
the bit time, or Tbit. The bit time is also referred to as one Unit Interval, or UI, in the jitter and eye
diagram specifications. Schematic diagrams contained in this chapter are for illustration only and
do not represent the only feasible implementation.

3.1. Overview
The conceptual schematic of one T.M.D.S. differential pair is shown in Figure 4-1. T.M.D.S.
technology uses current drive to develop the low voltage differential signal at the receiver side of
the DC-coupled transmission line. The link reference voltage AVcc sets the high voltage level of
the differential signal, while the low voltage level is determined by the current source of the
transmitter and the termination resistance at the receiver. The termination resistance (RT) and the
characteristic impedance of the cable (Z0) must be matched.

A single-ended differential signal, representing either the positive or negative terminal of a

differential pair, is illustrated in Figure 4-2. The nominal high-level voltage of the signal is AVcc
and the nominal low-level voltage of the signal is (AVcc - Vswing). Since the swing is differential
on the pair, the net signal on the pair has a swing twice that of the single-ended signal, or

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Digital Visual Interface
2*Vswing. The differential signal, as shown in Figure 4-3, swings between positive Vswing and
negative Vswing.

The signal test points for a T.M.D.S. link are shown in Figure 4-4. The first test point (TP1), at the
pins of the T.M.D.S. transmitter, is not utilized for testing under this specification. Rather, the
transmitter is tested at TP2, which includes the network from the transmitter to the connector as
well as the connector to the cable assembly. The input to the receiver is similarly described by
signal testing at TP3 rather than at TP4, the pins of the receiver. By imposing the signal quality
requirements of these networks on transmitter and receiver components, link testing is reduced to
measurements at only two test points. Cable assembly requirements are given by the allowable
signal degradation between test points TP2 and TP3.

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Digital Visual Interface

3.2. Transmitter Electrical Specifications

The DVI interface requires a DC-coupled T.M.D.S. link. Transmitter electrical testing shall be
performed using the test load shown in Figure 4-5.

The transmitter shall meet the DC specifications in Table 4-3 for all operating conditions specified
in Table 4-2 when driving clock and data signals. The Vswing parameter identifies the minimum
and maximum single-ended peak-to-peak signal amplitude that may be delivered by the transmitter
into the test load).

Rise and fall times are defined as the signal transition time between 20% and 80% of the nominal
swing voltage (Vswing) of the device under test. The transmitter intra-pair skew is the maximum
allowable time difference (on both low-to-high and highto-low transitions) as measured at TP2,
between the true and complement signals. This time difference is measured at the midpoint on the
single-ended signal swing of the true and complement signals. The transmitter inter-pair skew is
the maximum allowable time difference (on both low-to-high and high-to-low transitions) as
measured at TP2, between any two single-ended data signals that do not constitute a differential
pair.

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Digital Visual Interface
The time axis is normalized to the bit time at the testing frequency, while the amplitude axis is
normalized to the average differential swing voltage. The average differential swing voltage is
defined as the difference between the average differential amplitude when driving a logic one and
the average differential amplitude when driving a logic zero. The average logic one appears at
positive 0.5 on the vertical axis, while the average logic zero appears at negative 0.5. The
normalized amplitude limits in Figure 4-6 allow 15% (of the average differential swing voltage)
maximum overshoot and 25% maximum undershoot, relative to the amplitudes determined to be
logic one and zero.

Combining the single-ended swing voltage (Vswing) specified in Table 4-3 with the overshoot and
undershoot requirements of Figure 4-6, it is possible to calculate the minimum and maximum high-
levelvoltage (Vhigh) and low-level voltage (Vlow) that is allowable on the interface.

Vhigh (max) = Vswing (max) + 15% * (2*Vswing (max) ) = 600 + 180 = 780 mV
Vhigh (min) = Vswing (min) - 25% * (2*Vswing (min) ) = 400 - 200 = 200 mV
Vlow (max) = -Vswing (max) - 15% * (2*Vswing (max) ) = -600 - 180 = -780 mV
Vlow (min) = -Vswing (min) + 25% * (2*Vswing (min) ) = -400 + 200 = -200 mV
Minimum opening at transmitter = Vhigh (min) - Vlow (min) = 400 mV

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Digital Visual Interface

3.3. Receiver Electrical Specifications

The receiver shall meet the signal requirements listed in Table 4-5, Table 4-6, and Table 4-7 for all
operating conditions specified in Table 4-2.

a. Within the Exception_window no single impedance excursion shall exceed the

Through_connection impedance tolerance for a period of twice the TDR rise time specification.
The maximum excursion within the Exception_window at TP3 shall not exceed +75% and –25%
of the nominal cable impedance.

b. Through_connection impedance describes the impedance tolerance through a mated connector.

This tolerance is greater than the termination or cable impedance due to limits in the technology of
the connectors.

c . The input impedance at TP3, for the termination, shall be recorded 4.0ns following the
reference location determined by an open connector between TP3 and TP4. For all channels under
all operating conditions specified in Table 4-2, the receiver shall reproduce a test data stream, with
pixel error rate 10-9, when presented with input amplitude illustrated by the eye diagram of Figure
4-7. Figure 4-7 Absolute Eye Diagram Mask at TP3

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Digital Visual Interface

3.4. Cable Assembly Specifications

When driven by an input waveform meeting the eye diagram mask requirements of Figure 4-6 a
DVI cableassembly must a produce an output waveform that meets the receiver eye diagram mask
of Figure 4-7. In addition, the cable assembly must meet the signal skew requirements of Table 4-
8.

Item Value
Maximum Cable Assembly Intra-Pair Skew 0.25 Tbit
Maximum Cable Assembly Inter-Pair Skew 0.4 Tpixel
Table 4-8 Cable Assembly Skew Budget (informative)

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Digital Visual Interface

3.5. Jitter Specifications

The differential clock of the T.M.D.S. link shall meet the total jitter specifications defined in Table
4-9. The clock to data jitter is not specified in the table but the system shall produce the eye
diagram shown in Figure 4-7 when measured at test point TP3. Normative values are highlighted
in bold. All other values are informative. Compliance test points are defined in Figure 4-4. The
Unit Interval (UI) is equal to one bit time (Tbit).

The total jitter from TP2 to TP3 is calculated based on the assumption that the distribution of the
jitter is Gaussian.

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Digital Visual Interface

3.6. Electrical Measurement Procedures

Electrical measurements shall be performed as described in this clause.

Test Patterns
Two different test patterns are used to evaluate T.M.D.S. interface components. For pixel error rate
measurements, a (223-1) bit pseudo-random data pattern is transmitted. Other measurements
specify a “half clock” sequence. The half clock pattern consists of alternating 0x3FF (all ones) and
0x000 (all zeros) T.M.D.S. characters. This pattern is useful for determining average swing
voltage, logic one, and logic zero voltage levels.

Normalized Amplitudes
Normalized amplitude measurements are necessary for both single-ended and differential testing of
theT.M.D.S. interface. These measurements are made with transmission of the half clock test
pattern, and thetime base of the measurement equipment set to a scale that is coarse enough to
observe at least two full pixel times. The average high-level and low-level amplitudes are
determined at the point where signal ringing has subsided. These averages establish the swing
voltage and are used to normalize the eye
diagram.

Clock Recovery
Eye diagram measurements require a clock which has been recovered from the transmit stream.
The clock recovery unit is used to remove low frequency jitter from the measurement as shown in
Figure 4-8. The clock recovery unit has a low pass filter with 20dB/decade rolloff with –3dB point
of 4 MHz. It is used to approximate the phase locked loop in the receiver. The receiver is able to
track a large amount of low frequency jitter (such as drift or wander) below this bandwidth. This
low frequency jitter would create a large measurement penalty, but does not affect the operation of
the link. The eye diagrams produced with by this method will contain only high frequency jitter
components that are not tracked by the clock recovery circuit of the receiver. The clock recovery
unit may be a T.M.D.S. receiver meeting the filter requirements above.

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Digital Visual Interface

COMPARISON BTN ANALOG AND DIGITAL CONTROLLERS

TFT LCD monitors with an analog VGA interface dominate the market. Because it is easy to
install PC basis and not purchase a new graphics board. Although digital TFT LCD monitors don't
need to adjust clock and phase and the no signal losses advantage. The Digital Interface standard
has totally different connectors and it is not easy to buy a suitable graphic board. So the analog
TFT LCD monitors still dominate the market. The following table gived you an overview of the
most important points:

Digital Control Analog Control

Advantages Advantages

o No signal losses due to DA and AD o Compatible with standard

conversion VGA boards on a broad installed
o Geometry, clock and phase settings PC basis
unnecessary - therefore simple to use o Not necessary to purchase
o Lower costs as less electronic seperate board
circuitry required

Disadvantages Disadvantages

o Currently three standards (P & D o Clock and phase of the

(M1DA), DFP, and DVI) TFTs must be synchronized with
o Low availability of models with the analog signal to avoid pixel
digital interfaces jitter, which is a relatively
complex issue
o Requires graphic board with digital o Cables sensitive to
output external influences
o High cost of signal
conversion inside the display

o Upgrade to digital
interface not possible

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OTHER DIGITAL INTERFACING STANDARDS

Currently there are three digital interface standards (P & D (M1DA), DFP, and DVI) in the
market. The following table is the comparison and summary of the three interface standards.

Standard P & D (M1DA) DFP DVI

DFP Group (Digital
VESA (Video Electronics DDWG (Digital Display
Owner Flat Panel Group)
Standards Organization) Working Group)
and later VESA

Revision / Date 1.0 / Jun 06, 1997 1.0 / Feb 14, 1999 1.0 / Apr 02, 1999
www.dfp-
Web page www.vesa.org www.ddwg.org
group.org
Workgroup leader VESA Compaq Intel
P & D (M1DA) P & D (M1DA) and DFP
Compatibility Own standard compatible compatible (adapter
(adapter possible) possible)
TMDS - Transmission
Transfer protocol Minimizing Differential TMDS (PanelLink) TMDS (PanelLink)
Signaling (PanelLink)
Max. Pixel rate (Dot
165 MHz x 1 165 MHz x 1 165 MHz x 1
Clock)
Max. number of 3 channels (single
3 channels (single link) 6 channels (dual link)
channels link)
Color depths 12 or 24 bit 12 or 24 bit 12 or 24 bit
Max. Resolution SXGA (1280 x 1024) SXGA (1280 x 1024) HDTV (1920 x 1080)
Optional transfer of
other signals possible Analog VESA video, No, only digital
Analog VESA video
using the same USB, IEEE 1394-1995 video
connector
Digital Connector P & D (M1DA)-D (30 pin) MDR20 (20 pin) DVI-D (24 pin)

Analog/Digital P & D (M1DA)-a/d (30+4

No DVI-I (24 + 4 pin)
combination connector pin)
Connector width 40.6 mm 33.4 mm 37.0 mm

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Digital Visual Interface

CONCLUSION

The DVI interface enables content to remain in the lossless digital domain from creation to
consumption, Display technology independence, Plug and play through hot plug detection, EDID
and DDC2B Digital and Analog support in a single connector. There are some inherent advantages
such as, no signal losses due to DA and AD conversion Geometry, clock and phase settings
unnecessary - therefore simple to use Lower costs as less electronic circuitry required.A potential
replacement for DVI is the Unified Display Interface (UDI). It is intended to be a lower-cost
implementation while providing compatibility with existing HDMI and DVI displays.

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Digital Visual Interface

REFERENCE

1. www.ddwg.org
2. www.answers.com
3. www.pacificcable.com/DVI_Tutorial.htm
4 www.wikipedia.org/wiki/DVI

Dept. of Electronics and Communication 31 VJEC