Instruction Set

INSTRUCTION SET, PROCEDURES, MACROS
SEGMENT OVERRIDE PREFIX

The segment override prefix is an additional byte which can be added to any instruction
in any memory addressing mode. It allows the programmer to deviate from the default
segment and select any other segment. Only JUMP and CALL instructions cannot be
prefixed by this. For e.g. MOV AX, [DI] instruction accesses data within the data
segment by default. If the data has to be accessed in extra segment rather than data
segment, then it can be written as MOV AX, ES: [DI].
Assembly language
MOV AX, DS: [BP]
MOV AX, ES: [BP]
MOV AX, SS: [DI]
MOV AX, CS: LIST
MOV AX, ES: [SI]
LODS ES:DATA1
Segment accessed
Data
Extra
Stack
Code
Extra
Extra
Default segment
Stack
Stack
Data
Data
Data
Data
The operands in a program can be modified by using arithmetic or logic operands.

Operator
+
*
/
MOD
AND
OR
NOT
Example
MOV AL, 6+3
MOV AL, 8-2
MOV AL, 4*3
MOV AX, 12/5
MOV AX, 12 MOD 7
MOV AX, 12 AND 4
MOV AX, 12 OR 1
MOV AL, NOT 1
Comment
Copies 9 into AL
Copies 6 into AL
Copies 12 into AL
Copies 2 into AX, reminder is lost
Copies 5 into AX, quotient is lost
Copies 4 into AX (0100)
Copies 13 into AX (1101)
Copies 254 into AL (1111 1110)
INSTRUCTION SET
The instructions of 8086 can be broadly classified under the following headings:
1. Data transfer instructions
2. Data conversion instructions
3. Logical instructions
4. String instructions
5. Arithmetic instructions
6. Branch instructions
7. Processor control instructions
DATA TRANSFER INSTRUCTIONS
In this group large number of instructions is present which perform data transfer of the
following type:
a. Move contents of a register or contents of a memory location, or immediate data to a
register or memory location and move data to or from Accumulator using direct
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addressing (address and segment directly specified in the instruction itself, e.g. MOV
AX, DS:34H, MOV AL,SS:34, MOV AX, LOC, MOV SS:23H,AL, MOV LIST,AX)
b. Data transfer between a segment register and a register or a memory location (e.g.
MOV DS, BX, MOV SS, DX, MOV 1234H [BX+SI], SS)
c. Push and Pop instructions (PUSH, POP)
d. Exchange instructions (XCHG)
e. Data transfer with I/O ports (IN, OUT)
PUSH: In 8086, the PUSH instruction always transfers 2 bytes of data to the stack,
depending on the register or the size of the memory location. The source of the data
may be any internal 16 bit register, any segment register, or any two bytes of memory
data. The PUSHF instruction (push flags) copies the contents of the flag register to
the stack.
Whenever data is pushed on to the stack, the first i.e. the most significant data byte
moves into the stack segment memory location addressed by SP 1. The second or the
least significant data byte moves into the stack segment memory location addressed by
SP 2. After the data are stored by a PUSH instruction, the contents of the SP register
decrement by 2. The PUSH AX instruction copies the contents of AX on to the stack
where address SS:[SP 1] = AH , SS:[SP 2] = AL , and afterwards SP = SP 2.
Symbolic
PUSH reg16
PUSH mem16
PUSH seg
PUSHF
Note
16-bit register
16-bit pointer
Segment register
Save flags
POP: The POP instruction performs the reverse of PUSH instruction. It removes data
from the stack and places it into the target 16 bit register, segment register or 16 bit
memory location. The POPF instruction (pop flags) removes a 16 bit number from the
stack and places it into the flag register. The POP BX instruction removes the first
byte of data from the stack segment memory location addressed by SP and places it
into BL register. The second byte of data is removed from the stack segment memory
location addressed by SP + 1 and places it into BH register. After both the bytes are
removed from the stack, the SP register is incremented by 2.
POP CS instruction is not valid as if this instruction executes, only a portion of the
address (CS) of the next instruction changes, which makes the POP CS instruction un
predictable and therefore not allowed.
Symbolic
POP reg16
POP mem16
POP seg
POP F
Note
16-bit register
16-bit pointer
Segment register
pop flags
XCHG: The XCHG (exchange) instruction exchanges the contents of a register with
the contents of any register or memory location. This instruction cannot exchange the
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segment registers or memory to memory data. A byte or a word can be exchanged by
this instruction. The XCHG instruction, using 16 bit AX register and any other 16 bit
register, occupies 1 byte of memory and other XCHG instructions occupy 2 or more
memory locations.
Assembly language
Operation
XCHG AL,CL
XCHG CX,BP
XCHG AX,[DI]
XCHG AL,DATA2
Exchanges the contents of AL with CL

Exchanges the contents of CX with BP
Exchanges the contents of AX with memory location addressed by DI
Exchanges the contents of AL with Data segment memory location
DATA2
IN and OUT: These instructions perform I/O operations. The contents of AL or AX

are transferred between I/O devices and the microprocessor. An IN instruction
transfers data from an external I/O device to AL or AX; an OUT transfers data from
AL or AX to an external I/O device. Two forms of I/O device addressing exist for IN
and OUT: fixed port and variable port. Fixed port addressing allows data transfer
between AL /AX and 8 bit I/O port address. Here the port number follows the
instructions Opcode. The port address appears on the address bus during I/O
operation. 8 bit port address is zero extended (6Ah is converted to 006AH) and put on
the address bus (A0-A15). Other address bus lines, A16-A19 are undefined during
I/O operation. Variable port addressing allows data transfer between AL/AX and a
16 bit port address, which is stored in DX register. The 16 bit port address appears on
A0-A15.
Assembly language
Operation
IN AL,P8
IN AX,P8
IN AL,DX
IN AX,DX
OUT P8,AL
OUT P8,AX
OUT DX,AL
OUT DX,AX
8 bits are input to AL from I/O port P8

16 bits are input to AX from I/O port P8
8 bits are input to AL from I/O port addressed by DX
16 bits are input to AX from I/O port addressed by DX
8 bits are output from AL to I/O port P8
16 bits are output from AX to I/O port P8
8 bits are output from AL to I/O port addressed by DX
16 bits are output from AX to I/O port addressed by DX
ALP: Interchange contents of 2 bytes at memory locations represented by opr1 &

opr2
.model small
.data
opr1 db 10h
opr2 db 20h
.code
mov ax, @data
mov ds, ax
mov al, opr1
xchg al, opr2
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INSTRUC
I
CTION SE
ET, PROCEDURES, MACRO
OS
mov opr1, al
m
m ah, 4ch
mov
innt 21h
ennd
TA CONVE
ERSION INS
STRUCTIO
ONS
DAT
This group includ
des the following instrucctions:
v
in AL (XLAT)
(
a. Traanslate the value
b. Looad Effectivee address of a memory loocation into a register (L
LEA)
c. Load DS and another
a
regisster with conntents of 2 memory
m
wordds (LDS)
d. Looad ES and another
a
regisster with conntents of 2 memory
m
wordds (LES)
e. Load AH with LS byte of flag
f registerss (LAHF)
f. Stoore AH into LS
L byte of flag
fl registerss (SAHF)
XL
LAT: The XLAT
X
(transslate) instrucction converrts the conteents of AL register
r
into a
nuumber stored
d in memorry table. Thhis instructioon performs the direct table lookuup
tecchnique used
d to convertt one code too another. First, the conntents of AL
L are added to
t
BX
X to form a memory adddress in the data segmennt. It then coopies the coontents of thiis
adddress to thee AL registeer. The num
mber to be translated iss placed in AL and BX
X
coontains the sttarting offsett of the mem
mory table.
ALP: convert un
npacked BC
CD digits to seven segm
ment code ussing XLAT instruction
i
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.model small
.data
table db 3Fh, 06h, 5Bh, 4Fh. 66h, 6Dh, 7Dh, 07h, 7Fh, 6Fh
stg_bcd db 09, 03, 05, 01, 10, 07, 02, 04, 06, 08
stg_disp db 10 dup (?)
.code
mov ax, @data
mov ds, ax
mov es, ax
lea bx, table
lea si, stg_bcd
lea di, stg_disp
cld ; DF=0, pointers (SI & DI) automatically increment after execution of string inst
mov cx, length stg_bcd ; cx=10
convert: lodsb ; al=bcd no. from mem loc in DS pointed by SI
cmp al,09
ja invalid
xlat table
stosb; contents of AL (converted 7 segment code) stored in mem loc in ES pointed by DI
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jmp next
invalid: mov al, 00h

stosb
next: loop convert
mov ah, 4ch
int 21h
end
ALP: Using XLAT instruction implement the given multiple output logical network.
The input variables are A, B, C, D with D being LSB and outputs are X, Y and Z
with Z being LSB.
X = ABC D + ABC D + ABCD + ABCD
Y = ABC D + ABCD + ABC D
Z = ABCD + ABCD + ABC D + ABCD
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
Y
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
Z
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
1
.model small
.data
table db 010b, 000b, 000b, 010b, 000b, 000b, 000b, 101b, 000b, 110b, 000b, 001b, 100b,
001b, 000b, 101b
data_in db 09h, 0Ah, 05h, 0Fh, 0Ch, 07, 02, 04, 06, 08
mult_out db 10 dup (?)
.code
mov ax, @data
mov ds, ax
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lea bx, table
lea si, data_in
lea di, mult_out
mov cx, length data_in ; cx=10
convert: mov al, [si] ; al=bcd no. from mem loc in DS pointed by SI
xlat table
mov [di], al; contents of AL (converted) stored in mem loc pointed by DI
inc si
inc di
loop convert
mov ah, 4ch
int 21h
end
The LEA instruction loads any 16 bit register with the address, as determined by the
addressing mode selected for the instruction. The LDS and LES instructions load any 16
bit register with the offset address retrieved from a memory location, and then load either
DS or ES with a segment address retrieved from the memory.
LEA: The LEA instruction loads any 16 bit register with the offset address of the data
specified by the operand. LEA AX, NUMB instruction loads the operand address of
NUMB into the register AX. LEA BX, [DI] loads the offset address specified by [DI]
(contents of DI) into the BX register. MOV BX, DI performs this task in less time and
is often preferred to LEA BX, [DI]. MOV AX, OFFSET NUMB instruction uses the
OFFSET directive and performs the same function as an LEA BX, NUMB instruction
if the operand is a displacement. Both the instructions load the offset address of the
memory location NUMB into BX register. But OFFSET only functions with simple
operands such as labels (e.g. NUMB). It is not used for operands such as registers
[DI], LIST [SI] etc. Time taken to execute LEA instruction is more than that using
OFFSET directive because the assembler calculates the offset address of NUMB while
the microprocessor calculates the LEA instruction. LEA SI, [BX+DI] instruction adds
BX and DI and stores the sum in SI. The sum generated by this instruction is modulo64K sum (drops any carry out of the 16 bit result).
LDS, LES: The LDS and LES instructions load any 16 bit register with an offset
address, and the DS and ES segment register with the segment address. These
instructions use any of the memory addressing modes (not the register addressing
mode) to access a 32 bit section of the memory that contains both the segment (16 bit)
and offset address (16 bit). LDS BX, [DI] instruction transfers the 32 bit number,
addressed by DI in the data segment, into the BX and DS registers. For e.g. if
DS=1000H, DI=1000H, DSX10+DI=11000H. Data at location 11000H is transferred
to BL, at 11001H is transferred to BH, at 11002H and 11003H is transferred to DS
register. These instructions obtain a new far address from the memory. The offset
address appears first, followed by the segment address. This format is used to store all
the 32 bit memory addresses. A far address can be stored in the memory by the
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assembler. E.g. ADDR DD FAR PTR DAT instruction stores the offset and segment
address (far address) of DAT in the 32 bits of memory at location ADDR. The DD
directive tells the assembler to store a double word in memory address ADDR.
Assembly language
LEA AX,NUMB
LDS DI,LIST
LES BX,CAT
Operation
Loads AX with the address of NUMB
Loads DS and DI with the 32 bit contents of data segment memory
location LIST
Loads ES and BX with the 32 bit contents of data segment memory
location CAT
LAHF and SAHF: These instructions allowed 8085 software to be translated into 8086
software by a translation program. The LAHF instruction transfers the right most 8
bits of the flag register into AH register and the SAHF instruction transfers AH
register into rightmost 8 bits of the flag register. The SAHF instruction is used with
numeric coprocessor to transfer the contents of status register in coprocessor to the
flag register.
ALP: copy contents of flag register into accumulator register using any
arithmetic or logic operations
.model small
.stack
.code
mov ax, @data
mov ds, ax
PUSHF
POP AX
mov ah, 4ch
int 21h
end
LOGICAL INSTRUCTIONS
These can perform AND, OR, EXOR, NOT, TEST, SHIFT, ROTATE etc operations.
Rotate instructions
a. Rotate left contents of memory location or register
b. Rotate right contents of memory location or register
c. Rotate left including carry contents of memory location or register
d. rotate right including carry contents of memory location or register
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Shift instructions
a. Shift right the contents of memory location or register
b. Arithmetic shift right the contents of a register or a memory location
c. shift left the contents of a register or a memory location
TEST INSTRUCTION
This performs bitwise AND of the 2 operands. But the operand values remain unchanged
after the TEST instruction. The result of the AND operation is stored in a register which
is not accessible to the programmer. Only the flags are affected depending on the result of
AND operation.
S and Z flags are updated based on the result. C and O flags are reset to 0. AF is
undefined. P flag updates based on the result.
In this group, we have instructions to
(a) AND contents of 2 registers or a register and a memory location, using TEST
instruction.
(b) AND a register or a memory location with immediate data, using TEST
instruction.
(c) AND accumulator contents with immediate data, using TEST instruction.
Some of the examples are
TEST AX, BX
(2 BYTE INSTRUCTION)
TEST CX, 0083H
TEST CL, 83H
TEST AX, 0083H
TEST AL, 83H
TEST instruction tests a single bit (or occasionally multiple bits), while CMP instruction
tests the entire byte or a word. TEST instruction is followed by JZ or JNZ instruction.
The destination operand is normally tested against an immediate operand. The value of
immediate data is 1 to test the right most bit position; 2 to test the next bit, 4 for next and
so on.
AND, OR, EXOR INSTRUCTIONS
In this group we have the instructions to
a. AND/ OR/ XOR the contents of 2 registers or a register and a memory location
b. Immediate data with the contents of a register or a memory location
c. Immediate data with Accumulator.
AND instruction performs bitwise AND of 2 operands. It is used for selectively resetting
to 0 some bits of operand-1. Bits of operand-1 which are ANDed with 0s are reset to 0,
and the bits of operand-1 which are ANDed with 1s are not changed. Flags are affected.
AND operation performs logical multiplication. It clears bits of a binary number, and this
is called masking.
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OR instruction performs bitwise OR of 2 operands. It is used for selectively setting to 1
some bits of operand-1. Bits of operand-1 which are ORed with 1s are set to 1, and the
bits of operand 1 which are ORed with 0s are not changed. Flags are affected. OR
instruction performs logical addition and is often called inclusive OR function.
XOR instruction performs bitwise EXOR of 2 operands. This instruction has the
mnemonic XOR. It is used for selectively inverting some bits of operand-1. Bits of
operand-1 which are EXORed with 1s are inverted, and the bits of operand 1 which are
EXORed with 0s are not changed. Flags are affected.
AND/ OR/ XOR instruction use any addressing mode except memory to memory and
segment register addressing.
AND/ OR/ XOR instruction results in change of destination operand.
AND/ OR/ EXOR instructions affect the flags as follows: S and Z flags are updated
based on the result. C and O flags are reset to 0. AF is undefined. P flag is updated based
on the result.
Some of the examples are
AND AX, BX
AND DS:0F246H[BP], DX
AND CX, 0083H
AND CL, 43H
AND AX, 0083H
AND AL, 83H
OR AX, BX
OR [DI], DX
OR CX, 0083H
OR CL, 43H
OR AX, 0083H
OR AL, 83H
XOR AX, BX
XOR DS:[BP], DX
XOR DX, 0083H
XOR CL, 43H
XOR AX, 0083H
XOR AL, 83H
NOT INSTRUCTION
It performs logical inversion of the contents of a register or a memory location. It
replaces the number with its 1s complement.
NOT BX
NOT CL
NOT TEMP
NOT BYTE PTR [BX]
ROTATE INSTRUCTIONS
a. Rotate left contents of memory location or register
b. Rotate right contents of memory location or register
c. Rotate left including carry contents of memory location or register
d. rotate right including carry contents of memory location or register
Rotate left contents of a register or a memory location: The mnemonic for this
instruction is ROL. It rotates left the contents of a memory location or a register. The
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operation can be on a byte or a word data. The rotation can be by one bit position or
more.
If the rotation is by 1 bit, it has to be clearly indicated in the instruction. If it is by more
than one bit position, CL must be loaded with the count value to indicate the number of
bit positions by which the rotation has to be made.
After performing rotate left operation by one bit position, the bit moved out from the MS
bit position goes to the vacancy created in the LS bit position. Also, C flag gets a copy of
the bit moved out from the MS bit position. In the case of rotation by several bit
positions, C flag will get a copy of the most recently moved out bit from the MS bit
position.
Only C and O flags are affected by the rotation. The O flag will be set to 1, if there is a
change in the MS bit value.
The ROL instruction can be used for swapping the hex digits in a byte by using a count
value of 4 in CL, or for swapping the bytes in a word by using a count value of 8 in CL. It
can also be used to test the value of MS bit.
C
Register/memory contents
The template for this instruction is 110100VW MOD-000-R/M. There are 7 bits in this
template for identifying the operands. The V bit stands for the count value. This bit will
be 0 for the rotation by 1 bit position. If this bit is 1, it means that CL contains the count
value.
The W bit is 0 to indicate it is a byte operation or it is 1 to indicate a word operation.
Example 1: ROL CX, 1
It rotates left the contents of CX by 1 bit position.
Example 2: ROL BX, CL
It rotates left the contents of BX by a number of bit positions whose value is given in CL.
Example 3: ROL BYTE PTR DS: 0F246H [BP], CL
This instruction rotates left the contents of a memory location whose Effective address is
given as the sum of the 16 bit offset value 0F246H and the contents of BP register. The
physical address is generated using DS as segment register. The number of times the
rotation is performed is given by the contents of CL register. The result is stored in the
same memory location.
Rotate right contents of a register or a memory location: The mnemonic for
this instruction is ROR. It rotates right the contents of a memory location or a register.
The operation can be on a byte or a word data. The rotation can be by one bit position or
more.
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After performing rotate right operation by one bit position, the bit moved out from the LS
bit position goes to the vacancy created in the MS bit position. Also, C flag gets a copy of
the bit moved out from the LS bit position. In the case of rotation by several bit positions,
C flag will get a copy of the most recently moved out bit from the LS bit position.
The ROR instruction can be used for swapping the hex digits in a byte by using a count
value of 4 in CL, or for swapping the bytes in a word by using a count value of 8 in CL. It
can also be used to test the value of LS bit.
value.
Example 1: ROR CX, 1
It rotates right the contents of CX by 1 bit position.
Example 2: ROR BX, CL
It rotates right the contents of BX by a number of bit positions whose value is given in
CL.
Example 3: ROR BYTE PTR DS: 0F246H [BP], CL
This instruction rotates right the contents of a memory location whose Effective address
is given as the sum of the 16 bit offset value 0F246H and the contents of BP register. The
Rotate left including carry on contents of a register or a memory location:
The mnemonic for this instruction is RCL. It rotates left the contents of a memory
location or a register by involving the carry flag in the loop. The operation can be on a
byte or a word data. The rotation can be by one bit position or more.
After performing rotate left operation by one bit position, the bit moved out from the MS
bit position goes to the carry flag, and in the process moves out the earlier carry bit to the
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vacancy created in the LS bit position. In the case of rotation by several bit positions, C
flag will get a copy of the most recently moved out bit from the MS bit position.
C
The RCL instruction is useful for testing the value of the MS bit of an operand. It is also
used for moving the carry flag value to the LS bit position of an operand.
template for identifying the operands.
The V bit stands for the count value. This bit will be 0 for the rotation by 1 bit position. If
this bit is 1, it means that CL contains the count value.
Example 1: RCL CX, 1
It rotates left with carry, the contents of CX by 1 bit position.
Example 2: RCL BX, CL
It rotates left with carry, the contents of BX by a number of bit positions whose value is
given in CL.
Example 3: RCL BYTE PTR DS: 0F246H [BP], CL
This instruction rotates left with carry, the contents of a memory location whose Effective
address is given as the sum of the 16 bit offset value 0F246H and the contents of BP
register. The physical address is generated using DS as segment register. The number of
times the rotation is performed is given by the contents of CL register. The result is
stored in the same memory location.
Rotate right including carry on contents of a register or a memory location:
The mnemonic for this instruction is RCR. It rotates right the contents of a memory
location or a register by involving the carry flag in the loop. The operation can be on a
byte or a word data. The rotation can be by one bit position or more.
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After performing rotate right operation by one bit position, the bit moved out from the LS
bit position goes to the carry flag, and in this process moves out the earlier carry bit to the
vacancy created in the MS bit position. In the case of rotation by several bit positions, C
flag will get a copy of the most recently moved out bit from the LS bit position.
The RCR instruction is useful for testing the value of the LS bit of an operand. It is also
used for moving the carry flag value to the MS bit position of an operand.
value.
Example 1: RCR CX, 1
It rotates right with carry, the contents of CX by 1 bit position.
Example 2: RCR BX, CL
It rotates right with carry, the contents of BX by a number of bit positions whose value is
given in CL.
Example 3: RCR BYTE PTR DS: 0F246H [BP], CL
This instruction rotates right with carry, the contents of a memory location whose
Effective address is given as the sum of the 16 bit offset value 0F246H and the contents
of BP register. The physical address is generated using DS as segment register. The
number of times the rotation is performed is given by the contents of CL register. The
result is stored in the same memory location.
SHIFT INSTRUCTIONS
a. Shift right the contents of memory location or register
b. Arithmetic shift right the contents of a register or a memory location
c. Shift left the contents of a register or a memory location
Shift right the contents of memory location or register: The mnemonic for this
instruction is SHR. It shifts right the contents of a register or a memory location. The
operation can be on a byte or a word data. The shift can be by one bit position or more.
This operation is used with unsigned numbers.
If the shift is by 1 bit, it has to be clearly indicated in the instruction. If it is by more than
one bit position, CL must be loaded with the count value to indicate the number of bit
positions by which the shift has to be made.
0
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After performing shift right operation by one bit position, the bit moved out from the LS
bit position goes to the carry flag. In the vacancy created in the MS bit position a zero
will be moved. In the case of shift by several bit positions, C flag will get a copy of the
most recently moved out bit from the LS bit position.
S and Z flags are updated based on the result. C equals the most recently shifted bit from
the LS position. O flag is set to 1 if there is a change in the MS bit value. AF flag is
undefined. P flag is updated based on the result. It is meaningful only for a byte
operation.
The SHR instruction is useful for dividing an unsigned binary number by a power of 2.
Right shifting once will divide by 2, shifting twice will divide by 4, thrice will divide by
8, etc. When an odd number is shifted this way, the result will be truncated. For example,
number 5 shifted right once will give 2 as the result.
be 0 for the shifts by 1 bit position. If this bit is 1, it means that CL contains the count
value.
Example 1: SHR CX, 1
It shifts right the contents of CX by 1 bit position.
Example 2: SHR BX, CL
It shifts right the contents of BX by a number of bit positions whose value is given in CL.
Example 3: SHR BYTE PTR DS: 0F246H [BP], CL
This instruction shifts right the contents of a memory location whose Effective address is
Shift left the contents of a register or a memory location: The mnemonic for
this instruction is SHL or SAL (Shift Arithmetic Left). This operation can be used for
both signed and unsigned numbers. It shifts left the contents of a memory location or a
register. The operation can be on a byte or a word data. The shift can be by one bit
position or more.
C
After performing shift left operation by one bit position, the bit moved out from the MS
bit position goes to the carry flag. In the vacancy created in the LS bit position a 0 is
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moved. In the case of shift by several bit positions, C flag will get a copy of the most
recently moved out bit from the MS bit position.
the MS position. O flag is set to 1 if there is a change in the MS bit value. A flag is
operation.
The SHL / SAL instruction is useful for multiplying an unsigned binary number by a
power of 2. Left shifting once will multiply by 2, shifting twice will multiply by 4, thrice
will multiply by 8, etc. If the MS bit of a number is a 1, then after left shifting, the result
will be incorrect.
be 0 for the shift by 1 bit position. If this bit is 1, it means that CL contains the count
value.
Example 1: SHL CX, 1 or SAL CX, 1
It shifts left the contents of CX by 1 bit position.
Example 2: SHL BX, CL
It shifts left the contents of BX by a number of bit positions whose value is given in CL.
Example 3: SHL BYTE PTR DS: 0F246H [BP], CL
This instruction shifts left the contents of a memory location whose Effective address is
Arithmetic shift right the contents of a register or a memory location: The
mnemonic for this instruction is SAR. It shifts right the contents of a register or a
memory location. The operation can be on a byte or a word data. The shift can be by one
bit position or more. This operation is used with signed numbers. In arithmetic shifts the
sign of the number is not changed after the shift operation.
After performing shift right operation by one bit position, the bit moved out from the LS
bit position goes to the carry flag. In the vacancy created in the MS bit position once
DKDEPTOFTCE,APSCE
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again the original MS bit value will be moved. Thus the sign of the number is not
changed after the arithmetic shift. In the case of shift by several bit positions, C flag will
get a copy of the most recently moved out bit from the LS bit position.
the LS position. O flag is set to 1 if there is a change in the MS bit value. A flag is
operation.
The SAR instruction is useful for dividing a signed binary number by a power of 2.
Arithmetic Right shifting once will divide by 2, shifting twice will divide by 4, thrice will
divide by 8, etc. When an odd number is shifted this way, the result will be truncated. For
example, number 5 shifted right once will give 2 as the result. Number -5 (byte FBH)
Arithmetic right shifted once will give -3 (byte FDH) as the result.
be 0 for the shift by 1 bit position. If this bit is 1, it means that CL contains the count
value.
Example 1: SAR CX, 1
It arithmetic shifts right the contents of CX by 1 bit position.
Example 2: SAR BX, CL
It arithmetic shifts right the contents of BX by a number of bit positions whose value is
given in CL.
Example 3: SAR BYTE PTR DS: 0F246H [BP], CL
This instruction arithmetic shifts right the contents of a memory location whose Effective
address is given as the sum of the 16 bit offset value 0F246H and the contents of BP
register. The physical address is generated using DS as segment register. The number of
times the rotation is performed is given by the contents of CL register. The result is
stored in the same memory location.
ALP: Selectively set bits 0 & 2 of DL register, change bits 1 & 6, clear bits 3 & 4 and
then test bits 1 & 7 and branch to exit if they both are set.
NOTE: (i) to check if both bits are set, perform not operation of given data and then
use test. Condition is false if ZF=1.
(ii) to check if either of the bits are set, directly use test on the given data and
condition is false if ZF=0.
.model small
.data
x db 0b3h
msg1 db bits 1 & 7 are both set,$
msg2 db bits 1 or 7 or both are not set,$
DKDEPTOFTCE,APSCE
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.code
mov ax, @data
mov ds, ax
mov dl, x
or dl, 00000101b; dl= 10110111
xor dl, 01000010b; dl= 11110101
and dl, 11100111b; dl= 111001001
mov al, dl;
al=111001001
not al;
al= 000110110
test al, 10000010b; 000000010
jz exit;
ZF=0 indicating result not 0
lea dx, msg1
jmp disp
exit: lea dx, msg2
disp: mov ah, 09h
int 21h
end
ALP: (i) if bits 1 & 14 or bits 7 & 9 are set, branch to task1;
(ii) If condition 1 is not satisfied, no branch is made to task1. If either bit 3 or
bit 4 is set, branch to task2.
(iii) Else branch to task3
.model small
.data
x dw 0bd23h
.code
mov ax, @data
mov ds, ax
mov ax, x
not ax
test ax, 4002h; bit 14 and bit 1 tested
jz task1
test ax, 280h; bit 7 and bit 9 tested
jz task1
not ax
test ax, 18h; bit 3 or bit 4 tested
jnz task2
task3: .
DKDEPTOFTCE,APSCE
Page18

.
.
task1: .
.
.
task2: .
.
.
mov ah, 4ch
int 21h
end
ALP: conversion of 16 digit unpacked bcd to packed bcd
,model small
.data
unpked db 9, 7, 3, 2, 1, 5, 6, 8, 3, 5,
4, 9, 2, 5, 7, 0
pked db 8 dup (?)
.code
mov ax, @data
mov ds, ax
mov dx,8
mov cl,4
mov si, 0
mov di, si
convert: mov ax, word
unpked[si]
shl al, cl
shr ax, cl
mov pked[di], al
add si, 2
inc di
dec dx
jnz convert
ptr ax= 07 09
al=90, ax=0790
ax=0079
store 79
si to next word
di to next byte
count dec=7
repeat
ax=02 03
al=30,ax=0230
ax=0023
store 23
si=4
di=2
count dec=6
repeat
mov ah, 4ch

int 21h
ax= 05 01
al=10,ax=0510
ax=0051
store 51
si=6
di=3
count dec=5
repeat
this loop repeats till
dx= 0
end
result: 79, 23, 51, 86, 53, 94, 52, 07
DKDEPTOFTCE,APSCE
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STRING INSTRUCTIONS
It can perform load, store, movement, comparison and scan operations on the string.
a. store string instruction (STOSB or STOSW with REP prefix)
b. Load string instruction (LODSB or LODSW)
c. move string instruction (MOVSB or MOVSW with REP prefix)
d. compare string instruction (CMPSB or CMPSW with REPE or REPNE prefix)
e. scan string instruction (SCASB or SCASW with REPE or REPNE prefix)
LODS, STOS, MOVS, INS, and OUTS are the 5 string data transfer instructions. Data
transfers can be either a single byte, or a word or if repeated, a block of bytes, or words.
The direction flag or the D flag bit is used during string instructions to select either
increment or decrement for the SI and DI registers. If D=1, the registers are automatically
decremented and if D=0, they are incremented. The D flag is set with the STD (set
direction) and cleared with the CLD (clear direction) instructions.
Whenever a string instruction transfers a byte, the contents of SI and/or DI will increment
or decrement by 1. If a word is transferred, the contents of SI and/or DI will increment or
decrement by 2. Only the actual register used by the string instruction will increment or
decrement. LODS instructions use SI register to address the memory data and STOS
instructions use DI register to address a memory location.
The contents of either DI or SI or both are used to access or address the memory location.
The DI offset address accesses data in Extra Segment for all the string instructions that
use it. The SI register accesses data, by default, in data segment. The segment assignment
of SI can be changed with a segment override prefix, but the DI segment assignment is
always in the extra segment, when a string instruction executes. The MOVS instructions
can transfer 64K bytes of data from one segment of memory to another.
LODS: This instruction loads AL or AX with data stored at the data segment offset
address indexed by the SI register. The contents of SI increment (if D = 0) or
decrement (if D = 1) by 1 if a byte is loaded (into AL), and increment (if D = 0) or
decrement (if D = 1) by 2 if a word is loaded (into AX). The LODSB instruction
(loads a byte) causes a byte to be loaded into AL register, LODSW instruction (loads
a word) causes a word to be loaded into AX. LODS instruction can also be followed
by a byte or a word operand to select a byte or a word transfer.
Assembly language
LODSB
LODSW
LODS LIST
LODS DATA1
Operation
AL = DS:[SI] i.e. DSX10+SI, SI=SI+1 OR SI-1
AX = DS:[SI] i.e. DSX10+SI, SI=SI+2 OR SI-2
AL = DS:[SI] i.e. DSX10+SI, SI=SI+1 OR SI-1(LIST is 1 byte)
AX = DS:[SI] i.e. DSX10+SI, SI=SI+2 OR SI-2(DATA1 is a
word)
DKDEPTOFTCE,APSCE
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STOS: This instruction stores a byte or a word from AL or AX at the Extra segment
memory location addressed by the DI register. The STOS instruction can be appended
with a B or a W or followed by a byte or word sized operand to select a byte or a
word transfer. The STOSB instruction (stores a byte) stores the contents of AL (1
byte) in the Extra segment memory location addressed by DI. The STOSW
instruction (stores a word) stores the contents of AX (1 word) in the Extra segment
memory location addressed by DI. After the contents of AL or AX are stored, the
contents of DI are incremented (D = 0) or decremented (D = 1) (by 1 for byte
transfer, by 2 for word transfer).
Assembly language
STOSB
STOSW
STOS LIST
STOS DATA1
Operation
ES:[DI]=AL i.e. ESX10+DI, DI=DI+1 OR DI-1
ES:[DI]=AX i.e. ESX10+DI, DI=DI+2 OR DI-2
ES:[DI]=AL i.e. ESX10+DI, DI=DI+1 OR DI-1(LIST is 1 byte)
ES:[DI]=AX i.e. ESX10+DI, DI=DI+2 OR DI-2(DATA1 is a
word)
STOS with a REP: The repeat prefix (REP) is added to any string data transfer
instruction, except the LODS instruction. The REP prefix causes the CX register to
decrement by 1 each time the string instruction executes. After CX decrements, the
string instruction repeats. If CX reaches a value 0, the instruction terminates and the
program continues with the next sequential instruction. For e.g. if CX is loaded with
10, and a REP STOSB instruction executes, the microprocessor automatically repeats
the STOSB instruction 10 times. This instruction stores the contents of AL in a block
of memory, as the DI register is automatically incremented or decremented and each
time points to next memory location.
MOVS: This instruction is used to transfer data from one memory location to another.
The MOVS instruction transfers a byte or a word from data segment location
addressed by SI to the extra segment location addressed by DI. The pointers SI and
Assembly language
MOVSB
MOVSW
MOVS N1,N2
MOVS D1,D2
Operation
ES:[DI]=DS:[SI], DI=DI+1 ; SI+1
ES:[DI]= DS:[SI], DI=DI+2 ; SI+2
ES:[DI]= DS:[SI], DI=DI+1 ; SI+1, (N1,N2 are bytes)
ES:[DI]= DS:[SI], DI=DI+2 ; SI+2; (D1,D2 are words)
DI then increment or decrement depending on the direction flag. The destination

operand pointed by DI must always be located in extra segment. The source operand
present in data segment, pointed by SI can be overridden so that another segment can
be used. REP prefix can be added to MOVS instruction to transfer a block of data in
one segment to another segment.
COMPARE STRINGS INSTRUCTION
It can be a byte or a word operation. The mnemonic for the byte operation is CMPSB,
which stands for compare string byte. It has the Opcode A6H. The mnemonic for the
DKDEPTOFTCE,APSCE
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word operation is CMPSW, which stands for compare string word and its Opcode is
A7H.
This instruction compares the byte or word at location DS: SI with the byte or word at
location ES: DI. It subtracts byte or word at location ES: DI from byte or word at location
DS: SI, but the operand values are not changed. The status flags are affected depending
on the result of subtraction.
If D = 0, the SI and DI registers are incremented by 1 or 2 depending on whether it is a
byte or a word operation. If D = 1, the SI and DI registers are decremented by 1 or 2
depending on whether it is a byte or a word operation.
Example 1: CMPSB instruction
The string Nivedita is at an offset of 1231H in the Data Segment. Another string
Niranjan starting at an offset 3451H is in Extra Segment.
To compare these strings of 8 characters each, the instruction CMPSB is used to compare
a byte at a time. This instruction should be executed 8 times in a loop to perform the
desired string comparison. CMPSB instruction expects that the source string is pointed by
the DS: SI, or that the segment base for the source string must be provided in DS and the
offset in SI. Similarly, ES: DI should point to the destination string.
Therefore, SI = 1231H and DI = 3451H. This result in comparison of first bytes of both
strings and SI and DI automatically increment to 1232H and 3452H respectively so that
next time through the loop, the CMPSB instruction compares the next character in the
two strings, and so on.
Automatic increment of the contents of SI and DI takes place only if Direction flag D = 0.
D is reset to zero by executing the instruction CLD. If the D flag is set to 1 by executing
the instruction STD, the SI and DI registers are automatically decremented after
executing the instruction CMPSB.
Thus the same string movement is achieved by executing CMPSB 8 times in a loop, by
initially loading SI with 1238H and DI with 3458H, and setting D = 1.
Example 2: CMPSW instruction
The word string Ni, ve, di, ta starts at offset address 1231H in data segment and
the word string Ni, ra, nj, an is at offset 3451H in extra segment. These 2 strings
are of 8 characters or 4 words.
CMPSW instruction is used to compare 1 word at a time in the strings. This instruction
should be executed 4 times in a loop to perform the desired string comparison. CMPSW
instruction expects that the source string is pointed by the DS: SI, or that the segment
base for the source string must be provided in DS and the offset in SI. Similarly, ES: DI
should point to the destination string.
Therefore, SI = 1231H and DI = 3451H. This result in comparison of first words of both
strings and SI and DI automatically increment to 1233H and 3453H respectively so that
next time through the loop, the CMPSW instruction compares the next word in the two
strings, and so on.
Automatic increment by 2 of the contents of SI and DI takes place only if Direction flag
D = 0. D is reset to zero by executing the instruction CLD. If the D flag is set to 1 by
DKDEPTOFTCE,APSCE
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executing the instruction STD, the SI and DI registers are automatically decremented by
2 after executing the instruction CMPSW.
Thus the same string movement is achieved by executing CMPSW 4 times in a loop, by
It is possible to use CMPS instead if CMPSB / CMPSW as the mnemonic, but the
assembler is informed about byte/word operation by indicating the names of source and
destination strings in the instruction itself, like CMPS SRC,DST. The assembler will
code the instruction for byte operation if SRC and DST are declared as bytes (DB) and
will code it as word operation if the SRC and DST are declared as words (DW).
If 2 strings are to be compared, it is not necessary to execute CMPSB / CMPSW
instruction in a loop because 8086 provides the REPE (Repeat While Equal) or REPZ or
REPNE or REPNZ prefix facility.
REPE Prefix for CMPSB
REPE prefix is not an instruction by itself. It has the code F3H. REPZ (repeat if the result
is zero) is another equivalent mnemonic for the same operation.
The REPE CMPSB instruction will cause CMPSB to be repeated as long as the compared
bytes are equal (Z flag = 1) and CX contents is not yet 0. Thus the repetition is terminated
whenever the compared bytes are not equal or when CX contents become zero.
For the above Example 1, the comparison of the strings can be achieved by the following
instructions:
CLD ; SI = 1231H, DI = 3451H
MOV CX, 08H
REPE CMPSB
Or
STD ; SI = 1238H, DI = 3458H
MOV CX, 08H
REPE CMPSB
REPNE Prefix for CMPSB
The REPNE Prefix is not an instruction by itself and its Opcode is F2H. The REPNE
CMPSB instruction will cause CMPSB to be repeated as long as the compared bytes are
not equal (Z flag = 0) and CX contents is not yet 0. Thus the repetition terminates
whenever the compared bytes are equal or CX = 0.
REPNZ (repeat if result is not zero) is another mnemonic for the same operation.
REPE Prefix for CMPSW
The REPE CMPSW instruction will cause CMPSW to be repeated as long as the
compared words are equal (Z flag = 1) and CX contents is not yet 0. Thus the repetition is
terminated whenever the compared words are not equal or when CX contents become
zero.
DKDEPTOFTCE,APSCE
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For the above Example 2, the comparison of the strings can be achieved by the following
instructions:
CLD ; SI = 1231H, DI = 3451H
MOV CX, 04H
REPE CMPSW
Or
STD ; SI = 1237H, DI = 3457H
MOV CX, 04H
REPE CMPSW
REPNE Prefix for CMPSW
CMPSW instruction will cause CMPSW to be repeated as long as the compared words
are not equal (Z flag = 0) and CX contents is not yet 0. Thus the repetition terminates
whenever the compared words are equal or CX = 0.
SCAN STRING INSTRUCTION
It can be a byte or a word operation. The mnemonic for the byte operation is SCASB,
which stands for Scan string byte and its Opcode is AEH. For word operation, the
mnemonic is SCASW, which stands for Scan string word and its Opcode is AFH.
This instruction compares the byte or word in AL or AX with the byte or word at location
ES: DI. It subtracts byte or word at location ES: DI from byte or word in AL or AX, but
the operand values are not changed. The status flags are affected depending on the result
of subtraction.
If D = 0, the SI and DI registers are incremented by 1 or 2 depending on whether it is a
byte or a word operation. If D = 1, the SI and DI registers are decremented by 1 or 2
depending on whether it is a byte or a word operation.
Example 1: SCASB instruction
String Advitiya starts at offset address of 3451H in the extra segment and this string of
8 characters has to be scanned for the occurrence of character t.
SCASB instruction performs this comparison, 1 byte at a time. This instruction should be
executed a maximum of 8 times in a loop to perform the desired string scan operation.
SCASB instruction expects that the destination string is pointed by ES: DI.
So, to facilitate the scan operation of the string, DI is loaded with 3451. Then the SCASB
instruction is executed. This result in the comparison of character t in AL with the
character A at ES: 3451H. Then automatically DI is incremented to 3452H, so that the
next time through the loop, the SCASB instruction compares the next character in the
string and so on.
However this automatic increment of DI takes place only if the D flag is reset to 0 by
executing the instruction CLD. If the D flag is set to 1 by the instruction STD, DI will be
automatically decremented after the execution of SCASB instruction.
Thus the same scan operation of the string can be achieved by executing SCASB in a
loop 8 times, by initially loading DI with 3458H, and setting D flag to 1.
DKDEPTOFTCE,APSCE
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Example 2: SCASW instruction
The word string Ad, vi, ti, ya starts at an offset address of 3451H in the Extra
segment. The string which contains 8 characters or 4 words is to be scanned for the
occurrence of the word ti.
SCASW instruction performs this comparison, 1 word at a time. This instruction should
be executed a maximum of 4 times in a loop to perform the desired string scan operation.
SCASW instruction expects that the destination string is pointed by ES: DI.
So, to facilitate the scan operation of the string, DI is loaded with 3451. Then the
SCASW instruction is executed. This result in the comparison of word ti in AX with the
word Ad at ES: 3451H. Then automatically DI is incremented to 3453H, so that the
next time through the loop, the SCASW instruction compares the next word in the string
and so on.
However this automatic increment of DI by 2 takes place only if the D flag is reset to 0
by executing the instruction CLD. If the D flag is set to 1 by the instruction STD, DI will
be automatically decremented by 2 after the execution of SCASW instruction.
Thus the same scan operation of the string can be achieved by executing SCASW in a
loop 4 times, by initially loading DI with 3457H, and setting D flag to 1.
It is possible to use SCAS instead if SCASB / SCASW as the mnemonic, but the
assembler is informed about byte/word operation by indicating the name of destination
string in the instruction itself, like SCAS DST. The assembler will code the instruction
for byte operation if DST is declared as bytes (DB) and will code it as word operation if
the DST is declared as words (DW).
If a string is checked for a byte or a word, it is not necessary to execute SCASB /
SCASW instruction in a loop 8 or 4 times respectively, because 8086 provides the REPE
(Repeat While Equal) or REPZ or REPNE or REPNZ prefix facility.
REPNE prefix for SCASB
SCASB instruction will cause SCASB to be repeated as long as the compared bytes are
whenever the compared bytes are equal or CX = 0.
Thus the same scan string operation can be achieved by the execution of the following 2
instructions, instead of repeatedly executing SCASB in a loop.
MOV CX, 08
REPNE SCASB
REPE prefix for SCASB
The REPE SCASB instruction will cause SCASB to be repeated as long as the compared
bytes are equal (Z flag = 1) and CX contents is not yet 0. Thus the repetition is terminated
whenever the compared bytes are not equal or when CX contents become zero.
DKDEPTOFTCE,APSCE
Page25
REPNE prefix for SCASW

SCASW instruction will cause SCASW to be repeated as long as the compared words are
whenever the compared words are equal or CX = 0.
Thus the same scan string operation can be achieved by the execution of the following 2
instructions, instead of repeatedly executing SCASW in a loop.
MOV CX, 04
REPNE SCASW
REPE prefix for SCASW
The REPE SCASW instruction will cause SCASW to be repeated as long as the
compared words are equal (Z flag = 1) and CX contents is not yet 0. Thus the repetition is
terminated whenever the compared words are not equal or when CX contents become
zero.
MOVE STRING INSTRUCTION
It can be a byte or a word operation. The mnemonic for the byte operation is MOVSB,
which stands for move string byte. It has the Opcode A4H. The mnemonic for the word
operation is MOVSW, which stands for move string word and its Opcode is A5H.
This instruction copies the contents of a byte or a word at location DS: SI to a byte or a
word location at ES: DI. It does not affect the flags.
Example 1: MOVSB instruction
The string Nivedita is at an offset of 1231H in the Data Segment. This string of 8
characters is to be moved to another memory area, starting at an offset 3451H is in Extra
Segment.
To move the string of 8 characters, the instruction MOVSB is used to move a byte at a
time. This instruction should be executed 8 times in a loop to perform the desired string
movement. MOVSB instruction expects that the source string is pointed by the DS: SI, or
that the segment base for the source string must be provided in DS and the offset in SI.
Similarly, ES: DI should point to the destination string.
Therefore, SI = 1231H and DI = 3451H. Then the MOVSB instruction is executed. This
result in movement of first byte (character N) of string to offset address 3451H in the
extra segment and SI and DI automatically increment to 1232H and 3452H respectively
so that next time through the loop, the MOVSB instruction moves the next character in
the string, and so on.
Automatic increment of the contents of SI and DI takes place only if Direction flag D = 0.
D is reset to zero by executing the instruction CLD. If the D flag is set to 1 by executing
the instruction STD, the SI and DI registers are automatically decremented after
executing the instruction MOVSB.
DKDEPTOFTCE,APSCE
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Thus the same string movement is achieved by executing MOVSB 8 times in a loop, by
Example 2: MOVSW instruction
The word string Ni,ve, di, ta starts at offset address 1231H in data segment. This
string of 8 characters or 4 words is to be moved to another memory area, starting at an
offset 3451H is in Extra Segment.
To move the string of 4 words, the instruction MOVSW is used to move a word at a time.
This instruction should be executed 4 times in a loop to perform the desired string
movement. MOVSW instruction expects that the source string is pointed by the DS: SI,
or that the segment base for the source string must be provided in DS and the offset in SI.
Similarly, ES: DI should point to the destination string.
Therefore, SI = 1231H and DI = 3451H. Then the MOVSW instruction is executed. This
result in movement of first word (characters Ni) of string to offset address 3451H in the
extra segment and SI and DI automatically increment to 1233H and 3453H respectively
so that next time through the loop, the MOVSW instruction moves the next word in the
string, and so on.
Automatic increment of the contents of SI and DI by 2 takes place only if Direction flag
D = 0. D is reset to zero by executing the instruction CLD. If the D flag is set to 1 by
executing the instruction STD, the SI and DI registers are automatically decremented by
2 after executing the instruction MOVSW.
Thus the same string movement is achieved by executing MOVSW 4 times in a loop, by
It is possible to use MOVS instead if MOVSB / MOVSW as the mnemonic, but the
assembler is informed about byte/word operation by indicating the names of source and
destination strings in the instruction itself, like MOVS SRC,DST. The assembler will
code the instruction for byte operation if SRC and DST are declared as bytes (DB) and
will code it as word operation if the SRC and DST are declared as words (DW).
If a string is to be moved to another memory location, it is not necessary to execute
MOVSB / MOVSW instruction in a loop because 8086 provides the REPE (Repeat
While Equal) or REPZ or REPNE or REPNZ prefix facility.
REP - Repeat prefix for MOVSB
The REP (stands for repeat) prefix is not an instruction by itself and its Opcode is F3H.
The result of execution of this instruction REP MOVSB is as follows:
1. If CX content is 0, proceed with next instruction.
2. Else execute MOVSB instruction.
3. Decrement CX by 1.
4. Go to step 1.
Thus the same string movement can be achieved by the execution of the following 2
instructions, instead of repeatedly executing MOVSB in a loop.
MOV CX, 08
REP MOVSB
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REP - Repeat prefix for MOVSW
The REP (stands for repeat) prefix is not an instruction by itself and its Opcode is F3H.
The result of execution of this instruction REP MOVSW is as follows:
1. If CX content is 0, proceed with next instruction.
2. Else execute MOVSW instruction.
3. Decrement CX by 1.
4. Go to step 1.
Thus the same string movement can be achieved by the execution of the following 2
instructions, instead of repeatedly executing MOVSW in a loop.
MOV CX, 04
REP MOVSW
ALP: Replace every $ in character string with -.
.model small
.data
ascii_strg db abc$njm$87, $
.code
mov ax, @data
mov ds, ax
mov es, ax
loop1:
done:
mov cx, length ascii_strg

mov al, $
lea di, ascii_strg
cld
repnz scas ascii_strg; or repnz scasb
jnz done
mov byte ptr [di-1], -
jmp short loop1
lea dx, ascii_strg
mov ah,9
int 21h
cx=10
al=24h ascii code of $
di pointing to ascii_strg
DF=0
if CX not 0 and ZF=0, repeat;
if CX=0 or ZF=1 come out
if ZF=1, replace $ with
after completion of loop, display
the string in ascii_strg
end
ALP: compare two strings stored in strg1 and strg2 and display if they are same or
not.
.model small
.data
strg1 db be peaceful, $
.model small
.data
strg1 db be peaceful, $
DKDEPTOFTCE,APSCE
Page28

strg2 db talk polite, $
msg1 db both strings are same,$
msg2 db both strings are not same,$
strg2 db talk polite, $

msg1 db both strings are same,$
msg2 db both strings are not same,$
.code
.code
next:
exit:
disp:
mov ax, @data

mov ds, ax
mov es, ax
lea si, strg1
lea di, strg2
mov cx, length strg1
cld
cmps strg1, strg2; or cmpsb
jne exit
loop next
lea dx, msg1
jmp near ptr disp
lea dx, msg2
mov ah, 9
int 21h
mov ah, 4ch
int 21h
next:
exit:
disp:
mov ax, @data

mov ds, ax
mov es, ax
lea si, strg1
lea di, strg2
mov cx, length strg1
cld
repe cmpsb
jne exit
lea dx, msg1
jmp near ptr disp
lea dx, msg2
mov ah, 9
int 21h
mov ah, 4ch
int 21h
end
end
ALP: transfer a given source string to destination string using string instructions
.model small
.stack
.data
x db aruna,$
y db 5 dup(?),$
.model small
.stack
.data
x db aruna,$
y db 5 dup(?),$
.code
.code
back:
mov ax,@data
mov ds,ax
lea si,x
lea di,y
mov cx,0005h
mov al,[si]
mov [di], al
loop back
mov ah,09h
lea dx,y
int 21h
mov ax,@data
mov ds,ax
mov es,ax
lea si,x
lea di,y
mov cx,0005h
cld
rep movsb
mov ah,09h
lea dx,y
int 21h
DKDEPTOFTCE,APSCE
Page29

mov ah,4ch
int 21h
end
mov ah,4ch
int 21h
end
ALP: reverse a string stored in memory location X and display the result
.model small
.data
count equ 05h
x db aruna,$
res db 5 dup (?),$
.model small
.data
count equ 05h
x db aruna,$
res db 5 dup (?),$
.code
.code
back:
mov ax, @data

mov ds, ax
lea si, x
lea di, res
mov cx, count
add di, cx
dec di
mov al,[si]
mov [di], al
inc si
dec di
loop back
mov ah,09h
lea dx,res
int 21h
mov ah, 4ch
int 21h
end
back:
mov ax, @data

mov ds, ax
mov es, ax
lea si, x
lea di, res
mov cx, count
add di, cx
dec di
cld
lodsb
std
stosb
loop back
mov ah,09h
lea dx,res
int 21h
mov ah, 4ch
int 21h
end
ALP: check whether a string is palindrome or not

.model small
.stack
.data
count equ 05h
x db aruna,$
msg1 db palindrome,$
msg2 db not palindrome,$
.code
mov ax, @data
.model small
.data
count equ 05h
x db aruna,$
res db 5 dup (?),$
msg1 db palindrome,$
msg2 db not palindrome,$
.code
mov ax, @data
DKDEPTOFTCE,APSCE
Page30

mov ds, ax
lea si, x
lea di, x+4
mov cx, count
back: mov al, [si]
mov bl, [di]
cmp al, bl
jnz fail
inc si
dec di
loop back
lea dx, msg1
jmp disp
fail: lea dx, msg2
disp: mov ah, 09h
int 21h
mov ah, 4ch
int 21h
end
mov ds, ax
mov es, ax
lea si, x
lea di, res
mov cx, count
add di, cx
dec di
back: cld
lodsb
std
stosb
loop back
cld
lea si, x
lea di, res
mov cx, count
repe cmpsb
jnz fail
lea dx, msg1
jmp disp
fail: lea dx, msg2
disp: mov ah, 09h
int 21h
mov ah, 4ch
int 21h
end
ALP: move a block of data between two overlapping areas. Source location address
is stored in memory location src_addr and destination location address is stored in
memory location dst_addr. The number of data is stored in memory location labeled
by N (using string instructions)
DKDEPTOFTCE,APSCE
Page31
.model small
.data
src_addr dw
dst_addr dw
src db
dst db
.code
mov ax, @data
mov ds, ax
.model small
.data
src_addr dw
dst_addr dw
src db
dst db
.code
mov ax, @data
mov ds, ax
mov es, ax
mov si, src_addr

mov di, dst_addr
mov cx, N
next:
next1:
cmp si, di
ja next1
add si, cx
dec si
add di, cx
dec di
mov al,[si]
mov [di], al
dec si
dec di
loop next
jmp exit
mov al,[si]
mov [di], al
mov si, src_addr

mov di, dst_addr
mov cx, N
next:
cld
cmp si, di
ja next
std
add si, cx
dec si
add di, cx
dec di
movsb
loop next
mov ah, 4ch
int 21h
DKDEPTOFTCE,APSCE
Page32

inc si
inc di
loop next1
exit:
end
mov ah, 4ch

int 21h
end
ALP: scan 80 characters of a string which ends with a blank. If string consists of
only blank characters, a branch is taken to NOT_FOUND location; otherwise
beginning with the 1st non blank character, a substring of LINE of up to 31
characters is moved to SYMBOL until a blank is found or 31 characters have been
moved.
.model small
.data
line db
abcdefghijklmnopqrstuvwxyzabcse
,$
symbol db 31 dup(?), $
msg db not_found, $
.code
mov ax, @data
mov ds, ax
mov es, ax
lea di, line
mov cx, 80
mov al, 20h; ascii code for blank
cld
next:
scas line
loope next
je not_found
mov si, di
dec si
lea di, symbol
mov cx, 31
jmp short same
fill:
stos symbol; mem loc=al=char
same:
lods line ; al=char
cmp al, 20h
loopne fill
jmp exit
not_found: lea dx, msg
mov ah, 9
int 21h
DKDEPTOFTCE,APSCE
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exit:
mov ah, 4ch

int 21h
end
ALP: Searches an array table consisting of 20 byte strings until the 1st 8 bytes of an
element are matched by the string beginning at symbol. The offset and segment
address of table and symbol are in tablept and symbolpt.
.model small
.data
tablept dw . ; offset & segment address of table
symbolpt dw
; offset & segment address of symbol
table_size dw . ; no. of entries in table
table db .,$,.,$,.
symbol db .,$
msg1 db match found,$
msg2 db match not found,$
.code
mov ax, @data
mov ds, ax
les di, tablept
mov dx, di
lds si, symbolpt
mov bx, table_size
cld
loop1:
mov cx, 8
repe cmpsb
je found
add dx, 20
mov di, dx
lea si, symbol
dec bx
jne loop1
not_found: lea dx, msg2
jmp disp
found:
disp:
lea dx, msg1

mov ah, 9
int 21h
.exit
end
DKDEPTOFTCE,APSCE
Page34

ARITHMETIC INSTRUCTIONS
These can perform addition, subtraction, multiplication, and division operations on 8 or
16 bit quantities which can be signed or unsigned numbers.
1. Add group of instructions
a. add contents of 2 registers with or without carry
b. add contents of a register and a memory location with or without carry
c. add immediate data to a register or a memory location with or without carry
d. increment contents of a register or memory location
e. to perform decimal adjust after addition
f. to perform ASCII adjust after addition
2. Subtract group of instructions
a. subtract contents of 2 registers with or without borrow
b. subtract contents of a register and a memory location with or without borrow
c. subtract immediate data to a register or a memory location with or without borrow
d. decrement contents of a register or memory location
e. to perform decimal adjust after subtract
f. to perform ASCII adjust after subtraction
3. Negate instruction
4. Compare instructions
a. compare the contents of 2 registers
b. compare contents of a register and a memory location
c. compare immediate data with the contents of a register or a memory location
5. Data size conversion instructions
a. convert byte to word
b. convert word to double word
6. Multiply instructions
a. perform unsigned multiplication
b. perform signed multiplication
c. perform ASCII adjust after multiplication
7. Division instructions
a. perform unsigned division
b. perform signed division
c. perform ASCII adjust before division
Arithmetic involving one word operands is called single precision arithmetic, involving 2
words is called double precision arithmetic and multiple words are called multiprecision
data.
A word is treated as non-negative in unsigned numbers and as 2s complement number
for signed numbers.
ALU executes all additions as if the numbers are unsigned. For signed number
operations, the carry out should be taken care of.
DKDEPTOFTCE,APSCE
Page35

ADDITION & SUBTRACTION INSTRUCTIONS
ADD, SUBTRACT INSTRUCTIONS (ADD, ADC, SUB, SBB, INC, DEC)
1. Add group of instructions
a. add contents of 2 registers with or without carry
b. add contents of a register and a memory location with or without carry
c. add immediate data to a register or a memory location with or without carry
d. increment contents of a register or memory location
e. to perform decimal adjust after addition
f. to perform ASCII adjust after addition
2. Subtract group of instructions
a. subtract contents of 2 registers with or without borrow
b. subtract contents of a register and a memory location with or without borrow
c. subtract immediate data to a register or a memory location with or without borrow
d. decrement contents of a register or memory location
e. to perform decimal adjust after subtract
f. to perform ASCII adjust after subtraction
ADD dst, src
ADC dst, src
SUB dst, src
SBB dst, src
INC dst
DEC dst
ADD AX, BX
ADD DS:0F246H[BP], DX
ADD CX, 0083H
ADC CL, 43H
ADC AX, 0083H
ADC AL, 83H
INC WORD PTR DS:[BP]
INC DX
INC CL
Dst dst + src

Dst dst + src+CF
Dst dst - src
Dst dst src-CF
dst dst+1
dst dst-1
SUB AX, BX
SUB [DI], DX
SUB CX, 0083H
SBB CL, 43H
SBB AX, 0083H
SBB AL, 83H
DEC WORD PTR DS:[BP]
DEC DX
DEC CL
PERFORM DECIMAL ADJUST AFTER ADDITION (DAA INSTRTUCTION)

If two decimal numbers 38 & 45 are added they will be represented in packed BCD as
00111000 & 01000101. The addition results in 01111101. If this result is interpreted as
a packed BCD number the answer is incorrect and illegal because 1101 is an illegal BCD
number. This is where the DAA instruction proves to be useful. All that is required to be
done is to add the BCD numbers and store the result in AL, and then execute DAA
instruction. DAA stands for Decimal Adjust After Addition. Opcode for this instruction
is 27H.
DKDEPTOFTCE,APSCE
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The working of DAA instruction depends on the contents of AL register in effect, it adds
00H, 06H, 60H, or 66H to a AL so that correct packed BCD answer is obtained in AL.
If the LS Hex digit in AL is <=9 and auxiliary carry flag is 0, the LS Hex digit value will
not be altered.
If the LS Hex digit is >9 or if auxiliary carry flag is set to 1, it adds 6 to the LS Hex digit
of AL and increments the MS Hex digit if this addition results in a carry to the MS digit
position. In this process, the carry flag will set to 1 if the MS Hex digit was incremented
from F to 0.
Now, if the MS Hex digit <= 9 and carry flag is 0 the MS Hex digit will not be altered
and carry flag is reset to 0
If the MS Hex digit >9 or if carry flag is set to 1 it adds 6 to the MS Hex digit of AL and
sets carry flag to 1.
Example 1:
45 BCD + 38 BCD
The result 7DH is stored in AL. C Flag = 0, A Flag = 0. But as D is invalid BCD code,
the DAA instruction adds 06H to AL. Thus we get 83H in AL which will now be
interpreted as 83BCD, the correct sum of 45 & 37
Example 2:
63 BCD + 88 BCD = EBH
The DAA instruction Adds 66H to AL. Thus we get 51H in AL and C Flat will be set to
1, which is the correct sum of 63 & 88.
PERFORM ASCII ADJUST AFTER ADDITION (AAA INSTRTUCTION)
The data that is entered from the key board is in ASCII format. When two characters are
added, to get the result in the unpacked BCD format, the AAA instruction is used. It
stands for ASCII Adjust After Addition. Opcode for this instruction is 37H.
The working of AAA instruction depends on the contents of AL register. It always
makes the MS Hex digit of the AL as 0. If the LS Hex digit in AL <= 9 and Auxiliary
carry flag is 0, the LS Hex digit value will not be altered.
If the LS Hex digit is > 9 or the aux carry flag is set to 1, it does the following
1. Adds 6 to the LS Hex digit position of AL
2. Carry and Aux Carry Flags are set to 1 State
3. Increment the contents of AH.
Example
AL=37H, the ASCII for 7, BL=38H, the ASCII code for 8
ADD AL, BL
DKDEPTOFTCE,APSCE
Page37

Gets 6FH in AL and let AH contain 00H. To get the correct answer, AAA instruction is
executed. Since F>9, it add 6 to the LS Hex digit, make MS Hex digit as 0 and
increments AH. This we get correct unpacked BCD result of 0105 in AH & AL.
PERFORM DECIMAL ADJUST AFTER SUBTRACTION (DAS INSTRTUCTION)
If two decimal numbers 45 & 38 are subtracted they will be represented in packed BCD
as 01000101 & 00111000. This results in 00001101. If this result is interpreted as a
packed BCD number the answer is incorrect and illegal because 1101 is an illegal BCD
number. This is where the DAS instruction proves to be useful. All that is required to be
done is to subtract the BCD numbers and store the result in AL, and then execute DAS
instruction. DAS stands for Decimal Adjust After Subtraction. Opcode for this
instruction is 2FH.
The working of DAS instruction depends on the contents of AL register in effect, it
subtracts 00H, 06H, 60H, or 66H from AL so that correct packed BCD answer is
obtained in AL.
If the LS Hex digit in AL is <=9 and auxiliary carry flag is 0, the LS Hex digit value will
not be altered.
If the LS Hex digit is >9 or if auxiliary carry flag is set to 1, it subtracts 6 from the LS
Hex digit of AL.
Now, if the MS Hex digit <= 9 and carry flag is 0 the MS Hex digit will not be altered
and carry flag is reset to 0
If the MS Hex digit >9 or if carry flag is set to 1 it subtracts 6 from the MS Hex digit of
AL and sets carry flag to 1. In such a case, the result is interpreted to be negative and the
value in AL represents 10s complement of the absolute value of correct difference.
Example 1:
45 BCD - 38 BCD
The result 0DH is stored in AL. C Flag = 0, A Flag = 1. But as D is invalid BCD code,
the DAS instruction subtracts 06H from AL. Thus we get 07H in AL which will now be
interpreted as 07BCD, the correct difference of 45 & 38
Example 2:
63 BCD - 88 BCD = DBH
The DAS instruction subtracts 66H from AL. Thus we get 75H in AL and C Flag will be
set to 1, which means result is negative. 75BCD is 10s complement of 25 BCD which is
the magnitude of the correct difference.
DKDEPTOFTCE,APSCE
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PERFORM ASCII ADJUST AFTER SUBTRACTION (AAS INSTRTUCTION)
The data that is entered from the key board is in ASCII format. When two characters are
subtracted, to get the result in the unpacked BCD format, the AAS instruction is used. It
stands for ASCII Adjust After Subtraction. Opcode for this instruction is 3FH.
The working of AAS instruction depends on the contents of AL register. It always makes
the MS Hex digit of the AL as 0. If the LS Hex digit in AL <= 9 and Auxiliary carry flag
is 0, the LS Hex digit value will not be altered.
If the LS Hex digit is > 9 or the aux carry flag is set to 1, it does the following
1. Subtracts 6 to the LS Hex digit position of AL
2. Carry and Aux Carry Flags are set to 1 State
3. Decrements the contents of AH.
In such a case the results is interpreted to be negative, and the value in LS Hex position
of AL represents 10s complement of the absolute value of correct difference.
Example
AL=35H, the ASCII for 5, BL=38H, the ASCII code for 8
SUB AL, BL
Gets FDH in AL, C Flag=1 & A Flag =1 and let AH contain 00H. To get the correct
answer, AAS instruction is executed. Since A Flag =1, it subtracts 6 from the LS Hex
digit, make MS Hex digit as 0 and decrements AH, so that AX contained FF07H. As C
Flag = 1, the result is negative. 7BCD is the 10s complement of 3BCD, which is the
magnitude of the correct difference.
NEGATE INSTRUCTION
This instruction negates the contents of a register or a memory location. That is, a
positive number will be converted to a negative number of the same magnitude and vice
versa. In effect, it replaces the number with its 2s complement.
It can work on a byte or a word data. All the flags are affected depending on the result.
Overflow flag is set to 1 if 80H or 8000H is negated.
The template of the instruction is 1111011W MOD-011-R/M. The mnemonic for this
instruction is NEG.
Example 1: NEG WORD PTR DS: 0F246H [BP]
This instruction negates the contents of a word location whose effective address is given
as the sum of the 16 bit offset value F246H and the contents of BP register. The physical
address is generated using DS as the segment register.
Before:
After:
BP DS: F356
0100
1230
0100
EDD0
DKDEPTOFTCE,APSCE
Page39

Example 2: NEG CL
This instruction negates the contents of CL register. It is a byte operation.
CL
Before:
60
After:
A0
Example 3: NEG CX
This instruction negates the contents of CX register. It is a word operation.
Before:
After:
CX
2360
DCA0
COMPARE INSTRUCTIONS
In this group there are instructions to
a. compare the contents of 2 registers
b. compare contents of a register and a memory location
c. compare immediate data with the contents of a register or a memory location
Compare the contents of 2 registers or a register and a memory location: A compare
instruction compares the two operands, and affects the status flags values depending on
the result of comparison. The compare instruction actually computes the value of
operand_1 minus operand_2. The original values of the operands are not changed. The
result is stored in a register which is not accessible to the programmer. Based on the
result, the flags are affected.
Template for this instruction is 001110DW MOD-REG-R/M. The mnemonic for this
instruction is CMP.
Example 1: CMP AX, BX
This instruction compares the contents of AX and BX registers. After the compare
operation, the status flags are affected depending on the result.
BX
FLAGS
AX
Before: 122F 70F7
After: 122F 70F7 Z=0,S=1,P=0,C=1,A=0,O=0
In the above example, the result of comparison is 122FH 70F7H = A138H. The result is
non zero, negative, number of 1s in the result are odd, contents of AX are less than BX
and a borrow is needed to perform subtraction, no borrow is required during subtraction
of LS hex digits. The overflow flag is reset because the subtraction of 2 positive numbers
never results in an overflow.
Example 2: CMP DS: 0F246H [BP], DX
This instruction compares the contents of a memory location whose effective address is
given as the sum of the 16 bit offset value F246H and the contents of BP register with
DX register contents. The physical address is generated using DS as segment register.
FLAGS
BP DS:F346 DX
DKDEPTOFTCE,APSCE
Page40

Before:
After:
0100
0100
122F
122F
70F7
70F7 Z=0,S=1,P=0,C=1,A=0,O=0
Compare immediate data with the contents of a register or a memory location: The
template for this instruction is 100000SW MOD-111-R/M. The S bit stands for sign
extension. When W=0 (byte), the S bit is also 0. If W = 1 (word), the S bit must be a 1
only if the immediate data is <= 7FH. In such a case, the assembler will generate only 1
byte code for the immediate data. However, during execution, the 1 byte data will be sign
extended to make it a 2 byte operand. If the immediate data is >7FH, the S bit must be 0,
and the assembler generates a 2 byte code for the immediate data.
Example 1: CMP CX, 83H
It is a word operation (W = 1) with immediate data > 7FH, S bit is 0. After the compare
operation the status flags are affected depending on the result.
Example 2: CMP CL, 83H
It is a byte operation, and the S bit is 0. After the compare operation the status flags are
affected depending on the result.
Example 3: CMP CX, 43H
It is a word operation (W = 1) with immediate data <= 7FH, S bit is 1. After the compare
operation the status flags are affected depending on the result.
Compare Accumulator contents with immediate data: template for this instruction is
0011110W. There are only 2 instructions in this category. The assembler generates 1 byte
or 2 byte code for the immediate data depending on whether it is a byte or a word
operation. The accumulator contents are compared with the immediate data and the status
flags are affected depending on the result.
Example 1: CMP AX, 83H
It is a word operation. After the compare operation the status flags are affected depending
on the result.
Example 2: CMP AL, 83H
It is a byte operation. After the compare operation the status flags are affected depending
on the result.
DATA SIZE CONVERSION INSTRUCTIONS
In this category there are instructions to convert the byte in AL to sign extended word in
AX, and convert the word in AX to sign extended double word in DX & AX. These
instructions do not affect the flags.
CONVERT BYTE TO WORD
To convert a byte into a word, without changing its value sign extension is done. For a
positive byte valued number (MS bit=0), sign extension is achieved by making the MS
byte of the word as 00H and LS byte of the word as the byte to be converted. For a
negative byte valued number (MS bit=1), sign extension is achieved by making the MS
byte of the word as FFH and LS byte of the word as the byte to be converted. Only AL
DKDEPTOFTCE,APSCE
Page41

contents can be converted to its equivalent word using CBW instruction. CBW stands for
Convert Byte to Word. AH will have the MS byte of the converted result. Opcode for
this instruction is 98H.
Example 1:
Before:
After :
AH
34H
00H
AL
02H
02h
Thus after CWB instruction we get 0002H in AX, which is the sign extended value of
02H in AL.
Example 2
AH
AL
Before: 34H 92H
After :
FFH 92H
Thus after CWB instruction we get FF92H IN AX, which is the sign extended value of
92H in AL.
CONVERT WORD TO DOUBLE WORD
To convert a word into a double word, without changing its value sign extension is done.
For a positive word valued number (MS bit=0), sign extension is achieved by making the
MS word of the double word as 0000H and LS word of the double word as the word to be
converted. For a negative word valued number (MS bit=1), sign extension is achieved by
making the MS word of the double word as FFFFH and LS word of the double word as
the word to be converted. Only AX contents can be converted to its equivalent double
word using CBD instruction.
CBD stands for Convert Word to Double Word. DX will have the MS word of the
converted result. Opcode for this instruction is 99H.
Example 1:
Before:
After :
DX
1234G
0000H
AX
5678H
5678H
Thus after CWD instruction we get 00005678H in register pair DX-AX, which is the sign
extended value of 5678H in AX.
Example 2
DX
AX
Before:
1234H
9678H
After :
FFFFH 9678H
Thus after CWD instruction we get FFFF9678H in register pair DX-AX, which is the
sign extended value of 5678H in AX.
DKDEPTOFTCE,APSCE
Page42

MULTIPLY INSTRUCTIONS
8086 provides instructions to perform multiplication of 2 unsigned numbers or 2 signed
numbers. The numbers being multiplied can be of word or byte sized.
PERFORM UNSIGNED MULTIPLICATION: MUL is the mnemonic for the
instruction to perform unsigned multiplication. Template for this instruction is
1111011W MOD-100-R/M.
For multiplication of byte valued numbers, one operand is implied to be in AL, and the
other is specified to be in a byte register or a byte location in memory. The 16 bit product
will be stored in AX.
For multiplication of word valued numbers one operand is implied to be in AX and the
other is specified to be in a word register or a word location in memory. The 32 bit
product will be stored in the register pair DX-AX.
Carry and overflow flags are set to 1 if AH <> 00H after 8 bit multiplication or if DX
<>0000H after 16 bit multiplication. Values of other flags are undefined after
multiplication.
Example 1: MUL WORD PTR DS: 0F246H [BP]
This instruction multiplies the contents of a word location whose effective address is
given as the sum of 16 bit offset value F246H and the contents of BP register with AX.
The physical address is generated using DS as the segment register. The result is stored
in DX-AX.
DS:F346
AX
DX
BP
Before: 0100
0030
9180 2345
After:
0100
0030
4800 001B
Thus the unsigned product of 0030H & 9180H is obtained in DX-AX as 001B4800H
Example 2: MUL CL
Before:
After:
CL
60
60
AL
A0
00
AH
45
3C
Thus the unsigned product of 60H & A0H is obtained in AX as 3C00H

Example 3: MUL CX
Before:
After:
CX
9180
9180
AX
0030
4800
DX
4567
0001B
Thus the unsigned product of 0030H & 9180H is obtained in DX-AX as 001B4800H
DKDEPTOFTCE,APSCE
Page43

PERFORM SIGNED MULTIPLICATION: IMUL is the mnemonic for the instruction
to perform signed multiplication. Template for this instruction is 1111011W MOD-101R/M. For multiplication of byte valued numbers, one operand is implied to be in AL and
the other is specified to be in byte register or a byte location in memory. The 16 bit
product will be stored in AX.
For multiplication of word valued numbers, one operand is implied to be in AX, and the
other is specified to be in a world register or a word location in memory. The 32 bit
product will be stored in the register pair DX-AX.
Carry and Overflow flags are set to 1 if AH<>00H or FFH after 8 bit multiplication, or if
DX <>0000H or FFFFH after 16 bit multiplication. Values of other flags are undefined
after multiplication.
Example 1: IMUL WORD PTR DS: 0F246H [BP]
This instruction multiplies the contents of a word location whose effective address is
given as the sum of 16 bit offset value F246H and the contents of BP register with AX.
The physical address is generated using DS as the segment register. The result is stored
in DX-AX.
BP
DS:F346
AX
DX
Before: 0100
0030
9180
2345
After:
0100
0030
4800 FFEB
Thus the signed product of 0030H (=+30H) &
as FFEB4800H (=-0014B800H).
Example 2: IMUL CL
CL
Before:
60
After:
60
9180H (=-6E80H) is obtained in DX-AX

AL
A0
00
AH
45
DC
Thus the signed product of 60H (+60H) & A0H (=-60H) is obtained in AX as DC00H (=2400H)
Example 3: IMUL CX
Before:
After:
CX
9180
9180
AX
0030
4800
DX
4567
FFEB
Thus the signed product of 0030H (=+30H) & 9180H (=-6E80H) is obtained in DX-AX
as FFEB4800H (=-0014B800H).
DKDEPTOFTCE,APSCE
Page44

PERFORM ASCII ADJUST AFTER MULTIPLICATION (AAM INSTRTUCTION)
During the execution of AAM instruction, contents of AL are divided by 1010 and
quotient is stored in AH and remainder is stored in AL registers. It converts binary to
unpacked BCD.
AL=3510=23h, Execution of AAM instruction
AL/10=23h/0Ah, AH=quotient=03, AL=remainder=05
A) 2 3 ( 3
1E
______
05
______
AX= 03 05 ( unpacked BCD of binary 23h=3510)
The data that is entered from a key board is in ASCII format. If 9 and 8 are entered
on the key board, its representation in side the computer will be 39H & 38H. If
multiplication of the characters 9 & 8is performed, to get the result as 0702 in
unpacked BCD format AAM instruction is used, which stands for ASCII ADJUST
AFTER MULTIPLICATION. Opcode for this instruction is D40AH. The working of
an AAM instruction depends on the contents of AL register. Suppose AL content is 3FH.
It is 63 BCD. It can be represented in unpacked BCD as 0603 BCD. All that AAM
instruction does is to convert 3FH in AL to 0603 in AX. The result in AX does not the
ASCII characters 6 & 3. It only represents unpacked BCD numbers.
Example
Let AL contain 39H, the ASCII code for 9, and BL contains 37H, the ASCII code for
7. If we subtract from AL & BL, the immediate value 30H, we get 09H in AL and 07H
in BL. If we now multiply these unpacked BCD numbers in AL & BL using MUL BL,
we get 00 in AH & 3FH in AL. Now execution of AAM results in AH getting 06 and AL
getting 03. This 0603 is interpreted as the correct unpacked BCD product of the
unpacked BCD number 09 & 07. If the result of multiplication should be represented as
ASCII characters 6 & 3, all that is needed is to add 3030H to AX.
After the multiplication is performed on unpacked BCD numbers, we have to convert the
binary result to 2 digit unpacked BCD using AAM instruction.
DIVIDE INSTRUCTIONS
8086 provides instructions to perform division of 2 unsigned numbers or 2 signed
numbers. It is integer division only. The divisor can be of byte size or word size. The
dividend is always double the size of the divisor.
PERFORM UNSIGNED DIVISION: DIV is the mnemonic of the instruction to perform
unsigned division. Template for this instruction is 1111011W MOD-110-R/M.
For byte valued divisor, the dividend is implied to be in AX, and the divisor is specified
to be in a byte register or a byte location in the memory. The 8 bit quotient will be stored
in AL and the 8 bit remainder in AH. If the divisor is 0, or if the correct quotient is larger
than FFH, the 8086 branches to an interrupt service subroutine, to take appropriate action
to deal with this error. It could be an error message display on the terminal.
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For word valued divisor, the dividend is implied to be in DX-AX, and the divisor is
specified to be in a word register or a word location in the memory. The 16 bit quotient
will be stored in AX and the 16 bit remainder in DX. If the divisor is 0, or if the correct
quotient is larger than FFFFH, the 8086 branches to an interrupt service subroutine, to
take appropriate action to deal with this error. It could be an error message display on the
terminal.
Flags are undefined after the execution of DIV instruction.
Example 1: DIV WORD PTR DS: 0F246H [BP]
This instruction divides the contents of register pair DX-AX by the contents of a word
location whose effective address is given as the sum of 16 bit offset value F246H and
the contents of BP register. The physical address is generated using DS as the segment
register. The quotient is stored in AX and the remainder in DX.
Before:
After:
BP
0100
0100
DS:F346
0030
0030
AX
9192
0308
DX
0000
0012
Thus after the unsigned division of 00009192H by 0030H, the quotient is obtained in AX
as 0308H and the remainder in DX as 0012H.
Example 2: DIV CL
CL AL AH
Before:
60
A0
45
After:
60
B9
40
Thus after the unsigned division of 45A0H by 60H, the quotient is obtained in AL as
B9H and the remainder in AH as 40H.
Example 3: DIV CX
CX
AX
DX
Before: 0030 9192
0000
After:
0030 0308
0012
Thus after the unsigned division of 00009192H by 0030H, the quotient is obtained in AX
as 0308H and the remainder in DX as 0012H.
PERFORM SIGNED DIVISION: IDIV is the mnemonic of the instruction to perform
signed division. Template for this instruction is 1111011W MOD-111-R/M.
For byte valued divisor, the dividend is implied to be in AX, and the divisor is specified
to be in a byte register or a byte location in the memory. The 8 bit quotient will be stored
in AL and the 8 bit remainder in AH. If the divisor is 0, or if the correct quotient is more
positive than 7FH, or more negative than 80H, the 8086 branches to an interrupt service
subroutine, to take appropriate action to deal with this error. It could be an error message
display on the terminal.
For word valued divisor, the dividend is implied to be in DX-AX, and the divisor is
specified to be in a word register or a word location in the memory. The 16 bit quotient
will be stored in AX and the 16 bit remainder in DX. If the divisor is 0, or if the correct
quotient is more positive than 7FFFH, or more negative than 8000H, the 8086 branches
DKDEPTOFTCE,APSCE
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to an interrupt service subroutine, to take appropriate action to deal with this error. It
could be an error message display on the terminal.
Flags are undefined after the execution of IDIV instruction.
Example 1: IDIV WORD PTR DS: 0F246H [BP]
This instruction divides the contents of register pair DX-AX by the contents of a word
location whose effective address is given as the sum of 16 bit offset value F246H and the
contents of BP register. The physical address is generated using DS as the segment
register. The quotient is stored in AX and the remainder in DX.
Before:
After:
BP
0100
0100
DS:F346
FFB0
FFB0
AX
0FE0
0300
DX
FFFF
FFE0
Thus after the signed division of FFFF0FE0H (=-0000F020H) by FFB0H (-0050H), the
quotient is obtained in AX as 0300H and the remainder in DX as FFE0H (-0020H).
Example 2: IDIV CL
CL AL AH
Before:
30
EE
E7
After:
30
80
EE
Thus after the signed division of E7EEH (=-1812H) by 30H, the quotient is obtained in
AL as 80H (=-80H) and the remainder in AH as EEH (-12H).
Example 3: IDIV CX
CX
AX
DX
Before: FFB0 0FE0
FFFF
After:
FFB0 0300
FFE0
Thus after the signed division of FFFF0FE0H (=-0000F020H) by FFB0H (-0050H), the
quotient is obtained in AX as 0300H and the remainder in DX as FFE0H (-0020H).
PERFORM ASCII ADJUSTMENT BEFORE DIVISION (AAD INSTRTUCTION)

During the execution of AAD instruction, contents of AH is multiplied by 1010 and added
to the contents of AL. Then AH is made 00h. It converts unpacked BCD to binary.
AX= 03 05
Execution of AAD instruction
AH X 1010 + AL=03 X 0A + 05=1E + 05= 23h ( binary of 3510)
The data that is entered from a key board is in ASCII format. If 6 and 2 are entered
on the key board, its representation in side the computer will be 36H & 32H. If division
of the characters 62 by 8is performed, to get the quotient as 07 and remainder as 06 in
unpacked BCD format AAD instruction is used, which stands for ASCII ADJUST
BEFORE DIVISION. Opcode for this instruction is D50AH. The working of an AAD
DKDEPTOFTCE,APSCE
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instruction depends on the contents of AX register. Suppose AX content is 0602H. It is
62 in BCD. All that AAD instruction does is to convert 0602H in AX to 003E in AX. In
effect, AAD instruction converts the 2 digit unpacked BCD in AX to the equivalent
binary in AX.
Example
Let AH contain 36H, the ASCII code for 6, and AL contains 32H, the ASCII code for
2. If we subtract from AX, the immediate value 3030H, we get 06H in AH and 02H in
AL. Now, execution of AAD results in AX getting the value 003EH.
Suppose CL contains 38H, the ASCII code for 8. If DIV CL is executed, quotient 07H
will be stored in AL and remainder 06H in AH. 3030H is to be added to the result to get
the result in the form of ASCII characters 6 and 7.
Before the division is performed on unpacked BCD numbers, we have to convert the 2
digit unpacked BCD to binary using AAD instruction.
ALP: Add contents of location x and y, add 24 to the sum, subtract the contents of
location z, and store the result in w. All variables x, y, z are single precision data.
Modify the program for double precision inputs w x + y + 24 z
double precision inputs
.model small
.data
x dw 1234h, 7684h
y dw 4567h, 5409h
z dw 6587h, 5689h
w dw 2 dup (?)
.code
mov ax, @data
mov ds, ax
mov ax, x
add ax, y
mov dx, x+2
adc dx, y+2
add ax, 24
adc dx, 0
sub ax, z
sub dx, z+2
mov w, ax
mov w+2, dx
mov ah, 4ch
int 21h
end
ALP: sum of 2 double words. Lower order words of the operands and the sum are
in dp1, dp2 and dpsum. Corresponding higher order words are in dp1+2, dp2+2,
and dpsum+2.
.model small
.data
single precision data
.model small
.data
x dw 1234h
y dw 4567h
z dw 6587h
w dw ?
.code
mov ax, @data
mov ds, ax
mov ax, x
add ax, y
add ax, 24
sub ax, z
mov w, ax
mov ah, 4ch
int 21h
end
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dp1 dw 1234h, 7684h; no.=76841234h
dp2 dw 9087h, 3475h; no.=34759087h
dpsum dw 2 dup (?)
.code
.startup
mov ax, dp1
add ax, dp2
mov dpsum, ax
mov ax, dp1+2
adc ax, dp2+2
mov dpsum+2, ax
.exit
end
ALP: bcd3=bcd1+bcd2 (packed BCD addition) bcd1 and bcd2 are defined as byte
variables that store 4 digit 10s complement numbers with most significant digits in
the higher order bytes of their words.
18|34
00011000 00110100
27|89
00100111 10001001
------------------------------------46|23
01000000 10111101
0110 01100110
------------------------------01000110 00100011
.model small
.data
bcd1 db 34, 18
bcd2 db 89, 27
bcd3 dw ?
.code
.startup
AL
CF
AF
mov al, bcd1
34
------add al, bcd2
BD
0
0
daa
23
1
*
mov bcd3, al
23
1
*
mov al, bcd1+1
18
1
*
adc al, bcd2+1
40
0
1
daa
46
0
*
mov bcd3+1, al
46
0
*
.exit
end
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ALP: bcd3=bcd1-bcd2 (packed BCD subtraction). bcd1 and bcd2 are defined as
byte variables that store 4 digit 10s complement numbers with most significant
digits in the higher order bytes of their words.
12|34
00010010 0 0110100
46|12
01000110 00010010
-------------------------- ---------------------------------------66|22
11001100 00100010
=-3378
01100110
-----------------------------------------01100110 00100010
As CF=1, result is ve, find 10s complement.
.model small
.data
bcd1 db 34, 18
bcd2 db 89, 27
bcd3 dw ?
.code
.startup
mov al, bcd1
sub al, bcd2
das
mov bcd3, al
mov al, bcd1+1
sbb al, bcd2+1
das
mov bcd3+1, al
AL
34
22
22
22
12
CC
66
66
CF
---0
0
0
0
1
1
1
AF
---0
*
*
*
1
*
*
.exit
End
ALP: unpacked BCD addition & subtraction (ascii codes) of 2 digit 10s
complement numbers. (DX)= up1+up2-up3
.model small
.data
up1 db 03, 05
up2 db 02, 08
up3 db 04, 03
.code
.startup
mov al, up1
add al, up2
aaa
mov dl, al
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mov al, up1+1
adc al, up2+1
aaa
xchg al, dl
sub al, up3
aas
xchg al, dl
sbb al, up3+1
aas
mov dh, al
.exit
end
ALP: signed mixed mode arithmetic with 2 different precisions: add single precision
number in bx to double precision number in dp & dp+2, put the result back in same
memory location
.model small
.data
num dw 1234h
dp dw 3024h, 6745h
; no.=67453024h
.code
mov ax, @data
mov ds, ax
mov bx, num
mov ax, bx
cwd
add dp, ax
adc dp+2, dx
.exit
end
ALP: multiplication of double precision numbers (32 bit numbers)
a216 + b
c216 + d
----------------------------------bd
ad216
32
bc216
ac2
-----------------------------------
mcand (20)
mcand+2 (216)
mplier (20)
mplier+2 (216)
--------------------------------------------------232
216
20
264
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prod+6
prod+4
prod+2 prod
dx-------------ax
(mcand)(mplier)
dx------------ax
(mcand+2)(mplier)
dx------------ax
(mcand)(mplier+2)
dx-----------ax
(mcand+2)(mplier+2)
-----------------------------------------------.model small
.data
mcand dw 1234h, 2345h
; (mcand=23451234)
mplier dw 3245h, 2098h
; (mplier=20983245)
prod dw 4 dup (00)
.code
.startup
mov ax, mcand
mul mplier
mov prod, ax
add prod+2, dx
mov ax, mcand+2
mul mplier
add prod+2, ax
adc prod+4, dx
mov ax, mcand
mul mplier+2
add prod+2, ax
adc prod+4, dx
mov ax, mcand+2
mul mplier+2
add prod+4, ax
adc prod+6, dx
.exit
end
ALP: unpacked BCD multiplication (2 digit). a, b, c are defined as byte variables

that store 2 digit 10s complement numbers.
.model small
.data
a db 4, 3 ; 34
b db 6, 5 ; 56
c db 4 dup (?) ; 1904
c0 db 3 dup (?)
c1 db 3 dup (?)
.code
.startup
mov al, a ; al=4
mul b
; ax= 4 X 6= 0018h
aam
; ax= 02 04 (unpacked BCD)
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mov word ptr c0, ax
; c0+1: c0=02 04
mov al, a+1
; al=03
mul b
; ax= 3 X 6 = 0012h
aam
; ax= 01 08 (unpacked BCD)
add al, c0+1 ; al= 08+02= 0Ah, ah=01
aaa
; ax= 02 00
mov word ptr c0+1, ax ; c0+2: c0+1=02 00
mov al, a; al= 4
mul b+1; ax= 4 X 5=00 14h
aam; ax= 02 00 (unpacked BCD)
mov word ptr c1, ax; c1+1: c1=02 00
mov al, a+1; al= 3
mul b+1; ax= 3 X 5= 000Fh
aam; ax= 01 05 (unpacked BCD)
add al, c1+1; al=07, ah= 01
aaa, ax= 01 07
mov word ptr c1+1, ax; c1+2: c1+1= 01 07
mov al, c0; al=4
mov c, al; c=4
mov al, co+1; al=00
add al, c1; al=00+00=00
aaa
mov c+1, al; c+1=00
mov al, c0+2; al=02
adc al, c1+1; al=09
aaa
mov c+2, al; c+2=09
mov al, 0
adc al, c1+2; al=01
aaa
mov c+3, al
.exit
end
c0+2 c0+1 c0
02 00 04
c1+2 c1+1 c1
01 07 00
___________________
c+3 c+2 c+1 c
01 09
00 04
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ALP: Division of double precision nos.
Dividend= b232+c216+d
Divisor= a
a| b232+c216+d | q2232+q1216+q0
r2232+c216
------------- ------------------------------------
r1216+d
-------------------------------r0
b/a
r2232+c216 /a
r1216+d /a
Quotient
q2
q1
q0
remainder
r2
r1
r0
ALP: (v-(x.y+z-540))/x: single precision data
.model small
.data
x dw 1234h
y dw 2099h
z dw 3457h
v dw 1098h
res dw 2 dup (00)
.code
.startup
mov ax,x
imul y; dx-ax
mov res, ax
add res+2, dx
mov ax, z
cwd; dx-ax
add res, ax
adc res+2, dx
sub res, 540
sbb res+2, 0
mov ax, v
cwd; dx-ax
sub ax, res
sbb dx, res+2
idiv x; quo=ax, rem=dx
mov res, ax
mov res+2, dx
.exit
end
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ALP: Unpacked BCD division: 2 digit no. (B+1, B) / 1 digit no. (A), quotient (C),
remainder (r)
.model small
.data
B db 03, 05
A db 03
C db ?
R db ?
.code
mov ax, @data
mov ds, ax
mov ah, 0
mov al, B+1 ; al=05
div A ; 0005/03= ah=rem=02, al= quo=01
mov cl, al; cl=01
mov al, B; al=03
aad; ax= 02 03=> 17h
div A; 0017/03= ah=rem=02, al= quo=07
mov C, al
mov R, ah
mov ah, 4ch
int 21h
end
BRANCH INSTRUCTIONS
a. conditional jumps based on a single flag
b. conditional jumps based on more than one flag
c. unconditional jump instruction
d. iteration instructions
e. CALL instructions
f. Return instruction
UNCONDITIONAL JUMP INSTRUCTION
The mnemonic for the instruction is JMP. The execution of this instruction always results
in a branch. The branch could be within the same code segment, in which case it is called
a NEAR jump or an INTRASEGMENT jump.
NEAR jump instruction can provide the destination address using a label in a relative
mode, with 1 or 2 bytes of signed displacement, or the destination address is provided
indirectly in a register or a memory location. A NEAR jump instruction using 1 byte
displacement is termed as a SHORT jump.
Thus the 3 types of NEAR jumps are:
(i) NEAR jump with 1 byte displacement (i.e. SHORT jump).
(ii) NEAR jump with 2 byte signed displacement.
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(iii) NEAR jump of INDIRECT type (destination address in a register or memory
location).
If the branch is to a location in code segment which has different name from the segment
in which JMP instruction is present, it is called a FAR jump or an INTER SEGMENT
jump.
FAR jump instructions can provide the destination address using a label in a direct mode,
with 2 words to indicate CS and IP value of the destination address, or the destination
address is provided indirectly in 2 consecutive memory word locations.
Thus the 2 types of FAR jumps are:
(i) FAR DIRECT jump.
(ii) FAR INDIRECT jump.
Thus there are 5 templates for jump instruction.
1. JMP - Intra-segment Relative Short Jump Instruction: It is a 2 byte instruction,
where the 1st byte provides the Opcode and the 2nd byte provides the displacement in 2's
complement notation. Opcode for this instruction is EBH.
Example: Given below is an example for backward branch.
BACK: SUB BX,AX ; This is executed next after JMP BACK
.
.
.
JMP BACK
NEXT: MOV AX,CX
It is assumed that (Offset address of NEXT - Offset address of BACK) is < =128. While
translating JMP BACK, the assembler can easily calculate the required displacement, as
the assembler has earlier come across the label BACK. Only if we are required to go back
by < = 128 bytes, the JMP BACK is translated by the assembler as EBH, followed by the
1 byte displacement.
Example: Given below is an example for forward branch.
JMP SHORT SAME
NEXT: MOV AX,CX
.
.
SAME: SUB BX,CX ; This is executed next after JMP SAME.
It is assumed that (Offset address of SAME - Offset address of NEXT) is < = 127. While
translating JMP SHORT SAME, the assembler is informed by the programmer using the
SHORT assembler directive that the required displacement will be within the range -128
to +127 bytes. Thus, the JMP SHORT SAME is translated by the assembler as EBH,
followed by the 1 byte displacement.
If in this forward branch example, the jump instruction was written without the SHORT
directive as JMP SAME, the assembler will not have an idea of the required forward
displacement. In such a case, the assembler reserves 2 bytes for the forward displacement
after the Opcode for JMP, so that a total of 3 bytes are reserved for this instruction by the
assembler.
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Finally when the assembler comes across the label SAME, it calculates the displacement
for the forward jump in the instruction JMP SAME. If the displacement is < = 127 bytes,
the assembler realizes that only 1 byte is sufficient for the displacement and codes the
instruction as EBH, followed by 1 byte for displacement. The 3rd byte reserved by the
assembler is replaced with 1 byte NOP instruction which will never be executed as it is
after the unconditional jump instruction.
SHORT JUMPS are called relative jumps because they can be moved to any location in
the current code segment without a change. This is because; the jump address isnt stored
with the opcode. Instead of the jump address, a distance, or displacement, follows the
opcode. When the microprocessor executes a short jump, the displacement is sign
extended and added to the instruction pointer (IP) to generate the jump address within the
current code segment.
2. JMP - Intra-segment Relative Jump with 2 byte displacement: It is a 3 byte
instruction, where the 1st byte provides the Opcode and the next 2 bytes provide the 16
bit displacement in 2's complement form. Opcode for this instruction is E9H.
The 16 bit displacement indicates the number of bytes by which the jump takes place.
The range for a 16 bit 2's complement number is -32768 (8000H) to +32767 (7F00H). If
it is a positive number, the jump is usually to a forward location. If it is a negative
number, the jump is usually to a backward location. Thus the memory location specified
by the label in the JMP instruction should be generally in the range of -32768 to +32767
bytes from the beginning of the next instruction after the JMP.
During a jump to backward location if the calculated required displacement is < = 128
bytes, the jump instruction is translated by the assembler as EBH, followed by the 1 byte
displacement (SHORT jump). If the calculated displacement is > 128 bytes, the jump
instruction is translated to be E9H, followed by 2 byte displacement (NEAR jump).
During a jump to forward location, the assembler will have no idea of the required
forward displacement, when it encounters the jump instruction. The assembler then
reserves 2 bytes for the displacement after the Opcode for the JMP. So, a total of 3 bytes
are reserved for the instruction by the assembler.
Finally when the assembler comes across the label of the destination for the jump
instruction, it calculates the displacement for the forward jump. If this forward
displacement is < =127 bytes, the assembler codes the jump instruction as EBH followed
by 1 byte displacement (SHORT jump). The 3rd byte reserved by the assembler is
replaced with the 1 byte NOP instruction.
If the forward displacement is > 127 bytes, the assembler codes the jump instruction as
E9H, followed by 2 byte displacement (NEAR jump).
If a forward jump instruction is present at the start of 64K byte segment, say at offset
location 000DH. Then the next instruction will be at location 0010H after a distance of 3
bytes. If the destination address in the jump instruction is at the end of the segment, say at
memory location FFF0H, then the required displacement will be > 32767 bytes. The
assembler will automatically translate this instruction as SHORT backward jump
instruction with a 1 byte displacement of -20H=E0H (0010H - FFF0H=-0020H).
If a backward jump instruction is present at the end of the segment, say at memory
location FFEEH, then the next instruction will be at a distance of 2 bytes, at the location
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FFF0H. If the destination address of the branch is near the start of the segment, at 0010H,
then the required backward displacement is >32768 bytes. In this case, the assembler
automatically translates the jump instruction as a SHORT forward jump instruction with
1 byte displacement value equal to 20H (FFF0 - 0020).
NEAR JUMP is similar to short jump, except that the distance is farther. The signed
displacement adds to IP to generate jump address. Near jump is also relocatable because
it is also a relative jump. If the code segment moves to a new location in the memory, the
distance between the jump instruction and the operand address remains same. This allows
a code segment to be relocated by simply moving it.
This feature along with relocatable data segments makes INTEL family of
microprocessors ideal for use in a general purpose computer system.
3. JMP - Intra-segment Indirect Jump or Near Indirect Jump: Here the jump address
is given as the contents of a word register or a word location in the memory. This form of
jump is used to select one of the several jump destinations based on the computed value.
The template for this instruction is 11111111 MOD-100-R/M. MOD = 11 if R/M is a
register, it is 10 if R/M is memory.
Example: JMP DX; DX contains 1234H. Then the execution of JMP DX instruction
results in an unconditional branch to 1234H in the same code segment. 1234H is not a
relative displacement. JMP DX is a 2 byte instruction with code FF E2H (11111111 11
100010)
Example: JMP WORD PTR 2000H[BX], BX contains 1234H and the contents of word
location 3234H is 5678H. This is an unconditional branch instruction which jumps to the
current code segment location addressed by the contents of the data segment memory
location addressed by BX + displacement = 1234H+ 2000H = 3234H. Thus the branch
address is the offset location 5678H in the same segment. It is a 4 byte instruction with
Opcode FF A7 20 00H (11111111 10 100 111 20 00H).
JMP DX: copies the contents of DX into IP when jump occurs, in current code segment.
JMP [BX]: jumps to current code segment location addressed by contents of data
segment memory location addressed by BX. (20 bit address of memory location in data
segment= DS X 10 + BX, contents of this location is copied into IP.
4. JMP- Inter-segment Direct Jump or FAR Jump: As it is desired to jump or branch
to a different segment, it is necessary to provide the segment base and the offset values of
the destination in the instruction. Thus it is a 5 byte instruction, where the first byte
provides the Opcode and the next 2 bytes provide the offset and the last 2 bytes provide
the segment base value of the destination. Opcode for this instruction is EAH. In
assembly language program, the programmer just provides the label of the location where
jump is desired and the assembler will be told that it is a FAR jump, using the FAR
pointer as JMP FAR PTR LOC.
Opcode
Offset (low)
Offset (high)
Segment (low) Segment (high)
EA
00
00
00
10
The FAR JUMP instruction appears with FAR PTR directive.
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Another way to obtain a far jump is to define a label as a FAR label. A label is far if it is
external to the current code segment or procedure.
E.g. JMP UP, then label UP is defined as a far label by EXTRN UP:FAR
Another way of defining a label as global is to use double colon (label ::).
5. JMP-Inter-segment Indirect Jump or FAR Indirect Jump: Jump address is given
as the contents of a double word in memory.
Example: JMP DWORD PTR 2000H[BX]; the contents of the word location 3234H is
5678H and the contents of the word location 3236H is ABCDH. Then, when above
instruction is executed, the unconditional branch to location in a different segment,
whose segment base is ABCDH and whose offset is 5678H, takes place. It is a 4 byte
instruction with Opcode FF AF 200 00.
ITERATION INSTRUCTIONS
8086 provides a very convenient way to implement loops in a program. These loop
instructions can result in a branch both conditionally and unconditionally. Without such
loop instructions, it requires more code and more execution time to achieve the same
effect using other instructions. These iteration instructions are described below.
1. LOOP - Decrement CX and branch if CX is not equal to zero: The mnemonic for the
instruction is LOOP and it is a 2 byte instruction, where the first byte provides the
Opcode and the second byte provides the displacement in 2's complement notation.
However, in assembly language programming, the programmer provides the label of the
location where jump is desired. The assembler then generates the displacement in 2's
complement notation. Thus the destination must be within a distance of -128 to +127
bytes from the beginning of next instruction after the LOOP instruction. If the label is
defined at a distance outside this range, an error message will be flashed by the assembler
during assembly process.
Although theoretically, it is possible to branch forward using a LOOP instruction, it is
invariably used for a backward branch only. The execution of this instruction does not
affect any of the flags.
The execution of 'LOOP BACK' instruction will result in the following.
a. CX is decremented by 1.
b. If CX content is not 0, a branch to BACK takes place.
c. If CX content is 0, execution of next instruction after LOOP takes place.
In a LOOP instruction CX is always used as an implied counter. Thus LOOP BACK is
equivalent to the following pair of instructions:
DEC CX
JNZ BACK
2. LOOPZ or LOOPE - Decrement CX and branch if CX is not equal to zero and
Z flag = 1: The mnemonic for this instruction is LOOPZ and it stands for 'Loop while Z
flag = 1'. It is a 2 byte instruction, where the first provides the Opcode and the second
byte provides the displacement in 2's complement notation.
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Another equivalent mnemonic for the instruction is LOOPE, which stands for 'Loop
while equal'.
Generally LOOPE is used after a CMP instruction and LOOPZ is used after an arithmetic
operation like addition.
bytes from the beginning of next instruction after the LOOPZ instruction. If the label is
Although theoretically, it is possible to branch forward using a LOOPZ instruction, it is
The execution of 'LOOPZ BACK' instruction will result in the following:
b. If CX contents are not zero, and Z flag = 1, a branch to BACK takes place.
c. If CX contents are 0 or Z flag = 0, execution of next instruction after LOOPZ takes
place.
3. LOOPNZ or LOOPNE - Decrement CX and branch if CX is not equal to zero and Z
flag = 0: The mnemonic for this instruction is LOOPNZ and it stands for 'Loop while Z
flag = 0'. It is a 2 byte instruction, where the first provides the Opcode and the second
byte provides the displacement in 2's complement notation.
Another equivalent mnemonic for the instruction is LOOPNE, which stands for 'Loop
while not equal'.
Generally LOOPNE is used after a CMP instruction and LOOPNZ is used after an
arithmetic operation like addition.
bytes from the beginning of next instruction after the LOOPNZ instruction. If the label is
Although theoretically, it is possible to branch forward using a LOOPNZ instruction, it is
The execution of 'LOOPNZ BACK' instruction will result in the following:
b. If CX contents are not zero, and Z flag = 0, a branch to BACK takes place.
c. If CX contents are 0 or Z flag = 1, execution of next instruction after LOOPNZ takes
place.
4. JCXZ - Jump if CX is equal to zero: The mnemonic for this instruction is JCXZ and it
stands for 'Jump if CX value is equal to 0'. It is a 2 byte instruction, where the first
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provides the Opcode and the second byte provides the displacement in 2's complement
notation.
bytes from the beginning of next instruction after the JCXZ instruction. If the label is
JCXZ instruction execution does not affect any flags. The execution of this instruction is
not affected by the Z flag, and it is only affected by the value of CX register. CX value is
not altered after the execution. The execution of 'JCXZ BACK' instruction will result in
the following:
a. If CX contents are zero, a branch to BACK takes place.
b. If CX contents are not equal to zero, execution of next instruction after JCXZ takes
place.
The JCXZ is very useful to check if the iterative count value in CX is zero or not before
the iteration starts.
ALP: add an array of m binary numbers stored in word locations.
.model small
.data
m equ 5
array dw 1234h, 4562h, 6982h, 7852h, 5643h
total dw ?
.code
.startup
mov cx, m
mov ax, 0
mov si, ax
start: add ax, array[si]
add si, 2
loop start
mov total, ax
.exit
end
ALP: add 2 16 digit packed bcd nos. (1 digit= 4 bits, 16 digits= 64 bits= 8 byte
locations)
.model small
.data
augend db 12, 23, 24, 15, 19, 78, 69, 56
addend db 52, 65, 85, 96, 35, 65, 20, 80
sum db 8 dup (?)
.code
.startup
mov cx, 8
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mov si, 0
clc
start: mov al, augend[si]
adc al, addend[si]
daa
mov sum[si], al
inc si
loop start
.exit
end
ALP: string stored in ascii_str location with L characters, search for space
character (20h) in the string using loopne instruction
.model small
.data
ascii_str db work is worship,$
msg1 db space character found,$
msg2 db space character not found,$
.code
.startup
mov cx, L
mov si, -1
mov al, 20h
next: inc si
cmp al, ascii_str[si]
loopne next
jnz not_found
mov dx, msg1
jmp disp
not_found: mov dx, msg2
disp: mov ah, 9
int 21h
.exit
end
CONDITIONAL JUMPS BASED ON A SINGLE FLAG
Described below are the instructions which perform a branch based on the value of a
single status flag. The status flags used in these instructions are Z, S, O, C, and P. All
these are 2 byte instructions, where the first byte provides the opcode and the second byte
provides the displacement in 2s complement notation.
The 8 bit displacement indicates the number of bytes by which the jump takes place. The
range for an 8 bit 2s complement number is from -128 (80H) to +127 (7FH). If
it is a positive number, the jump is to a forward location. If it is a negative number, the
jump is to a backward location. Thus the memory location specified by the label in jump
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instruction must be in the range of -128 to +127 bytes from the beginning of the next
instruction after jump instruction.
However, in ALP, the programmer just provides the label for the location where jump is
desired. The assembler then generates the displacement in 2s complement notation. If
the label is at a distance outside this range, an error message will be flashed by the
assembler during assembly process. In such a case, a conditional branch instruction has to
be combined with an unconditional branch instruction to circumvent the problem.
1. JE/ JZ, (jump if equal/ jump if zero):
JE is used after CMP instruction and JZ is used after arithmetic operation.
If ZF=1, this instruction execution results in a jump to the label specified in the
instruction.
If ZF=0, execution continues with the next instruction after JE.
2. JNE/ JNZ , (jump if not equal/ jump if not zero):
JNE is used after CMP instruction and JNZ is used after arithmetic operation.
If ZF=0, this instruction execution results in a jump to the label specified in the
instruction.
If ZF=1, execution continues with the next instruction after JNE.
3. JS (jump on sign):
If SF=1, this instruction execution results in a jump to the label specified in the
instruction.
If SF=0, execution continues with the next instruction after JS.
4. JNS (jump on no sign):
If SF=0, this instruction execution results in a jump to the label specified in the
instruction.
If SF=1, execution continues with the next instruction after JNS.
5. JO (jump on overflow):
If OF=1, this instruction execution results in a jump to the label specified in the
instruction.
If OF=0, execution continues with the next instruction after JO.
6. JNO (jump on no overflow):
If OF=0, this instruction execution results in a jump to the label specified in the
instruction.
If OF=1, execution continues with the next instruction after JNO.
7. JC/ JB/ JNAE (jump if carry/ jump if below/ jump if not above or equal):
JB or JNAE is used after CMP instruction and JC is used after arithmetic operation.
The terms below and above are used when we are comparing unsigned numbers.
If operand-1 > operand-2, operand-1 is above operand-2 and CF=0.
If operand-1 < operand-2, operand-1 is below operand-2 and CF=1.
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If CF=1, this instruction execution results in a jump to the label specified in the
instruction.
If CF=0, execution continues with the next instruction after JC.
8. JNC/ JAE/ JNB (jump if no carry/ jump if above or equal/ jump if not below):
JNB or JAE is used after CMP instruction and JNC is used after arithmetic operation.
If CF=0, this instruction execution results in a jump to the label specified in the
instruction.
If CF=1, execution continues with the next instruction after JNC.
9. JP/ JPE (jump if parity/ jump if parity even):
If PF=1, this instruction execution results in a jump to the label specified in the
instruction.
If PF=0, execution continues with the next instruction after JP.
10. JNP/ JPO (jump on no parity/ jump if parity odd):
If PF=0, this instruction execution results in a jump to the label specified in the
instruction.
If PF=1, execution continues with the next instruction after JNP.
CONDITIONAL JUMPS BASED ON MORE THAN ONE FLAG
JG, JL, JGE, JLE etc. are used when signed numbers are compared.
JA, JB, JAE, JBE etc. are used when unsigned numbers are compared.
i.e. the terms greater than, less than refer to signed numbers and the terms above or below
refer to unsigned numbers.
1. JBE/ JNA (jump if below or equal/ jump if not above):
Used after CMP instruction to check if operand-1 > or < operand-2. This instruction
results in a branch based on values of CF and ZF.
If CF=1 or ZF=1 (i.e. op1 < op2 or op1 = op2) this instruction execution results in a
jump to the label specified in the instruction.
If CF=0 & ZF=0, execution continues with the next instruction after JBE.
2. JNBE/ JA (jump if not below or equal/ jump if above):
If CF=0 & ZF=0 (i.e. op1 > op2) this instruction execution results in a jump to the
label specified in the instruction.
If CF=1 or ZF=1, execution continues with the next instruction after JBE.
3. JLE/ JNG (jump if less or equal/ jump if not greater):
If SF=1 & OF=0, op1 < op2, op1-op2 = negative result and the result is correct as OF=0.
Therefore, op1 < op2, JLE instruction results in a branch.
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If SF=0 & OF=1, op1-op2 = positive result and the result is wrong as OF=1. Therefore,
op1 < op2, JLE instruction results in a branch.
If ZF=1, op1=op2, hence a branch should take place.
i.e. if SF is different from OF or if ZF=1, this instruction execution results in a jump to
the label specified in the instruction.
If SF has same value as OF & ZF=0, execution continues.
4. JNLE/ JG (jump if not less or equal/ jump if greater):
If SF=0 & OF=0, & ZF=0 op1 > op2, op1-op2 = positive result and the result is correct as
OF=0. Therefore, op1 > op2, JNLE/ JG instruction results in a branch.
If SF=1 & OF=1, & ZF=0 op1-op2 = negative result and the result is wrong as OF=1.
Therefore, op1 > op2, JNLE/ JG instruction results in a branch.
i.e. if SF is same as OF & if ZF=0, this instruction execution results in a jump to the label
specified in the instruction.
If SF has different value from OF or ZF=1, execution continues.
5. JL/ JNGE (jump if less/ jump if not greater or equal):
If SF=1 & OF=0, & ZF=0 op1-op2 = negative result and the result is correct as OF=0.
Therefore, op1 < op2, JL instruction results in a branch.
If SF=0 & OF=1, & ZF=0 op1-op2 = positive result and the result is wrong as OF=1.
Therefore, op1 < op2, JL instruction results in a branch.
i.e. if SF is different from OF & if ZF=0, this instruction execution results in a jump to
the label specified in the instruction.
If SF has same value as OF OR ZF=1, execution continues.
6. JNL/ JGE (jump if not less/ jump if greater than or equal):
If SF=0 & OF=0, op1 > op2, op1-op2 = positive result and the result is correct as OF=0.
Therefore, op1 > op2, JNL/ JGE instruction results in a branch.
If SF=1 & OF=1, op1-op2 = negative result and the result is wrong as OF=1. Therefore,
op1 > op2, JLE/ JGE instruction results in a branch.
If ZF=1, op1=op2, hence a branch should take place.
i.e. if SF is same as OF or if ZF=1, this instruction execution results in a jump to the label
specified in the instruction.
If SF has different value from OF and ZF=0, execution continues.
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PROCESSOR CONTROL
INSTRUCTIONS)
INSTRUCTIONS
(OR
MACHINE
CONTROL
These instructions provide control of flags, sample the TEST pin, provide external
synchronization etc.
1. INSTRUCTIONS TO SET/RESET FLAGS
a) Set/Clear/Complement carry flag (STC/CLC/CMC): The carry flag propagates the
carry or borrow in multiple word addition and subtraction. The most common task for the
carry flag is to indicate an error upon return from a procedure. Suppose that a procedure
reads data from a disk memory file. This operation can be successful or an error such as
file not found can occur. On return from procedure, if C = 1, an error has occurred; if C =
0, no error occurred. Most of the DOS and BIOS procedures use the carry flag to indicate
error conditions.
STC (Set carry), CLC (Clear carry), CMC (Complement carry) control the contents of the
carry flag.
b) Set/Clear Direction flag (STD/CLD): Execution of STD instruction results in setting of

the direction flag to 1 and other flags are not affected. During string manipulations, this
instruction is used to decrement the contents of SI and DI automatically.
Execution of CLD instruction results in resetting of the direction flag to 0 and other flags
are not affected. During string manipulations, this instruction is used to increment the
contents of SI and DI automatically
c) Set/Clear Interrupt Enable flag (STI/CLI): Execution of STI instruction results in
setting the Interrupt flag to 1. Only if Interrupt flag is set, 8086 will be interrupted
when the INTR line is activated. However 8086 will be interrupted if NMI line is
activated immaterial of the status of IF. Although IF is set to 1 by the execution of STI
instruction, 8086 can get interrupted because of INTR pin only after the execution of the
next instruction.
Execution of CLI instruction results in resetting the Interrupt flag to 0. Other flags are not
affected and the 8086 will not get interrupted when the INTR line is activated by some
external device.
2. HALT INSTRUCTION (HLT)
The halt instruction (HLT) stops the fetching and execution of the software or
instructions. This instruction normally appears in a program to wait for an interrupt. It
synchronizes external hardware interrupts with the software system. The only way the P
comes out or exits this state is because of the activation of interrupts (NMI or INTR), by
hardware reset (RESET signal), or during a DMA operation.
3. WAIT INSTRUCTION (WAIT)
The WAIT instruction monitors the hardware TEST pin of 8086. The WAIT instruction
is used to synchronize the 8086 with external hardware such as 8087 numeric
coprocessor. The TEST pin of 8086 is connected to BUSY pin of 8087 coprocessor.
This connection allows 8086 to wait until the coprocessor 8087 finishes its task. When
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8087 is busy it sends logic 1 at the BUSY pin and thus logic 1 at TEST pin. When 8087
finishes its task, it sends logic 0 at BUSY pin and thus logic 0 at TEST pin of 8086.
If the WAIT instruction executes while the TEST pin is 0, nothing happens and the next
instruction executes. If the TEST pin is not active i.e. at logic 1, 8086 enters an idle state
where it does not do any processing. However it fetches the next instruction in the queue
which is required by 8087 coprocessor, and ignores that instruction. The 8086 stays in
this idle state until one of the following conditions occur. (i) TEST pin is made low for
outlast 5 clock cycles by the 8087. Then 8086 executes its next instruction. (ii) NMI
interrupt line is activated. (iii) INTR line is activated, when IF = 1. If 8086 is interrupted
because of NMI or INTR activation, the 8086 returns to its idle state, after the execution
of interrupt service routine. This is because the address of the WAIT instruction is stored
on top of the stack, when 8086 branches to the interrupt service routine.
4. LOCK PREFIX (LOCK)
The LOCK prefix appends an instruction and causes the LOCK pin to become a logic 0
which disables the external bus masters or other system components. The LOCK prefix
causes the LOCK pin to get activated for the duration of a locked instruction. If more
than one sequential instruction is locked, the LOCK pin remains at logic 0 for the
sequence of locked instructions.
A microcomputer system can contain several microprocessors, each of which has its own
local bus for accessing local resources like local memory. The various microprocessors in
the system are connected by a system bus and thus can access global resources like disk
drives or global memory. The LOCK prefix for an instruction allows a microprocessor to
make sure that another microprocessor does not take control of the system bus during
execution of a critical instruction which uses a system bus. This is achieved by the 8086
activating LOCK signal, which is one of the signals in the maximum mode of the
operation. This signal is connected to an external bus controller, which prevents any other
microprocessor from taking control of the system bus.
5. ESCAPE TO COPROCESSOR (ESC)
The escape (ESC) instruction passes information to the coprocessor. The instruction
template of these instructions start with 11011 and will be treated by 8086 as an
instruction to a coprocessor, which shares the address bus and data bus with 8086.
Instructions for coprocessor (ESC instruction) are given by the 6 bit code and the
coprocessor decodes the 6 bits in the ESC instruction to determine the action to be
performed. As the 8086 fetches instruction bytes, the coprocessor also fetches them on
the data bus and puts them in its queue, and treats all normal 8086 instructions as no
operation instructions. In most cases, 8086 also treats ESC instructions as a NOP. In
some cases, 8086 accesses a data item in memory for the coprocessor.
6. NO OPERATION INSTRUCTION (NOP)
When 8086 encounters NOP, it takes a short time to execute. NOP finds application in
time delays to waste time.
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PROCEDURES
Very often it is needed to use a particular sequence of instructions at several points in the
program. The writing of the same sequence of instructions at various points can be
avoided by writing the series of instructions as a SUBPROGRAM. In 8086 terminology,
such sub-programs are termed as PROCEDURES.
A procedure is a group of instructions that usually perform one task. A procedure is a

reusable section of the software that is stored in memory once, but used as often as
necessary. This saves the memory space and makes it easier to develop software. The
only disadvantage of a procedure is that it takes the computer a small amount of time to
link to the procedure and return from it. The CALL instruction links to the procedure, and
RET instruction returns from the procedure. The stack stores the return address whenever
a procedure is called during the execution of a program. The CALL instruction pushes
the address of the instruction following the CALL (return address) on the stack. The RET
instruction removes an address from the stack so the program returns to the instruction
following the CALL. A procedure begins with the PROC directive and ends with ENDP
directive. Each directive appears with the name of the procedure. The PROC directive is
followed by the type of the procedure: NEAR (intra segment) or FAR (inter segment). In
MASM version 6.X, the NEAR or FAR type can be followed by USES statement. The
USES statement allows any number of the registers to be automatically pushed on to the
stack and popped from the stack within the procedure. Procedure of type NEAR has an
Opcode of C3H and the procedure of type FAR has an Opcode of CBH. A NEAR return
removes the 16-bit number from stack and places into the instruction pointer to return
from the procedure in the current code segment. A FAR return removes a 32-bit number
from the stack and places it into both IP & CS to return from procedure to any memory
location. Procedures that are to be used by all software (Global) should be written as
FAR procedures. Procedures that are used by a given task (Local) are normally defined
as NEAR Procedures.
Label PROC NEAR/FAR
.
.
.
Label ENDP
In 8086, there are no conditional CALL or RET instructions.
CALL INSTRUCTION
The difference between a JMP and a CALL is as follows:
If JMP is executed, then the program control jumps to the destination location and
execution carries on from there without bothering to come back later to the instruction
after the JMP. If a CALL is executed, the program control jumps to the destination
location and execution carries on from there, and the program control returns back to the
instruction after the CALL.
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Whenever the instructions in the procedure are required to be executed, branch to
procedure takes place using CALL instructions. CALL stands for "CALL A
PROCEDURE". After executing the instructions in the procedure, the RET instruction
(RETURN FROM PROCEDURE) placed at the end of the procedure, returns the
program control to the next instruction after the CALL in the main program.
Using this approach the procedure can be called any number of times, which is written
only once. This saves a lot of memory space for the complete program. It also helps in
modular design for solving a programming problem. It makes the main program look
very simple and compact. The execution of CALL always results in a branch to a
procedure. The branch could be within the same code segment, in which case it is called
a NEAR CALL or an Intra-segment CALL. NEAR call can provide the destination
address directly using the label in relative mode, with two bytes of signed displacement,
or the destination address is provided indirectly in a register or a memory location. Thus
the two types of NEAR calls are
a.
NEAR Call or Intra-Segment Call of direct type
b.
NEAR Call or Intra-Segment Call of indirect type. (Destination Address in a
register or a memory Location.
If the procedure is in a code segment which has a different name from the segment in the
call is present, it is called a FAR Call or an Inter-segment Call.
FAR Call can provide the procedure address using a label in a direct mode, with two
words to indicate CS & IP value of the destination address, or the procedure address is
provided indirectly in to consecutive memory word locations. Thus the two types of
FAR calls are
a. FAR Call or Inter-Segment Call of Direct type
b. FAR Call or inter-Segment Call of Indirect type
Thus there are four templates for the CALL instruction and the mnemonic for these
instructions is CALL.
CALL - Intra-segment call or NEAR CALL of direct type
It is a 3 byte instruction, where the first byte provides the Opcode and the next two bytes
provide the 16 bit displacement in 2's complement notation. The Opcode for this
instruction is E8H. The 16 bit displacement indicates the number of bytes by which the
jump takes place. The range for a 16 bit 2's complement number is from -32768 (8000H)
to +32767 (7F00H). If it is a positive number, the jump is to a forward location. If it is a
negative number the jump is to a backward location. Thus the memory location specified
by the label in the CALL instruction should be generally in the range of -32768 to
+32767 bytes from the beginning of the next instruction after CALL.
The execution of a NEAR direct CALL results in the following
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a. The offset value of the next instruction after CALL, which is present in the instruction
pointer register (IP), is saved above the top of the stack.
b. IP value is replaced by the sum of IP value and 16 bit signed displacement provided in
the instruction. Thus the new IP value is the offset address of the procedure, and hence
branch to the procedure takes place.
CALL - Intra-segment Indirect Call or NEAR Indirect Call
The call address is given as the contents of a word register or word location memory.
This form of call is used to select one of the several procedures based on a computed
value.
The execution of a NEAR Indirect CALL results in the following
a. The offset value of the next instruction after CALL, which is present in the instruction
pointer register (IP), is saved above the top of the stack.
b. IP value is replaced by the contents of word register, or of a word location in memory,
which is provided in the instruction. Thus the new IP value is the offset address of the
procedure, and hence branch to the procedure takes place.
CALL - Inter-segment Direct Call or FAR direct Call
As it is desired to branch to a different segment, it is necessary to provide the segment

base and offset values of the procedure in the instruction. Thus it is 5 byte instruction
where the 1st byte provides the Opcode, the next 2 bytes provide the offset value and the
last 2 bytes provide the segment base value of the procedure.
In assembly language programming, the programmer just provides the name of the
procedure where jump is desired. Further the assembler will be told that it is a FOR call
as in 'CALL FOR PTR LOC', in case the procedure LOC is defined at a later point in the
program. The assembler directive "FOR PTC" is not needed in the CALL instruction if
the procedure LOC is defined in a different segment earlier to the CALL instruction.
The execution of a FAR Direct CALL results in the following
The Segment value of the next instruction after CALL, which is present in the Code
Segment register (CS), is saved above the top of the stack.
The offset value of the next instruction after CALL, which is present in the instruction
pointer register (IP), is next saved above the top of the stack.
IP value is replaced by the 16 bit offset value provided in the 2nd & 3rd bytes of the
instruction. Thus the new IP value is the offset address of the procedure.
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CS value is replaced by the 16 bit segment base value provided in the 4th & 5th bytes of
the instruction. Thus the new CS value is the Segment base address of the procedure, and
hence branch to the procedure takes place.
CALL - Inter-segment Indirect Call or FAR indirect Call
The CALL address is given as the contents of a double word in memory. The execution
of a FAR Direct CALL results in the following
The Segment value of the next instruction after CALL, which is present in the Code
Segment register (CS), is saved above the top of the stack.
The offset value of the next instruction after CALL, which is present in the instruction
pointer register (IP), is next saved above the top of the stack.
IP value is replaced by the 16 bit offset value provided in the word location whose
address is given in the instruction. Thus the new IP value is the offset address of the
procedure.
CS value is replaced by the 16 bit segment base value provided in the next word location.
Thus the new CS value is the Segment base address of the procedure, and hence branch
to the procedure takes place.
RETURN INSTRUCTION
The CALL instruction pushes the address of the instruction following the CALL on the
stack. The address saved above the top of the stack is generally termed as RETURN
ADDRESS.
The return address is the contents of the IP, in case of a NEAR CALL, whether of
DIRECT or INDIRECT type. The return address is the contents of IP and CS, in case of a
FAR CALL, whether direct or indirect type.
The RET instruction, which is at the end of the procedure, pops out from top of the stack,
the return address, to IP only or IP and CS, so that a branch back to the calling program at
the next instruction after CALL is achieved.
If the calling program is in the same code segment as the called procedure, then a NEAR
return or an intra segment return instruction is used to achieve the objective.
Execution of NEAR return instruction results in popping out the one word return address
to IP. In addition to popping the return address, it can also optionally remove a specified
number of bytes from the stack. This is achieved by adding a 16 bit immediate value
provided in the RET instruction, to the contents of SP register. Thus the 2 types of NEAR
return instructions are
a. NEAR return or intra segment return
b. NEAR return or intra segment return with a 16 bit immediate value added to the SP
contents.
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The execution of the RET instruction always results in a branch back to the calling
program, to the next instruction after the CALL. If the calling program is in a different
segment from the called procedure, then a FAR return or inter segment return instruction
is used to achieve the objective.
Execution of FAR return instruction results in popping out the two word return address to
IP and CS. In addition to popping the return address, it can also optionally remove a
specified number of bytes from the stack. This is achieved by adding a 16 bit immediate
value provided in the RET instruction, to the contents of SP register. Thus the 2 types of
FAR return instructions are
a. FAR return or inter segment return
b. FAR return or inter segment return with a 16 bit immediate value added to the SP
contents.
Thus there are 4 templates for the return instruction and the mnemonic for these is RET.
The assembler codes the RET as NEAR or FAR based on the type specification of the
procedure.
RET - Intra segment or NEAR return
It is a 1 byte instruction and it Opcode is C3H. The offset value of the next instruction
after CALL, which was earlier saved by the NEAR CALL on the stack, is now popped
from top of the stack to the IP register. And so the branch back to the calling program
takes place.
RET - Intra segment Return with Immediate value added to SP register
It is a 3 byte instruction, where the first byte provides the Opcode, and the next 2 bytes
provide the immediate value to be added to SP. An example for this instruction is
RET 12H. Opcode for this instruction is C2H. The execution of this instruction results
in the following.
1. The offset value of the next instruction after call, which was earlier saved by the
NEAR CALL instruction on the stack is now popped from the top of the stack to the IP
Register. And so the branch back to the calling program takes place
2. The 16 bit immediate value provided in the instruction is added to the SP register
contents. In other words, the immediate value provided in the RET Instruction indicates
the number of bytes that are removed from the top of the stack after popping out the
return address.
RET - Inter Segment or FAR RETURN
It is a 1 byte instruction. The Opcode for this instruction is CBH. The execution of a
FAR RET instruction results in the following
The segment base and offset value of the next instruction after call, which was earlier
saved by FAR CALL instruction on the stack, is now popped from the top of the stack to
IP & CS registers and so the branch back to the calling program takes place.
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RET- Inter Segment or FAR RETURN with immediate value added to SP register
It is a 3 byte instruction, where the first byte provides the Opcode, and the next 2 bytes
provide the immediate value to be added to SP. An example for this instruction is
RET 12H. Opcode for this instruction is CAH. The execution of this instruction results
in the following.
1. The segment base and offset value of the next instruction after call, which was earlier
saved by FAR CALL instruction on the stack, is now popped from the top of the stack to
IP & CS registers and so the branch back to the calling program takes place.
2. The 16 bit immediate value provided in the instruction is added to the SP register
contents. In other words, the immediate value provided in the RET Instruction indicates
the number of bytes that are removed from the top of the stack after popping out the
return address.
MACROS
A Macro is a group of instructions that perform one task, just as a procedure performs
one task. The difference is that a procedure is accessed via a CALL instruction, while a
macro and all the instructions defined in the macro is inserted in the program at the point
of usage.
The name of the macro and any parameters associated with it are typed, and the
assembler then inserts them into the program.
Macro sequences execute faster than procedure because there are no CALL and
RET instructions to execute. The instructions of the macro are placed in the program by
the assembler at the point they are invoked.
The MACRO and ENDM directives delineate or separate a macro sequence. The
st
1 statement of macro is the MACRO instruction, which contains the name of the macro
and any parameters (formal parameters) associated with it
Eg: TRANSFER MACRO A,B
TRANSFER=name of macro
A,B=formal parameters
The last statement of a macro is the ENDM instruction, before which a label should never
be written.
The eg of macro shown below moves the word sized contents of memory location
B into word sized memory location A.
TRANSFER MACRO A,B
PUSH AX
MOV AX,B
MOV A,AX
POP AX
ENDM
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In the main program, the macro is invoked by the following statement and the instruction
prefixed by * are the macro instructions inserted by the assembler which are not typed in
the source program.
TRANSFER VAR1,VAR2
* PUSH AX
* MOV AX,VAR2
* MOV VAR1,AX
* POP AX
Disadvantage of using a MACRO is that large memory space is required for the program
using MACRO as, each time the MACRO instructions are inserted, when the MACRO is
invoked.
The comment in the MACRO is preceded with ;; instead of ;. MACRO sequences must
always be defined before they are used in a program, so they generally appear at the top
of the code segment.
LOCAL VARIABLES IN A MACRO
Macros contain local variables. A local variable is one that appears in the
MACRO, but is not available outside the MACRO. LOCAL directive is used to define
local variables. LOCAL directive must always immediately follow the MACRO
directive, without any intervening space or comments. In the example below, jump
address (label) is defined as local variable, otherwise, assembler flags it as an error.
READ MACRO A
LOCAL READ1
READ1: MOV AH, 6
MOV DL, OFFH
INT 21H
JE READ1
MOV A, AL
ENDM
READ BX
* ??0000: MOV AH, 6
*MOV DL, OFFH
*INT 21H
*JE ??0000
*MOV BX, AL
This example reads a character from the keyboard and stores it into the byte sized
memory location indicated as a parameter with the MACRO. ??0000 is assembler
generated label.
PARAMETER PASSING TECHNIQUES
The various parameter passing techniques are using registers, using memory locations,
using pointers passed in registers, using stack.
1. PARAMETER PASSING USING REGISTERS
The data, to be passed as parameters is stored in the registers and these registers are
accessed in the procedure to process the data.
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This method is convenient when the parameters to be passed to procedure are less.
.model small
.data
n1 dw 1234h
n2 dw 2354h
res dw ?
.code
sum proc
pushf
add ax, bx
popf
ret
sum endp
begin: mov ax, @data
mov ds, ax
mov ax, n1
mov bx, n2
call sum
mov res, ax
mov ah, 4ch
int 21h
end
2. PARAMETER PASSING USING MEMORY LOCATIONS
The data, to be passed as parameters is stored in the memory locations and these are
accessed in the procedure to process the data.
The memory location must be dedicated to hold the parameters when the procedure is
called. This method cannot be used when data need to be passed from some other
location.
.model small
.data
n1 dw 1234h
n2 dw 2354h
res dw ?
.code
sum proc
pushf
push ax
mov ax, n1
add ax, n2
mov res, ax
pop ax
popf
ret
sum endp
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mov ds, ax
call sum
mov ah, 4ch
int 21h
end
3. PARAMETER PASSING WITH POINTERS PASSED IN REGISTERS
The offset address of the data to be passed is stored in pointer registers, BX, SI or DI.
Any addressing mode can be used to access the memory.
The data, to be passed as parameters is stored in the memory locations and these are
accessed by using the pointers in the procedure to process the data.
.model small
.data
n1 dw 1234h
n2 dw 2354h
res dw ?
.code
sum proc
pushf
push ax
mov ax, [si]
add ax, [si+2]
mov [di], ax
pop ax
popf
ret
sum endp
mov ds, ax
lea si, n1
lea di, res
call sum
mov ah, 4ch
int 21h
end
4. PARAMETER PASSING USING STACK
The data, to be passed as parameters are pushed onto the stack and the procedure is
called. In the procedure the parameters are obtained from the stack using BP register
The programmer should keep track of what is pushed on to the stack and where the stack
pointer points to when the procedure is called.
.model small
.data
n1 dw 1234h
n2 dw 2354h
res dw ?
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.code
sum proc
pushf
mov bp, sp
mov ax, [bp]
mov bx, [bp+2]
add ax, bx
mov res, ax
popf
ret
sum endp
mov ds, ax
mov ax, n1
mov bx, n2
push ax
push bx
call sum`
mov res, ax
mov ah, 4ch
int 21h
end
Difference between procedure and Macro
PROCEDURE
Accessed using CALL and RET
instructions during execution
The procedure uses stack mechanism. The

return address is stored on to stack during
CALL and retrieved back during RET
instruction execution.
Takes more time to execute since control
has to be transferred to/ from procedure.
The machine code generated for the
procedure is placed in the memory only
once. Thus usage of memory space is less.
The size of the executable file is less.
Parameters can be passed using registers,
memory locations or stack.
MACRO
Accessed using macro name by the
assembler during conversion from
assembly language to machine code
Macros do not use the concept of stack
Takes less time to execute since there is no

transfer of control
The machine code generated for the macro
each time it is invoked. Thus usage of
memory space is more.
The size of the executable file is more.
Parameters are passed as part of the
statement which invokes the macro.
PUBLIC and EXTRN Directives: The directive PUBLIC is used to declare labels of
code, data, or entire segments are available to other program modules. EXTRN (external)
informs the assembler that the names, procedures and labels declared after this directive
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are external to the module and have already been defined in some other assembly
language module. Without these statements, modules cannot be linked to create a
program using modular programming.
The PUBLIC directive is used in the Opcode field of an assembly language statement to
define a label as public, so that the label can be used by other modules. The label
declared as PUBLIC can be a jump address, a data address, or an entire segment.
When segments are made public, they are combined with other public segments that
contain the data with same segment name.
The EXTRN statement appears in both data and code segments to define labels as
external to the segment. If the data are declared as external, their sizes must be defined as
BYTE, WORD or DWORD. If a jump or call address is external, it must be defined as
NEAR or FAR. An example is shown below.
.model small
.data
public data1 ; declare data1 and data2 as public
public data2
data1 db 100 dup (?)
data2 dw 100 dup (?)
.code
.startup
public read
; declare read as public
read proc far
mov ah, 6
; read key board
mov dl, 0ffh
int 21h
je read ; go back if no key is pressed and scan the key board again
ret
read endp
end
.model small
.data
extrn data1: byte
extrn data2: word
extrn data3: dword
.code
extrn read: far
.startup
lea di, data1
mov cx, 10
cld
start: call read
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stosb
loop start
.exit
end
DATA CONVERSIONS
In computer system, the data will not be in correct form. The system converts the data
from one form to another. Binary data are removed from a register or memory and
converted to ASCII for the video display. ASCII data are converted to binary as they are
typed on the keyboard.
BINARY TO ASCII
2 METHODS
1. By aam instruction if the number is less than 100

2. By a series of decimal divisions (divide by 10)
METHOD 1
.model small
.code
.startup
mov al, 4ah
call disp
.exit
disp proc near
mov ah, 0
aam
add ah, 20h
cmp ah, 20h
je disp1
add ah, 10h
disp1: mov dl, ah
mov ah, 6
push ax
int 21h
pop ax
mov dl, al
add dl, 30h
int 21h
ret
disp endp
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end
METHOD 2
1. Divide by 10 and save reminder on the stack as a significant bcd digit

2. Repeat step 1 until quotient is 0
3. Retrieve each remainder and add 30h to convert to ascii before displaying
.model small
.stack
.code
mov ax,@data
mov ds,ax
mov ax, 04a3h
call dispx
mov ah, 4ch
int 21h
dispx proc near
mov cx, 0
mov bx, 10
dispx1: mov dx, 0
div bx
push dx
inc cx
or ax, ax
jnz dispx1
dispx2: pop dx
mov ah, 6
add dl, 30h
int 21h
loop dispx2
ret
dispx endp
end
ASCII TO BINARY CODE CONVERSION
1.
2.
3.
4.
Begin with a binary result of 0.

Subtract 30h from the character typed on keyboard to convert it to bcd
Multiply result by 10, then add the new bcd digit
Repeat steps 2 and 3 until the character typed is not an ascii coded number
.model small
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.data
temp dw ?
.code
mov ax, @ data
mov ds, ax
call readn
mov temp, ax
mov ah, 4ch
int 21h
readn proc near
mov cx, 10
mov bx, 0
; result
readn1: mov ah, 1
int 21h
cmp al, 0
; if below 0
jb readn2
cmp al. 9
; if above 9
ja readn2
sub al, 0
; convert to binary
push ax
; save digit
mov ax, bx
mul cx ; multiply result by 10
mov bx, ax
pop ax
mov ah, 0
add bx, ax
; add digit value to result
jmp readn1
readn2: mov ax, bx
ret readn endp
end
READING HEXADECIMAL NUMBER
HEXADECIMAL
0-9
A-F
a-f
ASCII
CODE
30-39
41H-46H
61H-66H
.model small
.stack
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.data
temp dw ?
.code
mov ax,@data
mov ds,ax
; the resulted binary equivalent value to be stored

;initialize ds
call readh
mov temp, ax
mov ah,4ch
int 21h
readh proc near
mov cx, 4
mov si. cx
mov bx, 0
readh1: mov ah, 1
int 21h
call conv
shl bx, cl
add bl, al
dec si
jnz readh1
mov ax, bx
ret
readh endp
;ascii coded form
conv proc near

cmp al,9
jbe conv2
cmp al, a
jb conv1
sub al, 20h
conv1: sub al, 7
conv2: sub al, 30h
ret
conv endp
end
DISPLAYING HEXADECIMAL NUMBER
.model small
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.code
.startup
mov ax, 0abch
call disph
.exit
disph proc near
mov cl, 4
; load rotate count
mov ch, 4 ; load digit count
h1: rol ax, cl
; position the digit
push ax
and al, 0fh
add al, 30h ; convert to ascii
cmp al, 9
jbe h2
add al, 7
h2: mov ah, 2
mov dl, al
int 21h
pop ax
dec ch
jnz h1
ret
disph endp
; display hex digit
end
The date is read from the system by using INT 21H function call number 2AH. This
leaves the day of the week in AL, the year in CX, the day of the month in DL, and
the month in DH.
The date is set by using INT 21h and function no. 2bh in AH register with the day of
the week in AL, the year in CX, the day of the month in DL, and the month in DH.
The time is read from the system DOS, using INT 21H function call number 2CH.
This returns with hours in CH, minutes in CL, Seconds in DH, hundredths of
second in DL.
The date is set by using INT 21h and function no. 2dh in AH register with hours in
CH, minutes in CL, Seconds in DH, hundredths of second in DL.
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PROGRAM TO READ SYSTEM TIME
.model small
.data
.code
disp macro char
push ax
push dx
mov dl, char
mov ah,2
int 21h
pop dx
pop ax
endm
mov ax, @data
mov ds, ax
call times
mov ah, 4ch
int 21h
; The time is available from DOS, using INT 21H function call number 2CH.
; This returns with hours in CH and minutes in CL. Also available are seconds ; in
DH and hundredths of second in DL.
times proc near

mov ah, 2ch
int 21h
; get time, hours in ch and minutes in cl registers
mov bh, a
cmp ch, 12
jb times1
; set a for am
; if below 12:00 noon
mov bh, p
sub ch, 12
; set p for pm
; adjust to 12 hrs
times1: or ch, ch
jne times2
mov ch, 12
; test for 0 hrs

; if not 0 hrs
; change 0 hrs to 12
times2: mov al, ch

mov ah, 0
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aam
; convert hours into unpacked bcd format
times3: add ax, 3030h; convert units place

push ax
disp ah
; display tens place
pop ax
disp al
; display units place
disp :
; display colon
mov al, cl
mov ah, 0
aam
; convert minutes
add ax, 3030h

push ax
disp ah
; display tens
pop ax
disp al
disp
disp bh
disp .
disp m
disp .
; display units
; display space
; display a or p
; display .
; display m
; display .
ret
times endp
end
PROGRAM TO READ SYSTEM DATE
.model small
.data
.code
disp macro char
push ax
push dx
mov dl, char
mov ah,2
int 21h
pop dx
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pop ax
endm
mov ax, @data
mov ds, ax
call dates
mov ah, 4ch
int 21h
; The date is available by using INT 21H function call number 2AH. This
leaves the day of the week in AL, the year in CX, the day of the month in
and the month in DH.
;
; DL,
dates proc near

mov ah, 2ah
int 21h
push dx
mov al, dl
mov ah, 0
aam
; get day of the month
dates1: add ax, 3030h

push ax
disp ah
; display tens
pop ax
disp al
; display units
disp .
pop dx
mov al, dh
mov ah, 0
aam
dates2: add ax, 3030h
push ax
disp ah
pop ax
disp al
; get month
; display tens
; display units
disp .
dates3: disp 2
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disp 0
dates4: sub cx, 2000
mov ax, cx
aam
add ax, 3030h
push ax
disp ah
pop ax
disp al
ret
dates endp
end
; scale to 00-99
; convert to bcd
; convert to ascii
; display tens
; display units
USING THE KEYBOARD AND DISPLAY

READING THE KEYBOARD WITH DOS FUNCTIONS
The keyboard of a personal computer is read via a DOS function call, which uses
INT 21H. Data read from the key board are either in ASCII coded form or in extended
ASCII coded form. Each function key has 4 sets of codes selected by the function key
alone, shift-function key combination, the alternate-function key combination and the
control-function combination.
There are three ways to read the keyboard.
The first method reads a key and echoes (or displays) the key on the video screen. The
second method tests to see if the key is pressed & if it is, it reads the key else returns
without any key. The third method allows an entire character string or line to be read
from the keyboard.
1. Reading a key with an ECHO:

DOS function number 01H is used. If a key is pressed, the value of the key pressed is
stored in the AL register. This function automatically echoes the character typed, onto the
screen. If AL=00H, the function call must be invoked again to read an extended ASCII
character. It responds to the Ctrl-C key combination and exits to DOS if it is typed. It
waits for a key to be typed and until a key is pressed, it doesnt return from the procedure
that processes DOS function CALL.
key proc far

mov ah, 01h
int 21h
or al, al
jnz key1
int 21h
stc
; test for 00h, clear carry

; get extended ascii character
: indicate extended ascii character
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key1: ret
key endp
To read and echo character, the AH register is loaded with DOS function number 01H.
This is followed by INT 21H instruction which calls a procedure that processes DOS
function call. Upon return from INT 21H, the AL register contains the ASCII character
typed; the video display also shows the typed character. If AL=0 after the return, the INT
21H instruction must again be executed to obtain the extended ASCII character. Carry
flag is set to indicate an extended ASCII character and carry flag cleared (0) indicates a
normal ASCII character. When this procedure is called, the CALL instruction might be
followed by a / JC extended / to process the extended ASCII character.
2. Reading a key without an ECHO
DOS function number 06H reads a key without an echo to the screen. It also allows
extended ASCII characters and does not respond to control-c key combination. The value
of key typed will be stored in AL register. This function uses AH for function number
06H and DL =0FFH to indicate that the function call (INT 21H) will read the keyboard
without an echo. It returns from the INT 21H, even if no key is typed.
If a character is read, the zero flag (ZF) indicates whether a character was typed. A zero
condition (ZF=1) indicates that no key was typed, and a non zero condition (ZF=0)
indicates that AL contains the ASCII code of the key typed or a 00H. If AL=00H, the
function must again be invoked to read an external ASCII character from the keyboard.
keys proc far
mov ah, 06h
mov dl, 0ffh
int 21h
je keys
or al, al
jnz keys1
int 21h
stc
keys1: ret
keys endp
; if no key is typed
; test for 00h, clear carry
; get extended ascii character
; indicate extended ascii character
3. Read an entire line with an ECHO
Function call number 0AH reads an entire line of information or data up to 255
characters, from the keyboard. It continues to acquire the keyboard data or read the
keyboard (displaying data as typed) until either the specified number of characters are
typed or until the enter key is typed .This function requires that AH=OAH & DS:DX
address the keyboard buffer (a memory area where ACII data are stored) i.e DX contains
the offset address of the buffer. The first byte of the buffer area must contain maximum
number of keyboard characters read by this function (maximum number can be 255). The
DKDEPTOFTCE,APSCE
Page88

second byte of the buffer contains the count of the actual number of characters typed, and
the remaining locations in buffer contain the ACII keyboard data.
.model small
.data
buf db 257 dup (?),$
.code
.startup
line proc
mov ah, 0ah
int 21h
ret
line endp
start: mov buf, 255
lea dx, buf
call line
.exit
end
WRITING TO VIDEO DISPLAY WITH DOS FUNCTIONS
Video data are displayed in a number of different ways with DOS function calls. DOS
function numbers 02H or 06H can be used to display one character at a time of function
or 09H can be used to display an entire string of characters.
1. Displaying one ASCII character
If AH=02H and DL=ASCII character to be displayed, then the function called INT 21H
normally displays the data in DL on the video screen.
Similarly if AH=06H and DL = ASCII character to be displayed, then this function
displays the ASCII character on the video screen.
.model small
.code
disp macro a
mov ah, 06h
mov dl, a
int 21h
endm
.startup
disp 0dh
*mov ah, 06h
*mov dl, 0dh
; mov ah, 02h
; display carriage return

; mov ah, 02h
DKDEPTOFTCE,APSCE
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*int 21h
disp 0ah
; display line feed
*mov ah, 06h

*mov dl, 0ah
*int 21h
; mov ah, 02h
.exit
end
2. Displaying a character string
A character string is a series of ASCII coded character that end with a $ when used with
DOS function calls number 09H. This function requires that DS:DX address the character
string to be displayed, before executing the INT 21H instruction. i.e. DX contains the
offset address of the string to be displayed.
.model small
.data
mes db 13, 10,this is a test line ,$
.code
.startup
mov ah, 09h
mov dx, offset mes
int 21h
.exit
end
Program that displays ab followed by carriage return and line feed combination
using macro
.model small
.code
disp macro var
mov dl, var
mov ah, 6
int 21h
endm
.startup
disp a
; display a
*mov ah, 06h

*mov dl, a
*int 21h
mov al, b
; move b to al
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disp al
; display contents of al
*mov ah, 06h

*mov dl, al
*int 21h
disp 13
; display carriage return
*mov ah, 06h

*mov dl, 13
*int 21h
disp 10
; display line feed
*mov ah, 06h

*mov dl, 10
*int 21h
.exit
end
ALP: Conversion from decimal to binary
.model small
.data
D db 37h
B db ?
.code
.startup
mov bl, D
and bl, 0f0h
mov cl, 4
shr bl, cl
mov al, 0ah
mul bl
mov dl, D
and dl, 0fh
add al, dl
.model small
.data
D db 37h
B db 0h
.code
.startup
L1: cmp D, 09h
jle L2
sub D, 10h
add B, 0ah
jmp L1
L2: mov al, D
add B, al
.exit
end
mov B, al
.exit
end
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Page91
ALP: Binary to decimal
.model small
.data
D db ?, ?
B db 0ffh
.code
.startup
mov al, B
mov ah, 0h
mov bl, 100 ; =64h
div bl ; Q=al=02h, R=ah=37h
mov D, al
mov bl, 10 ; =0ah
mov al, ah
mov ah, 0h
div bl ; Q=al=05h, R=ah= 05h
mov cl, 4
shl al, cl
add al, ah
mov D+1, al
.exit
end
.model small
.data
D db 0h
B db 0ffh
.code
.startup
L1: cmp B, 09h
jle L2
sub B, 0ah
add D, 10h
daa
jmp L1
L2: mov al, B
add D, al
.exit
end
ALP: LCM (another method)

.model small
.data
m dw 0010h
n dw 0006h
lcm dw ?
.code
.startup
mov ax, m
mov bx, n
L1: cmp ax, bx
je L3
jb L2
add bx, n
jmp L1
L2: add ax, m
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Page92

jmp L1
L3: mov lcm, ax
.exit
end
ALP: packed BCD to 2 ASCII characters
.model small
.data
bcd db 59h
ascii db ?, ?
.code
.startup
mov ah, bcd
and ah, 0f0h
mov cl, 4
shr ah, cl
mov al, bcd
and al, 0fh
add ax, 3030h
mov ascii, ax
.exit
end
ALP: convert 2 ASCII characters to packed BCD
.model small
ascii db 5, 9
bcd db ?
.code
.startup
mov ah, ascii
mov al, ascii+1
sub ax, 3030h
mov cl, 4
shl al, cl
shr ax, cl
mov bcd, al
.exit
end
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Page93
ALP: average of 2 numbers
.model small
.data
n1 dw 1122h
n2 dw 2233h
N equ 2
avg dw ?, ?
.code
.startup
mov dx, 0
mov bx, N
mov ax, n1
add ax, n2
jnc next
inc dx
next: div bx
mov avg, ax
mov avg+2, dx
.exit
end
(sum of numbers do not generate carry)

.model small
.data
n1 dw 1122h
n2 dw 2233h
N equ 2
avg dw ?, ?
.code
.startup
mov ax, n1
add ax, n2
shr ax,1
mov avg, ax
.exit
end
ALP: sort a given set of 16 bit unsigned integers into ascending order using
insertion sort algorithm
.model small
.stack
.data
a dw 0004h, 0003h, 0001h, 0002h
L dw ($-a)/2
.code
mov ax,@data
; initialize the ax register
mov ds,ax
;initialize ax value to ds register
mov cx,02h
;initialize 2 to cx register
ol:mov dx, cx
dec dx
mov si, dx
add si, si
mov ax, a[si]
inl:cmp a[si-2], ax
jbe next
mov di, a[si-2]
DKDEPTOFTCE,APSCE
Page94

mov a[si], di
dec si
dec si
dec dx
jnz inl
next:mov a[si], ax
inc cx
cmp cx,L
jbe ol
mov ah,4ch
int 21h
end
;yes, terminate the program
ALP: sort a given set of 8bit unsigned integers into ascending order using the
bubble sort algorithm.
.model small
.stack
.data
a db 0dh,0ch,0ah,0bh,0eh
L dw $-a
;calculate the size of numbers
.code
mov ax,@data
;initialize the data segment
mov ds,ax
mov bx,L
;the number of data byte is initialized in bx register
dec bx
;load bx with (n-1)
nxtpass:mov cx,bx
;save the count in cx register
mov si,0
;initialize the pointer
nxtcomp:mov al,a[si]
;load the data in to al pointed by si
inc si
;increment the point
cmp al,a[si]
;is the content of al less than that of si pointed data?
jb next
;yes, go to next
xchg al,a[si]
;no, exchange two data in memory
mov a[si-1],al ;repeat till the end of the memory
next:loop nxtcomp
;has all the comparison over in this pass?
;no, go to nxtcomp to continue
dec bx
;has all the passes completed?
jnz nxtpass
;no, go to nxtpass
mov ah,4ch
;terminate the program
int 21h
end
ALP: sort a given set of 8bit unsigned integers into ascending order using the
selection sort algorithm.
.model small
DKDEPTOFTCE,APSCE
Page95

.data
a db 44h, 11h, 22h, 66h
L dw $-a
NC dw ?
; no. of comparisons
.code
.startup
mov dx, L
decd x
mov NC, 0
OL: mov cx, dx
mov si, 0
mov ah, a[si]
mov bx, si
IL: inc si
inc NC
cmp ah, a[si]
jb go_on
mov ah, a[si]
mov bx, si
go_on: loop IL
xchg ah, a[si]
mov a[bx], ah
decd x
jnz OL
mov ah, 4ch
int 21h
end
ALP: find whether a given byte is in the string using Linear search. Find out the
relative address of the byte from the starting location of the string.
.model small
.data
cr equ 13
Lf equ 10
a db 55h, 33h, 44h, 66h, 22h
L dw $-a
srckey db 35h
asc1 equ (srckey/10h) + 0
asc2 equ (srckey mod 10h) + 0
msg1 db element ,asc1,asc2,found at position:
res db ?, cr, Lf, $
msg2 db element ,asc1,asc2, not found, cr, Lf, $
.code
DKDEPTOFTCE,APSCE
Page96

.startup
mov es, ax
cld
lea di, a
mov bx, di
mov al, srckey
mov cx, L
repne scasb
jz success
lea dx, msg2
jmp disp
success: dec di
sub di, bx
add di, 30h
mov res, di
lea dx, msg1
disp: mov ah, 09h
int 21h
.exit
end
ALP: implement a binary search algorithm. Assume that the data consists of sorted
16 bit unsigned integers. The search key is also a 16-bit unsigned integer.
.model small
.stack
.data
msg1 db 'search fails $'
msg2 db 'search successful position is:'
result db ?,$
array dw 00ffh,01feh,23fdh,45fch,0abfbh,0bbfah,0cdf0h,0eeeeh
L dw ($-array)/2
key dw 0eeeeh
.code
mov ax,@data
;initialize the data segment
mov ds,ax
mov bx, 1
mov dx, L
mov cx, key
again:cmp bx, dx
ja fail
mov ax, bx
add ax, dx
DKDEPTOFTCE,APSCE
Page97

shr ax, 1
mov si, ax
dec si
add si, si
cmp cx, array [si]
jae big
dec ax
mov dx, ax
jmp again
big: je success
inc ax
mov bx, ax
jmp again
success: mov result, al
add result, 30h
lea dx, msg2
jmp display
fail: lea dx, msg1
display: mov ah, 9
int 21h
exit: mov ah, 4ch
int 21h
end
; terminate the program normally
ALP: Find largest/ smallest byte in an array.
.model small
.data
count equ 05h
largest db 01h dup(?)
list db 52h, 23h, 26h, 45h, 15h
.code
mov ax, @data
mov ds, ax
lea si, list
mov cl, count
mov al, [si]
dec cl
again:cmp al, [si+1]
jnc next
;(jc next for smallest number)
mov al, [si+1]
DKDEPTOFTCE,APSCE
Page98

next: inc si
dec cl
jnz again
lea di, largest
mov [di], al
mov ah, 4ch
int 21h
end
ALP: multiply two 3 X 3 matrices of signed 8 bit integers. Assume each of the
elements of the product matrix can be stored in 1 byte locations.
Algorithm:
for i=1 to 3
for j= 1 to 3
c[i,j]= 0
for k= 1 to 3
c[i, j]= c[i, j] + a[i, k] * b[k, j]
end
end
end
.model small
.data
ar1 db 1, 2, -3
ar2 db 4, 5, 6
ar3 db 2, -1, 3
br1 db 2, 4, -4
br2 db 3, -2, 5
br3 db 1, 5, 2
c db 9 dup (?)
L2 db ?
L1 db ?
.code
.startup
mov bp, 0
mov L2, 3
lea si, ar1
loop1: lea di, br1
DKDEPTOFTCE,APSCE
Page99

mov L1, 3
loop2: call matprod
mov ds:[bp], dl
inc bp
add di, 3
dec L1
jne loop2
add si, 3
dec L2
jne loop1
.exit
matprod proc
mov cx, 3
mov bx, 0
mov dl, 0
back: mov al, [si][bx]
imul byte ptr [di][bx]
add dl, al
inc bx
loop back
ret
matprod endp
end
ALP: compute nCr given n and r, using recursive procedure.
Algorithm:
if r= 0 or r= n then nCr=1
if r= 1 or r= n-1 then nCr=n
in other cases, nCr=(n-1)Cr +(n-1)C(r-1)
.model small
.data
n db 4
r db 2
ncr db ?
.code
.startup
DKDEPTOFTCE,APSCE
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mov ncr, 0
mov al, n
mov bl, r
call encr
.exit
encr proc
p1:
cmp al, bl
je p8
p2:
cmp bl, 0
je p8
p3:
cmp bl, 1
je p10
p4:
dec al
cmp bl, al
je p9
p5:
push ax
push bx
call encr
p6:
pop bx
pop ax
dec bl
push ax
push bx
call encr
p7:
pop bx
pop ax
ret
p8:
inc ncr
ret
p9:
inc ncr
p10: add ncr, al
ret
encr endp
end
ALP: compute nth term of Fibonacci sequence using recursive procedure
Algorithm:
if n= 0, then f[n]=0
In other cases, f[n]=f[n-1] + f[n-2]
DKDEPTOFTCE,APSCE
Page101

.model small
.data
n db 5
fib dw ?
.code
.startup
mov bl, n
mov fib, 0
call fibo
.exit
fibo proc
cmp bl, 0
je exit1
cmp bl, 1
je exit2
dec bl
push bx
call fibo
pop bx
dec bl
call fibo
ret
exit1: ret
exit2: inc fib
ret
fibo endp
end
ALP: find Fibonacci sequence from 0 to N using recursive procedure.
Algorithm:
In other cases, f[n]=f[n-1] + f[n-2]
DKDEPTOFTCE,APSCE
Page102

.model small
.data
n db 10
fib db 15 dup (?)
.code
.startup
mov bx, 0
newterm: mov dl, 0
push bx
call fibo
pop bx
cmp dl, n
ja exit
mov fib[bx], dl
inc bx
jmp newterm
.exit
fibo proc
cmp bx, 0
je exit1
cmp bx, 1
je exit2
dec bx
push bx
call fibo
pop bx
dec bx
call fibo
ret
exit1: ret
exit2: inc dl
ret
fibo endp
DKDEPTOFTCE,APSCE
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DKDEPTOFTCE,APSCE
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INSTRUCTION SET, PROCEDURES, MACROS

SEGMENT OVERRIDE PREFIX

The operands in a program can be modified by using arithmetic or logic operands.

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

Exchanges the contents of AL with CL

IN and OUT: These instructions perform I/O operations. The contents of AL or AX

8 bits are input to AL from I/O port P8

ALP: Interchange contents of 2 bytes at memory locations represented by opr1 &

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

invalid: mov al, 00h

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

mov ah, 4ch

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

DI then increment or decrement depending on the direction flag. The destination

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

REPNE prefix for SCASW

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

mov cx, length ascii_strg

INSTRUCTION SET, PROCEDURES, MACROS

strg2 db talk polite, $

mov ax, @data

mov ax, @data

INSTRUCTION SET, PROCEDURES, MACROS

mov ax, @data

mov ax, @data

ALP: check whether a string is palindrome or not

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

mov si, src_addr

mov si, src_addr

INSTRUCTION SET, PROCEDURES, MACROS

mov ah, 4ch

INSTRUCTION SET, PROCEDURES, MACROS

mov ah, 4ch

lea dx, msg1

INSTRUCTION SET, PROCEDURES, MACROS

INSTRUCTION SET, PROCEDURES, MACROS

Dst dst + src

PERFORM DECIMAL ADJUST AFTER ADDITION (DAA INSTRTUCTION)

INSTRUCTION SET, PROCEDURES, MACROS