8086 INTERFACING

8086 INTERFACING
.
DIFFERENCE BETWEEN 8088 AND 8086
8088
1. has 8 bit data bus and thus, 8 bit ALU.
2. The address bus A8-A15 is not
multiplexed and hence no need to be
latched.
3. Since the data is only 8 bit, the memory
is not organized into lower and higher
banks and hence the signal BHE is not
required.
4. For word operation, the memory is
accessed twice. Thus there is increase in
execution time.
5. The size of instruction queue is 4 bytes.
6. The data through data bus is buffered
using 1 transceiver (bidirectional buffers).
7. Memory or IO device is identified by
IO/M bar signal.
8. BHE pin is not present, instead the pin is
named as SS0 bar

8086
1. has 16 bit data bus and hence 16 bit
ALU.
2. The higher order data bus is multiplexed
with address lines (AD8-AD15)
3. To realize 16 bit data, the external
memory is organized into lower and higher
banks. These banks are selected using A0
and BHE respectively.
4. If the address is even, 16 bit data can be
accessed in 1 bus cycle.
5. The size of instruction queue is 6 bytes.
6. The data through data bus is buffered
using 2 transceivers (bidirectional buffers)
7. The corresponding signal is M/IO bar.
8. BHE is used to select higher bank of the
memory.

DELAY CALCULATION
mov cx, count
back: dec cx
jnz back

clock cycles required

4
2
16/4

Total clock cycles required to execute the given program:

1st instruction----- 4 clk cycles
in loop, 2nd & 3rd instructions---------- (count 1)(2 + 16) clk cycles
last loop--------------- (2 + 4) clk cycles
= 4 + 2(count) + 16(count 1) +4 = [18(count)-8] clk cycles
Required delay time
Number of required clk cycles=
time for 1 clk cycle
required clk cycle + 8
count=
18
Let clock frequency= 10MHz, i.e. time period= 0.1 s. Total time= [18(count)8]X(0.1s)
In the above eg, [18(count)-8](0.1 X 10-6 s) = 20 X 10-3 s
18(count)-8= 200000, count= 200008/ 18= 11112 = 2B68H
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TIMER DELAY USING NESTED LOOP
mov bx, c1
loop1: mov cx, c2
loop2: dec cx
jnz loop2
dec bx
jnz loop1
Total clock cycles required to execute the given program:
4+4c1+[2c2+(c2-1)16+4]c1 +2c1+(c1-1)16+4= 18c1c2+10c1-8
If c1=50, c2=100, Total clock cycles required = 18c1c2+10c1-8 = 18(100)(50)+10(50)8=90492
Total time= 90492 X 1s=90.492 ms
DIFFERENT METHODS OF INTERFACING I/O DEVICES
I/O mapped I/O (Isolated I/O): It is the most common I/O data transfer technique. The
term isolated indicates that the I/O locations are isolated from the memory system in a
separate I/O address space. The address for the I/O ports is separate from the memory and
is 8 or 16 bit. It is 8 bit for direct addressing, and 16 bit for indirect (variable) addressing.
Separate control signals for I/O read and I/O write are generated, RD, WR, M / IO = 0 in
minimum mode configuration of 8086 and IORC, IOWC generated by 8288 in maximum
mode configuration of 8086. Maximum number of I/O devices that can be connected are
256 for direct and 65536 for indirect addressing. This scheme requires decoding of 8 or
16 address lines and hence comparatively less hardware is required. Memory can be
expanded to its full size but the disadvantage of this scheme is that data is transferred
between 8086 and I/O device only by IN and OUT instructions.
Memory mapped I/O: In this scheme, the address of I/O devices is 20 bits and is
connected as if it is a memory location. Any instruction that transfers data between 8086
and memory can be used for transferring data between 8086 and I/O devices. The same
control signals used for accessing the memory are used for accessing the I/O devices,
RD, WR, M / IO = 1 in minimum mode configuration of 8086 and MRDC, MWTC
generated by 8288 in maximum mode configuration of 8086. Theoretically, maximum
number of I/O devices that can be accessed is 1M byte. This scheme requires decoding
of 20 address lines and hence more hardware is required. The main disadvantage of this
scheme is that a portion of memory is used as the I/O map. This reduces the amount of
memory available for
applications.
(Generation of IOR and
IOW in minimum mode)

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DIFFERENCE BETWEEN I/O MAPPED I/O AND MEMORY MAPPED I/O

DEVICES
I/O mapped I/O (Isolated I/O)
1. The address for the I/O ports is separate
from the memory and is 8 or 16 bit. It is 8
bit for direct addressing, and 16 bit for
indirect (variable) addressing.
2. In this IN and OUT instructions are used
to transfer data through I/O ports.
3. I/O device is activated or selected when
M / IO is low.
4. Number of I/O devices that can be
connected are 256 for direct and 65536 for
indirect addressing.
5. This scheme requires decoding of 8 or
16 address lines and hence comparatively
less hardware is required.

Memory mapped I/O

1. In this scheme, the address of I/O
devices is 20 bits and is connected as if it is
a memory location.
2. All memory related instructions can be
used to access I/O device.
3. I/O device is activated or selected when
M / IO is high.
4. Maximum number of I/O devices
connected can be 1M theoretically.
5. This scheme requires decoding of 20
address lines and hence more hardware is
required.

PROGRAMMABLE PERIPHERAL INTERFACE (PPI) 8255

The parallel input-output port chip 8255 is also called as programmable peripheral inputoutput port. The Intels 8255 is designed for use with Intels 8-bit, 16-bit and higher
capability microprocessors.
It has 24 input/output lines which may be individually programmed in two groups of
twelve lines each, or three groups of eight lines.
The two groups of I/O pins are named as Group A and Group B. Each of these two
groups contains a subgroup of eight I/O lines called as 8-bit port and another subgroup of
four lines or a 4-bit port. Thus Group A contains an 8-bit port A along with a 4-bit port C
upper.
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The port A lines are identified by symbols PA0-PA7 while the port C lines are identified
as PC4-PC7. Similarly, Group B contains an 8-bit port B, containing lines PB0-PB7 and
a 4-bit port C with lower bits PC0- PC3. The port C upper and port C lower can be used
in combination as an 8-bit port C.
Both the port C are assigned the same address. Thus one may have either three 8-bit I/O
ports or two 8-bit and two 4-bit ports from 8255. All of these ports can function
independently either as input or as output ports. This can be achieved by programming
the bits of an internal register of 8255 called as control word register ( CWR ).
It has a 40 pins of 4 groups.
1. Data bus buffer
2. Read Write control logic
3. Group A and Group B controls
4. Port A, B and C
Data bus buffer: This is a tristate bidirectional buffer used to interface the 8255 to
system databus. Data is transmitted or received by the buffer on execution of input or
output instruction by the CPU. Control word and status information are also transferred
through this unit.
Read/Write control logic: This unit accepts control signals (RD, WR) and also inputs
from address bus and issues commands to individual group of control blocks (Group A,
Group B).
It has the following pins:
a) CS Chip select: A low on this PIN enables the communication between CPU
and 8255.
b) RD (Read) A low on this pin enables the CPU to read the data in the ports or
the status word through data bus buffer.
c) WR (Write): A low on this pin, the CPU can write data on to the ports or on to
the control register through the data bus buffer.
d) RESET: A high on this pin clears the control register and all ports are set to the
input mode
e) A0 and A1 (Address pins ): These pins in conjunction with RD and WR pins
control the selection of one of the 3 ports.
Group A and Group B controls : These block receive control from the CPU and issues
commands to their respective ports.
Group A - PA and PCU ( PC7 PC4)
Group B - PCL ( PC3 PC0)
Control word register can only be written into no read operation of the CW register is
allowed.
a) Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be
programmed in 3 modes mode 0, mode 1, mode 2.
b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be
programmed in mode 0, mode1.
c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer.
This port can be divided into two 4 bit ports and can be used as control signals for
port A and port B. it can be programmed in mode 0.

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BLOCK DIAGRAM

CONTROL WORD

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PIN DETAILS
This buffer receives or transmits data upon the execution of input or output instructions
by the microprocessor. The control words or
status information is also transferred through the
buffer.
The signal description of 8255 is briefly
presented as follows:
PA7-PA0: These are eight port A lines that
acts as either latched output or buffered input
lines depending upon the control word loaded
into the control word register.
PC7-PC4: Upper nibble of port C lines. They
may act as either output latches or input buffers
lines. This port also can be used for generation
of handshake lines in mode 1 or mode 2.
PC3-PC0: These are the lower port C lines,
other details are the same as PC7-PC4 lines.
PB0-PB7: These are the eight port B lines
which are used as latched output lines or
buffered input lines in the same way as port A.
RD: This is the input line driven by the microprocessor and should be low to indicate
read operation to 8255.
WR: This is an input line driven by the microprocessor. A low on this line indicates
write operation.
CS: This is a chip select line. If this line goes
low, it enables the 8255 to respond to RD and WR
signals, otherwise RD and WR signal are
neglected.
A1-A0: These are the address input lines and
are driven by the microprocessor. These address
lines are used for addressing any one of the four
registers, i.e. three ports and a control word
register. In case of 8086 systems, if the 8255 is to
be interfaced with lower order data bus, the A0
and A1 pins of 8255 are connected with A1 and
A2 respectively.
D0-D7: These are the data bus lines those carry
data or control word to/from the microprocessor.
RESET: A logic high on this line clears the
control word register of 8255. All ports are set as
input ports by default after reset.

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MODE 1

MODE 1 INPUT

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MODE 1 OUTPUT

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MODE 2

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MODE SUMMARY

STATUS WORD

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MODE 1 STATUS WORD

MODE 2 STATUS WORD

INTERFACING A MICROPROCESSOR TO KEYBOARDS

KEYBOARD TYPES
1. MECHANICAL KEY SWITCHES:
When key is pressed, two pieces of metal are pushed together. The actual switch elements
are often made of a phosphor bronze alloy with gold plating on the contact areas. The key
switch usually contains a spring to return the key to the non pressed position and perhaps
a small piece of foam to help damp out bouncing. Some mechanical key switches now
consist of a molded silicone dome with a small piece of conductive rubber on the
underside. When a key is pressed, the rubber foam shorts two traces on the printed circuit
board to produce the key pressed signal. Higher quality mechanical switches typically
have a rated lifetime of about 1 million keystrokes. The silicone dome type typically last
25 million keystrokes.
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Disadvantages: They suffer from contact bounce.
A pressed key may make and break contact
several times before it makes solid contact. The
contacts may become oxidized or dirty with age,
so they no longer make a dependable connection.
2. MEMBRANE KEYSWITCHES:
These are a special type of mechanical switch.
They consist of a three layer plastic or rubber
sandwich. The top layer has a conductive line of
silver ink running under each row of keys. The
middle layer has a hole under each key position.
The bottom layer has a conductive line of silver
ink running under each column of keys. When
key is pressed, it pushes the top ink line through
the hole to contact the bottom ink line.
Advantage: They can be made as very thin,
sealed units.
3. CAPACITIVE KEY SWITCHES:
It has 2 small metal plates on the printed circuit board and another metal plate on the
bottom of a piece of foam. When key is pressed, the movable plate is pushed closer to the
fixed plate. This changes the capacitance between the fixed plates. Sense amplifier
circuitry detects this change in capacitance and produces a logic level signal that
indicates a key has been pressed.
Advantage: These have a rated lifetime of about 20 million keystrokes.
Disadvantages: Specialized circuitry is needed to detect the change in capacitance.
4. HALL EFFECT KEY SWITCHES:
It takes advantage of the deflection of a moving charge by a
magnetic field. A reference circuit is passed through a
semiconductor crystal between two opposing faces. When a
key is pressed, the crystal is moved through a magnetic field
which has its flux lines perpendicular to the direction of current
flow in the crystal. Moving the crystal through the magnetic
field causes a small voltage to be developed between two of the
other opposing faces of the crystal. This voltage is amplified
and used to indicate that a key has been pressed.
Disadvantage: Hall Effect keyboards are more expensive
because of the more complex switch mechanism
Advantage: They are very dependable and have typical rated
lifetime of 100 million or more keystrokes.
KEYBOARD CIRCUIT CONNECTIONS AND INTERFACING
In most keyboards, the key switches are connected in a matrix of rows and columns.
Getting meaningful data from a keyboard requires 3 major tasks.
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1. Detect a key pressed.
2. Debounce the key pressed
3. Encode the key pressed (produce a standard code for the pressed key)
The three tasks can be done with hardware, software or a combination of both depending
on application.
DEBOUNCER CIRCUIT
A key is a type of push button switch, toggle switch, or electromechanical relay, having
spring contacts. Whenever a mechanical push-button is pressed or released once, the
mechanical component of the key do not change the position smoothly, rather, it
generates a transient response. These transient variations may be interpreted as the
multiple key pressures and responded accordingly by the microprocessor system.

To avoid this problem, there are two schemes:

1. HARDWARE DEBOUNCING METHOD: A bistable multivibrator or a latch is
used at the output of the key debounce.
In the above circuit, output of flipflop is logic 1 when key is at position A
(unpressed) and logic 0 when key is at position B. When key is between A and B,
output does not change, preventing bouncing of key output. Thus output does not
change during transition period, eliminating key bouncing.
2. SOFTWARE DEBOUNCING METHOD: The microprocessor should be made to
wait for transient period so that transient response settles down and reaches steady
state.

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8086 INTERFACING
SOFTWARE KEYBOARD INTERFACING
Hexadecimal keypad can be connected to a
couple of microcomputer ports. Rows of the
matrix are connected to 4 output port lines.
Column lines of the matrix are connected to
4 input port lines. Row lines are also
connected to 4 input lines.
When no keys are pressed, the column lines
are held high by the pull up resistors
connected to +5V. Pressing a key connect a
row to a column. If a low is output on a row
and a key in that row is pressed, then the
low will appear on the column which
contains that key and can be detected on the
input port.
In the algorithm, first output lows to all the
rows and check the columns over and over
until the columns are all high. This is done
to make sure that previous key has been
released before looking for the next one.
This is called two-key lock out.

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FLOW CHART
No key pressed, columns are held high. Row enabled by sending 0 to it. If key
pressed, col=0. Port a o/p, port b i/p byte read from i/p port=4 bit code for row
& 4 bit code for column
.model small
.stack
.data
pa dw 20c0h
pb dw 20c1h
pc dw 20c2h
cr dw 20c3h
table db 77h, 7bh, 7dh, 7eh, 0b7h, 0bbh, 0bdh, 0beh, 0d7h, 0dbh, 0ddh, 0de, 0e7,
0ebh, 0edh, 0eeh ; each byte indicates row no. and column no. of the key
.code
.startup
mov dx, cr
mov al, 8bh
out dx, al
call keybrd
.exit
; find the key
keybrd proc near
mov al, 0feh
pushf
mov cl, al
push bx
nxt_row: mov dx, pa
push cx
push dx
out dx, al
mov dx, pb
;send 0s to all rows
in al, dx
mov al, 0
and al, 0fh
m0v dx, pa
cmp al, 0fh
out dx, al
jne encode
; read column to see if all keys are
rol cl, 1
open
mov dx, pb
mov al, cl
wait_open: in al, dx
jmp nxt_row
encode: mov bx, 000fh; counter
and al, 0fh
cmp al, 0fh
in al, dx
try_nxt: cmp al, table[bx]
jne wait_open
je done
;read column to see key pressed
wait_press: in al, dx
dec bx
and al, 0fh
jns try_nxt
mov ah, 01h; pass an error code
cmp al, 0fh
jmp exit
je wait_press
done: mov al, bl
; debounce key press
mov ah, 00h
mov cx, 16eah; 20ms delay
exit: pop dx
delay: loop delay
pop cx
; read column to see if key is still
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8086 INTERFACING
pop bx
popf
ret
keybrd endp
end

pressed
in al, dx
and al, 0fh
cmp al, 0fh
je wait_press

Q. Interface a 4 * 4 keyboard with 8086 using 8255 and write an ALP for detecting a
key closure and return the key code in AL. The debounce period for a key is 10ms.
Use software debouncing technique. The address of port A and port B will
respectively 8000H and 8002H while address of CWR will be 8006H.
ADDRESS
PORT A
PORT B
PORT C
CWR

A15
1
1
1
1

A14
0
0
0
0

A13
0
0
0
0

A12
0
0
0
0

A11
0
0
0
0

A10
0
0
0
0

A9
0
0
0
0

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A8
0
0
0
0

A7
0
0
0
0

A6
0
0
0
0

A5
0
0
0
0

A4
0
0
0
0

A3
0
0
0
0

A2
0
0
1
1

A1
0
1
0
1

Page16

A0
0
0
0
0

8086 INTERFACING
.model small
.data
pa dw 8000h
pb dw 8002h
pc dw 8004h
cr dw 8006h
.code
.startup
mov dx, cr
mov al, 82h ; port A o/p, port B i/p
out dx, al
mov bl, 0
xor ax, ax
mov dx, pa
out dx, al
mov dx, pb
wait: in al, dx
and al, 0fh
cmp al, 0fh
jz wait
call debounce
mov al, 7fh ; to activate a row, send 0
mov bh, 4 ; set row counter
nxtrow: rol al, 1
mov ch, al
mov dx, pa
out dx, pa
mov dx, pb
in al, dx
and al, 0fh
mov cl, 4 ; set column counter
nxtcol: ror al, 1
jnc codekey ; key closure is found when CF=0
inc bl ; increment bl for next binary key code
dec cl
jnz nxtcol
mov al, ch
dec bh
jnz nxtrow
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jmp wait
codekey: mov al, bl
.exit
debounce proc near
moc cl, count ; count=0e2h
back: nop
dec cl
jnz back
ret
debounce endp
end
Q. Scan the 4x4 keypad for key closure and to store the code of the key pressed in a
memory location or display on the screen. Also display row and column numbers of
the key pressed.
(In the given program, one row is enabled by sending logic 1 through port C. If a key is
pressed logic 1 is read through port A.)
LAB PROGRAM (no. of rows=4, no. of SIMPLE PROGRAM TO READ KEY
PRESSED IN MEMORY
columns=4)
.model small
disp macro msg
.stack
lea dx, msg
.data
mov ah, 09h
pa equ ___; address of port A
int 21h
pb equ __; address of port B
endm
pc equ ____; address of port C
cr equ__; address of control register
.model small
cw equ 90h; port A i/p, port C o/p
.stack
row db ?
.data
col db ?
pa equ ___; address of port A
key db ?
pb equ __; address of port B
pc equ ____; address of port C
.code
cr equ__; address of control register
start1:mov ax, @data
cw equ 90h; port A i/p, port C o/p
mov ds, ax
m1 db 13,10,'entered key is:','$'
mov al,cw
m2 db 13,10,'row number is:','$'
mov dx, cr
m3 db 13,10,'column number is:','$'
out dx, al
m4 db 13,10,'press c to continue:','$'
row db ?
start: mov al, 80h
col db ?
mov row, 1
mov col, 1
.code
mov ch, 0
start1:mov ax, @data
mov bl, 4
mov ds, ax
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mov al,cw
mov dx, cr
out dx, al
start: mov al, 80h
mov row, 1
mov col, 1
mov ch, 0
mov bl, 4
nextrow: rol al, 1
mov bh, al
mov dx, pc
out dx, al ; enable one row
mov cl, 4
mov dx, pa
in al, dx
nextcol: ror al, 1
jc display
inc ch
inc col
dec cl
jnz nextcol
mov col, 1
inc row
mov al, bh

x:

nextrow: rol al, 1

mov bh, al
mov dx, pc
out dx, al ; enable one row
mov cl, 4
mov dx, pa
in al, dx
nextcol: ror al, 1
jc display
inc ch
inc col
dec cl
jnz nextcol
mov col, 1
inc row
mov al, bh
dec bl
jnz nextrow
display:
mov key, ch
mov ah, 4ch
int 21h
end

dec bl
jnz nextrow
jmp start

display:disp m1
mov dl, ch
cmp dl, 0ah
jc digit
add dl, 07h
digit: add dl, 30h
mov ah,2
int 21h
add row, 30h
add col, 30h
disp m2
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8086 INTERFACING
mov dl, row
mov ah, 2
int 21h
disp m3
mov dl, col
mov ah, 2
int 21h
disp m4
mov ah, 8
int 21h
cmp al, 'c'
jz x
mov ah, 4ch
int 21h
end

INTERFACING TO ALPHANUMERIC DISPLAYS

Seven segment displays consists of eight LED segments and are available in a single
dual-in-line package (DIP). There is one pin for each segment named from a to g and
another LED for decimal point (dp or h). One pin for power supply is available.

There are two types of seven segment displays- common cathode and common anode.
In common anode type of display, the anodes of all the LEDs is connected together. To
illuminate a segment, the common anode is connected to power supply and segment
inputs a to g is connected to logic 0 or low-level voltage.
In common cathode type of display, the cathodes of all the LEDs is connected together.
To illuminate a segment, the common cathode is connected to ground and segment inputs
a to g is connected to logic 1 or high-level voltage. This forward biases the LEDs and
illuminates them.

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DIRECTLY DRIVING LED DISPLAYS (STATIC DISPLAY)

The BCD to seven segment
display decoder IC 7447
converts 4-bit BCD code
applied at its input into the
patterns required to display
the BCD number in a seven
segment LED. The patterns
generated are active low
outputs, i.e. logic 0 is given as
output. To illuminate the
seven
segment
LEDs,
common anode display is
suitable for use with IC 7447. This circuit connection is referred to as static display
because current is being passed through the display at all times.
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Each segment requires a current between 5 to 30mA to light the LED.
Assume current = 20mA.
Drop across LED when lit= 1.5V
The o/p low voltage for 7447 is a maximum of 0.4V at 40mA
For 20mA, drop= 0.2V
Voltage across current limiting resistor= 5-1.5-0.2= 3.3V = IR

R=

3.3V
= 168 (Standard value= 220)
20mA

This scheme has problem when more displays need to be used.

1. Power consumption is more
If 8 seven segment displays are connected and all are LEDs are glowing. Total
current= 7 LEDs X 8 displays X 20mA = 1.12A
2. Second problem of the static approach is that each display digit requires a
separate 7447 decoder, each of which uses 13mA (assume). The current used by
decoders and LED displays will be several times the current required by the rest
of the circuitry in the instrument.
To solve the problems of static display approach, multiplex method is used.
Q. Assume the port addresses 40h, 42h, 44h and 46h assigned to port a, b, c and
control register of 8255, respectively. Write a program to display the data 7 in the
seven segment display.
.model small
.data
pa equ 40h
pb equ 42h
pc equ 44h
cr equ 46h
cw equ 80h
; port A is output port.
.code
.startup
mov al, cw
out cr, al
mov al, 07h
out pa, al
.exit
end

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MULTIPLEXED DISPLAY
4 seven segment LED displays are connected. Common anode type LEDs are used (Logic
0 to the segment indicates it is enabled or ON). Anodes of the seven segment displays are
connected to +5V through transistors. Cathodes are connected in parallel and then to o/p
of 7447 IC through resistors.

In multiplexed display, segment information is sent to all seven segment displays through
same lines, but only one seven segment is turned ON at a time. The PNP transistors
connected in series with common anode of each seven segment act as an ON and OFF
switch for that display. If a low (logic 0) is sent through port B to the base of a particular
PNP transistor, that transistor would turn ON and connect the common anodes of that
seven segment display to +5V. The segment information sent from port A through 7447
IC would then be displayed on the selected display unit.
After a certain delay (say 2ms), the digit being displayed in turned OFF and then next
digit segment information is sent through port A and next PNP transistor is turned ON.
This process is continued.
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Q. Interface an 8255 with 8086 at 80h as an I/O address of port A. Interface five 7
segment displays with 8255. Write a sequence of instructions to display 1, 2, 3, 4, 5
over the five displays continuously as per their positions starting with 1 at the least
significant position.

In the above diagram, NPN transistors are used. The seven segment displays are common
cathode type. Logic 1 or active high to the base of transistor turns it ON.
ADDRESS
PORT A
PORT B
PORT C
CWR

80h
82h
84h
86h

A7
1
1
1
1

A6
0
0
0
0

A5
0
0
0
0

A4
0
0
0
0

A3
0
0
0
0

A2
0
0
1
1

A1
0
1
0
1

A0
0
0
0
0

Logic 1 to the segment indicates it is enabled or ON (common cathode type display)

.model small
.data
pa equ 80h
pb equ 82h
pc equ 84h
cr equ 86h
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8086 INTERFACING
cw equ 80h ; port A and port B as o/p ports
table db 0cfh, 92h, 86h, 0cch, 0a4h
.code
.startup
again: lea bx, table
mov cl, 5
mov ch, 1 ; 1st number to be dispalyed
mov al, cw
out cr, al
mov dl, 1 ; enable code for least significant 7-seg display
nxtdgt: mov al, ch
xlat
out pa, al
mov al, dl
out pb, al
rol dl
inc ch
dec cl
jnz nxt dgt
jmp again
.exit
end

Q. Display messages APSC with flickering effects on a 7 segment display

interface for a suitable period of time. Ensure a flashing rate that makes it
easy to read both the messages.

For the program below, a non multiplexed seven segment display interfacing is provided
by a set of shift registers and their corresponding common anode seven segment display.
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8086 INTERFACING
.model small
.data
pa equ 20c0h ; ADDRESS OF PORT A
pb equ 20c1h; ADDRESS OF PORT B
pc equ 20c2h; ADDRESS OF PORT C
cr equ 20c3h; ADDRESS OF CONTROL REGISTER
first db 0C6H, 92H, 8CH, 88H
.code
begin: mov ax, @data
mov ds, ax
mov al, 80h
mov dx, cr
out dx, al
mov cx, 05h
next: lea si, first
call flash
call delay
call delay
loop next
mov ah, 4ch
int 21h
flash proc near
push cx
push bx
mov cx, 04h
loop1: mov bl, 08h
mov al, [si]
loop2: rol al, 1
mov dx, pb
out dx, al
push ax
mov dx, pc
mov al, 0ffh
out dx, al
mov al, 00h
out dx, al
pop ax
dec bl
jz next1
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8086 INTERFACING
jmp loop2
next1: inc si
loop loop1
pop bx
pop cx
ret
flash endp
delay proc near
push cx
push bx
mov cx, 08fffh
l1:
mov bx, 0fffh
l2:
dec bx
jnz l2
loop l1
pop bx
pop cx
ret
delay endp
end
Q. With necessary hardware and software, show an interface of seven segment led
display to 8086 processor. Port A provides the segment data input to the display and
port B provides a digit driver code function selecting a particular seven segment
display. Display good.

Common anode type of LEDs is used in the above multiplexed display. Port A outputs
the data to be displayed and port B outputs data to select one seven segment display. PNP
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8086 INTERFACING
transistors are used to connect the common anode point to +5V, when the transistor is
ON (base connected to logic 0)
.model small
.data
table db 0a1h, 0a3h, 0a3h, 90h
.code
.startup
mov al, 80h
out cr, al
again: lea si, table
mov cx, 4
mov ah, 07fh ; 0111 1111
disp:

rol ah, 1
mov al, [si]
out pa, al
mov al, ah
out pb, al
call delay
dec cx
jnz disp
jmp again

delay proc near

mov bx, count
l2:
dec bx
jnz l2
ret
delay endp
end
STEPPER MOTOR
The basic principle of driving the stepper motor is to generate a
rotating magnetic field to which the rotor aligns. The rotating
field is generated in the stator by currents in the two phase
windings. If phase A and B are energized, the rotor can step
from position 1 to position 3, 5, 7 and so on in either direction,
depending on the magnetic flux direction which is controlled by
the current direction in the two windings. This drive is normally
referred to as two-phase-on drive. If only one stator coil is
energized at a time the rotor can step from position 2 to 4, 6, 8
and so on. This drive mode is referred to as one phase-on drive. Both of these two drive
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8086 INTERFACING
modes will result in full stepping, but the full step positions are shifted one half of a full
step.
Half stepping:
If these two drive modes are combined and correct sequences are fed into the windings
the rotor can be made to align at all positions i.e. 1, 2, 3, 4, and so on. This is referred to
as half step mode
The main advantage of half-step is the increased resolution. The main disadvantage of
half step operation is that in the half-step state the motor has only about 70% of the
torque as when driven to the full-step state. This is the direct result of lower flux density
in the stator. In the full-step state the magnetic vector generated by the stator is the vector
sum of the magnetic vectors of the two coils. When both coils are excited evenly, the
vector sum of the two is at a 45 angle and has a magnitude of 2 times the magnitude of
each individual vector. When only one coil is driven, as in the half-step states, the total
magnetic vector is only the vector for one coil. This results in a 30% reduction in torque
for the half-steps. The reduction in torque can be compensated for by increasing the
current in the one driven coil for the half-steps.
A stepper motor is a special motor that rotates in incremental steps, unlike other motors
that run continuously. They find application in printers, plotters, robots, etc. They are
excited by pulses to get incremental displacements. The common step size of stepper
motor ranges from 0.9 to 30 degrees. They are made of permanent magnet rotors with
static field excitation. Two phase excitation and four phase excitation are common. A 4phase motor has 4 stator poles, which are excited by pulses. Each pole winding can be
excited such that the pole can be made either North Pole or a south pole. The number of
teeth or number of poles in the rotor will decide the minimum incremental step angle
when a particular phase is excited. In this arrangement, the poles should be properly
excited in a particular sequence so that the rotor rotates in a particular direction. If the

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8086 INTERFACING
excitation is reversed, the rotor rotates in the reverse direction. A typical stepper motor
has a step angle of 1.8 degrees. This motor has 50 teeth on rotor and 8 poles on stator.

The interfacing of 4-phase stepper motor to

8086 through the 8255 is shown. The stepper
motor has six terminals- 4 terminals A, B, C,
D for excitation and two more terminals for
power supply. The 4 terminals A, B, C, D are
connected to 8255 ports through transistor
drivers. The transistor drivers or buffers are
essential as the port pins cannot directly source
the current required for the motor drive. The
motor terminals have to be excited in a proper
sequence so that the rotor rotates continuously
in one direction. Two types of excitations are possible with 4-phase motor- one-phase
excitation (only one phase of the stepper motor is excited at a time) and two-phase
excitation (two phases are excited at a time). The exciting sequence is fixed for a rotation
in a particular direction. The excitation sequence for the interface diagram shown is in the
table below. The table also shows hexadecimal values to be given to port A assuming
higher order 4 bots of the data are zero.

WAP to drive the stepper motor continuously at 60 rpm. Assume the addresses 80H,
82H, 84H and 86H are assigned to port A, B, C and Control register of 8255
respectively.
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8086 INTERFACING
1 minute= 60 seconds-------------N revolutions
1 second----------------------------- N/60 revolution
1 revolution (=360 degrees) ----------------------60/ N second
1.8 degrees-------------------------------------------- 60 X 1.8/360N = 0.3/N second
For N=60, time delay= 0.3/60= 5ms

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8086 INTERFACING
WAP to drive the stepper motor by 180 degrees. Assume the addresses 80H, 82H,
84H and 86H are assigned to port A, B, C and Control register of 8255 respectively.
The motor coils have to be excited by two-phase excitation method and for anticlockwise rotation.

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8086 INTERFACING

Full step excitation:

1 coil excitation: 01h, 02h, 04h, 08h
2 coil excitation: 03h, 06h, 0ch, 09h
Half step mode: combine both the excitations
03h, 01h, 06h, 02h, 0ch, 04h, 09h, 08h
WAP to rotate stepper motor for 270 degrees in anticlockwise direction
1.8 degrees-------- 1 step
360 degrees ------- 200 steps
270 degrees-------150 steps
.model small
.data
pa equ _________ ; ADDRESS OF PORT A
pb equ _________; ADDRESS OF PORT B
pc equ _________; ADDRESS OF PORT C
cr equ _________; ADDRESS OF CONTROL REGISTER

l1:

.code
mov dx, cr
mov al, 80h
out dx, al
mov cx, 150
mov dx, pc
mov al, 88h
out dx, al
call delay
rol al, 1
loop l1
mov ah, 4ch
int 21h
delay proc near

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8086 INTERFACING
l2:
l3:

push cx
mov cx, 0fffh
mov bx, 0fffh
dec bx
jnz l3
loop l2
pop cx
ret
delay endp
end

WAP to rotate stepper motor in clockwise direction 5 rotations

1 rotation---360 degrees-----200 steps
5 rotations----------------------1000 steps
.model small
.data
pa equ _________ ; ADDRESS OF PORT A
pb equ _________; ADDRESS OF PORT B
pc equ _________; ADDRESS OF PORT C
cr equ _________; ADDRESS OF CONTROL REGISTER
.code
mov dx, cr
mov al, 80h
out dx, al
mov cx, 1000
mov dx, pc
mov al, 88h
l1:

out dx, al
call delay
rol al, 1
loop l1

;for anticlockwise

mov cx, 1000

mov dx, pc
mov al, 88h
l2:

out dx, al
call delay
ror al, 1
loop l2
mov ah, 4ch
int 21h

; for clockwise

delay proc near

push cx
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8086 INTERFACING
l2:
l3:

mov cx, 0fffh

mov bx, 0fffh
dec bx
jnz l3
loop l2
pop cx
ret
delay endp
end

WAP to drive the stepper motor continuously at 60 rpm.

1 minute= 60 seconds-------------N revolutions
1 second----------------------------- N/60 revolution
1 revolution (=360 degrees) ----------------------60/ N second
1.8 degrees-------------------------------------------- 60 X 1.8/360N = 0.3/N second
For N=60, time delay= 0.3/60= 5ms. Calculate the delay for 5ms
WAP to rotate a motor for 64 degrees in clockwise direction. The motor has step
angle of 2 degrees. Use 4 step sequence (2 coils ON at same time)
2 degrees-------- 1 step
360 degrees ------- 180 steps
64 degrees-------32 steps
for movement of 64 degrees, send 8 consecutive 4 step sequences i.e 32 steps.
Excitation: 03h, 06h, 0ch, 09h
WAP to rotate a motor for 180 degrees in anticlockwise direction. The motor has
step angle of 1.8 degrees. Use 4 step sequence (2 coils ON at same time)
1.8 degrees-------- 1 step
360 degrees ------- 200 steps
180 degrees-------100 steps
for movement of 180 degrees, send 25 consecutive 4 step sequences i.e 100 steps.
Excitation: 09h, 0ch, 06h, 03h

Write an algorithm and program for 8086 procedure to drive the stepper motor.
Assume the desired direction of rotation is passed to the procedure in AL (AL=1 is
clockwise, AL=0 is counter clockwise) and the number of steps is passed to the
procedure in CX. Also assume full step mode and delay of 20ms between each step.
.model small
.data
pa equ _________ ; ADDRESS OF PORT A
pb equ _________; ADDRESS OF PORT B
pc equ _________; ADDRESS OF PORT C
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8086 INTERFACING
cr equ _________; ADDRESS OF CONTROL REGISTER
.code
mov dx, cr
mov al, 80h
out dx, al
mov cx, 200
mov al, 1
call step
mov cx, 200
mov al, 0
call step
mov ah, 4ch
int 21h
step proc near
mov dx, pc
cmp al, 1
je clkwise
l1:

mov al, 88h

out dx, al
call delay
rol al, 1
loop l1
jmp fwd

clkwise: mov al, 88h

l2:
out dx, al
call delay
ror al, 1
loop l2
fwd:
ret
step endp
delay proc near
push cx
mov cx, 2B68H
l3:
loop l3
pop cx
ret
delay endp
end

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