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Multi Clock Design

This document provides an introduction to multiple clock domains and clock domain crossing issues in integrated circuit design. It discusses topics such as metastability, data loss, data incoherency, and synchronization techniques like gray coding and handshaking. Examples of synchronous clock domain crossings are also presented, including the use of integer multiple clocks and constant phase differences between clocks. The document concludes with an exercise on designing a dual clock FIFO to transfer data between asynchronous clock domains.

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Roc Kim Sí Điểu
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205 views

Multi Clock Design

This document provides an introduction to multiple clock domains and clock domain crossing issues in integrated circuit design. It discusses topics such as metastability, data loss, data incoherency, and synchronization techniques like gray coding and handshaking. Examples of synchronous clock domain crossings are also presented, including the use of integer multiple clocks and constant phase differences between clocks. The document concludes with an exercise on designing a dual clock FIFO to transfer data between asynchronous clock domains.

Uploaded by

Roc Kim Sí Điểu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 37

Vietnam National University

Integrated Circuit Design Research and Education Center

Hardware Description Language


Verilog HDL

Multiple Clock Domains


D+ Training Program
Lecturer: Ngc Qunh
E-mail:[email protected]

Contents

Product in
Mind

Introduction
Clock Domain Crossing Issues
Synchronous clock domain crossings
examples
Exercise Dual clock FIFO design

(2)

Vietnam National University


Integrated Circuit Design Research and Education Center

Multiple Clock Domains

INTRODUCTION

Introduction

Product in
Mind

cpu_clock
CPU_core

MEM_
CONTROLLER

CPU clock domain

bus_clock

timer_clock
uart_clock
UART

TIMER

Timer clock domain


UART clock domain
(4)

Two clock domains

Product in
Mind
A

FA
C1

FB
C2

Signal A is output of the C1 clock domain and be


captured by the C2 clock domain.
Depending on the relationship between the two clocks,
there could be different types of problems in transferring
data from the source clock to the destination clock.
Along with that, the solutions to those problems can
also be different.
(5)

Vietnam National University


Integrated Circuit Design Research and Education Center

Multiple Clock Domains

CLOCK DOMAIN CROSSING


ISSUES

FF Setup & hold times (review)

Product in
Mind

clock edge

D
CLK
Q

DFF

tsu

setup time

CLK

th

hold time
7

(7)

Data change at clock edge


A generated by C1

Product in
Mind

setup or hold violation

C1
A
C2
B

A sampled by C2

Clock signal is
initially metastable
(8)

Metastability effect
Vdd

on

Product in
Mind

Ileakage

Imax
on

NOT gate

If the unstable data is fed to several other places in the


design, it may lead to a high current flow and even chip
burnout in the worst case.
The design can enter into an unknown functional state,
leading to functional issues in the design.
The propagation delay could be high leading to timing
issues.

(9)

Metastable solution

Product in
Mind

Metastability problems can be avoided by adding


special structures known as synchronizers in the
destination domain. The synchronizers allow sufficient
time for the oscillations to settle down and ensure that a
stable output is obtained in the destination domain. A
commonly used synchronizer is a multi-flop
synchronizer.
A
D

FA

FB

Bsync
D

FB

C1
C2

(10)

Data Loss
A generated by C1

Product in
Mind

A change very closely


with C2 posedge

C1
A
C2
B
Data capture in 2nd
clock cycle

Data capture in 1nd


clock cycle
(11)

No loss data example

Product in
Mind

Clock C1 is twice as fast as the destination clock C2 and


there is no phase difference between the two clocks.
Assume that the input data sequence A generated on the
positive edge of clock C1 is 00110011. The data B captured
on the positive edge of clock C2 will be 0101.
All the transitions on signal A are captured by B, the data is
not lost.
C1
A
C2
B
(12)

Data bit loss

Product in
Mind

C1
A
C2
B

Data bit loss


The data change in the C1 domain must held long enough to
be properly captured in the C2 domain
After every transition on A, at least one C2 clock edge
should arrive where there is no setup or hold violation so that
the source data is captured properly in the destination
domain.
(13)

Data Incoherency

Product in
Mind

C1
X[0]
X[1]

Invalid data

C2
Y[0]
Y[1]

Valid data

X[1:0] signals change from 00 to 11, but Y[1:0] signals


change from 00 to 01 to 11
(14)

MUX recirculation technique


0

Data captured when Bsync = 1


(2 cycles ofA[0]
C2 after EN = 1)
D

Product in
Mind
B[0]
D

FB

FA
C1

0
A[1]
D

B[1]
D

FB

FA
C1

EN
D

FA

FB

Bsync
D

FB

C1
C2

(15)

Gray Encoding to Avoid Data


Incoherence
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Bin [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Gray [3:0]
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000

Product in
Mind

For vector control


signals (multi-bit
signals, such as
address buses), the
usual solution is to use
a Gray code when
crossing a clock domain
boundary. A Gray code
ensures that only a
single bit changes as
the bus counts up or
down.

(16)

Handshaking Data between Clock


Domains (1/2)
B

req
(Transit active)

Product in
Mind

req_sync
D

FB

FB

C2

Clock
Domain
C1

ack_sync

ack

QD

QD

FA

FA

(transit_done)

Clock
Domain
C2

C1
Data bus

(17)

Handshaking Data between Clock


Domains (2/2)
req
(Transit active)

Synchornizer

Clock
Domain
C1

Product in
Mind
Clock
Domain
C2

req_sync

C2
Idle

Idle
ack_sync

Synchornizer

Start
req

Done

ack_sync

go

Wait
req

ack
(transit_done)

C1
!ack_sync

req_sync
Done

Start

Process
ack

Data bus

(18)

Using FIFO for Passing Data


between Clock Domains

Product in
Mind

Dual clock
FIFO
Clock
Domain
C1

C1

C2

Clock
Domain
C2

Dual clock
FIFO

One of the most popular methods of passing data


A dual port memory is used for the FIFO storage.
One port is controlled by the sender, the other port is controlled by
the receiver.
Two control signals are used to indicate if the FIFO is empty, full
(19)

Vietnam National University


Integrated Circuit Design Research and Education Center

Multiple Clock Domains

SYNCHRONOUS CLOCK
DOMAIN CROSSINGS
EXAMPLES

Same frequency, same phase clocks

Product in
Mind

C1
A
C2
B

The clocks C1 and C2 have the same frequency and 0


phase difference.
The clocks C1 and C2 are identical and generated from
the same root clock, the data transfer from C1 to C2 is
essentially not a clock domain crossing.
For all practical purposes, this is the case of a single
clock design.
(21)

Same frequency and constant


phase difference

Product in
Mind

C1
A

C2

3/4 clock
cycle

These are the clocks having the same time period but a
constant phase difference. A typical example is the use of a
clock and its inverted clock.
Another example is a clock which is phase shifted from its
parent clock, for example by T/4 where T is the time period
of the clocks.
(22)

Integer multiple clocks (TC2 = 3TC1)

Product in
Mind

Data change points

The worst case is T time

C1
C2
T
2T
3T

problem of data loss in


the case of fast to slow
clock crossing ?

T, 2T, or 3T time available for data capture


depending on data change point
(23)

Vietnam National University


Integrated Circuit Design Research and Education Center

Questions and
Discussion
(24)

Vietnam National University


Integrated Circuit Design Research and Education Center

Multiple Clock Domains

EXERCISE DUAL CLOCK


FIFO DESIGN

Single clock FIFO

Product in
Mind
clk

rst_n

rd

data_out[7:0]
status signals

data_in[7:0]

wr
26

(26)

Dual clock FIFO

Product in
Mind
wclk domain

wdata

wdata

waddr
FIFO
wptr
and
full
flag

wq2_rptr

wclk
wrst_n

rdata

rdata

wenable

wfull

winc

rclk domain

waddr

raddr

raddr
FIFO
rptr and
empty
flag

rempty

rinc

rq2_rptr

rclk
rrst_n

(27)

Problem

Product in
Mind

Upgrade the single clock FIFO in subject 2 to dual clock


FIFO
Two clock domains are asynchronous
Using Gray code technique for read & write pointers
Checking RTL code with Leda
Simulating the design with ModelSim

(28)

Binary count values sampled in


mid-transition

Product in
Mind

(29)

Binary-to-Gray
b[n-1]

b[n-2]

Product in
Mind
b[n-3]

b[1]

b[0]

Binary to Gray
converter

(MSB)

g[n-1]

gray[0]
gray[1]
gray[2]
gray[3]

=
=
=
=

g[n-2]

bin[0]
bin[1]
bin[2]
bin[3]

g[n-3]

g[0]

^ bin[1];
^ bin[2];
^ bin[3];
^ 1'b0 ; // same as gray[3] = bin[3];

(30)

Product in
Mind

(31)

FIFO full & empty with Binary

Product in
Mind

(32)

Counter with different size problem

Product in
Mind

(33)

Full & empty flags with Gray

Product in
Mind

(34)

FIFO empty flag

Product in
Mind
only use n-1 bits to address the FIFO memory
rbin [ASIZE:0]

rbnext
rinc

binary
reg

rempty

Binary to
Gray
converter

rgnext

rptr [ASIZE:0]
gray
reg

rclk

rrst_n

=?

rempty

rq2_wptr

wptr [ASIZE:0]
rq1_wptr

rptr [ASIZE:0] = rq2_wptr [ASIZE:0]


(35)

FIFO full flag

Product in
Mind
only use n-1 bits to address the FIFO memory
wbin [ASIZE:0]

wbnext
winc

binary
reg

wfull

Binary to
Gray
converter

wgnext

wptr [ASIZE:0]
gray
reg

wclk

{~wptr [ASIZE:ASIZE-1],
wptr [ASIZE-2:0]

=?

wrst_n

wfull

wq2_rptr

rptr [ASIZE:0]
wq1_rptr

{~wptr [ASIZE:ASIZE-1], wptr [ASIZE-2:0] == wq2_rptr


(36)

Vietnam National University


Integrated Circuit Design Research and Education Center

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