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Code No: X0524/R07 Set No. 1

II B.Tech I Semester Regular Examinations, November 2009
DIGITAL LOGIC DESIGN
( Common to Computer Science & Engineering and Information
Technology)
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Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. Convert the following to Decimal and then to Binary.

(a) 123416
(b) ABCD16
(c) 11228
(d) 17268
(e) 99710
(f) 65410 [3+3+3+3+2+2]
2. (a) For the given Boolean function F = xy’z + x’y’z + w’xy + wx’y + wxy.
i. Draw the logic diagram
ii. Simplify the function to minimal literals using Boolean algebra.
(b) Obtain the Dual of the following Boolean expressions. [8+8]
i.AB’C + AB’D + A’B’
ii.A’B’C + ABC’ + A’B’C’D
iii.ABCD + ABC’D’ + A’B’CD
iv. AB + ABC’.
P
3. (a) If F1 (A, B, C, D) =
P (1, 3, 4, 5, 9, 10, 11) + d6, 8 And
F2 (A, B, C, D) = (0, 2, 4, 7, 8, 15) + d9, 12 Obtain minimal SOP expression
for F1 ⊕ F2 using K- map and draw the circuit using NAND gates.
(b) Draw the multiple
-level NAND circuit for the following Boolean - expression:
AB + CD E + BC (A + B) [8+8]
4. (a) Using five lower - order demultiplexer, construct 6 to 64 line demultiplexer
circuit. Use only block diagrams.
(b) Design a Combinational logic circuit with three inputs A, B, C and three
outputs x, y, z. If the binary input is 0, 1, 2, or 3, the binary output is one
greater than the input. When the binary input is 4, 5, 6, or 7, the binary
output is one less than the input. Draw the circuit using three-2 input AND
gates, one 3 input OR gate, one 3 input X - OR gate and one inverter. [4+12]
5. A sequential circuit with 3 D-flip-flops A, B and C has only one input ‘X’ and one
output ‘X’ with following relationship
DA = B ⊕ C ⊕ X, DB = A, DC = B
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(a) Draw the logic diagram of the circuit.
(b) Obtain logic diagram, state table and state diagram. [16]
6. (a) Explain the following systems
i. shift registers
ii. counters.
(b) Draw and explain 4-bit binary ripple counter using D- flip-flops. [10+6]
7. Tabulate the PLA programming table for the four Boolean functions:
A(x,y,z) = Σ ( 1,2,4,6)
B(x,y,z) = Σ ( 0,1,6,7)
C(x,y,z) = Σ ( 2,6)
D(x,y,z) = Σ ( 1,2,3,5,7)
Minimize the number of product terms and also show the internal logic in the PLA
structure. [16]
8. (a) Describe the analysis procedure of asynchronous sequential logic using flow
table
(b) An asynchronous sequential circuit has two internal states and one output.
The excitation and output functions describing the functions are: [6+10]
Y1 = x 1 x 2 + x 1 y 2 + x 2 y 1
0 0
Y2 = x2 + x1 y10 y2 +x01 y1
z = x2 + y 1
i. Draw the logic diagram of the circuit.
ii. Derive the transition table and output map.
iii. Obtain a flow table for the circuit.
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Technology)
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1. (a) Perform the following using BCD arithmetic. Verify the result. [4+4]
i. 748410 + 366810
ii. 825410 + 827710
(b) Convert the following:
i. A616 = ( )10
ii. 12668 = ( )10
iii. 101000112 = ( )10
iv. 37210 = ( )16 [2+2+2+2]
2. (a) Find the complement of the following and show that F.F’ = 0 and F + F’ =
1.
i. F = xy’ + x’y
ii. F = (x + y’ + z)(x’ + z’)(x + y).
(b) Obtain the Dual of the following Boolean expressions. [8+8]
i. B’C’D + (B + C + D)’ + B’C’D’E
ii. AB + (AC)’ + (AB + C)
iii. A’B’C’ + A’BC’ + AB’C’ + ABC’
iv. AB + (AC)’ + AB’C.
3. (a) Show that: A ⊕ B ⊕ (A + B) = AB
(b) Show that: A ⊕ C ⊕ B = A B C
(c) Obtain minimal POS expression for the complement of the given expression:
F (A, B, C) = Σ0,3,4,6 And draw the circuit using NOR-gates. [4+4+8]
4. (a) Implement 64 × 1 multiplexer with four 16 × 1 and one 4 ×1 multiplexer.
(Use only block diagram).
(b) A combinational logic circuit is defined by the following Boolean functions.
F1 = ABC + AC
F2 = ABC + AB
F3 = ABC + AB
Design the circuit with a decoder and external gates. [8+8]
5. (a) Draw the circuit diagram of clocked D- flip-flop with NAND gates and explain
its operation using truth table. Give its timing diagram.
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(b) Explain the procedure for the design of sequential circuits with example. [8+8]
6. (a) Draw and explain 4-bit universal shift register.

(b) Explain different types of shift registers. [8+8]
7. (a) Explain the block diagram of a memory unit. Explain the read and write
operation a RAM can perform.
(b) i. How many 32K * 8 RAM chips are needed to provide a memory capacity
of 256K bytes.
ii. How many lines of the address must be used to access 256K bytes? How
many of these lines are connected to the address inputs of all chips?
iii. How many lines must be decoded for the chip select inputs? Specify the
size of the decoder. [8+8]
8. (a) Describe the operation of the SR Latch using NAND gate with the help of
truth table, transition table and the circuit.
(b) Explain the operation and use of De bounce circuit. [8+8]
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Technology)
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1. A 12-bit Hamming code word containing 8-bits of data and 4 parity bits is read from
memory. What was the original 8-bit data word that was written in to memory if
12-bit words read out is as follows? [4×4]
(a) 001111101010
(b) 101110010110
(c) 101110110100
(d) 110011010111.
2. (a) Reduce the following Boolean expressions.

i. AB’ (C + BD) + A’B’
ii. A’B’C + (A + B + C’)’ + A’B’C’D
iii. ABCD + AB(CD)’ + (AB)’CD
iv. (A + A’)(AB + ABC’).
(b) Obtain the complement of the following Boolean expressions. [8+8]
i. ABC + A’B + ABC’
ii. (BC’ + A’D)(AB’ + CD’)
iii. x’yz + xz
iv. xy + x (wz + wz’).
3. (a) If
F1 (A, B, C) = A ⊕ B ⊕ C
F2 (A, B, C) = AΘ C Θ B
Show that = F1 = F2
(b) Show that A ⊕ B ⊕ AB = A + B
(c) Obtain minimal
Q SOP expression for the complement of the given expression:
F (A, B, C) = (1, 2, 5, 7) And draw the circuit using NOR - gates. [4+4+8]
4. (a) A combinational logic circuit is defined by the following Boolean function

f (A, B, C, D) = AB + BCD + ABD + ACD
Implement this function using 4 × 1 multiplexer and external gates.
Let A, B inputs as select lines S1 , S0 of multiplexer and C, D inputs used for
data inputs.

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(b) An 8 × 1 multiplexer has inputs A, B and C connected to the selection inputs
the selection inputs S2 ,S1 , and S0 respectively. Data inputs I0 through I7 are
as follows:
[8+8]
I1 = I2 = I7 = 0; I3 = I5 =1; I0 = I4 = D; I6 = D
Determine the Boolean function that the multiplexer implements.
5. (a) Explain the operation of R-S master slave flip-flop. Explain its truth table.
(b) Explain the operation of master slave J-K flip-flop with neat sketch. Distin-
guish with edge triggering. [16]
6. (a) Explain the following systems

i. shift registers
ii. counters.
(b) Draw and explain 4-bit binary ripple counter using D- flip-flops. [10+6]
7. (a) Draw and explain the block diagram of PLA.

(b) Tabulate the PLA programmable table for the four Boolean functions given
below:
A(x,y,z) = Σ m (1,2,4,6)
B(x,y,z) = Σ m (0,1,6,7)
C(x,y,z) = Σ m (2,6)
D(x,y,z) = Σ m (1,2,3,5,7). [16]
8. (a) i. Explain the difference between asynchronous and synchronous sequential
circuits.
ii. Define fundamental-mode operation.
iii. Explain the difference between stable and unstable states.
iv. What is the difference between an internal state and a total state.
(b) Explain critical and non critical races with the help of examples. [8+8]
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Technology)
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1. (a) Generate Hamming code for the given 11 bit message 10001110101 and rewrite
the entire message with Hamming code.
(b) The binary numbers listed have a sign bit in the left most position and , if neg-
ative numbers are in 2’s complement form. Perform the arithmetic operations
indicated and verify the answers. [8+8]
i. 101011 + 111000
ii. 001110 + 110010
iii. 111001 - 001010
iv. 101011 - 100110.
2. (a) Express the following functions in sum of minterms and product of maxterms.
i. F (A,B,C,D) = B’D + A’D + BD
ii. F(x,y,z) = (xy + z)(xz + y).
(b) Obtain the complement of the following Boolean expressions. [8+8]
i.(AB’ + AC’)(BC + BC’)(ABC)
ii.AB’C + A’BC + ABC
iii.(ABC)’(A + B + C)’
iv. A + B’C (A + B + C’).
P
3. (a) If F1 (A, B, C, D) =
P (1, 3, 4, 5, 9, 10, 11) + d6, 8 And
F2 (A, B, C, D) = (0, 2, 4, 7, 8, 15) + d9, 12 Obtain minimal SOP expression
for F1 ⊕ F2 using K- map and draw the circuit using NAND gates.
(b) Draw the multiple
-level NAND circuit for the following Boolean - expression:
AB + CD E + BC (A + B) [8+8]
4. (a) Implement 64 × 1 multiplexer with four 16 × 1 and one 4 ×1 multiplexer.

(Use only block diagram).
(b) A combinational logic circuit is defined by the following Boolean functions.
F1 = ABC + AC
F2 = ABC + AB
F3 = ABC + AB
Design the circuit with a decoder and external gates. [8+8]
5. (a) Explain the following terms related to filp-flops.

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i. race round conditions
ii. propagation delay
iii. clock.
(b) Explain the operation of R-S flip-flop with negative edge triggering with neat
sketch. And explain its truth table. [8+8]
6. Draw the sequential circuit for serial adder using shift registers, full adder and
D-FF. Explain its operation with state equations and state table . [16]
7. (a) Explain the block diagram of a memory unit. Explain the read and write
operation a RAM can perform.
(b) i. How many 32K * 8 RAM chips are needed to provide a memory capacity
of 256K bytes.
ii. How many lines of the address must be used to access 256K bytes? How
many of these lines are connected to the address inputs of all chips?
iii. How many lines must be decoded for the chip select inputs? Specify the
size of the decoder. [8+8]
8. (a) Describe the analysis procedure of asynchronous sequential logic using transi-
tion table.
(b) An asynchronous sequential circuit is described by the excitation and output
functions. [6+10]
Y = x1 x2 + (x1 + x2 )y
0 0
z=y
i. Draw the logic diagram of the circuit.
ii. Derive the transition table and output map.
iii. Obtain a two-state flow table.
iv. Describe in words the behavior of the circuit.
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www.andhracolleges.

com The Complete Information About Colleges in Andhra Pradesh

Code No: X0524/R07 Set No. 1

1. Convert the following to Decimal and then to Binary.

Code No: X0524/R07 Set No. 1

6. (a) Explain the following systems

Seminar Topics - Scholarships - Admission/Entrance Exam Notifications

Code No: X0524/R07 Set No. 2

Code No: X0524/R07 Set No. 2

6. (a) Draw and explain 4-bit universal shift register.

Code No: X0524/R07 Set No. 3

2. (a) Reduce the following Boolean expressions.

4. (a) A combinational logic circuit is defined by the following Boolean function

Seminar Topics - Scholarships - Admission/Entrance Exam Notifications

Code No: X0524/R07 Set No. 3

6. (a) Explain the following systems

7. (a) Draw and explain the block diagram of PLA.

8. (a) i. Explain the difference between asynchronous and synchronous sequential

Seminar Topics - Scholarships - Admission/Entrance Exam Notifications

Code No: X0524/R07 Set No. 4

4. (a) Implement 64 × 1 multiplexer with four 16 × 1 and one 4 ×1 multiplexer.

5. (a) Explain the following terms related to filp-flops.

Code No: X0524/R07 Set No. 4

Seminar Topics - Scholarships - Admission/Entrance Exam Notifications

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