Computer Architecture

Instruction Set Principles (Part 3)

Madhu Mutyam
PACE Laboratory
Department of Computer Science and Engineering
Indian Institute of Technology Madras

Type and Size of Operands

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Type and Size of Operands

Common operand types

I

Character (8 bits), half-word (16 bits), word (32 bits), single-precision FP

(1 word), double-precision FP (2 words)

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Type and Size of Operands

Common operand types

I

Character (8 bits), half-word (16 bits), word (32 bits), single-precision FP

(1 word), double-precision FP (2 words)

Integers are represented as 2s complement binary number

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Type and Size of Operands

Common operand types

I

I
I

Character (8 bits), half-word (16 bits), word (32 bits), single-precision FP

(1 word), double-precision FP (2 words)

Integers are represented as 2s complement binary number

Characters are represented in ASCII
I

16-bit unicode is gaining popularity

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Type and Size of Operands

Common operand types

I

I
I

Integers are represented as 2s complement binary number

Characters are represented in ASCII
I

Character (8 bits), half-word (16 bits), word (32 bits), single-precision FP

(1 word), double-precision FP (2 words)

16-bit unicode is gaining popularity

IEEE standard 754 is used for FP numbers

I

Single-precision: Sign(1):Exponent(8):Mantissa(23)

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Type and Size of Operands

Common operand types

I

I
I

Integers are represented as 2s complement binary number

Characters are represented in ASCII
I

Character (8 bits), half-word (16 bits), word (32 bits), single-precision FP

(1 word), double-precision FP (2 words)

16-bit unicode is gaining popularity

IEEE standard 754 is used for FP numbers

I
I

Single-precision: Sign(1):Exponent(8):Mantissa(23)
Double-precision: Sign(1):Exponent(11):Mantissa(52)

Madhu Mutyam (IIT Madras)

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Type and Size of Operands

Common operand types

I

I
I

Integers are represented as 2s complement binary number

Characters are represented in ASCII
I

Character (8 bits), half-word (16 bits), word (32 bits), single-precision FP

(1 word), double-precision FP (2 words)

16-bit unicode is gaining popularity

IEEE standard 754 is used for FP numbers

I
I
I

Single-precision: Sign(1):Exponent(8):Mantissa(23)
Double-precision: Sign(1):Exponent(11):Mantissa(52)
Consider biased exponent and normalised mantissa

Madhu Mutyam (IIT Madras)

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Type and Size of Operands

Common operand types

I

I
I

Integers are represented as 2s complement binary number

Characters are represented in ASCII
I

16-bit unicode is gaining popularity

IEEE standard 754 is used for FP numbers

I
I
I

Character (8 bits), half-word (16 bits), word (32 bits), single-precision FP

(1 word), double-precision FP (2 words)

Single-precision: Sign(1):Exponent(8):Mantissa(23)
Double-precision: Sign(1):Exponent(11):Mantissa(52)
Consider biased exponent and normalised mantissa

BCD format can also be needed

I

Calculations that are exact in decimal can be inexact in binary

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Common Instruction Operations

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Common Instruction Operations

I

Arithmetic/Logical: Integer ALU operations

I

ADD, SUB, DIV, AND, OR, ...

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Common Instruction Operations

I

Arithmetic/Logical: Integer ALU operations

I

ADD, SUB, DIV, AND, OR, ...

Load/Stores: Data transfer between memory and registers

I

LOAD, STORE, MOVE

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Common Instruction Operations

I

Arithmetic/Logical: Integer ALU operations

I

Load/Stores: Data transfer between memory and registers

I

ADD, SUB, DIV, AND, OR, ...

LOAD, STORE, MOVE

Control: Instructions to change the flow of instruction execution

I

Conditional branches, jumps, procedure calls, procedure returns

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Common Instruction Operations

I

Arithmetic/Logical: Integer ALU operations

I

Load/Stores: Data transfer between memory and registers

I

ADD, SUB, DIV, AND, OR, ...

LOAD, STORE, MOVE

Control: Instructions to change the flow of instruction execution

I
I

Conditional branches, jumps, procedure calls, procedure returns

PC-relative the target address is known at compile time

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Common Instruction Operations

I

Arithmetic/Logical: Integer ALU operations

I

Load/Stores: Data transfer between memory and registers

I

ADD, SUB, DIV, AND, OR, ...

LOAD, STORE, MOVE

Control: Instructions to change the flow of instruction execution

I
I
I

Conditional branches, jumps, procedure calls, procedure returns

PC-relative the target address is known at compile time
Register indirect the target address is not known at compile time

Madhu Mutyam (IIT Madras)

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Common Instruction Operations

I

Arithmetic/Logical: Integer ALU operations

I

Load/Stores: Data transfer between memory and registers

I

ADD, SUB, DIV, AND, OR, ...

LOAD, STORE, MOVE

Control: Instructions to change the flow of instruction execution

I
I
I
I

Conditional branches, jumps, procedure calls, procedure returns

PC-relative the target address is known at compile time
Register indirect the target address is not known at compile time
Condition codes are used to specify branch conditions

Madhu Mutyam (IIT Madras)

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Common Instruction Operations

I

Arithmetic/Logical: Integer ALU operations

I

Load/Stores: Data transfer between memory and registers

I

ADD, SUB, DIV, AND, OR, ...

LOAD, STORE, MOVE

Control: Instructions to change the flow of instruction execution

I
I
I
I
I

Conditional branches, jumps, procedure calls, procedure returns

PC-relative the target address is known at compile time
Register indirect the target address is not known at compile time
Condition codes are used to specify branch conditions
Procedure call places the return address in a register (ARM) or on a stack
in memory (80x86)

Madhu Mutyam (IIT Madras)

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Common Instruction Operations

I

Arithmetic/Logical: Integer ALU operations

I

Load/Stores: Data transfer between memory and registers

I

ADD, SUB, DIV, AND, OR, ...

LOAD, STORE, MOVE

Control: Instructions to change the flow of instruction execution

I
I
I
I
I

Conditional branches, jumps, procedure calls, procedure returns

PC-relative the target address is known at compile time
Register indirect the target address is not known at compile time
Condition codes are used to specify branch conditions
Procedure call places the return address in a register (ARM) or on a stack
in memory (80x86)
BEQZ, BNEQ, JMP, CALL, RETURN, TRAP

Madhu Mutyam (IIT Madras)

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Common Instruction Operations

I

Arithmetic/Logical: Integer ALU operations

I

Load/Stores: Data transfer between memory and registers

I

LOAD, STORE, MOVE

Control: Instructions to change the flow of instruction execution

I
I
I
I
I

ADD, SUB, DIV, AND, OR, ...

Conditional branches, jumps, procedure calls, procedure returns

PC-relative the target address is known at compile time
Register indirect the target address is not known at compile time
Condition codes are used to specify branch conditions
Procedure call places the return address in a register (ARM) or on a stack
in memory (80x86)
BEQZ, BNEQ, JMP, CALL, RETURN, TRAP

System: OS instructions, virtual memory management instructions

I

INT

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Common Instruction Operations

I

Arithmetic/Logical: Integer ALU operations

I

Load/Stores: Data transfer between memory and registers

I

I
I
I
I

Conditional branches, jumps, procedure calls, procedure returns

PC-relative the target address is known at compile time
Register indirect the target address is not known at compile time
Condition codes are used to specify branch conditions
Procedure call places the return address in a register (ARM) or on a stack
in memory (80x86)
BEQZ, BNEQ, JMP, CALL, RETURN, TRAP

System: OS instructions, virtual memory management instructions

I

LOAD, STORE, MOVE

Control: Instructions to change the flow of instruction execution

I

ADD, SUB, DIV, AND, OR, ...

INT

Floating-point: FP operations
I

FADD, FMULT, ...

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Encoding An Instruction Set

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Encoding An Instruction Set

I

The number of registers and the number of addressing modes have an

impact on the size of instructions

Madhu Mutyam (IIT Madras)

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Encoding An Instruction Set

I

The number of registers and the number of addressing modes have an

impact on the size of instructions

Fixed Length Encoding:

Opera&on

Address
eld 1

Address
eld 2

Address
eld 3

Madhu Mutyam (IIT Madras)

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Encoding An Instruction Set

I

The number of registers and the number of addressing modes have an

impact on the size of instructions

Fixed Length Encoding:

Opera&on

I
I
I

Address
eld 1

Address
eld 2

Address
eld 3

The operation and the addressing mode are encoded into the opcode
Instruction decoding is simple
Example ISA: ARM

Madhu Mutyam (IIT Madras)

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Encoding An Instruction Set

I

The number of registers and the number of addressing modes have an

impact on the size of instructions

Fixed Length Encoding:

Opera&on

I
I
I

Address
eld 1

Address
eld 2

Address
eld 3

The operation and the addressing mode are encoded into the opcode
Instruction decoding is simple
Example ISA: ARM

Variable Length Encoding:

Opera&on and
Address
no. of operands specier 1

Address
eld 1

Address
specier n

Address
eld n

Madhu Mutyam (IIT Madras)

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Encoding An Instruction Set

I

The number of registers and the number of addressing modes have an

impact on the size of instructions

Fixed Length Encoding:

Opera&on

I
I
I

Address
eld 1

Address
eld 2

Address
eld 3

The operation and the addressing mode are encoded into the opcode
Instruction decoding is simple
Example ISA: ARM

Variable Length Encoding:

Opera&on and
Address
no. of operands specier 1
I
I
I

Address
eld 1

Address
specier n

Address
eld n

Separate address specifier is needed for each operand

Takes less space
Example ISA: 80x86

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CISC Vs RISC

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CISC Vs RISC
I

Complex Instruction Set Computer (CISC) Architecture uses multi-word

instructions

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CISC Vs RISC
I

Complex Instruction Set Computer (CISC) Architecture uses multi-word

instructions
I

I
I
I

The primary goal is to complete a task in as few lines of assembly as

possible
supporting the operations and data structures used by the high-level
language
Supporting a large variety of memory addressing modes
Results in variable length instructions
Example ISA: x86

Madhu Mutyam (IIT Madras)

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CISC Vs RISC
I

Complex Instruction Set Computer (CISC) Architecture uses multi-word

instructions
I

I
I
I

The primary goal is to complete a task in as few lines of assembly as

possible
supporting the operations and data structures used by the high-level
language
Supporting a large variety of memory addressing modes
Results in variable length instructions
Example ISA: x86

Reduced Instruction Set Computer (RISC) Architecture uses one-word

instructions

Madhu Mutyam (IIT Madras)

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CISC Vs RISC
I

Complex Instruction Set Computer (CISC) Architecture uses multi-word

instructions
I

I
I
I

The primary goal is to complete a task in as few lines of assembly as

possible
supporting the operations and data structures used by the high-level
language
Supporting a large variety of memory addressing modes
Results in variable length instructions
Example ISA: x86

Reduced Instruction Set Computer (RISC) Architecture uses one-word

instructions

Uses processor registers extensively

Operands must be from registers only
Load-store architecture
Register-based addressing is used

Example ISA: ARM

I
I
I

Memory addressing modes are used only for loads/stores

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Thank You

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