PRELIMINARY

Am29LV800T/Am29LV800B
8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit)
CMOS 3.0 Volt-only, Sectored Flash Memory
DISTINCTIVE CHARACTERISTICS
Single power supply operation
Extended voltage range: 2.7 to 3.6 volt read and
write operations for battery-powered
applications
Standard voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors

Embedded Algorithms
Embedded Erase algorithms automatically
preprogram and erase the entire chip or any
combination of designated sectors
Embedded Program algorithms automatically
write and verify bytes or words at specified
addresses

High performance
Extended voltage range: access times as fast as
100 ns
Standard voltage range: access times as fast as
90 ns

Minimum 100,000 write cycle guarantee per

sector

Ultra low power consumption

Automatic Sleep Mode: 200 nA typical
Standby mode: 200 nA typical
Read mode: 2 mA/MHz typical
Program/erase mode: 20 mA typical
Flexible sector architecture
One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
Supports control code and data storage on a
single device
Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Temporary Sector Unprotect feature allows code
changes in previously locked sectors

Compatibility with JEDEC standards

Pinout and software compatible with singlepower supply Flash
Superior inadvertent write protection

Package options
48-pin TSOP
44-pin SO

Data Polling and toggle bits

Provides a software method of detecting
program or erase operation completion
Ready/Busy pin (RY/BY)
Provides a hardware method of detecting
program or erase cycle completion
Erase suspend/resume commands
Suspends the erase operation to read data from
or program data to another sector, then resumes
the erase operation
Hardware reset pin (RESET)
Hardware method to reset the device to the read
mode

Top or bottom boot block configurations

available

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.

Publication# 20478 Rev: D Amendment/0

Issue Date: November 1997

Refer to AMDs Website (www.amd.com) for the latest information.

P R E L I M I N A R Y

GENERAL DESCRIPTION
The Am29LV800 is an 8 Mbit, 3.0 Volt-only Flash memory organized as 1 Mbyte of 8 bits each or 512K words
of 16 bits each. For flexible erase and program capability, the 8 Mbits of data is divided into 19 sectors of one
16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64
Kbytes. The x8 data appears on DQ0DQ7; the x16
data appears on DQ0DQ15. The Am29LV800 is offered in 44-pin SO and 48-pin TSOP packages. This
device is designed to be programmed in-system with
the standard system 3.0 Volt VCC supply. The device
can also be reprogrammed in standard EPROM
programmers.
The Am29LV800 provides two levels of performance.
The first level offers access times as fast as 100 ns with
a VCC range as low as 2.7 volts, which is optimal for
battery powered applications. The second level offers a
90 ns access time, optimizing performance in systems
where the power supply is in the regulated range of 3.0
to 3.6 volts. To eliminate bus contention, the device has
separate chip enable (CE), write enable (WE), and
output enable (OE) controls.
The Am29LV800 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an internal state-machine which
controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
The Am29LV800 is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically pre-programs the array
if it is not already programmed before executing the
erase operation. During erase, the device automatically
times the erase pulse widths and verifies proper cell
margin.
This device also features a sector erase architecture.
This allows for sectors of memory to be erased and reprogrammed without affecting the data contents of

other sectors. A sector is typically erased and verified

within 1.0 second. The Am29LV800 is fully erased
when shipped from the factory.
The Am29LV800 device also features hardware sector
protection. This feature will disable both program and
erase operations in any combination of nineteen sectors of memory.
AMD has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from or program data to a sector that
was not being erased. Thus, true background erase
can be achieved.
The device features single 3.0 Volt power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The end of program or erase is detected by the
RY/BY pin. Data Polling of DQ7, or by the Toggle Bit
(DQ6). Once the end of a program or erase cycle has
been completed, the device automatically resets to the
read mode.
The Am29LV800 also has a hardware RESET pin.
When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm
will be terminated. The internal state machine will then
be reset into the read mode. The RESET pin may be
tied to the system reset circuitry. Therefore, if a system
reset occurs during the Embedded Program Algorithm
or Embedded Erase Algorithm, the device will be automatically reset to the read mode and will have erroneous data stored in the address locations being
operated on. These locations will need rewriting after
the Reset. Resetting the device will enable the systems microprocessor to read the boot-up firmware
from the Flash memory.
AMDs Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The Am29LV800 memory electrically erases
all bits within a sector simultaneously via FowlerNordhiem tunneling. The bytes/words are programmed
one byte/word at a time using the EPROM programming mechanism of hot electron injection.

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

Flexible Sector Architecture

One 8 Kword, two 4 Kwords, one 16 Kword, and
fifteen 32 Kwords sectors in word mode

Individual-sector or multiple-sector erase capability

Sector protection is user definable

One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and

fifteen 64 Kbyte sectors in byte mode

(x8) Address
Range

(x16) Address
Range

(x8) Address
Range

(x16) Address
Range

SA18

16 Kbytes
8 Kwords

FC000h-FFFFFh 7E000h-7FFFFh

SA18

64 Kbytes
32 Kwords

F0000h-FFFFFh

78000h-7FFFFh

SA17

8 Kbytes
4 Kwords

FA000h-FBFFFh 7D000h-7DFFFh

SA17

64 Kbytes
E0000h-EFFFFh
32 Kwords

70000h-77FFFh

SA16

8 Kbytes
4 Kwords

F8000h-F9FFFh 7C000h-7CFFFh

SA16

64 Kbytes
D0000h-DFFFFh 68000h-6FFFFh
32 Kwords

SA15

32 Kbytes
16 Kwords

F0000h-F7FFFh

78000h-7BFFFh

SA15

64 Kbytes
C0000h-CFFFFh 60000h-67FFFh
32 Kwords

SA14

64 Kbytes
E0000h-EFFFFh
32 Kwords

70000h-77FFFh

SA14

64 Kbytes
B0000h-BFFFFh 58000h-5FFFFh
32 Kwords

SA13

64 Kbytes
D0000h-DFFFFh 68000h-6FFFFh
32 Kwords

SA13

64 Kbytes
A0000h-AFFFFh
32 Kwords

50000h-57FFFh

SA12

64 Kbytes
C0000h-CFFFFh 60000h-67FFFh
32 Kwords

SA12

64 Kbytes
32 Kwords

90000h-9FFFFh

48000h-4FFFFh

SA11

64 Kbytes
B0000h-BFFFFh 58000h-5FFFFh
32 Kwords

SA11

64 Kbytes
32 Kwords

80000h-8FFFFh

40000h-47FFFh

SA10

64 Kbytes
A0000h-AFFFFh
32 Kwords

50000h-57FFFh

SA10

64 Kbytes
32 Kwords

70000h-7FFFFh

38000h-3FFFFh

SA9

64 Kbytes
32 Kwords

90000h-9FFFFh

48000h-4FFFFh

SA9

64 Kbytes
32 Kwords

60000h-6FFFFh

30000h-37FFFh

SA8

64 Kbytes
32 Kwords

80000h-8FFFFh

40000h-47FFFh

SA8

64 Kbytes
32 Kwords

50000h-5FFFFh

28000h-2FFFFh

SA7

64 Kbytes
32 Kwords

70000h-7FFFFh

38000h-3FFFFh

SA7

64 Kbytes
32 Kwords

40000h-4FFFFh

20000h-27FFFh

SA6

64 Kbytes
32 Kwords

60000h-6FFFFh

30000h-37FFFh

SA6

64 Kbytes
32 Kwords

30000h-3FFFFh

18000h-1FFFFh

SA5

64 Kbytes
32 Kwords

50000h-5FFFFh

28000h-2FFFFh

SA5

64 Kbytes
32 Kwords

20000h-2FFFFh

10000h-17FFFh

SA4

64 Kbytes
32 Kwords

40000h-4FFFFh

20000h-27FFFh

SA4

64 Kbytes
32 Kwords

10000h-1FFFFh

08000h-0FFFFh

SA3

64 Kbytes
32 Kwords

30000h-3FFFFh

18000h-1FFFFh

SA3

32 Kbytes
16 Kwords

08000h-0FFFFh

04000h-07FFFh

SA2

64 Kbytes
32 Kwords

20000h-2FFFFh

10000h-17FFFh

SA2

8 Kbytes
4 Kwords

06000h-07FFFh

03000h-03FFFh

SA1

64 Kbytes
32 Kwords

10000h-1FFFFh

08000h-0FFFFh

SA1

8 Kbytes
4 Kwords

04000h-05FFFh

02000h-02FFFh

SA0

64 Kbytes
32 Kwords

00000h-0FFFFh

00000h-07FFFh

SA0

16 Kbytes
8 Kwords

00000h-03FFFh

00000h-01FFFh

20478D-1

Am29LV800T Sector Architecture

20478D-2

Am29LV800B Sector Architecture

Notes:
The address range is A18:A-1 if in byte mode (BYTE = VIL).
The address range is A18:A0 if in word mode (BYTE = VIH).

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Am29LV800T/Am29LV800B

Family Part Number

Ordering Part Number:

VCC = 3.03.6 V

-90R

VCC = 2.73.6 V

-100

-120

-150

Max access time (ns)

90

100

120

150

CE access time (ns)

90

100

120

150

OE access time (ns)

40

40

50

55

BLOCK DIAGRAM
RY/BY

Sector
Switches

DQ0DQ7

Erase Voltage
Generator

Input/Output
Buffers

VCC
VSS
RESET

WE
BYTE

State
Control
Command
Register

PGM Voltage
Generator
Chip Enable
Output Enable
Logic

CE
OE

VCC Detector

A0A18

Timer

Address Latch

STB

STB

Data Latch

Y-Decoder

Y-Gating

X-Decoder

Cell Matrix

20478D-3

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

CONNECTION DIAGRAMS
SO
RY/BY

44

RESET

A18

43

WE

A17

42

A8

A7

41

A9

A6

40

A10

A5

39

A11

A4

38

A12

A3

37

A13

A2

36

A14

A1

10

35

A15

A0

11

34

A16

CE

12

33

BYTE

VSS

13

32

VSS

OE

14

31

DQ15/A-1

DQ0

15

30

DQ7

DQ8

16

29

DQ14

DQ1

17

28

DQ6

DQ9

18

27

DQ13

DQ2

19

26

DQ5

DQ10

20

25

DQ12

DQ3

21

24

DQ4

DQ11

22

23

VCC

Am29LV800T/Am29LV800B

20478D-4

P R E L I M I N A R Y

CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

20478D-5

Standard TSOP

A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
20478D-6

Reverse TSOP

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

PIN CONFIGURATION
A0A18

LOGIC SYMBOL

= 19 addresses

19

DQ0DQ14 = 15 data inputs/outputs

A0A18

DQ15/A-1

= DQ15 data input/output (word mode),

A-1 (LSB address input, byte mode)

BYTE

= Selects 8-bit or 16-bit mode

CE

= Chip enable

OE

= Output enable

WE

= Write enable

RESET

RESET

= Hardware reset pin, active low

BYTE

RY/BY

= Ready/Busy output

VCC

= Standard voltage range

(3.0 to 3.6 V) for -90R

16 or 8
DQ0DQ15
(A-1)

CE
OE
WE

RY/BY

20478D-7

Extended voltage range

(2.7 to 3.6 V) for -100, -120, -150
VSS

= Device ground

NC

= Pin not connected internally

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

Am29LV800

-90R

OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
TEMPERATURE RANGE
C = Commercial (0C to +70C)
I = Industrial (40C to +85C)
E = Extended (55C to +125C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
SPEED OPTION
-xxx = 2.7 to 3.6 V VCC
-xxR = 3.0 to 3.6 V VCC
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29LV800
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory
3.0 Volt-only Program and Erase

Valid Combinations
Valid Combinations
Am29LV800T-90R,
Am29LV800B-90R
VCC = 3.03.6 V

Am29LV800T-100,
Am29LV800B-100

EC, EI, FC, FI, SC, SI

Am29LV800T-120,
Am29LV800B-120
Am29LV800T-150,
Am29LV800B-150

Am29LV800T/Am29LV800B

SC, SI, SE, SEB,

EC, EI, EE, EEB,
FC, FI, FE, FEB

P R E L I M I N A R Y
Table 1.

Am29LV800 User Bus Operations (BYTE = VIH)

Operation

CE

OE

WE

A0

A1

A6

A9

Autoselect, Manufacturer Code (Note 1)

VID

Code

Autoselect Device Code (Note 1)

VID

Code

Read

A0

A1

A6

A9

DOUT

Standby

HIGH Z

Output Disable

HIGH Z

Write

A0

A1

A6

A9

DIN (Note 2)

Enable Sector Protect (Note 3)

VID

Pulse/H

VID

Code

Verify Sector Protect (Note 4)

VID

Code

Temporary Sector Unprotect

VID

Reset

HIGH Z

Table 2.
Operation

DQ0DQ15 RESET

Am29LV800 User Bus Operations (BYTE = VIL)

CE

OE

WE

A0

A1

A6

A9

DQ0DQ7

Autoselect, Manufacturer Code

(Note 1)

VID

Code

HIGH Z

Autoselect, Device Code

(Note 1)

VID

Code

HIGH Z

Read

A0

A1

A6

A9

DOUT

HIGH Z

Standby

HIGH Z

HIGH Z

Output Disable

HIGH Z

HIGH Z

Write

A0

A1

A6

A9

DIN (Note 2)

HIGH Z

Enable Sector Protect (Note 3)

VID

Pulse/H

VID

Code

HIGH Z

Verify Sector Protect (Note 4)

VID

Code

HIGH Z

Temporary Sector Unprotect

HIGH Z

VID

Reset

HIGH Z

HIGH Z

DQ8DQ15 RESET

Legend:
L = Logic 0, H = Logic 1, VID = 12.0 0.5 Volts, X = Dont care. See DC Characteristics (Table 12 and 13) for voltage levels.
Notes:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 6.
2. Refer to Table 6 for valid Data in (DIN) during a write operation.
3. Set VCC = 3.0 Volts 10%.
4. Refer to Sector Protection section.

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

USER BUS OPERATIONS

Read Mode
The Am29LV800 has three control functions which
must be satisfied in order to obtain data at the outputs:
CE is the power control and should be used for
device selection (CE = VIL)
OE is the output control and should be used to gate
data to the output pins if the device is selected
(OE = VIL)
WE remains at VIH
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses
and stable CE to valid data at the output pins. The output enable access time (tOE) is the delay from the falling edge of OE to valid data at the output pins
(assuming the addresses have been stable at least
tACC tOE time).

Standby Mode
The Am29LV800 is designed to accommodate two
modes for low standby power consumption. Both
modes are enabled by applying the voltages specified
below to the CE and RESET pins. These modes are
available for either TTL/NMOS or CMOS logic level designs. The first mode, ICC3 for TTL/NMOS compatible I/
Os (current consumption <1 mA max.), is enabled by
applying a TTL logic level 1 (VIH) to the CE control pin
with RESET = VIH. ICC3 for CMOS compatible I/Os
(current consumption <5 A max.), is enabled when a
CMOS logic level 1 (VCC 0.3 V) is applied to the CE
control pin with RESET = VCC 0.3 V. While in the ICC3

10

standby mode, the data I/O pins remain in the high impedance state independent of the voltage level applied
to the OE input. See the DC Characteristics section for
more details on Standby Modes.
Deselecting CE (CE = VIH or VCC 0.3 V, with RESET
= VIH or VCC 0.3 V), will put the device into the ICC3
standby mode. If the device is deselected during an
Embedded Algorithm operation, it will continue to
draw active power (ICC2), prior to entering the standby
mode, until the operation is complete. Subsequent
reselection of the device for active operations
(CE = VIL) will commence pursuant to the AC timing
specifications.

Automatic Sleep Mode

Advanced power management features such as the
automatic sleep mode minimize Flash device energy
c o n s u m p t i o n . T h i s i s ex t r e m e l y i m p o r t a n t i n
battery-powered applications. The Am29LV800 automatically enables the low-power, automatic sleep
mode when addresses remain stable for 200 ns. Automatic sleep mode is independent of the CE, WE, and
OE control signals. Typical sleep mode current draw is
200 nA (for CMOS-compatible operation). Standard
address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.

Output Disable
If the OE input is at a logic high level (VIH), output from
the device is disabled. This will cause the output pins to
be in a high impedance state.

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

Autoselect

without access to high voltage on the A9 pin. The

command sequence is illustrated in Table 6.

The Autoselect mode allows the reading out of a binary

code from the device and will identify its manufacturer
and type. The intent is to allow programming equipment
to automatically match the device to be programmed
with its corresponding programming algorithm. The
Autoselect command may also be used to check the
status of write-protected sectors (see Table 3). This
mode is functional over the entire temperature range of
the device.

Byte 0 (A0 = VIL) represents the manufacturers code

and byte 1 (A0 = VIH) the device identifier code. These
two bytes are given for the Am29LV800 in Table 3. All
identifiers for manufacturer and device exhibit odd
parity with DQ7 defined as the parity bit. In order to
read the proper device codes when executing Autoselect, A1 must be VIL (see Table 3). For device identification in word mode (BYTE = VIH), DQ9 and DQ13 are
equal to 1 and DQ8, DQ1012, DQ14, and DQ15 are
equal to 0.

To activate this mode, the programming equipment

must force VID (11.512.5 volts) on address pin A9.
Two identifier bytes may then be sequenced from the
device outputs by toggling address A0 from VIL to VIH.
All addresses are dont cares except A0, A1, and A6
(see Table 3).

If BYTE = VIH (for word mode), the device code is 22DAh

(for top boot block) or 225Bh (for bottom boot block). If
BYTE = VIL (for byte mode), the device code is DAh (for
top boot block) or 5Bh (for bottom boot block).

The manufacturer and device codes may also be read

via the command register, for instances when the
Am29LV800 is erased or programmed in a system
Table 3.
Type

Mode

Manufacturer Code:
AMD

29LV800 Device
(Top Boot Block)

29LV800 Device
(Bottom Boot Block)

Word

Autoselect/Sector Protection Codes

A12A18

A6

A1

A0

Code
(HEX)

DQ8DQ15

01h

High-Z

22DAh

DQ9 = 1,
DQ13 = 1,
Others = 0

X
L

Byte

DAh

High-Z

Word

225Bh

DQ9 = 1,
DQ13 = 1,
Others = 0

L
Byte

Sector Protection

In order to determine which sectors are write protected,

A1 must be at VIH while running through the sector
addresses. If the selected sector is protected, the
device outputs a 1 on DQ0.

X
Set Sector
Addresses

5Bh

High-Z

01h*

DQ DQ DQ DQ DQ DQ DQ DQ
7
6
5
4
3
2
1
0

X = Dont care.
* Outputs 01h at protected sector addresses.

Am29LV800T/Am29LV800B

11

P R E L I M I N A R Y
Table 4.

Sector Address Tables (Am29LV800T)

(x8)
Address Range

(x16)
Address Range

64 Kbytes
32 Kwords

00000h-0FFFFh

00000h-07FFFh

64 Kbytes
32 Kwords

10000h-1FFFFh

08000h-0FFFFh

64 Kbytes
32 Kwords

20000h-2FFFFh

10000h-17FFFh

64 Kbytes
32 Kwords

30000h-3FFFFh

18000h-1FFFFh

64 Kbytes
32 Kwords

40000h-4FFFFh

20000h-27FFFh

64 Kbytes
32 Kwords

50000h-5FFFFh

28000h-2FFFFh

64 Kbytes
32 Kwords

60000h-6FFFFh

30000h-37FFFh

64 Kbytes
32 Kwords

70000h-7FFFFh

38000h-3FFFFh

SA8

64 Kbytes
32 Kwords

80000h-8FFFFh

40000h-47FFFh

SA9

64 Kbytes
32 Kwords

90000h-9FFFFh

48000h-4FFFFh

SA10

64 Kbytes
32 Kwords

A0000h-AFFFFh

50000h-57FFFh

SA11

64 Kbytes
32 Kwords

B0000h-BFFFFh

58000h-5FFFFh

SA12

64 Kbytes
32 Kwords

C0000h-CFFFFh

60000h-67FFFh

SA13

64 Kbytes
32 Kwords

D0000h-DFFFFh

68000h-6FFFFh

SA14

64 Kbytes
32 Kwords

E0000h-EFFFFh

70000h-77FFFh

SA15

32 Kbytes
16 Kwords

F0000h-F7FFFh

78000h-7BFFFh

SA16

8 Kbytes
4 Kwords

F8000h-F9FFFh

7C000h-7CFFFh

SA17

8 Kbytes
4 Kwords

FA000h-FBFFFh

7D000h-7DFFFh

SA18

16 Kbyte
8 Kwords

FC000h-FFFFFh

7E000h-7FFFFh

A18

A17

A16

A15

A14

A13

A12

Sector Size

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

Note: The address range is A18:A-1 if in byte mode (BYTE = VIL). The address range is A18:A0 if in word mode (BYTE = VIH).

12

Am29LV800T/Am29LV800B

P R E L I M I N A R Y
Table 5.

Sector Address Tables (Am29LV800B)

(x8)
Address Range

(x16)
Address Range

16 Kbytes
8 Kwords

00000h03FFFh

00000h-01FFFh

8 Kbytes
4 Kwords

04000h05FFFh

02000h-02FFFh

8 Kbytes
4 Kwords

06000h07FFFh

03000h-03FFFh

32 Kbytes
16 Kwords

08000h0FFFFh

04000h-07FFFh

64 Kbytes
32 Kwords

10000h1FFFFh

08000h-0FFFFh

64 Kbytes
32 Kwords

20000h2FFFFh

10000h-17FFFh

64 Kbytes
32 Kwords

30000h3FFFFh

18000h-1FFFFh

64 Kbytes
32 Kwords

40000h4FFFFh

20000h-27FFFh

SA8

64 Kbytes
32 Kwords

50000h5FFFFh

28000h-2FFFFh

SA9

64 Kbytes
32 Kwords

60000h6FFFFh

30000h-37FFFh

SA10

64 Kbytes
32 Kwords

70000h7FFFFh

38000h-3FFFFh

SA11

64 Kbytes
32 Kwords

80000h8FFFFh

40000h-47FFFh

SA12

64 Kbytes
32 Kwords

90000h9FFFFh

48000h-4FFFF

SA13

64 Kbytes
32 Kwords

A0000hAFFFFh

50000h-57FFFh

SA14

64 Kbytes
32 Kwords

B0000hBFFFFh

58000h-5FFFFh

SA15

64 Kbytes
32 Kwords

C0000hCFFFFh

60000h-67FFFh

SA16

64 Kbytes
32 Kwords

D0000hDFFFFh

68000h-6FFFFh

SA17

64 Kbytes
32 Kwords

E0000hEFFFFh

70000h-77FFFh

SA18

64 Kbytes
32 Kwords

F0000hFFFFFh

78000h-7FFFFh

A18

A17

A16

A15

A14

A13

A12

Sector Size

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

Note: The address range is A18:A-1 if in byte mode (BYTE = VIL). The address range is A18:A0 if in word mode (BYTE = VIH).

Am29LV800T/Am29LV800B

13

P R E L I M I N A R Y

Write
Device erasure and programming are accomplished via
the command register. The command register is written
by bringing WE to VIL, while CE is at VIL and OE is at
VIH. Addresses are latched on the falling edge of CE or
WE, whichever occurs later, while data is latched on the
rising edge of the CE or WE pulse, whichever occurs
first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing parameters.

user attempts to erase a protected sector, Toggle Bit

will be activated for about 50 s; the device will then
return to read mode, without having erased the protected sector.
It is possible to determine if a sector is protected in the
system by writing an Autoselect command. Performing
a read operation at the address location XX02h, where
the higher order address A18A12 represents the sector address, will produce a logical 1 at DQ0 for a protected sector.

Temporary Sector Unprotect

Sector Protect
Sectors of the Am29LV800 may be hardware protected at the users factory with external programming
equipment. The protection circuitry will disable both
program and erase functions for the protected sectors, making the protected sectors read-only. Requests to program or erase a protected sector will be
ignored by the device. If the user attempts to write to
a protected sector, DATA Polling will be activated for
about 1 s; the device will then return to read mode,
with data from the protected sector unchanged. If the

The sectors of the Am29LV800 may be temporarily

unprotected by raising the RESET pin to 12.0 Volts
(VID). During this mode, formerly protected sectors
can be programmed or erased with standard command sequences by selecting the appropriate byte or
sector addresses. Once the RESET pin goes to TTL
level (VIH), all the previously protected sectors will be
protected again.

+12.0 V

RESET
500 ns min.
20478D-8

Figure 1.

Temporary Sector Unprotect Timing Diagram

Command Definitions

Autoselect Command

Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing
them in the improper sequence will reset the device
to the read mode. Table 6 defines the valid register
command sequences. Note that the Erase Suspend
(B0h) and Erase Resume (30h) commands are valid
only while the Sector Erase operation is in progress.

Flash memories are intended for use in applications

where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. The
Am29LV800 contains an autoselect command operation that provides device information and sector protection status to the system. The operation is initiated by
writing the autoselect command sequence into the
command register. Following the command write, a
read cycle from address XX00h retrieves the manufacturer code of 01h. A read cycle from address
XX01hreturns the device code DAh/5Bh for x8 configuration or 22DAh/225Bh for x16 configuration (see Table
3). All manufacturer and device codes will exhibit odd
parity with the MSB of the lower byte (DQ7) defined as
the parity bit. Scanning the sector addresses (A12,
A13, A14, A15, A16, A17, and A18) while (A6, A1, A0)
= (0, 1, 0) will produce a logical 1 code at device output
DQ0 for a write protected sector (See Table 3).

Read/Reset Command
The device will automatically power up in the read/
reset state. In this case, a command sequence is
not required to read data. Standard microprocessor cycles will retrieve array data. This default
value ensures that no spurious alteration of the
memory content occurs during the power transition. Refer to the AC Characteristics section for the
specific timing parameters.
The read or reset operation is initiated by writing the
read/reset command sequence into the command register. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for
reads until the command register contents are altered.
14

To terminate the Autoselect operation, it is necessary to write the read/reset command sequence
into the register.

Am29LV800T/Am29LV800B

P R E L I M I N A R Y
Table 6.
Command
Sequence
Read/Reset
(Note 2)

Bus
Write
Cycles
Reqd

Addr

XXX

Addr

Data

RA

RD

Fourth Bus
Read/Write
Cycle

Fifth Bus
Write Cycle

Sixth Bus
Write Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

F0

Word
Autoselect
Manufacturer ID Byte

Autoselect
Word
Device ID
(Top Boot Block) Byte

Autoselect
Sector Protect
Verify (Note 3)

Data

Third Bus Write

Cycle

XXF0

Byte

Autoselect
Device ID
(Bottom Boot
Block)

Second Bus
Read/Write
Cycle

First Bus
Write Cycle

Word
Reset/Read

Am29LV800 Command Definitions

555

XXAA

2AA

XX55

555

XX90

X00

XX01

AAA

AA

555

55

AAA

90

X00

01

555

XXAA

2AA

XX55

555

XX90

X01

22DA

AAA

AA

555

55

AAA

90

X02

DA

555

XXAA

2AA

XX55

555

XX90

X01

225B

Byte

AAA

AA

555

55

AAA

90

X02

5B

555

XXAA

2AA

XX55

555

XX90

SA
X02

XX00

Word

SA
X04

00

PA

PD

Word
3

XX01

3
Byte

AAA

Word
Program

AA

555

55

AAA

90

555

XXAA

2AA

XX55

555

XXA0

AAA

AA

555

55

AAA

A0

555

XXAA

2AA

XX55

555

XX80

555

XXAA

2AA

XX55

555

XX10

AAA

AA

555

55

AAA

80

AAA

AA

555

55

AAA

10

555

XXAA

2AA

XX55

555

XX80

555

XXAA

2AA

XX55

4
Byte
Word

Chip Erase

01

6
Byte
Word

Sector Erase

6
Byte

Erase Suspend
(Note 4)

Word

Erase Resume
(Note 5)

Word

XX30
SA

AAA

AA

555

55

AAA

80

AAA

AA

555

55

30

XXB0
1

XXX

Byte

B0
XX30
1

Byte

XXX
30

Legend:
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse.
SA = Address of the sector to be erased or verified. Address bits A18A12 uniquely select any sector.
Notes:
1. All values are in hexadecimal.
2. See Tables 1 and 2 for description of bus operations.
3. The data is 00h for an unprotected sector and 01h for a protected sector. The complete bus address is composed of the sector
address on A18A12 and 02h on A7A0.
4. Read and program functions in non-erasing sectors are allowed in the Erase Suspend mode. The Erase Suspend command
is valid only during a sector erase operation.
5. The Erase Resume command is valid only during the Erase Suspend mode.
6. Unless otherwise noted, address bits A18A11 = X = dont care.

Am29LV800T/Am29LV800B

15

P R E L I M I N A R Y

Word/Byte Programming

DATA Polling of DQ7

The device can be programmed on a word or byte basis. Programming is a four-bus-cycle operation. There
are two unlock write cycles. These are followed by the
program command and address/data write cycles. Addresses are latched on the falling edge of CE or WE,
whichever occurs later, while the data is latched on the
rising edge of CE or WE, whichever occurs first. The
rising edge of CE or WE, whichever occurs first, initiates programming using the Embedded Program Algorithm. Upon executing the write command, the
system is not required to provide further controls or
timing. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.

Checking the status of the toggle bit DQ6

The status of the Embedded Program Algorithm operation can be determined three ways:
DATA Polling of DQ7
Checking the status of the toggle bit DQ6
Checking the status of the RY/BY pin
Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware
reset occurs during a programming operation, the data
at that location will be corrupted.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data 0 cannot be
programmed back to a 1. Attempting to do so will
cause the device to exceed programming time limits
(DQ5 = 1) or result in an apparent success according
to the data polling algorithm. However, reading the device after executing the Read/Reset operation will
show that the data is still 0. Only erase operations can
convert 0s to 1s.
Figure 7 illustrates the Embedded Program Algorithm,
using typical command strings and bus operations.

Chip Erase
Chip erase is a six bus cycle operation. There are two
unlock write cycles, followed by writing the erase set
up command. Two more unlock write cycles are followed by the chip erase command.
Chip erase does not require the user to preprogram the
device to all 0s prior to erase. Upon executing the Embedded Erase Algorithm command sequence, the device automatically programs and verifies the entire
memory to an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations.
The Embedded Erase Algorithm erase begins on the
rising edge of the last WE or CE (whichever occurs
first) pulse in the command sequence. The status of the
Embedded Erase Algorithm operation can be determined three ways:

16

Checking the status of the RY/BY pin

Figure 8 illustrates the Embedded Erase Algorithm,
using a typical command sequence and bus operations.

Sector Erase
Sector erase is a six bus cycle operation. There are two
unlock writes. These are followed by writing the erase
set up command. Two more unlock writes are followed by the Sector Erase command (30h). The sector
address (any address location within the desired sector) is latched on the falling edge of WE or CE (whichever occurs last) while the command (30h) is latched
on the rising edge of WE or CE (whichever occurs first).
Multiple sectors can be specified for erase by writing
the six bus cycle operation as described above and
then following it by additional writes of the Sector Erase
command to addresses of other sectors to be erased.
The time between Sector Erase command writes must
be less than 80 s, otherwise that command will not be
accepted. It is recommended that processor interrupts
be disabled during this time to guarantee this condition.
The interrupts can be re-enabled after the last Sector
Erase command is written. A time-out of 80 s from the
rising edge of the last WE (or CE) will initiate the execution of the Sector Erase command(s). If another falling edge of the WE (or CE) occurs within the 80 s
time-out window, the timer is reset. During the 80 s
window, any command other than Sector Erase or
Erase Suspend written to the device will reset the device back to Read mode. Once the 80 s window has
timed out, only the Erase suspend command is recognized. Note that although the Reset command is not
recognized in the Erase Suspend mode, the device is
available for read or program operations in sectors that
are not erase suspended. The Erase Suspended and
Erase Resume commands may be written as often as
required during a sector erase operation. Hence, once
erase has begun, it must ultimately complete unless
Hardware Reset is initiated. Loading the sector erase
registers may be done in any sequence and with any
number of sectors (0 to 18).
Sector erase does not require the user to program the
device prior to erase. The device automatically preprograms all memory locations, within sectors to be
erased, prior to electrical erase. When erasing a sector
or sectors, the remaining unselected sectors or the
write protected sectors are unaffected. The system is
not required to provide any controls or timings during
sector erase operations. The Erase Suspend and
Erase Resume commands may be written as often as
required during a sector erase operation.

Am29LV800T/Am29LV800B

P R E L I M I N A R Y
Automatic sector erase operations begin on the rising
edge of the WE (or CE) pulse of the last sector erase
command issued, and once the 80 s time-out window
has expired. The status of the sector erase operation
can be determined three ways:

at which time the user can read or program from a sector that is not erase suspended. Reading data in this
mode is the same as reading from the standard read
mode, except that the data must be read from sectors
that have not been erase suspended.

DATA Polling of DQ7

Successively reading from the erase-suspended sector

while the device is in the erase-suspend-read mode will
cause DQ2 to toggle. Polling DQ2 on successive reads
from a given sector provides the system the ability to
determine if a sector is in Erase Suspend.

Checking the status of the toggle bit DQ6

Checking the status of the RY/BY pin
Further status of device activity during the sector erase
operation can be determined using toggle bits DQ2 and
DQ3.
Figure 8 illustrates the Embedded Erase Algorithm,
using a typical command sequence and bus operations.

Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data
read or programs in a sector not being erased. This
command is applicable only during the Sector Erase
operation, which includes the time-out period for Sector
Erase. The Erase Suspend command will be ignored if
written during the execution of the Chip Erase operation or Embedded Program Algorithm (but will reset the
chip if written improperly during the command sequences.) Writing the Erase Suspend command during
the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase
operation. Once in Erase Suspend, the device is available for read (note that in the Erase Suspend mode, the
Reset/Read command is not required for read operations and is ignored) or program operations in sectors
not being erased. Any other command written during
the Erase Suspend mode will be ignored, except for the
Erase Resume command. Writing the Erase Resume
command resumes the sector erase operation. The addresses are dont cares when writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during a
Sector Erase operation, the chip will take between 0.1
s and 20 s to actually suspend the operation and go
into erase suspended read mode (pseudo-read mode),

After entering the erase-suspend-read mode, the user

can program the device by writing the appropriate command sequence for Byte Program. This program mode
is known as the erase suspend-program mode. Again,
programming in this mode is the same as programming
in the regular Byte Program mode, except that the data
must be programmed to sectors that are not erase suspended. Successively reading from the erase suspended sector while the device is in the erase
suspend-program mode will cause DQ2 to toggle.
Completion of the erase suspend operation can be determined two ways:
Checking the status of the toggle bit DQ2
Checking the status of the RY/BY pin
To resume the operation of Sector Erase, the Resume
command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. However, another Erase Suspend command can be written
after the device has resumed sector erase operations.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended.
To resume the operation of Sector Erase, the Resume
command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.

Am29LV800T/Am29LV800B

17

P R E L I M I N A R Y

Write Operation Status

Once Erase Suspend is entered, address sensitivity

still applies. If the address of a non-erasing sector (that
is, one available for read) is provided, then stored data
can be read from the device. If the address of an erasing sector (that is, one unavailable for read) is applied,
the device will output its status bits. Confirmation of status bits can be done by doing consecutive reads to toggle DQ2, which is active throughout the Embedded
Erase mode, including Erase Suspend.

Address Sensitivity of Write Status Flags

Detailed in Table 7 are all the status flags that can be
used to check the status of the device for current mode
operation. During Sector Erase, the part provides the
status flags automatically to the I/O ports. The information on DQ2 is address sensitive. This means that if an
address from an erasing sector is consecutively read,
then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows the user to determine which
sectors are erasing and which are not.

Table 7.

Hardware Sequence Flags

Status

In Progress

DQ7

DQ6

DQ5

DQ3

DQ2

RY/BY

Byte and Word Programming

DQ7

Toggle

No Toggle

Program/Erase in Auto-Erase

Toggle

(Note 1)

Erase Sector Address

Erase
Suspend
Mode
Non-Erase Sector Address

No Toggle

Toggle
(Note 1)

Data

Data

Data

Data

Data
(Note 2)

DQ7
(Note 2)

Toggle

1
(Note 2)

Byte and Word Programming

DQ7

Toggle

No Toggle

Program/Erase in Auto-Erase

Toggle

(Note 3)

DQ7

Toggle

No Toggle

Program in Erase Suspend

Exceeded
Time Limits

In order to effectively use DATA Polling to determine if

the device has entered into erase-suspended mode, it
is necessary to apply a sector address from a sector
being erased.

Program in Erase Suspend

Notes:
1. DQ2 can be toggled when the sector address applied is that of an erasing or erase suspended sector. Conversely, DQ2 cannot
be toggled when the sector address applied is that of a non-erasing or non-erase suspended sector. DQ2 is therefore used
to determine which sectors are erasing or erase suspended and which are not.
2. These status flags apply when outputs are read from the address of a non-erase-suspended sector.
3. If DQ5 is high (exceeded timing limits), successive reads from a problem sector will cause DQ2 to toggle.

DQ7: Data Polling

The Am29LV800 features DATA Polling as a method to
indicate to the host system that the embedded algorithms are in progress or completed.

Erase Algorithm, an attempt to read the device will produce a 0 at the DQ7 output. Upon completion of the
Embedded Erase Algorithm, an attempt to read the device will produce a 1 at DQ7.

During the Embedded Program Algorithm, an attempt

to read the device will produce the compliment of the
data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. Note
that just at the instant when DQ7 switches to true data,
the other bits, DQ6DQ0, may not yet be true data.
However, they will all be true data on the next read from
the device. Please note that Data Polling (DQ7) may
give an inaccurate result when an attempt is made
to write to a protected sector. During an Embedded

For chip erase, the DATA Polling is valid (DQ7 = 1) after

the rising edge of the sixth WE pulse in the six write
pulse sequence. For sector erase, the DATA Polling is
valid after the last rising edge of the sector erase WE
pulse. DATA Polling must be performed at sector addresses within any of the sectors being erased and not
a sector that is within a protected sector. Otherwise, the
status may not be valid.

18

Just prior to the completion of Embedded Algorithm operations, DQ7 may change asynchronously while the
output enable (OE) is asserted low. This means that the

Am29LV800T/Am29LV800B

P R E L I M I N A R Y
device is driving status information on DQ7 at one instant of time and then that byteUs valid data at the next
instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid
data. Even if the device has completed the Embedded
Algorithm operations and DQ7 has valid data, DQ0
DQ6 may still provide write operation status. The valid
data on DQ0DQ7 can be read on the next successive
read attempt.
The DATA Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend, erase suspend-program
mode, or sector erase time-out (see Table 7).
If the user attempts to write to a protected sector,
DATA Polling will be activated for about 1 s; the device will then return to read mode, with data from the
protected sector unchanged. If the user attempts to
erase a protected sector, Toggle Bit will be activated
for about 50 s; the device will then return to read
mode, without having erased the protected sector.
See Figure 18 for the DATA Polling timing specifications
and diagrams.
DQ6: Toggle Bit
The Am29LV800 also features a Toggle Bit as a
method to indicate to the host system whether the embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm,
successive attempts to read data from the device will
result in DQ6 toggling between one and zero. Once the
Embedded Program or Erase Algorithm is completed,
DQ6 will stop toggling and valid data can be read on
the next successive attempts. During programming, the
Toggle Bit is valid after the rising edge of the fourth WE
pulse in the four-write-pulse sequence. During Chip
erase, the Toggle Bit is valid after the rising edge of the
sixth WE pulse in the six-write-pulse sequence. During
Sector erase, the Toggle Bit is valid after the last rising
edge of the sector erase WE pulse. The Toggle Bit is
active during the Sector Erase time-out.
Either CE or OE toggling will cause DQ6 to toggle. If the
user attempts to write to a protected sector, DATA Polling
will be activated for about 1 s; the device will then return
to read mode, with data from the protected sector unchanged. If the user attempts to erase a protected sector, Toggle Bit will be activated for about 50 s; the
device will then return to read mode, without having
erased the protected sector.
DQ5: Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count).
Under these conditions, DQ5 will produce a 1 indicating that the program or erase cycle was not successfully completed. Write operation status and reset
command are the only operating functions under this

condition. The device will draw active power under this

condition.
The DQ5 failure condition will also appear if the user attempts to write a data 1 to a bit that has already been
programmed to a data 0. In this case, the DQ5 failure
condition is not guaranteed to happen, since the device
was incorrectly used. Please note that programming a
data 0 to a data 1 should never be attempted, and
only erasure should be used for this purpose. If programming to a data 1 is attempted, the device should
be reset.
If the DQ5 failure condition is observed while in Sector
Erase mode (that is, exceeded timing limits), then DQ2
can be used to determine which sector had the problem. This is especially useful when multiple sectors
have been loaded for erase.
DQ3: Sector Erase Timer
After the completion of the initial Sector Erase command sequence, the Sector Erase time-out will begin.
DQ3 will remain low until the time-out is complete.
DATA Polling (DQ7) and Toggle Bit (DQ6) are also valid
after the first sector erase command sequence.
If DATA Polling or the Toggle Bit indicates the device
has been written with a valid Sector Erase command,
DQ3 may be used to determine if the sector erase timer
window is still open. If DQ3 is high (1), the internally
controlled erase cycle has begun; attempts to write
subsequent commands to the device will be ignored
until the erase operation is completed as indicated by
the DATA Polling or Toggle Bit. If DQ3 is low (0), the
device will accept additional sector erase commands.
To be certain the command has been accepted, the
software should check the status of DQ3 following each
Sector Erase command. If DQ3 was high on the second status check, the command may not have been accepted.
It is recommended that the user guarantee the time between sector erase command writes be less than 80 s
by disabling the processor interrupts just for the duration of the Sector Erase (30h) commands. This approach will ensure that sequential sector erase
command writes will be written to the device while the
sector erase timer window is still open.
DQ2: Toggle Bit 2
This toggle bit, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause
DQ2 to toggle during the Embedded Erase Algorithm.
If the device is in the erase suspend-read mode, successive reads from the erase-suspended sector will
cause DQ2 to toggle. When the device is in the erase
suspend-program mode, successive reads from the
byte address of the non-erase suspended sector will

Am29LV800T/Am29LV800B

19

P R E L I M I N A R Y
indicate a logic 1 at the DQ2 bit. Note that a sector
which is selected for erase is not available for read in
Erase Suspend mode. Other sectors which are not selected for Erase can be read in Erase Suspend.
DQ6 is different from DQ2 in that DQ6 toggles only
when the standard program or erase, or erase
suspend-program operation is in progress.
If the DQ5 failure condition is observed while in Sector
Erase mode (that is, exceeded timing limits), the DQ2
toggle bit can give extra information. In this case, the
normal function of DQ2 is modified. If DQ5 is at logic
1, then DQ2 will toggle with consecutive reads only at
the sector address that caused the failure condition.
DQ2 will toggle at the sector address where the failure
occurred and will not toggle at other sector addresses.
RY/BY: Ready/Busy Pin
The Am29LV800 provides a RY/BY open-drain output
pin as a way to indicate to the host system that the

Table 8.
Mode

Embedded Algorithms are either in progress or have

been completed. If the output is low, the device is busy
with either a program or erase operation. If the output
is high, the device is ready to accept any read/write or
erase operation. When the RY/BY pin is low, the device will not accept any additional program or erase
commands with the exception of the Erase Suspend
command. If the Am29LV800 is placed in an Erase
Suspend mode, the RY/BY output will be high. For
programming, the RY/BY is valid (RY/BY=0) after the
rising edge of the fourth WE pulse in the four write
pulse sequence. For chip erase, the RY/BY is valid
after the rising edge of the sixth WE pulse in the six
write pulse sequence. For sector erase, the RY/BY is
also valid after the rising edge of the sixth WE pulse.
Since the RY/BY pin is an open-drain output, several
RY/BY pins can be tied together in parallel with a
pull-up resistor to VCC.

Toggle Bit Status

DQ7

DQ6

DQ2

DQ7

Toggles

Erase

Toggles

Toggles

Erase-Suspend Read (Note 1) (Erase-Suspended Sector)

Toggles

DQ7 (Note 2)

Toggles

1 (Note 2)

Program

Erase Suspend Program

Notes:
1. These status flags apply when outputs are read from a sector that has been erase suspended.
2. These status flags apply when outputs are read from the byte/word addresses of the non-erase suspended sector.
CE
LAST_BUS_CYCLE
WE

RY/BY
tBUSY
20478D-9

Figure 2.

20

RY/BY Timing Diagram

Am29LV800T/Am29LV800B

P R E L I M I N A R Y
RESET: Hardware Reset Pin
The RESET pin is an active low signal. A logic 0 on this
pin will force the device out of any mode that is currently
executing back to the reset state. This allows a system
reset to take effect immediately without having to wait for
the device to finish a long execution cycle. To avoid a potential bus contention during a system reset, the device
is isolated from the data I/O bus by tri-stating the data
output pins for the duration of the RESET pulse.
If RESET is asserted during a program or erase operation, the RY/BY pin will remain low until the reset operation is internally complete. This will require between
1 s and 20 s. Hence the RY/BY pin can be used to
signal that the reset operation is complete. Otherwise,
allow for the maximum reset time of 20 s. If RESET is
asserted when a program or erase operation is not executing (RY/BY pin is high), the reset operation will be
complete within 500 ns.

Asserting RESET during a program or erase operation

leaves erroneous data stored in the address locations
being operated on at the time of device reset. These locations need updating after the reset operation is complete. See Figure 4 for timing specifications.
The device enters ICC4 standby mode (200 nA) when
VSS 0.3 V is applied to the RESET pin. The device can
enter this mode at any time, regardless of the logical
condition of the CE pin. Furthermore, entering ICC4
during a program or erase operation leaves erroneous
data in the address locations being operated on at the
time of the RESET pulse. These locations need updating after the device resumes standard operations. After
the RESET pin goes high, a minimum latency period of
50 ns must occur before a valid read can take place.

tRL

RESET

RY/BY
20 s max
20478D-10

Figure 3.

Device Reset During a Program or Erase Operation

tRL

RESET

RY/BY
0V

20478D-11

Figure 4.

Device Reset During Read Mode

Am29LV800T/Am29LV800B

21

P R E L I M I N A R Y

Word/Byte Configuration
The BYTE pin of the Am29LV800 is used to set device
data I/O pins in the byte or word configuration. If the
BYTE pin is set at logic 1, the device is in word configuration, DQ015 are active and controlled by CE and
OE (see Figure 5).

If the BYTE pin is set at logic 0, the device is in byte

configuration, and only data I/O pins DQ07 are active
and controlled by CE and OE. The data I/O pins DQ8
14 are tri-stated. In byte mode, the DQ15 pin is used as
an input for the LSB (A-1) address function (see Figure 6).

CE

OE

BYTE
tELFH
DQ8DQ14

DQ8DQ14

DQ8DQ14

tFHQV
DQ15/A-1

A-1

DQ15
20478D-12

Figure 5.

Timing Diagram for Word Mode Configuration

CE

OE

BYTE
tELFL
DQ8DQ14

DQ8DQ14

DQ15/A-1

DQ15

DQ8DQ14

A-1

tFLQZ
20478D-13

Figure 6.

22

Timing Diagram for Byte Mode Configuration

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

Data Protection
The Am29LV800 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power-up, the device automatically resets
the internal state machine to the read mode. Also, with
its control register architecture, alteration of the memory contents only occurs after successful completion of
the command sequences.

be ignored until the VCC level is greater than VLKO. It is

the users responsibility to ensure that the control levels
are logically correct when VCC is above VLKO (unless
the RESET pin is asserted).

Write Pulse Glitch Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or
WE will not change the command registers.

Logical Inhibit

The Am29LV800 incorporates several features to prevent inadvertent write cycles resulting from V CC
power-up and power-down transitions or system noise.

Writing is inhibited by holding any one of OE = VIL, CE

= VIH, or WE = VIH. To initiate a write, CE and WE must
be logical zero while OE is a logical one.

Low VCC Write Inhibit

Power-Up Write Inhibit

To avoid initiation of a write cycle during VCC power-up

and power-down, a write cycle is locked out for VCC
less than VLKO (lock-out voltage). If VCC < VLKO, the
command register is disabled and all internal program/
erase circuits are disabled. Under this condition, the
device will reset to read mode. Subsequent writes will

Power up of the device with WE = CE = VIL and OE =

VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to
read mode on power up.

Am29LV800T/Am29LV800B

23

P R E L I M I N A R Y

EMBEDDED ALGORITHMS
START

Write Program Cmd Sequence

Data Poll Device

No

Verify Byte?

Yes

Increment Address

No

Last Address?

Yes
Programming Completed

20478D-14

Figure 7.

Embedded Program Algorithm

Embedded Program Algorithm

Bus Operation

Command Sequence

Comments

Program

Valid Address/Data

Standby*
Write
Read

DATA Polling to Verify Programming

Standby*

Compare Data Output to Data Expected

* Device is either powered-down, erase inhibit, or program inhibit.

24

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

START

Write Erase Cmd Sequence

Data Poll from Device

No

Data = FFH?

Yes
Erasure Completed

20478D-15

Figure 8.

Embedded Erase Algorithm

Embedded Erase Algorithm

Bus Operation

Command Sequence

Comments

Standby
Write

Erase

Read

DATA Polling to Verify Erasure

Standby

Compare Output to FFh

Am29LV800T/Am29LV800B

25

P R E L I M I N A R Y

Data Polling Algorithm

START

DQ7 = Data?

Yes

No
No

DQ5 = 1?

Yes

DQ7 = Data?

Yes

No
FAIL

PASS

20478D-16

Figure 9.

26

Data Polling Algorithm

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

Toggle Bit Algorithm

START

DQ6 = Toggle?

No

Yes
No

DQ5 = 1?

Yes

DQ6 = Toggle?

No

Yes
FAIL

PASS

20478D-17

Figure 10.

Toggle Bit Algorithm

20 ns

20 ns

+0.8 V
0.5 V
2.0 V
20 ns
20478D-18

Figure 11.

Maximum Negative Overshoot Waveform

20 ns

VCC + 2.0 V
VCC + 0.5 V
2.0 V
20 ns

20 ns
20478D-19

Figure 12.

Maximum Positive Overshoot Waveform

Am29LV800T/Am29LV800B

27

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . 65C to +150C

Commercial (C) Devices

Ambient Temperature
with Power Applied. . . . . . . . . . . . . . 55C to +125C

Industrial (I) Devices

Voltage with Respect to Ground

All pins except A9 (Note 1). . . . . 0.5 V to VCC +4.5 V

Extended (E) Devices

VCC (Note 1). . . . . . . . . . . . . . . . . . . . 0.5 V to +5.5 V

Ambient Temperature (TA). . . . . . . . . . . . 0C to +70C

Ambient Temperature (TA). . . . . . . . . . 40C to +85C
Ambient Temperature (TA). . . . . . . . . 55C to +125C

RESET, OE, A9 (Note 2) . . . . . . . . . 0.5 V to +13.0 V

VCC Supply Voltages

Output Short Circuit Current (Note 3) . . . . . . 200 mA

VCC for Am29LV800T/B-90R. . . . . . . . +3.0 V to 3.6 V

Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During
voltage transitions, inputs may overshoot VSS to 2.0 V for
periods of up to 20 ns. Maximum DC voltage on input and
I/O pins is VCC + 0.5 V. During voltage transitions, input
and I/O pins may overshoot to VCC + 2.0 V for periods up
to 20ns.

VCC for Am29LV800T/B-100,

-120, -150 . . . . . . . . . . . . . . . . . . . . . . +2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.

2. Minimum DC input voltage on A9 pin is 0.5 V. During

voltage transitions, A9 may overshoot VSS to 2.0 V for
periods of up to 20 ns. Maximum DC input voltage on A9
is +13.5 V which may overshoot to 14.0 V for periods up
to 20 ns.
3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for extended periods may affect device reliability.

28

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol

Parameter Description

Test Conditions

ILI

Input Load Current

VIN = VSS to VCC,

VCC = VCC max

ILIT

A9 Input Load Current

VCC = VCC max; A9 = 13.0 V

ILO

Output Leakage Current

VOUT = VSS to VCC,

VCC = VCC max

ICC1

Min

Max

Unit

1.0

35

1.0

CE = VIL, OE = VIH,
Byte Mode

5 MHz

16

1 MHz

CE = VIL, OE = VIH,
Word Mode

5 MHz

16

1 MHz

VCC Active Current (Note 1)

mA

ICC2

VCC Active Current (Notes 2 and 4)

CE = VIL, OE = VIH

30

mA

ICC3

VCC Standby Current

VCC = VCC max;

CE, RESET = VCC0.3 V

ICC4

VCC Reset Current

VCC = VCC max;

RESET = VSS 0.3 V

ICC5

Automatic Sleep Mode (Note 3)

VIH = VCC 0.3 V;

VIL = VSS 0.3 V

VIL

Input Low Voltage

0.5

0.8

VIH

Input High Voltage

0.7 x VCC

VCC + 0.3

VID

Voltage for Autoselect and Temporary

Sector Unprotect

VCC = 3.3 V

11.5

12.5

VOL

Output Low Voltage

IOL = 4.0 mA, VCC = VCC min

0.45

VOH1

Output High Voltage

VOH2
VLKO

IOH = 2.0 mA, VCC = VCC min

0.85 VCC

IOH = 100 A, VCC = VCC min

VCC0.4

Low VCC Lock-Out Voltage (Note 4)

2.3

2.5

Notes:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The
frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. ICC active while Embedded Erase or Embedded Program is in progress.
3. Automatic sleep mode enables the low power mode when addresses remain stable for 200 ns. Typical sleep mode current is
200 nA.
4. Not 100% tested.

Am29LV800T/Am29LV800B

29

P R E L I M I N A R Y

DC CHARACTERISTICS (Continued)

Supply Current in mA

25

20

15

10

5
0
0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns
Note: Addresses are switching at 1 MHz
20478D-20

Figure 13A.

ICC Current vs. Time

Supply Current in mA

15

10

3.6 V
2.7 V
5

0
1

3
Frequency in MHz

Note: T = 25 C

5
20478D-21

Figure 13B.

30

ICC vs. Frequency

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

DC CHARACTERISTICS (Continued)
TTL/NMOS Compatible
Parameter
Symbol

Parameter Description

ILI

Input Load Current

Test Description

Min

Max

Unit

1.0

35

1.0

Byte

30

mA

Word

35

VIN = VSS to VCC, VCC = VCC MAX

ILIT

A9 Input Load Current

VCC = VCC MAX, A9 = VID

ILO

Output Leakage Current

VOUT = VSS to VCC, VCC = VCC MAX

ICC1

VCC Active Read Current (Note 1)

CE = VIL, OE = VIH

VCC Active Write Current (Note 2)

CE = VIL, OE = VIH

35

mA

ICC3

VCC Standby Current

VCC = VCC MAX, CE = VIH, RESET = VIH

250

ICC4

VCC Standby Current During Reset

VCC = VCC MAX, CE = VIH, RESET = VIL

250

ICC5

Automatic Sleep Mode (Note 3)

CE = VIL, OE = VIH

250

VIL

Input Low Level

0.5

0.8

VIH

Input High Level

2.0

VCC +
0.5

VID

Voltage for Autoselect and Sector Protect

11.5

12.5

VOL

Output Low Level

IOL = 4.0 mA, VCC = VCC MIN

0.45

VOH

Output High Level

IOH = -2.0 mA, VCC = VCC MIN

VLKO

Low VCC Lock-Out Voltage (Note 4)

2.4
2.3

V
2.5

VCC = 2.7 V to 3.6 V

Notes:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. Automatic sleep mode enables the low power mode when addresses remain stable for 300 ns. Typical sleep mode current is
80 A.
4. Not 100% tested.

Am29LV800T/Am29LV800B

31

P R E L I M I N A R Y

AC CHARACTERISTICS
Read-Only Operations Characteristics
Parameter Symbols

Speed Option (Note 1)

JEDEC

Standard

Description

Test Setup

-90R

-100

-120

-150

Unit

tAVAV

tRC

Read Cycle Time (Note 3)

Min

90

100

120

150

ns

tAVQV

tACC

Address to Output Delay

CE = VIL
OE = VIL

Max

90

100

120

150

ns

tELQV

tCE

Chip Enable to Output Delay

OE = VIL

Max

90

100

120

150

ns

tGLQV

tOE

Output Enable to Output Delay

Max

40

40

50

55

ns

tEHQZ

tDF

Chip Enable to Output High Z (Notes 2, 3)

Max

30

30

30

40

ns

tGHQZ

tDF

Output Enable to Output High Z (Notes 2, 3)

Max

30

30

30

40

ns

tAXQX

tOH

Output Hold Time From Addresses, CE or

OE, Whichever Occurs First (Note 3)

Min

ns

tReady

RESET Pin Low to Read Mode (Note 3)

Max

20

20

20

20

Notes:
1. Test Conditions
Input Rise and Fall Times: 5 ns
Input Pulse Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level:
Input: 1.5 V
Output: 1.5 V
2. Output Driver Disable Time
3. Not 100% tested.

3.3 V
IN3064
or Equivalent

Device
Under
Test
CL

2.7 k

6.2 k

IN3064 or Equivalent

IN3064 or Equivalent

IN3064 or Equivalent

Notes:
CL = 30 pF for 90 and 100 ns
CL = 100 pF for 120 and 150 ns

20478D-15

Figure 14.

32

Test Conditions

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

AC CHARACTERISTICS
Write (Erase/Program) Operations
Parameter Symbols
JEDEC

Standard

Description

-90R

-100

-120

-150

Unit

tAVAV

tWC

Write Cycle Time (Note 2)

Min

90

100

120

150

ns

tAVWL

tAS

Address Setup Time

Min

ns

tWLAX

tAH

Address Hold Time

Min

50

50

50

65

ns

tDVWH

tDS

Data Setup Time

Min

50

50

50

65

ns

tWHDX

tDH

Data Hold Time

Min

ns

tOES

Output Enable Setup Time (Note 2)

Min

ns

Read (Note 2)

Min

ns

tOEH

Output Enable
Hold TIme

Toggle and Data Polling

(Note 2)

Min

10

10

10

10

ns

tGHWL

tGHWL

Read Recovery TIme Before Write

(OE High to WE Low)

Min

ns

tELWL

tCS

CE Setup TIme

Min

ns

tWHEH

tCH

CE Hold TIme

Min

ns

tWLWH

tWP

Write Pulse Width

Min

50

50

50

65

ns

tWHDL

tWPH

Write Pulse Width High

Min

30

30

30

35

ns

Byte

Typ

tWHWH1

tWHWH1

Programming Operation
Word

Typ

11

11

11

11

tWHWH2

tWHWH2

Sector Erase Operation (Note 1)

Typ

sec

tVCS

VCC Setup TIme

Min

50

50

50

50

tRB

Write Recovery Time from RY/BY

Min

ns

tRH

RESET High Time Before Read

Min

50

50

50

50

ns

tRPD

RESET To Power Down Time

Min

20

20

20

20

tBUSY

Program/Erase Valid to RY/BY Delay

Min

90

90

90

90

ns

Max

ns

tELFL/tELFH CE to BYTE Switching Low or High

tFLQZ

BYTE Switching Low to Output HIGH Z

Min

30

30

40

40

ns

tFHQV

BYTE Switching High to Output Active

Min

30

30

40

40

ns

tVIDR

Rise TIme to VID

Min

500

500

500

500

ns

tRP

RESET Pulse Width

Min

500

500

500

500

ns

t RRB

RESET Low to RY/BY High

Max

20

20

20

20

tRSP

RESET Setup Time for Temporary Sector

Unprotect

Min

Notes:
1. The duration of the program or erase operation is variable and is calculated in the internal algorithms.
2. Note 100% tested.

Am29LV800T/Am29LV800B

33

P R E L I M I N A R Y

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Must be
Steady

Will be
Steady

May
Change
from H to L

Will be
Changing
from H to L

May
Change
from L to H

Will be
Changing
from L to H

Dont Care,
Any Change
Permitted

Changing,
State
Unknown

Does Not
Apply

Center
Line is HighImpedance
Off State
KS000010-PAL

SWITCHING WAVEFORMS
3.0 V

Input

1.5 V

Measurement Level

1.5 V

Output

0.0 V
20478D-16

Figure 15.

34

Input Waveforms and Measurement Levels

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

SWITCHING WAVEFORMS
tRC
Addresses Stable

Addresses

tACC
CE
tOE

tDF

OE
tOEH
tCE

WE

tOH

HIGH Z

HIGH Z
Output Valid

Outputs

20478D-17

Figure 16.

tWC

AC Waveforms for Read Operations

tAS

Addresses
tAH

tRC

CE
tGHWL
OE
tWP
WE

tCS

tWHWH1_or_2
tDF

tWPH
tDH

tOE
DIN

DATA

DQ7

DOUT

tDS

tOH

VCC

tCE

Notes:
1. DIN is the data input to the device.
2. DQ7 is the output of the complement of the data written to the device.
3. DOUT is the output of the data written to the device.
20478D-18

Figure 17.

Program Operations Timings

Am29LV800T/Am29LV800B

35

P R E L I M I N A R Y

SWITCHING WAVEFORMS
tWC
Addresses

tAS

555h

555H for chip erase

2AAh

555h

555h

2AAh

SA

tAH
CE
tGHWL
OE
tWP
WE
tCS

tWPH

tDS
10h for Chip Erase

tDH
DATA

AAh

55h

80h

AAh

55h

30h

VCC

Notes:
1. SA is the sector address for Sector Erase. Addresses = Dont Care for Chip Erase.
2. These waveforms are for the x16 mode.
20478D-19

Figure 18.

AC Waveforms for Chip/Sector Erase Operations

tCH
CE

tDF

tOE
OE

tOEH

WE

tCE

DQ7

DQ7

tOH
DQ7=Valid Data

HIGH Z

tWHWH1_or_2
DQ0-DQ6

DQ0-DQ6=Invalid Data

DQ0-DQ6 Valid Data

HIGH Z

Note:
DQ7 = Valid Data (The device has completed the embedded operation.)
20478D-20

Figure 19.

36

AC Waveforms for Data Polling During Embedded Algorithm Operations

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

SWITCHING WAVEFORMS
CE

tOEH

WE
OE
DQ6/DQ2
tDH

tOE

Note:
DQ6 stops toggling (The device has completed the embedded operation.)
20478D-21

Figure 20.

Toggle Bit Timings (During Embedded Algorithm Operations)

CE
The rising edge of the last WE signal
WE

Entire programming
or erase operations

RY/BY
tBUSY

Note:
DQ7 = Valid Data (The device has completed the embedded operation.)
20478D-22

Figure 21.

RY/BY Timing Diagram (During Program/Erase Operations)

RESET

tRP
tReady

20478D-23

Figure 22.

RESET Timing Diagram

Am29LV800T/Am29LV800B

37

P R E L I M I N A R Y

SWITCHING WAVEFORMS
CE

OE

BYTE

tELFL
tELFH

Data Output
(DQ0DQ14)

DQ0DQ14

DQ15
Output

DQ15/A-1

Data Output
(DQ0DQ7)

Address
Input

tFLQZ

20478D-24

Figure 23.

BYTE Timing Diagram for Read Operation

CE
The falling edge of the last WE signal
WE

BYTE

tSET
(tAS)

tHOLD (tAH)

20478D-25

Figure 24.

38

BYTE Timing Diagram for Write Operations

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

Start

RESET = VID
(Note 1)
Perform Erase or
Program Operations

RESET = VIH

Temporary Sector
Unprotect Completed
(Note 2)

Notes:
1. All protected sectors unprotected.
All previously protected sectors are protected once again.
20478D-26

Figure 25.

Temporary Sector Unprotect Algorithm

tVIDR
12 V
RESET
0 V or 3 V

0 V or 3 V
CE

WE
tRSP

Program or Erase Command Sequence

20478D-27

Figure 26.

Temporary Sector Unprotect Timing Diagram

Am29LV800T/Am29LV800B

39

P R E L I M I N A R Y

AC CHARACTERISTICS
Write (Erase/Program) Operations
Alternate CE Controlled Writes
Parameter Symbols
JEDEC

Standard

Description

-90R

-100

-120

-150

Unit

tAVAV

tWC

Write Cycle Time (Note 2)

Min

90

100

120

150

ns

tAVWL

tAS

Address Setup Time

Min

ns

tELAX

tAH

Address Hold Time

Min

50

50

50

65

ns

tDVEH

tDS

Data Setup Time

Min

50

50

50

65

ns

tEHDX

tDH

Data Hold Time

Min

ns

tOES

Output Enable Setup Time

Min

ns

Read (Note 2)

Min

ns

tOEH

Output Enable
Hold TIme

Toggle and Data Polling

(Note 2)

Min

10

10

10

10

ns

tGHEL

tGHEL

Read Recovery TIme Before Write

(OE High to WE Low)

Min

ns

tWLEL

tWS

WE Setup TIme

Min

ns

tEHWH

tWH

WE Hold TIme

Min

ns

tELEH

tCP

CE Pulse Width

Min

50

50

50

65

ns

tEHEL

tCPH

CE Pulse Width High

Min

30

30

30

35

ns

Byte

Typ

tWHWH1

tWHWH1

Programming Operation
Word

Typ

11

11

11

11

tWHWH2

tWHWH2

Sector Erase Operation (Note 1)

Typ

sec

tFLQZ

BYTE Switching Low to Output HIGH Z

(Note 2)

Min

30

30

30

30

ns

Notes:
1. The duration of the program or erase operation is variable and is calculated in the internal algorithms.
2. Does not include the preprogramming time.
3. Not 100% tested.

40

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

SWITCHING WAVEFORMS
tWC
ADDRESSES

Data Polling

tAS

555h

PA

PA
tAH

WE
tGHWL
OE
tCP
CE

tWS

tWHWH1_or_2

tCPH
tDS
tDH
A0h

Data

PD

DQ7

DOUT

VCC
tVCS
20478D-33

Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the complement of the data written to the device.
4. DOUT is the data written to the device.
Figure indicates last two bus cycles of four bus cycle sequence

Figure 27.

Alternate CE Controlled Write Operation Timings

Am29LV800T/Am29LV800B

41

P R E L I M I N A R Y

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 2)

Max (Note 3)

Unit

Sector Erase Time

15

Chip Erase Time

19

Byte Programming Time

300

Word Programming Time

11

360

Byte Mode

27

Word Mode

5.8

17

Comments
Excludes 00h programming
prior to erasure (Note 4)

Excludes system level

overhead (Note 5)

Chip Programming Time

Erase/Program Endurance

1,000,000

cycles

Minimum 100,000 cycles

guaranteed

Notes:
1. The typical program and erase times are considerably less than the maximum times since most words/bytes program or erase
significantly faster than the worst case word/byte. The device enters the failure mode (DQ5=1) only after the maximum times
given are exceeded. See the section on DQ5 for further information.
2. Except for erase and program endurance, the typical program and erase times assume the following conditions: 25C, 3.0 V
VCC, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern.
3. Under worst case conditions of 90C, VCC = 2.7 V, 100,000 cycles.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 6
for further information on command definitions.

LATCHUP CHARACTERISTICS
Min

Max

Input Voltage with respect to VSS on all pins except I/O pins (Including A9 and OE)

1.0 V

13.0 V

Input Voltage with respect to VSS on all I/O pins

1.0 V

VCC + 1.0 V

100 mA

+100 mA

Current

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

PIN CAPACITANCE, 48-PIN TSOP

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

CIN

Input Capacitance

VIN = 0

7.5

pF

COUT

Output Capacitance

VOUT = 0

8.5

12

pF

CIN2

Control Pin Capacitance

VIN = 0

10

pF

Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25C, f = 1.0 MHz.

42

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

PIN CAPACITANCE, 44-PIN PSOP

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

CIN

Input Capacitance

VIN = 0

7.5

pF

COUT

Output Capacitance

VOUT = 0

8.5

12

pF

CIN2

Control Pin Capacitance

VIN = 0

10

pF

Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25C, f = 1.0 MHz.

DATA RETENTION
Parameter
Minimum Pattern Data Retention Time

Test Conditions

Min

Unit

150C

10

Years

125C

20

Years

Am29LV800T/Am29LV800B

43

P R E L I M I N A R Y

PHYSICAL DIMENSIONS*
TS 048
48-Pin Standard Thin Small Outline Package (measured in millimeters)

0.95
1.05
Pin 1 I.D.
1

48

11.90
12.10

0.50 BSC
24

25

0.05
0.15

18.30
18.50
19.80
20.20
0.08
0.20
0.10
0.21

1.20
MAX
0.25MM (0.0098") BSC

0
5
0.50
0.70

44

For reference only, not drawn to scale. BSC is an ANSI standard for Basic Space Centering.

Am29LV800T/Am29LV800B

16-038-TS48-2
TS 048
DA101
8-8-94 ae

P R E L I M I N A R Y

PHYSICAL DIMENSIONS (continued)

TSR048
48-Pin Reverse Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1

48

11.90
12.10

0.50 BSC
24

25

0.05
0.15

18.30
18.50
19.80
20.20

SEATING PLANE

0.08
0.20
0.10
0.21

1.20
MAX
0.25MM (0.0098") BSC

0
5

16-038-TS48
TSR048
DA104
8-8-94 ae

0.50
0.70

Am29LV800T/Am29LV800B

45

P R E L I M I N A R Y

PHYSICAL DIMENSIONS (continued)

SO 044
44-Pin Thin Small Outline Package (measured in millimeters)
44

23

13.10
13.50

15.70
16.30

22
1.27 NOM.
TOP VIEW

28.00
28.40

2.17
2.45

0.10
0.21

2.80
MAX.
0.35
0.50

0.10
0.35

SEATING
PLANE

SIDE VIEW

46

0
8

0.60
1.00
END VIEW
16-038-SO44-2
SO 044
DA82
11-9-95 lv

Am29LV800T/Am29LV800B

P R E L I M I N A R Y

REVISION SUMMARY FOR AM29LV800

Distinctive Characteristics:
Rearranged bullets. Renamed Extended voltage
range... bullet to Single power supply operation.
Under Single power supply operation and High performance bullets, defined standard and extended voltage ranges and added 90 ns speed option. Combined
Advanced power management and Low current consumption bullets into new Ultra low power consumption bullet. Under that bullet, revised the typical
standby and automatic sleep mode current specifications from 1 A to 200 nA; revised read current specification from 10 mA to 2 mA/MHz. Combined Sector
protection and Flexible sector architecture bullets.
Under flexible sector architecture bullet, added temporary sector unprotect feature description. Combined
Embedded Program and Embedded Erase bullets
under new Embedded Algorithms bullet; removed
designations. Clarified descriptions of sector protection, erase suspend/resume, hardware reset pin,
ready/busy pin, and data polling and toggle bits.
General Description:
Added text on -90R speed option and voltage range to
the second paragraph.

Table 6, Command Definitions:

Grouped address designators PA, PD, RA, RD, and SA
under the legend heading. Modified SA definition to accommodate the sector protect verify command. Since
unlock addresses only require address bits A0A10 to
be valid, the number of hexadecimal digits in the unlock
addresses were changed from four to three. The remaining upper address bits are dont care. Removed
H designation from hexadecimal values in table and
replaced with new Note 1. Revised Notes 5 and 6 to indicate when commands are valid; are now Notes 4 and
5. Expanded autoselect section to show each function
separately: manufacturer ID, device ID, and sector protect verify. Added Note 3 to explain sector protect
codes. Deleted Note 7. Added Note 6 to indicate which
addresses are dont care. Corrected unlock and command addresses for byte mode from 2AA to AAA.
Corrected byte-mode read cycle (fourth cycle) addresses from 01h to 02h for device ID, and from SAX02
to SAX04 for sector protect verification.
RESET: Hardware Reset Pin:
Fourth paragraph: Revised standby mode specification
to 200 nA.

Product Selector Guide:

Added -90R voltage range and speed option.

Figure 6, Timing Diagram for Byte Mode

Configuration:
Moved end of tFLQZ period from within the A-1 data flow
to the start of A-1 data flow.

Connection Diagrams
Corrected pinouts on pins 13 and 14 for the standard
TSOP drawing. (Revision C)

Operating Ranges:
VCC Supply Voltages: Expanded into two voltage
ranges; added -90R speed option.

Corrected pinouts on pins 33 and 32 for the reverse

TSOP drawing. (Revision C)

DC Characteristics:
CMOS Compatible: Changed ICC1 from 30 mA maximum at 6 MHz to 16 mA maximum at 5 MHz and 4 mA
maximum at 1 MHz. Changed ICC2 from 35 mA to 30
mA maximum. In Note 1, changed 6 MHz to 5 MHz. In
Note 3, changed address stable time from 300 ns to
200 ns; changed typical sleep mode current from 1 A
to 200 nA.

Corrected pinouts for pins 13, 14, 17, and 18 on standard TSOP package. (Revision D)
Pin Configuration:
Added new voltage range to VCC specification.
Ordering Information, Standard Products:
The -90R speed option is now listed in the example.
Revised Speed Option section to indicate both voltage ranges.

Valid Combinations: Added -90R speed option and

voltage range.
Automatic Sleep Mode:
Revised addresses stable time to 200 ns and typical
current draw to 200 nA.
Autoselect:
Fourth paragraph, last sentence: Corrected to ...DQ9
and DQ13 are equal to 1...
Table 4, Sector Address Table:
Corrected SA12, x8 starting address from D0000 to
C0000.

Figure 13A, ICC Current vs. Time, and Figure 13B,

ICC vs. Frequency:
Figure 8A illustrates current draw during the Automatic
Sleep Mode after the addresses are stable. Figure 8B
shows how frequency affects the current draw curves
for both voltage ranges.
AC Characteristics:
Read Only Operations Characteristics: Added -90R
column.
Test Conditions, Figure 13:
Added 90 ns speed to CL note.
AC Characteristics:
Write/Erase/Program Operations: Added the -90R column. Corrected tWAX to tWLAX.

Am29LV800T/Am29LV800B

47

P R E L I M I N A R Y
Figure 17, AC Waveforms for Chip/Sector Erase
Operations:
Added 555 chip erase to last cycle in sequence.
Changed addresses to three hexadecimal digits to
match command definitions (Table 6).
Figure 18, AC Waveforms for Data Polling During
Embedded Algorithm Operations:
Split data signal into DQ0DQ6 and DQ7 signals.
Figure 25, Temporary Sector Unprotect Timing
Diagram:
Corrected callout and waveform to show that tVIDR applies whether RESET rises from either 0 V or 3 V.
AC Characteristics:
Alternate CE Controlled Writes: Added the -90R column.

Erase and Programming Performance:

Added typical chip erase specification. Deleted column for minimum specifications. Created separate
chip program specifications for word and byte modes.
Renamed erase/program cycles specification to
erase/program endurance. Moved minimum 100,000
cycle endurance to comments section. Revised Note
1 to include write endurance, is now Note 2. Consolidated and moved Note 1 and Note 3 references in
table to table head. Combined Note 2 and Note 5 into
new Note 1, which applies to the entire table; revised
to indicate that DQ5=1 after the maximum times.
Comments for program and erase now straddle parameter rows. Separated the two sentences in Note 4
into new Notes 4 and 5; added corresponding note
references to comment section.

Figure 26, Alternate CE Controlled Write Operation

Timings:
Changed 5555H to 555H match command definitions
(Table 6).

Trademarks
Copyright 1997 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof and ExpressFlash are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

48

Am29LV800T/Am29LV800B