1

Vector current control of a three phase LC load connected to

a virtual grid (January 2016)
Biyadgie Ayalew, STEPS Student, Aregawi Gebru, STEPS student

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I. INTRODUCTION
In the new power system network, renewable energy
distributed generators are highly being used due to
environmental concern of traditional power generation system.
Distributed generation also enable to generate power with
locally available resources and the extra effort to build new
transmission and distribution network can be avoided[1].
But as the power output of many of the distributed generators
is variable due to their intermittent nature, there should be a
mechanism to make their power output usable for loads. This
can be realized through power electronic interfaces which
enable them to be able connect to a grid or loads[2].
The power electronics interface enables to control the power
injection of distributed generators. This is possible by
controlling the LC filter connected to the power electronics
interface of the distributed generators. The active and reactive
power injection of the distributed generators can be managed
by controlling the current through the LC filter. Vector control
method is important to control the active and reactive power
generation separately. There are different control methods like
non-linear (hysteresis control method) , linear control method
(PI with PWM) and deadbeat control. But PI controller is
simple and effective method to control the d- and q-axis
current of the LC filter[3].
The aim of this work is to built a prototype of grid connected
distributed generator based on three phase inverter. After some
literature reviews related to the topic, a methodology is
developed to model and implement the prototype. When the
distributed generators are connected to the grid, there are

different issues should be solved before. The generator should

be synchronized to the grid otherwise it will be a problem and
cause some short circuit disaster. The other issue that is
addressed in this project is the power factor of the generator to
control the active and reactive power injection of the generator
for the better performance of the grid. For grid
synchronization of the generator, two methods acrtan function
and synchronous PLL is tested . The control of power
factor(active and reactive power injection of the generator) is
implemented using vector control method.
PSIM software is used to model the system and to study the
performance like the dynamic response and steady state error
performance of the current controllers. Moreover, the
performance of the grid synchronization methods are
evaluated in the modeling before the system is implemented.
After checking the selected design parameters for the system
are working well, the prototype is implemented. Hardware
part which is PCB board to interface the inverter with the DSP
is designed using Altium software and constructed within the
university Lab. The software part which consist of the
controller and configuration of the DSP is implemented using
Code Composer Studio(CCS). Texas instrument F28335 DSP
is used to realize the digital controller.
II. MAIN COMPONENTS AND OVERVIEW OF THE PROTOTYPE
SYSTEM

It is shown in the diagram below that the main components

of the system are interface card(PCB), virtual grid, power
stage and DSP. The power stage consist of the inverter, LC
filter and the resistive load. A Gaush. company
inverter(MTL-CBI0020N12IXFE) is used and the inverter has
other auxiliary components like three phase current sensors, 7
fault signals feedback, DC-link voltage sensor, reset input and
relay input for the DC-link capacitor safety.
The PCB is manufactured in the university Lab and it has
signal conditioning circuits for voltage and current sensors,
reset circuit, relay circuit, DB25 interfaces for the inverter and
interfaces to the DSP.
Texas instrument F28335 DSP is used to implement the
digital controller. Digital PI controller is implemented with
sampling frequency of 10KHz. The main features of the DSP
used in this project are ADC, ePWM modules and GPIOs.
The virtual grid is used for emulation of synchronization of
the currents to the grid in real application. Two phases of the
virtual grid are read using voltage sensors assuming that the
three phases are balanced.

2
is synchronizing angle,
, and
are three
phase currents and
and
are synchronous frame
currents.
is due to the zero sequence currents in three
phase measurement.

Where

This transformation puts q- axis in negative direction but since

the reverse transformation is also negative, there isn't impact
on the controller performance.
V. CURRENT CONTROLLERS DESIGN
The transfer function is derived based on the voltage across
the filter and the load as input and the current through as
output. And it is assumed that all the three phases are
considered as balanced. The relationship between the d-and qaxis voltage across the filter and the load with the current
through can be derived as shown in the following.
=
=

Fig. 1 System components and their interaction

III. DETERMINATION OF THE FILTER PARAMETERS

Three phase filter is used to connect the inverter with grid
or load. It is used to control the amount of active and reactive
power that can be injected by the inverter.
Inductor and series resistance of the filter are determined
based on experimental test. The resistance of the filter is
obtained by supplying DC voltage and measuring the current
through and voltage across the filter. To determine the value
of the inductor, AC voltage is applied and from the measured
RMS voltage and current, the value of the inductor is
calculated. As the value of the capacitor is not necessary for
this project, it is not measured.
Table 1Filter parameters

Parameters
L(mH)
R(ohm)

three phase voltage from the virtual grid

three phase currents from the load
cos

cos

sin

sin

+ .

+
.

(2)
.

(3)

Where,
and
are the d-axis and q-axis voltage across the
filter and the load,
and
are the d- and q- axis currents
through load and filter,
is the filter inductance,
is the
system frequency,
and
are the filter and load resistance
respectively. A load of 4.7 ohm resistance is considered.
Therefore the s- domain transfer function which relates the
output currents with the input voltages can be derived to
model the plant for tuning of PI controllers. The coupling
terms are not considered in the transfer function instead they
are added as feed forward to enhance the transient response of
the system.
( )=
(4)
Where, is the gain of the plant which is 1
where
is the

values of

Park's transformation is used to convert three phase

measurements to synchronous frame d- and q-axis values for
vector control. In this transformation, the grid voltage is
aligned with the d-axis of the synchronous frame. Parameters
to be transformed to synchronous frame are:

cos( )

= sin( )

(1)

sum of filter and load resistance is the time constant of the

plant which is
where
is the filter inductance. The

Values
7.2
0.4

IV. ABC FRAME TO SYNCHRONOUS FRAME TRANSFORMATION

1.
2.

and are 0.196 and 1.412ms respectively.

For controlling the d-axis and q-axis .currents, PI controller is

used since it is simple and has efficient performance . The
transfer function of the PI controller is shown in equation 5.
There are different tuning methods by which the values of the
proportional and integrator gain are determine based on the
plant characteristics. The PI is tuned considering the
optimization between the overshoot, settling time and steady
state error of the current . As the plant is first order , the closed
loop system consist of the PI controller and the plant is a
second order system with a zero . But the closed loop system
can be reduced to first order system by setting the time
constant of the PI controller equals to the time constant of the
plant. Therefore, the gain is determined based on the desired
bandwidth for the first order system. The open loop transfer
function of the closed loop system can be shown in equation 6.
(

where

(5)
is the proportional gain and is the time constant

3
(

.
(6)
The reduced first order closed loop transfer function is look
like in the equation 7 .
.

( )=

(7)

To find the proportional gain

, a desired bandwidth
frequency of 267Hz is used and
is 12
The analog PI controller is converted to digital controller
using bilinear transformation. The sampling frequency used in
the digital implementation of the control is 10KHz.

assumed that the three phases are balanced and only two
phases of the voltage are read from the virtual grid. Therefore,
these two methods have equal performance in implementation
of grid synchronization for this specific project. But when the
three phase voltages are read for unbalanced virtual grid
system , dqPLL is better than arctan function since it has high
performance in unbalanced case[5].
1) Arctan function
The voltages are transformed from stationary abc frame to
stationary frame using the following transformation matrix.
= 0.5

=
Where

(8)

is the sampling period.

After transformation and rearranging the digital PI controller,

the equation which relates the controller effort and the error
signal is derived.
[ ] = [ 1] +

[ ]+

[ 1]

1 0.5 0.5

(12)

Where
and
are stationary frame alpha-beta
voltages and
,
and
are stationary frame three phase
voltages read from the virtual grid. Phase C of the virtual grid
voltage is obtained by using three phase balanced equation.
Therefore, the angle can be extracted using tan (
/
) and this result is converted to radian value.

(9)

Where [ ] and [ ] are the controller effort and error signals

in digital form.
and
are defined in the following
equations.
=
=

(1 +

(1 +

(10)
)

Plant gain(K)
Plant time constant ( )
Continous Proportional gain(Kp)
Integrator Time constant (
)
Desired frequency(BW)
coefficient for the digital PI
coefficient
for the digital PI
1

(11)
0.196
1.411ms
12
1.412ms
267Hz
12.425
-11.575

VI. GRID SYNCHRONIZATION

One of the main requirements to connect the inverter to the
grid is synchronization since if the it is not properly
synchronized, it will cause problems on the grid. Moreover,
the inverter can't keep generating reactive and active power
when short circuits or unbalancing happened in the grid [4]. In
this project, the inverter is not actually connected to the grid
but a virtual grid is used to imitate real grid synchronization.
Extracting the phase of the grid is also necessary to control
the amount of real and reactive power injection of the inveter
to the grid. There are different methods used for
synchronization. In this project, acrtan function( with low
pass filter) and synchronous frame dq PLL methods are used.
The arctan function with filters can have equivalent
performance with dqPLL. In addition, in the project, it is

Fig.2 with low pass filter grid synchronization

2) PLL
The synchronous frame dqPLL can be implemented by
controlling the q-axis voltage of the virtual grid to be zero. A
linear relation between the q-axis voltage and the angle
extracted by the dqPLL is derived by assuming that the
difference between the phase angle of the virtual grid and the
phase angle extracted by the dqPLL is very small [6].
=

(13)

Where is q-axis voltage ,

is the amplitude of the virtual
grid voltage, difference between the phase angle of virtual
grid and the dqPLL.
The controller is based on PI controller and the structure of the
dqPLL is shown in the following diagram . The transfer
function for the closed loop system that relates the phase angle
of the virtual grid and the phase angle of the PLL has a form
of second order system and it is used for tuning the PI
controller as it has advantages for performance and
stability[5].
( )
( )

(14)

Where ( ) and ( ) are phase angles from the PLL and

virtual grid .

Fig. 3 dqPLL structure

Bandwidth of 10Hz and damping ratio of 0.707 is considered

for tuning the PI and the values of the proportional integrator
and time constant are :
= 0.269
= 0.022
VII. HARDWARE DESIGN
A. Fault control
The inveter has 6 independent logic output signals
corresponding to faults at each IGBTs legs. Since one signal is
enough to indicate that there is fault inside the power stack,
they are connected by OR logic. To achieve this, six of the
fault indicators are wired with a pull up resistor connected to.
5V Dc power supply and voltage divider resistor to get
maximum voltage of 3.3V. Moreover, zener diode is
connected to assure the voltage limit for the DSP.
The moment fault occurs ,the voltage across the voltage
divider resistor will be zero since the transistor is switched on
by the fault current. This signal is sent to the trip zone 1 of the
PWM , thus the PWM halts generating PWM pulses cycle by
cycle till the fault is cleared.
On the other hand if there is no fault in either of the legs, the
voltage across the voltage divider resistor will be 3.3V as the
transistor is switched-off. Moreover, to indicate that a fault is
occurred in either of the legs an LED indicator is used.
B. Relay control for DC-link capacitor
In order to control the level of the capacitor charge, a pre
charge relay signal is used. The capacitor charge level is
compared with a reference signal using LM339 open collector
comparator which is connected to the pull-up resistor.
When the capacitor voltage is greater than the reference, the
pre charger relay is activated and closed , thereby the inverter
starts delivering power to the load. To check whether the
capacitor is fully charged or not an LED indicator is used.
C. Buffer for adapting PWM signals
A 6 PWM pulses are generate for each legs of the IGBT from
the DSP using three ePWM modules. However, the output
signal level from the DSP is not enough to drive the IGBT
legs and hence a non-inverting buffer IC (sn74hct541) is used
to adapt the DSP PWM signals. The reset signal for the
inverter from GPIO61 of the DSP also passes through the
buffer.
External switch is used to enable and disable the buffer in case
of emergency happen in the system.
D. Reset Circuit
When the fault occurs in power stack, the inverter will trip and
it won't start again unless reset signal is applied. For this

purpose a reset circuit is designed using push button, resistors

and capacitor. This circuit is implemented in the PCB board
and its output is connected to the IDC connector of the ADC
channels of the DSP. The reset is connected to the GPIO60 of
the DSP and the reset is active low. when the reset goes low,
GPIO61 of the DSP will be logic high to reset the inveter and
it is connected to IDC connector of the PWM in the PCB
board.
E. Sensor signal conditioning
The signal conditioning is typically needed to adapt the signals
from voltage and current sensors to the range of the ADC
input voltage of the DSC. Thus, a total of 4 signal
conditioning circuit are implemented, 2 for the current sensor
and 2 for the voltage sensor. The design of the electrical
circuit is based on the active inverting TL082 amplifier.
1) Inverting Amplifier and summer circuit
This circuit is used to scaled down the sensors' voltage output
down to -3V to 0V. The general formula of the circuit is
shown in equation 15.
Table 2 Sensors' electrical characteristics
Sensor
Voltage sensor
Current sensor
DC link

Voltage level
12V
7.5V
0-7.5V

Input ranges
326V
10A
0-750Vdc

Fig. 4 inverting amplifier and summer circuit

(15)

Where
is the input voltage from the sensors,
is DC
offset voltage used to shift the AC voltage up,
is the
output voltage,
is the feedback resistor,
and
resistors connected to the AC input voltage and DC offset
voltage respectively,

Fig. 5 inverting amplifier for current sensors

Fig 6 Inverting amplifier for voltage sensors.

2) Anti-aliasing filter design

Signals should be filtered before fed to ADC conversion to
avoid the harmonics and noises. Harmonics can exist in the
voltage and current signals read from the virtual grid and filter
even though synchronous sampling is used to reduce the
noises.
In order to satisfy the condition of the sampling theorem, the
cutoff frequency of the pre-filter must be at most equal to the
Nyquist frequency (fs/2), that is fmax<fs/2. In this project , the
sampling frequency of the ADC is taken to be 10 kHz, thus the
maximum cut of frequency of the low pass filter must be at
most 5 KHz. A cut-off frequency of 2.5KHz is specified to
design the filter. Moreover, the filter has a function of
inverting the signal from the inverting amplifier and summer
circuit to make the voltage in the range of 0 to
3V.Optimization is done to reduce phase delay of the filter .

Fig. 7 Anti-aliasing filter

The filter design is made by Filterpro software from Texas

instrument.
.
Table 3 summary of the anti-aliasing filter design

Circuit topology
Order of the filter
Cut-off frequency
Pass band gain
Corner frequency attenuation
Quality factor
Phase delay@50Hz

Butterworth, multiple
feedback, low pass filter
2
2.5KHz
1db
-3dB
0.71
1.64

Since the ADC of Texas F28335 instrument DSP use

maximum of 3V as reference, 3V rating zener diode is used
between each signal conditioning circuits and the ADC
channels.

F. PCB design and construction

An interface card (PCB) which interfaces the power stack and
DSC is designed using Altium designer 15 TM . The PCB
contains all the hardware components listed above and DC
power supply interfaces for its components. After appropriate
design to optimize the size and its functionality, the PCB is
manufactured in the university Lab. The Altium design of the
PCB is attached in the different file name ''altiumdesign.".
VIII. DEVELOPMENT OF THE SYSTEM MODEL USING PSIM
SOFTWARE
PSIM software has all the required components to model the
system. The software has SimCoder tool under which there are
components used to emulate different parts of Texas
instrument F28335 DSP. It is also possible to generate code
that can be compiled using Code Composer Studio (CCS) and
run in the DSP.
At the first step, a simple model is implemented using simple
analog blocks of PSIM software to test the performance of the
PI controller. It is used to tune better parameters of PI
controllers by studying the dynamic response and steady state
error performance of the controller. The digital model of the
system is implemented using digital control blocks to examine
the performance of the digital PI controller for further tuning
until the desired response is found since the real system will
be implemented in digital.
As the last step, the whole system including the signal
conditioners ( for voltage and currents sensors ) and the DSP
emulator is implemented to test it for modification and further
improvement before implementing the real parts of the system.
The control algorithm is also implemented using simplified C
block of the software.
The simulation results regarding the current controller
responses and grid synchronization performance of PSIM
model of the system is discussed in the simulation results and
analysis section.
IX. SOFTWARE DEVELOPMENT
In the software development, the main jobs are configuration
of ADC, PWM and GPIO modules of Texas instrument
F28335 and implementation of current controllers. Code
Composer Studio 6 is used to implement the software.
A. ADC configuration
Synchronous sampling is used to sample the two phase
voltages and two phase currents. Synchronous sampling is
chosen since it is advantageous to remove harmonics from the
signals. In synchronous sampling it is assumed that the system
time constant is very larger than the switching time[7].
Therefore, sampling of voltages and currents is undertaken at
10KHz which is frequency of the PWM signals. Four channels
(A2, B2 ,A3 and B3) of F28335 ADC are selected to sample
two phase voltages and two phase currents. Moreover, two
phase signals of voltage and current are sampled at the same
time since the ADC is configured for simultaneous sampling
mode.
The ADC is also configured for auto sequence conversion to
convert all the four channels automatically without start and

6
stop. Therefore, the ADC interruption is serviced once the
conversion of all the four channels is finished. The ADC is
configured to be triggered by the PWM.
B. PWM configuration
The PWM module 1,2 and 3 of the DSC are configured
to give 3 phase complementary PWM signals.
It is configured to have the minimum dead time of 2us
for the switching transition of two switches(IGBTs) of
the power stack not to make short circuit.
The shadow register in the compare and counter sub
module of the PWM is enabled to buffer the PWM duty
cycle not to overwrite the current duty cycle.
Clock prescaler of TBCTL for ePWM module are
configured to get the possible maximum value for
TBRD register.
maximum value of TBRD register to get high resolution
in the PWM signals at 10KHz frequency is 7500.
The PWM modules are synchronized by configuring
the PWM modules as master and slave mode of
operation. ePWM module 1 is configured as master.
To get symmetrical triangular wave, the counter is
configured for up-down count mode using time base
control register(TBCTL).
Trip zone one of ePWM module is configured to
disable PWM output cycle by cycle when there is fault.
The PWM is configured to start the ADC channels to
realize synchronous sampling.
C. GPIO configuration.
GPIO0-GPIO5 are configured for PWM output .
GPIO60 and GPIO61 is configured as general
purpose input output pins for reset purpose to reset
the inverter after the fault in the inverter is cleared to
restart the power stack.
GPIO60 is configured as input pin for reset input and GPIO61
is configured as output pin for reset output. There is one
resetInverter() function which reads the GPIO60 status and
when the pin status goes low, the function will set GPIO61
pin to go high to reset the power stack (Guasch inverter).
D. Controller
The controller functions including the grid synchronization
and PI current vector controllers. It is called approximately
every 100s under ADC interrupt service function to be
executed. The function will update the PWM duty cycles after
performing the controlling algorithm. The whole control
algorithm should be executed within 100s before the next
ADC conversion starts in order to assure that the sampling is
still synchronous. But this is not a problem for F28335 DSP
since it has 150MHz speed. In the following diagram, the flow
chart of the whole software is shown.

Fig. 8 flowchart for the controller algorithm

X. EXPERIMENTAL PROCEDURES USED TO TEST THE SYSTEM

Before testing the controller, the interface PCB board is tested
for proper functionality like checking short circuits ,undesired
connections and continuity of the circuits. All the fours signal
conditioners are checked if they have desired results using
signal generator as an input. They are checked for proper
shifting-up of the AC voltage output of the voltage and current
sensors and their voltage output level is also examined if it is
between 0 and 3V corresponding to the minimum and
maximum voltage output of the sensors respectively. Other
parts of the PCB are also tested.
The signal level of the reset circuit is tested to check if the
voltage output of the circuit is zero when the push button
is pressed and vice versa. The reset is active low.
Output of the comparator is tested by giving signal from
the signal generator if it can switch on the relay of the
DC-link capacitor when the capacitor voltage reaches the
appropriate charging level. The DC link relay is switchedon when the charging level of the capacitor reaches more
than 500V.
The buffer is tested to check if its voltage output level is
between 0 and 5.5V which is compatible to voltage level
of the drivers of the Guasch inverter. PWM signals are
generated from software implemented in Code Composer
Studio(CCS).
The configuration of the DSC clock, ADC and PWM modules
is also checked. The main jobs in this testing are:
The PWM configuration is checked for desired
frequency(10KHz), dead time(2s) and three phase
complementary output.
Using the signals from the signal generator, the ADC
configuration is tested to check if the selected channels
are working properly. In addition , synchronous sampling
is confirmed by toggling the output of GPIO6 in the ADC
interrupt function.
The final step of testing is done by setting up the whole
system including PCB board , the DSC , Guash inverter, LC

7
filter, Load , DC power suppliers for the PCB and the DC-link
of the inverter.
To confirm the dead time, fixed PWM duty cycle is
generated before testing the controller. The inverter is
working properly without tripping or triggering the
trip zone.
The controller is tested for DC current control i.e.
keeping the synchronization angle at zero. Different
Id reference values are used to check the controller is
working for different step responses.
After this, synchronization angle is generated by
creating function in Code Composer Studio and
specifying the frequency at 50Hz. The function is
called inside the ADC interrupt service function. This
synchronization has equivalent function to
synchronization of the currents to the virtual grid.
Therefore, it is possible to study the controller
performance for different power factors.
Both current controllers(Id and Iq) are tested using
maximum voltage of 66V supplied to the DC-link of
the inverter from the DC supplier. The controller is
tested for different power factors and step responses.
It is possible to change references in real time in
Code Composer Studio. Therefore different step
responses have been applied to the controller to study
its responses. Arrays are used to store Id and Iq
responses of the controller and to plot them in
Matlab.

since it has PI controller. But this doesn't affect the

performance of PLL as it

Fig. 10 grid synchronization by arctan function

Fig. 11 grid synchronization by dqPLL

2) Current controllers
Different Id and Iq step references are applied to check the
controller dynamic and steady state response. It can be seen
from the step responses that the settling time is around 0.004
second as expected from the design. The response of the
system is like first order system. The steady state error is
almost zero.

Fig. 12 step response for Id when Iq=0

Fig. 9Experimental setup during testing

Fig. 13 step response for Iq when Id=0

XI. EXPERIMENTAL AND SIMULATION RESULTS AND ANALYSIS

A. simulation results and analysis
The PSIM model of the system is tested to study its
performance for grid synchronization and vector control of
currents at different step responses and power factors.
1) Grid synchronization
Fig. 14 three phase currents through resistive load

The simulation result shows that both grid synchronization

methods have equivalent results since low pass filter is used to
filter the virtual grid voltages and only two phases are used
assuming that three phases are balanced. As it is shown in the
figure, phase tracking can't be achieved both by arctan and
PLL at zero second due to the delay created by the filter. In
addition, synchronization with PLL has very small overshoot

B. Experimental results and Analysis

During the experimental test, the inverter DC voltage input is
supplied from the DC power suppliers which can supply a
maximum of 66V. A resistive load of 4.7 ohm is connected to
the filter. The reference for Id and Iq are varied in real time on
Code Composer Studio.

8
The controller is tested for different step responses of Id and
Iq to check its performance for dynamic and steady state
response. There is some deviation from simulation results.
This is due to the delay created by the ADC, the switching
delay of IGBTs and deviation of components ( resistors ) used
to construct the PCB.

Fig. 15 Id current response when Id reference=1.4A

Fig. 16 Iq current response when Iq reference=1.4A

Fig. 17 Iq current response when Iq reference=1.4A

Fig. 18 Id current response when Id reference=0A

Fig. 19 step responses of Id current for different references.

Fig. 20 step responses of Iq current for different Iq references

To check synchronization, a synchronized sinusoidal three

phase voltage with maximum amplitude of 3V at 50Hz is
generated using Code Composer Studio. One of the phase of
this voltage and one of the phase of the load current is
compared for phase difference at different Id and Iq references
(different power factors) for checking synchronization as
shown in the following diagrams.