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Timer, Interrupt, Exception in ARM: Modifications From Prabal Dutta

The document discusses interrupts, timers, and exceptions in ARM processors. It covers where interrupts come from, how to save state for later continuation, and how to prioritize and share interrupts. It also discusses using timers to measure time intervals and generate periodic signals.

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ganesh
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
60 views

Timer, Interrupt, Exception in ARM: Modifications From Prabal Dutta

The document discusses interrupts, timers, and exceptions in ARM processors. It covers where interrupts come from, how to save state for later continuation, and how to prioritize and share interrupts. It also discusses using timers to measure time intervals and generate periodic signals.

Uploaded by

ganesh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Timer, Interrupt, Exception in ARM

Modifications from Prabal Dutta,

University of Michigan

Interrupts
Merriam-Webster:
to break the uniformity or continuity of

Informs a program of some external events


Breaks execution flow
Key questions:
Where do interrupts come from?
How do we save state for later continuation?
How can we ignore interrupts?
How can we prioritize interrupts?
How can we share interrupts?
2

I/O Data Transfer


Two key questions to determine how data is transferred
to/from a non-trivial I/O device:
1. How does the CPU know when data is available?
a. Polling
b. Interrupts
2. How is data transferred into and out of the
device?
a. Programmed I/O
b. Direct Memory Access (DMA)

Interrupts
Interrupt (a.k.a. exception or trap):
An event that causes the CPU to stop executing the current
program and begin executing a special piece of code called an
interrupt handler or interrupt service routine (ISR).
Typically, the ISR does some work and then resumes the
interrupted program.
Interrupts are really glorified procedure calls, except that they:
can occur between any two instructions
are transparent to the running program (usually)
are not explicitly requested by the program (typically)
call a procedure at an address determined by the type of
interrupt, not the program

Two basic types of interrupts


(1/2)

Those caused by an instruction


Examples:
TLB miss
Illegal/unimplemented instruction
div by 0
Names:
Trap, exception

Two basic types of interrupts


(2/2)

Those caused by the external world

External device
Reset button
Timer expires
Power failure
System error

Names:
interrupt, external interrupt

How it works
Something tells the processor core there is an
interrupt
Core transfers control to code that needs to be
executed
Said code returns to old program
Much harder than it looks.
Why?

is in the details
How do you figure out where to branch to?
How to you ensure that you can get back to
where you started?
Dont we have a pipeline? What about partially
executed instructions?
What if we get an interrupt while we are
processing our interrupt?
What if we are in a critical section?

Where

If you know what caused the interrupt


then you want to jump to the code that
handles that interrupt.
If you number the possible interrupt cases,
and an interrupt comes in, you can just
branch to a location, using that number as an
offset (this is a branch table)
If you dont have the number, you need to
poll all possible sources of the interrupt to
see who caused it.
Then you branch to the right code

Get back to where you once belonged


Need to store the return address somewhere.
Stack might be a scary place.
That would involve a load/store and might cause an
interrupt (page fault)!
So a dedicated register seems like a good choice
But that might cause problems later

Snazzy architectures

A modern processor has many (often 50+)


instructions in-flight at once.
What do we do with them?

Drain the pipeline?


What if one of them causes an exception?

Punt all that work


Slows us down

What if the instruction that caused the


exception was executed before some
other instruction?
What if that other instruction caused an
interrupt?

Nested interrupts

If we get one interrupt while handling


another what to do?
Just handle it
But what about that dedicated register?
What if Im doing something that cant be stopped?

Ignore it
But what if it is important?

Prioritize
Take those interrupts you care about. Ignore the
rest
Still have dedicated register problems.

Critical section
We probably need to ignore some interrupts but
take others.
Probably should be sure our code cant cause an
exception.
Use same prioritization as before.

The Reset Interrupt

1) No power
2) System is held in RESET as long as VCC15 < 0.8V
a) In reset: registers forced to default
b) RC-Osc begins to oscillate
c) MSS_CCC drives RC-Osc/4 into FCLK
d) PORESET_N is held low

3) Once VCC15GOOD, PORESET_N goes high


a) MSS reads from eNVM address 0x0 and 0x4
14

15

And the interrupt vectors


(in startup_a2fxxxm3.s found in CMSIS, startup_gcc)
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WdogWakeup_IRQHandler
.word BrownOut_1_5V_IRQHandler
.word BrownOut_3_3V_IRQHandler
.............. (they continue)
16

Pending interrupts

The normal case. Once Interrupt request is seen, processor puts it in


pending state even if hardware drops the request.
IPS is cleared by the hardware once we jump to the ISR.

17

In this case, the processor never took the interrupt because we cleared the
IPS by hand (via a memory-mapped I/O register)

18

19

20

21

22

23

24

25

26

27

28

29

30

Interrupt handlers

31

32

Time in Embedded Systems:


Where do we need accurate time?
Scheduling of computation
Scheduler in operating systems
Real time operating systems

Signal sampling and generation


Audio sampling at 44.1 kHz
TV/video generation (sync, vsync)
Pulse Width Modulated (PWM) signals

Communication
Media Access Control (MAC) protocols
Modulation

Navigation
GPS

Fine grain motion control

http://www.youtube.com/watch?v=SOESSCXGhFo

Clock generation and use

Resonating element/Driver:
Quartz crystal can be made to
resonate due to Piezoelectric effect.
Resonate frequency depends on
length, thickness, and angle of cut.
Issues: Very stable (<100ppm) but not
all frequencies possible.

MEMS Resonator
Arbitrary frequency, potentially cheap,
susceptible to temperature variations.

Others:
Inverter Ring, LC/RC circuits, Atomic
clock, and many more.

Clock Driver

Timers on the SmartFusion

Timers on the SmartFusion


SysTick Timer
ARM requires every Cortex-M3 to have this
timer
Essentially a 24-bit down-counter to generate
system ticks
Has its own interrupt
Clocked by FCLK with optional programmable
divider

See Actel SmartFusion MSS User Guide


for register definitions

Timers on the SmartFusion

http://www.actel.com/documents/SmartFusion_MSS_UG.pdf

Timers on the SmartFusion


System timer
The System Timer consists of two
programmable 32-bit decrementing
counters that generate interrupts to the
ARM Cortex-M3 and FPGA fabric. Each
counter has two possible modes of
operation: Periodic mode or One-Shot mode.
The two timers can be concatenated to create
a 64-bit timer with Periodic and One-Shot
modes. The two 32-bit timers are identical
http://www.actel.com/documents/SmartFusion_MSS_UG.pdf

Features of Timers
a.k.a. terms you need to know

Time is kept in the hardware counter

Resolution: How often the hardware counter


is updated.
Precision: The smallest increment the
software can read the counter.
Accuracy: How close we are to UTC
Range: The counter reads a value of (f*t)
mod 2n. Range is the biggest value we can
read.
UTC is Coordinated
Universal Time (French is Temps Universel Coordonn). I just work here

Who cares?
There are two basic activities one wants
timers for:
Measure how long something takes
Capture

Have something happen every X time period.


Compare

Example #1 -- Capture
FAN
Say you have a fan spinning and you want to know
how fast it is spinning. One way to do that is to have
it throw an interrupt every time it completes a
rotation.
Right idea, but might take a while to process the interrupt,
heavily loaded system might see slower fan than actually
exists.
This could be bad.

Solution? Have the timer note immediately how long


it took and then generate the interrupt. Also restart
timer immediately.

Same issue would exist in a car when measuring


speed of a wheel turning (for speedometer or
anti-lock brakes).

Example #2 -- Compare
Driving a DC motor via PWM.
Motors turn at a speed determined by the
voltage applied.
Doing this in analog land can be hard.
Need to get analog out of our processor
Need to amplify signal in a linear way (op-amp?)

Generally prefer just switching between Max and


Off quickly.
Average is good enough.
Now dont need linear amplifierjust on and
off. (transistor)

Need a signal with a certain duty cycle and


frequency.
That is % of time high.

Virtual timers
You never have enough timers.
Never.

So what are we going to do about it?


How about we handle in software?

Virtual Timers
Simple idea.
Maybe we have 10 events we might want to
generate.
Just make a list of them and set the timer to go off
for the first one.
Do that first task, change the timer to interrupt for the
next task.

Problems?
Only works for compare timer uses.
Will result in slower ISR response time
May not care, could just schedule sooner

Implementation issues
Shared user-space/ISR data structure.
Insertion happens at least some of the time in user
code.
Deletion happens in ISR.
We need critical section (disable interrupt)

How do we deal with our modulo counter?


That is, the timer wraps around.
Why is that an issue?

What functionality would be nice?


Generally one-shot vs. repeating events
Might be other things desired though

What if two events are to happen at the same


time?
Pick an order, do both

Implementation issues
(continued)
What data structure?
Data needs be sorted
Inserting one thing at a time

We always pop from one end


But we add in sorted order.

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