2-Lecture Notes Lesson2 6
2-Lecture Notes Lesson2 6
Lesson Objectives:
In addition to AND, OR, and NOT gates, other logic gates like NAND and NOR are
also used in the design of digital circuits.
The small circle (bubble) at the output of the graphic symbol of a NOT gate is
formally called a negation indicator and designates the logical complement.
NAND Gate:
The NAND gate represents the complement of the AND operation. Its name is an
abbreviation of NOT AND.
The graphic symbol for the NAND gate consists of an AND symbol with a bubble on
the output, denoting that a complement operation is performed on the output of the
AND gate.
The truth table and the graphic symbol of NAND gate is shown in the figure.
The truth table clearly shows that the NAND operation is the complement of the
AND.
NOR Gate:
The NOR gate represents the complement of the OR operation. Its name is an
abbreviation of NOT OR.
The graphic symbol for the NOR gate consists of an OR symbol with a bubble on the
output, denoting that a complement operation is performed on the output of the OR
gate.
The truth table and the graphic symbol of NOR gate is shown in the figure.
The truth table clearly shows that the NOR operation is the complement of the OR.
Universal Gates:
A universal gate is a gate which can implement any Boolean function without need to
use any other gate type.
In practice, this is advantageous since NAND and NOR gates are economical and
easier to fabricate and are the basic gates used in all IC digital logic families.
1. All NAND input pins connect to the input signal A gives an output A’.
2. One NAND input pin is connected to the input signal A while all other input pins
are connected to logic 1. The output will be A’.
Thus, the NAND gate is a universal gate since it can implement the AND, OR
and NOT functions.
2. One NOR input pin is connected to the input signal A while all other input pins are
connected to logic 0. The output will be A’.
Thus, the NOR gate is a universal gate since it can implement the AND, OR and
NOT functions.
Equivalent Gates:
The shown figure summarizes important cases of gate equivalence. Note that bubbles
indicate a complement operation (inverter).
Two NOT gates in series are same as a buffer because they cancel each other as A’’ =
A.
Two-Level Implementations:
We have seen before that Boolean functions in either SOP or POS forms can be
implemented using 2-Level implementations.
For SOP forms AND gates will be in the first level and a single OR gate will be in the
second level.
For POS forms OR gates will be in the first level and a single AND gate will be in the
second level.
Note that using inverters to complement input variables is not counted as a level.
We will show that SOP forms can be implemented using only NAND gates, while
POS forms can be implemented using only NOR gates.
Introducing two successive inverters at the inputs of the AND gate results in the
shown equivalent implementation. Since two successive inverters on the same line
will not have an overall effect on the logic as it is shown before.
(see animation in authorware version)
By associating one of the inverters with the output of the first level OR gates and the
other with the input of the AND gate, it is clear that this implementation is reducible
to 2-level implementation where both levels are NOR gates as shown in Figure.
There are some other types of 2-level combinational circuits which are
• NAND-AND
• AND-NOR,
• NOR-OR,
• OR-NAND
AND-NOR functions:
Example 3: Implement the following function
F = XZ + Y Z + X YZ or
F = XZ + Y Z + XYZ