Ee001a HW 2 - Solutions

1
EE001A Engineering Circuits I

Department of Electrical Engineering
University of California Riverside
Homework 2
SOLUTIONS
EE 001A
Fall 2015
Instructor: Roman Chomko
Homework1 2
Kirchhoffs Laws
SOLUTIONS
Problem #1 (Alexander, Problem 2.9) (Kirchhoffs Current Law)
Figure P1
Find i1, i2, and i3 in Figure P1.

For KCLs using a sign convention
in +
away -
KCL node A
+i1 + (-1A) + (-6A) = 0 => i1 = 7A
KCL node B:
(-i2) + (-7A) + (+6A) =0 => i2 = -1A
KCL node C:
(-2A) + (+7A) + (-i3) = 0 => i3 = 5A
Collaboration is allowed.
ee001a Engineering Circuits Analysis I

Homework 2 - Solutions
Problem #2 (Alexander, Problem 2.13) (Kirchhoffs Current Law)
Figure P2
Use KCL to find the branch currents I1 and I4 in Figure P2.
For KCLs using a sign convention

in +
away -
At node 1:
I1 + I2 - 2A = 0
At node 2:
-I2 3A - 7A = 0
=> I2 = -10A
At node 3:
7A I3 + I4 = 0
At node 4:
2A I4 - 4A = 0
=> I4 = -2A
From (1), (2):
=> I1 = 12A
From (3), (4):
=> I3 = 5A

Problem #3 (Alexander, Problem 2.14) (Kirchhoffs Voltage Law)
Figure P3
Use KVL to find voltages V1 and V4 in Figure P3.
loop 4
loop 3
loop 1
loop 2
Arbitrarily drawing KVL loop directions starting from arbitrary nodes.

For KVL equations if using a historical sign convention (as in the textbook):
loop + to - taking V with +
loop - to + taking V with -
Loop 1:
-V4 + (+2) + (+5) = 0
=> V4 = 7V
Loop 2:
(+4) + (+V3) + (+V4) = 0
=> V3 = -V4 4 = -11V
Loop 3:
(-3) + (+V1) + (-V3) = 0
=> V1 = V3 + 3 = -8V
Loop 4:
(-V1) + (-V2) + (-2) = 0
=> V2 = -V1 2 = 6V

4
Alternatively, for KVL equations if using a modern sign convention:
loop + to - taking V with - (voltage drop)
loop - to + taking V with + (voltage rise)
Loop 1:
V4 + (-2) + (-5) = 0
=> V4 = 7V
Loop 2:
(-4) + (-V3) + (-V4) = 0
=> V3 = -4 -V4 = -11V
Loop 3:
(+3) + (-V1) + (+V3) = 0
=> V1 = 3 + V3 = -8V
Loop 4:
(+V1) + (+V2) + (+2) = 0
=> V2 = -V1 2 = 6V
Note that the results are identical to the ones obtained using the historical sign
convention.
Problem #4 (redundant nodes removal)

Background
Nodes in electric circuits are used to indicate the points where circuit elements are
interconnected. However, the redundant nodes may either
1) clarify the schematics (especially when a circuit element is connected to a line or a
bus) or,
2) be provided automatically by a schematics capture software or,
3) sometimes even intentionally used in applications.
While analyzing circuits it is convenient to remove branches not containing circuit
elements. Otherwise a procedure shown in Figure P4 is used for joining the redundant
nodes into a single node.

E4
E1
E2
E3
a)
The whole blackened area is to be considered
as a single node for the circuit analysis
E4
E1
E2
E3
b)
2
Figure P4-1 a) given redundant nodes in a circuit, b) nodes for the circuit analysis
Statement
In the circuit shown in Figure P4-2
a) identify the redundant nodes and join them into single nodes;
b) enumerate ALL nodes in the circuit. Consider joined redundant nodes as a single
node as shown in Figure P4-1 b)
E8
E6
E1
E2
E7
E3
E4
E5
Figure P4-2 Circuit with the Initial Nodes

Problem #5 (Kirchhoffs Laws)
E7
E5
E1
E2
E6
E3
E4
Figure P5 Circuit with generic elements
1)
Similar to the procedure used in Problem 4 join the redundant nodes and
enumerate all the resulting nodes for a circuit shown in Figure P5;
2)
Assign arbitrary reference voltage polarities and reference current directions

for ALL the elements in the circuit
3)
For each node in the circuit write a corresponding KCL equation indicating (in
writing) a convention used for the sign of the reference currents
4)
Choose any 3 (three) loops in the circuit clearly indicating their directions and
write corresponding KVL equations
5)
Re-write the equations obtained in 3), 4) in a tabular form as shown below (if a
variable doesnt appear in the equation write 0 (zero) )

7
In KCLs: take current with a +sign if current enters the node, and with a - sign if
current leaves the node.
In KVLs: the modern sign convention is used - if a KVL loop passes through a voltage
rise (- +), take it with a + sign; otherwise if a loop passes through a voltage
drop (+ -), take it with a - sign. Arbitrarily assigning reference current directions
and reference voltage polarities. For example:
Coefficients of variables on the Left Hand Side of the Equations (LHS) RHS
vE1 vE2 vE3 vE4 vE5 vE6 vE7 iE1
iE2
iE3
iE4
iE5
iE6
iE7
1 node 1
-1
-1
-1
2 node 2
-1
-1
3 node 3
-1
-1
4 node 4
5 loop 1
6 loop 2
-1
7 loop 3
-1
-1
-1
Note


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What are Kirchhoff's Current and Voltage Laws used for?

What are Kirchhoff's Current and Voltage Laws used for?

How are redundant nodes handled in circuit analysis?

How are redundant nodes handled in circuit analysis?

1

EE001A Engineering Circuits I

Instructor: Roman Chomko

Problem #1 (Alexander, Problem 2.9) (Kirchhoffs Current Law)

Find i1, i2, and i3 in Figure P1.

ee001a Engineering Circuits Analysis I

Problem #2 (Alexander, Problem 2.13) (Kirchhoffs Current Law)

Use KCL to find the branch currents I1 and I4 in Figure P2.

For KCLs using a sign convention

From (1), (2):

From (3), (4):

ee001a Engineering Circuits Analysis I

Problem #3 (Alexander, Problem 2.14) (Kirchhoffs Voltage Law)

Use KVL to find voltages V1 and V4 in Figure P3.

Arbitrarily drawing KVL loop directions starting from arbitrary nodes.

=> V3 = -V4 4 = -11V

ee001a Engineering Circuits Analysis I

=> V3 = -4 -V4 = -11V

Problem #4 (redundant nodes removal)

ee001a Engineering Circuits Analysis I

Figure P4-2 Circuit with the Initial Nodes

ee001a Engineering Circuits Analysis I

Problem #5 (Kirchhoffs Laws)

Figure P5 Circuit with generic elements

Assign arbitrary reference voltage polarities and reference current directions

ee001a Engineering Circuits Analysis I

vE1 vE2 vE3 vE4 vE5 vE6 vE7 iE1

ee001a Engineering Circuits Analysis I

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