Globus

                                    Group Of Institution

Lab Manual
of
CMOS & VLSI
Design
Steps To Operate XILINX Software
Step 1 Click on the icon of xilinx software
Step 2 Go to file menu and click on “New Project”.
Step 3 Give the project name
Step 4 Click on “Next Button”.
Step 5 Select the family device and package name with the help of
manual Then click on “Next” button.
Step 6 Click on “New Source” then select “VHDL Modual” .Write the file
name in the window and then click on “Next” button.
Step 7 Enter the port name &select the direction of the port.Then Click on
“Next” button three times.
Step 8 Click on “Finish”button.
Step 9 Enter the necessary coding between “Begin” and “End behaviour”statement.
Step 10 Click on “Synthesis” icon in process window.
Step 11 Click on “User Contraints” then assign the package pin.
Step 12 Now when “Xilinx pace window” opens, give location of input &output
pin with the help of manual.
Step 13 Save the aforesid settings by going to “File” icon on Task Bar. Then click
on”Genreate File (Programming Fle)” .Now“Inpact Window” will open .
Step 14 Now click on “Configure Devices” and select “Using Slave Serial Mode”.
Step 15 Click on “Finish” button then “Add Device” window will open.Now select
the file .Then the “Impact” window will open.Right click on device and click
on “Program” button. In case the program has succeeded ,message
indicating the same will be displayed else “Programme Failed” will be
displayed .
Step 16 If the Programe had failed repeat step 1 to 14 till its succedes Now start
feeding inputs for the gate for which the necessary coding has been written in
step 9 and measure the out put. Depending upon the necessary coding
written for different types of gates (AND,NAND,OR EXOR,EXNOR etc),its
input /outputs characteristics can be verified.
 Experiment List

1. Write VHDL code for OR Gate.

2. Write VHDL code for AND Gate.
3. Write VHDL code for XOR Gate
4. Write VHDL code for MUX Gate
5. Write VHDL code for DECODER Gate
6. Write VHDL code for ADDER Gate
7. Write VHDL code for Comparator Gate
8. Write VHDL code for Multiplier
9. Write VHDL code for D FLIP FLOP
10.Write VHDL code for J K FLIP FLOP
Aim-Write the VHDL code for OR GATE
Theory - The OR gate is a logic gate that gives an output of '0' only when all of its
inputs are '0'. Thus, its output is '1' whenever at least one of its inputs is '1'.
Mathematically, Q = A + B.

1-Behavior Code ss
library ieee;
use ieee.std_logic_1164.all;

--------------------------------------

entity OR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end OR_ent;

---------------------------------------

architecture OR_arch of OR_ent is

begin

process(x, y)
begin
-- compare to truth table
if ((x='0') and (y='0')) then
F <= '0';
else
F <= '1';
end if;
end process;
end OR_arch;
2-Data Flow Code
architecture OR_beh of OR_ent is
begin

F <= x or y;

end OR_beh;
Write VHDL code for AND Gate
Theory- The AND gate is a logic gate that gives an output of '1' only when all of its
inputs are '1'. Thus, its output is '0' whenever at least one of its inputs is '0'.
Mathematically, Q = A · B.

library ieee;
use ieee.std_logic_1164.all;

--------------------------------------------------

entity AND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end AND_ent;

--------------------------------------------------

architecture behav1 of AND_ent is

begin

process(x, y)
begin
-- compare to truth table
if ((x='1') and (y='1')) then
F <= '1';
else
F <= '0';
end if;
end process;

end behav1;

architecture behav2 of AND_ent is

begin

F <= x and y;

end behav2;
Write VHDL code for Xor Gate

Theory - The EXOR gate (for 'EXclusive OR' gate) is a logic gate that gives
an output of '1' when only one of its inputs is '1'.

library ieee;
use ieee.std_logic_1164.all;

--------------------------------------

entity XOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end XOR_ent;

--------------------------------------

architecture behv1 of XOR_ent is

begin

process(x, y)
begin
-- compare to truth table
if (x/=y) then
F <= '1';
else
F <= '0';
end if;
end process;

end behv1;

architecture behv2 of XOR_ent is

begin

F <= x xor y;
end behv2;

Write VHDL code for MUX Gate

A multiplexer or mux is a device that performs multiplexing; it selects
one of many analog or digital input signals and forwards the selected
input into a single line. A multiplexer of 2n inputs has n select lines,
which are used to select which input line to send to the output.

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------

entity Mux is
port( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end Mux;

-------------------------------------------------

architecture behv1 of Mux is

beginss
process(I3,I2,I1,I0,S)
begin

-- use case statement

 case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others => O <= "ZZZ";
end case;

end process;
end behv1;

architecture behv2 of Mux is

begin

-- use when.. else statement

O <= I0 when S="00" else
I1 when S="01" else
I2 when S="10" else
I3 when S="11" else
"ZZZ";

end behv2;
Write VHDL code for DECODER Gate
library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------

entity DECODER is
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end DECODER;

-------------------------------------------------

architecture behv of DECODER is

begin

process (I)
begin

-- use case statement

case I is
when "00" => O <= "0001";
when "01" => O <= "0010";
when "10" => O <= "0100";
when "11" => O <= "1000";
when others => O <= "XXXX";
end case;

end process;

end behv;

architecture when_else of DECODER is

begin

O <= "0001" when I = "00" else

"0010" when I = "01" else
"0100" when I = "10" else
"1000" when I = "11" else
 "XXXX";

end when_else;

Write VHDL code for ADDER Gate

ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--------------------------------------------------------

entity ADDER is

generic(n: natural :=2);

port( A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
carry: out std_logic;
sum: out std_logic_vector(n-1 downto 0)
);

end ADDER;

--------------------------------------------------------

architecture behv of ADDER is

-- define a temparary signal to store the result

signal result: std_logic_vector(n downto 0);

begin

-- the 3rd bit should be carry

result <= ('0' & A)+('0' & B);

sum <= result(n-1 downto 0);
carry <= result(n);

end behv;
Write VHDL code for Comparator Gate
library ieee;
use ieee.std_logic_1164.all;

---------------------------------------------------

entity Comparator is

generic(n: natural :=2);

port( A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
less: out std_logic;
equal: out std_logic;
greater: out std_logic
);
end Comparator;

---------------------------------------------------

architecture behv of Comparator is

begin

process(A,B)
begin
if (A<B) then
less <= '1';
equal <= '0';
greater <= '0';
elsif (A=B) then
less <= '0';
equal <= '1';
greater <= '0';
else
less <= '0';
equal <= '0';
greater <= '1';
end if;
end process;

end behv;
Write VHDL code for Multiplier
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- two 4-bit inputs and one 8-bit outputs

entity multiplier is
port( num1, num2: in std_logic_vector(1 downto 0);
product: out std_logic_vector(3 downto 0)
);
end multiplier;

architecture behv of multiplier is

begin
process(num1, num2)

variable num1_reg: std_logic_vector(2 downto 0);

variable product_reg: std_logic_vector(5 downto 0);

begin

num1_reg := '0' & num1;

product_reg := "0000" & num2;

-- use variables doing computation

-- algorithm is to repeat shifting/adding
for i in 1 to 3 loop
if product_reg(0)='1' then
product_reg(5 downto 3) := product_reg(5 downto 3)
+ num1_reg(2 downto 0);
end if;
product_reg(5 downto 0) := '0' & product_reg(5 downto
1);
end loop;

-- assign the result of computation back to output signal

product <= product_reg(3 downto 0);

end process;

end behv;
Write VHDL code for D FLIP FLOP
library ieee ;
use ieee.std_logic_1164.all;
use work.all;
entity dff is
port( data_in: in std_logic;
clock: in std_logic;
data_out: out std_logic
);
end dff;

architecture behv of dff is

begin

process(data_in, clock)
begin

-- clock rising edge

if (clock='1' and clock'event) then

data_out <= data_in;
end if;

end process;

end behv;
Write VHDL code for J K FLIP FLOP.
library ieee;
use ieee.std_logic_1164.all;

entity JK_FF is
port ( clock: in std_logic;
J, K: in std_logic;
reset: in std_logic;
Q, Qbar: out std_logic
);
end JK_FF;

architecture behv of JK_FF is

-- define the useful signals here

signal state: std_logic;

signal input: std_logic_vector(1 downto 0);

begin

-- combine inputs into vector

input <= J & K;
p: process(clock, reset) is
begin

if (reset='1') then
state <= '0';
elsif (rising_edge(clock)) then

-- compare to the truth table

case (input) is
when "11" =>
state <= not state;
when "10" =>
state <= '1';
when "01" =>
state <= '0';
when others =>
null;
end case;
end if;
end process;
 Q <= state;
Qbar <= not state;

end behv;