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CS623: CVLSI: V. Kamakoti and Shankar Balachandran

This lecture discusses tasks and functions in Verilog. Tasks are used for code with delays and can enable other tasks, while functions are for combinational code that executes instantly and can only enable other functions. Functions always execute instantly, while tasks may have delays. Functions must have an input but tasks can have zero or more inputs/outputs. Tasks operate on module variables, while functions implicitly declare a register for the return value. Useful modeling techniques in Verilog like assign, force, and file output are also covered.

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Veeresh Tangadgi
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56 views

CS623: CVLSI: V. Kamakoti and Shankar Balachandran

This lecture discusses tasks and functions in Verilog. Tasks are used for code with delays and can enable other tasks, while functions are for combinational code that executes instantly and can only enable other functions. Functions always execute instantly, while tasks may have delays. Functions must have an input but tasks can have zero or more inputs/outputs. Tasks operate on module variables, while functions implicitly declare a register for the return value. Useful modeling techniques in Verilog like assign, force, and file output are also covered.

Uploaded by

Veeresh Tangadgi
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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CS623: CVLSI

Lecture 16
V. Kamakoti and
Shankar Balachandran

Overview of this lecture

Task and Functions


Useful Modeling Techniques
File output
Random number generation

Tasks and Functions


Both are defined inside a module
Tasks are used for common Verilog codes
that contain delays etc.
Functions for purely combinational code
that execute in zero simulation time and
gives exactly one output

Differences
A function can enable another function but
not another task. A task can enable
another task
Functions always execute in 0 simulation
time, tasks may not.
Functions should not contain any delays,
timing controls tasks may have

Differences
Functions must have at least one input
argument task may have zero or more
input, output and inout arguments
Function returns a single value, while task
may pass more than one value through
output/inout arguments. Functions cannot
have inout/output arguments

Example - Tasks

module operation;
parameter delay = 10;
//argument, parameter declarations
always @(A or B)
begin
bitwise_oper(AB_AND,AB_OR,A,B)
end
task bitwise_oper;
output [15:0] ab_and,ab_or;
input [15:0] a,b;
begin
#delay ab_and = a &b;
ab_or = a | b;
end
endtask
endmodule

Tasks (Continued)
Tasks operate on reg variables defined
in the module directly
module sequence;
reg clk;
initial

init_sequence;

.
task init_sequence;
begin
clk = 1b0;
end
endtask
endmodule

Functions - Example
module parity;

reg [31:0] addr;


reg parity;
always @(addr)
begin
parity = calc_parity(addr);
end
function calc_parity;
input [31:0] address;
begin
calc_parity = ^address;
end
endfunction
endmodule

Summary
A register with name as the function name
is declared implicitly when a function is
declared. The return value of the function
is passed back to this register
Tasks and functions are included in a
design hierarchy and can be addressed by
hierarchical name referencing.

Useful Modeling Techniques


assign and deassign for wires

always @(negedge clk)


begin
q = d; qbar = ~d;
end
always @(reset)
if (reset)
begin
assign q = 1b1; assign qbar = 1b0;
end
else
begin
deassign q; deassign qbar;
end

Contd

Force and release on registers


module stimulus
edge_dff dff(Q, Qbar,D,Clk,Reset)
initial
begin
#50 force dff.q = 1b1;
#50 release dff.q;
end

Contd

Force and release on nets


module xxx
assign out = a & b & c;
initial
begin
#50 force out = a| b & c;
#50 release out;
end
endmodule

Contd
Force and release to be used only in stimulus
blocks
Overriding parameters
module hello_world;

parameter id_num = 0;

endmodule
module top;
defparam w1.id_num = 1; w2.id_num = 2;
hello_world w1();
hello_world w2();
endmodule

Contd

hello_world #(1) w1();


hello_world #(2) w2();
module xxx;
parameter a = 1;
parameter b = 2;
endmodule
xxx #(3,4) b1();
xxx #(4,5) b2();

File output
integer handle1;

initial
handle1 = $fopen(file1.out);
$fclose(handle1);
$fdisplay(handle1,)
$fmonitor(handle1,)
Hierarchy display %m
module top;
M m1();
endmodule;
module M;
$display(%m) // output top.m1
endmodule

Random Numbers

$random
$random <seed>;
//seed is optional
initial r_seed = 2;
always @(posedge clk)
addr = $random(r_seed);

References
Chapter 9: Samir Palnitkar - Verilog HDL,
First edition
Chapter 3: J. Bhasker A Verilog HDL
Primer, First edition

Questions and Answers

Thank You

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