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Lab 2: Common Source Amplifier With Resistor Load and Source Degeneration

-3dB (Hz) G.B. (Hz) 0.7 5.36 1.44MHz 3.12MHz 1.5 4.32 1.12MHz 2.40MHz 2 3.28 840kHz 1.76MHz dB) 0.5 Vg(V) Table 2 Shows the change in gain and GB when the source resistance R2 and input voltage Vg is varied in the CS amplifier with source degeneration configuration. 1) The document describes simulations performed on common source amplifier circuits with varying

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100% found this document useful (1 vote)
335 views28 pages

Lab 2: Common Source Amplifier With Resistor Load and Source Degeneration

-3dB (Hz) G.B. (Hz) 0.7 5.36 1.44MHz 3.12MHz 1.5 4.32 1.12MHz 2.40MHz 2 3.28 840kHz 1.76MHz dB) 0.5 Vg(V) Table 2 Shows the change in gain and GB when the source resistance R2 and input voltage Vg is varied in the CS amplifier with source degeneration configuration. 1) The document describes simulations performed on common source amplifier circuits with varying

Uploaded by

ceferinotan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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ECE 126

Introduction to Analog Integrated Circuits Design

Lab 2: Common Source Amplifier with


Resistor Load and Source Degeneration

Submitted by:
Ceferino Kevin A. Tan
BSECE 4

Submitted to:
Prof. Allenn dela Cerna Lowaton

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Step 1:
Following the circuit of figure 4.1, simulate the V in-Vout
DC transfer curve as it was obtained in figure 4.2 and
the frequency response as in figure 4.3.
Relation of Vin and Vout
CODE
step1a_tan
.lib 'C:\synopsys\rf018.l'
TT
m1 vout g gnd gnd nch
l=0.18u w=0.6u
vdd vdd gnd 1.8v
vin g gnd 0.7v
r1 vout vdd 10k
cload vout gnd 10p
.op

.option post probe


.dc vin 0 2 0.01
.probe v(vout)
.end
.OP Output
subckt
element 0:m1
model 0:nch.12
region
Saturati
id
33.0209u
ibs
-8.681e-21

ibd
-3.2440n
vgs
700.0000m
vds
1.4698
vbs
0.
vth
539.2933m
vdsat 139.8792m
vod
160.7067m
beta
1.9179m
gam eff 969.4764m
gm
245.2395u

Figure 1 The Vin-Vout graph shows how the output voltage(y-axis) varies with our
input voltage(x-axis). As you can see, the output voltage decreases with increasing
input voltage. This is due to the fact that increased input voltage increases the drain
current, which consequently increases the voltage drop across the drain resistor,
which in turn minimizes the voltage of node v out.

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Frequency Response
CODE
step1b_tan
.lib 'C:\synopsys\rf018.l' TT
m1 vout vin gnd gnd nch l=0.18u
w=0.6u
vdd vdd gnd 1.8v
vin vin vg ac 1
vg vg gnd 0.7
r1 vout vdd 10k
cload vout gnd 10p

.probe v(vout)
.option post probe
.plot ac vdb(vout)
.ac dec 100 10 10g
.meas ac GB when vdb(vout) = 0
.alter
vg vg gnd 0.4
.alter
vg vg gnd 1
.alter
vg vg gnd 1.5
.end

.op

Figure 2 The gain-frequency response graph. At the bias point V in-DC=0.7V, the DC
gain of the circuit is 3.2216 dB. From top to bottom, the Gain-Bandwidths are:
4.3661MHz,3.5166MHz, N/A, N/A.

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Step 2:
Change the value of R in figure 4.1 and simulate the resulting waveforms of figure
4.4, then list the results as in table 4.1 and compare them with hand calculation
results.
CODE
Step2_tan

cload vout gnd 10p

.lib 'C:\synopsys\rf018.l'
TT
m1 vout vin gnd gnd
nch l=0.18u w=0.6u
vdd vdd gnd 1.8v
vin vin vg ac 1
vg vg gnd 0.7
r1 vout vdd 20k
.OP Output
subckt
element 0:m1
model
0:nch.12
region
Saturati
id
31.2239u
ibs
-8.209e21
ibd
-203.0900p
vgs
700.0000m
vds
1.1755
vbs
0.
vth
540.1286m
vdsat
139.5161m
vod
159.8714m
beta
1.9178m

.op
.probe v(vout)
.option post probe
.plot ac vdb(vout)
.ac dec 100 10 10g
.meas ac GB when
vdb(vout) = 0

vg vg gnd .4
r1 vout vdd 18k
.alter
vg vg gnd 1
r1 vout vdd 12k
.alter
vg vg gnd 1.5
r1 vout vdd 30k
.end

.alter

gam eff
969.4759m
gm
237.0856u
gds
6.2739u
gmb
66.6732u
cdtot
748.7119a
cgtot
1.0420f
cstot
1.5598f
cbtot
1.4965f
cgs
720.8171a
cgd
216.6205a

subckt
element 0:m1
model
0:nch.12

region
Cutoff
id
459.0688n
ibs
-1.209e22
ibd
-470.0210p
vgs
400.0000m
vds
1.7917
vbs
0.
vth
538.3571m
vdsat
45.7236m
vod
-138.3571m
beta
1.9381m
gam eff
969.4678m
gm
10.1735u

gds
167.4228n
gmb
2.8515u
cdtot
704.0967a
cgtot
667.5142a
cstot
953.4656a
cbtot
1.4384f
cgs
225.5888a
cgd
217.6838a

subckt
element 0:m1
model
0:nch.12
region
Saturati
id
105.8787u

Ceferino Kevin A. Tan


ibs
-2.774e20
ibd
-3.0073a
vgs
1.0000
vds
529.4553m
vbs
0.
vth
542.0152m
vdsat
251.5313m
vod
457.9848m
beta
1.8539m
gam eff
969.4956m
gm
289.1065u

BSECE 4
gds
32.8052u
gmb
84.2009u
cdtot
829.6260a
cgtot
1.0746f
cstot
1.5969f
cbtot
1.5675f
cgs
766.2829a
cgd
218.6239a

subckt
element 0:m1
model
0:nch.12

region
Linear
id
58.0057u
ibs
-1.523e20
ibd
-2.6919a
vgs
1.5000
vds
59.8283m
vbs
0.
vth
543.3185m
vdsat
395.2689m
vod
956.6815m
beta
1.6865m

September 27, 2015


gam eff
969.4830m
gm
37.1504u
gds
878.0483u
gmb
15.3454u
cdtot
1.9574f
cgtot
1.2250f
cstot
1.7965f
cbtot
1.7030f
cgs
595.0030a
cgd
581.1791a

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Figure 3 AC analysis with different values of R1. Notice that the curve for when
Vg=0.7v and R=20k now has the highest gain, but practically still has a smaller G.B.
than for Vg=1v and R=12k.
R1(k)

Rout(k)

Vg(V)

A (Gain in
dB)

-3dB (Hz)

G.B. (Hz)

20k

3.4832816
41

0.7

12.5

891k

3.6627M

18k

NA

0.4

-14.8

NA

NA

12k

2.6849974
43

7.92

1.84M

4.2088M

30k

NA

1.5

-27.8

NA

NA

Table 1 Shows the change in gain and GB for when the resistance R 1 and the input
voltage Vg is varied.

Ceferino Kevin A. Tan


Hand Calculations for step 2

BSECE 4

September 27, 2015

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Step 3:
Following the circuit of figure 4.5, simulate the V inVout DC transfer curve as in figure 4.6 and the
frequency response as in figure 4.7.
Relation of Vin and Vout
CODE
step3a_tan
.lib 'C:\synopsys\rf018.l'
TT
m1 vout g vs vs nch
l=0.18u w=0.6u
vdd vdd gnd 1.8v
vin g gnd 0.6v
r1 vout vdd 10k
r2 vs gnd 10k
cload vout gnd 10p

.op
.option post probe
.dc vin 0 2 0.01
.probe v(vout)
.end
.OP Result
subckt
element 0:m1
model 0:nch.12
region
Saturati
id
6.0080u

ibs
-1.581e-21
ibd
-3.2027n
vgs
539.8882m
vds
1.6798
vbs
0.
vth
538.6788m
vdsat
72.1341m
vod
1.2093m
beta
1.9343m
gam eff 969.4693m
gm
90.4431u
gds
1.7425u
gmb
25.1658u

Figure 4 Vin-Vout DC characteristic curve for CS with source degeneration. Note that
we have a much smaller slope magnitude at the saturation region.

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Frequency Response
CODE

.lib 'C:\synopsys\rf018.l'
TT
m1 vout vg vs vs nch
l=0.18u

.op
.probe v(vout)
.option post probe
.plot ac vdb(vout)
.ac dec 100 10 10g
.meas ac GB when
vdb(vout) = 0

w=0.6u

.end

vdd vdd gnd 1.8v


vin vin gnd ac 1
vg vg vin 0.7
r1 vout vdd 10k
r2 vs gnd 1k
cload vout gnd 10p

.OP Result

step3b_tan

subckt
element 0:m1
model 0:nch.12
region
Saturati

id
26.8756u
ibs
-7.067e-21
ibd
-3.6654n
vgs
673.1207m
vds
1.5043
vbs
0.
vth
539.1910m
vdsat 127.9119m
vod
133.9297m
beta
1.9217m
gam eff 969.4748m
gm
226.1405u
gds
5.2478u
gmb
62.8548u
gb= 2.4040E+06

Figure 5 AC analysis of CS amplifier with source degeneration. Placing a source


resistance of 1k has resulted in a new DC gain of 4.91dB. Our G.B. value(highlighted
above) is given by 2.4040MHz.

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Step 4:
Change the value of Rs in figure 4.5 and simulate the resulting waveforms of figure
4.8; list the results as in table 4.2. Then, compare them with hand calculation
results.
CODE
Step4_tan
.lib 'C:\synopsys\rf018.l'
TT
m1 vout vg vs vs nch
l=0.18u
w=0.6u

.OP Results
subckt
element 0:m1
model 0:nch.12
region
Saturati
id
29.5816u
ibs
-7.778e-21
ibd
-3.5038n
vgs
685.2074m
vds
1.4894
vbs
0.
vth
539.2353m
vdsat 133.3192m
vod
145.9721m
beta
1.9200m
gam eff 969.4755m
gm
235.2223u
gds
5.5817u
gmb
65.3912u
cdtot 723.8702a
cgtot
1.0378f
cstot
1.5530f
cbtot
1.4717f
cgs
714.0206a

vdd vdd gnd 1.8v


vin vin gnd ac 1
vg vg vin 0.7
r1 vout vdd 10k
r2 vs gnd 500
cload vout gnd 10p
.op
.probe v(vout)
.option post probe
.plot ac vdb(vout)

cgd

216.6196a

subckt
element 0:m1
model 0:nch.12
region
Saturati
id
41.6181u
ibs
-1.094e-20
ibd
-1.0508n
vgs
737.5713m
vds
1.3214
vbs
0.
vth
539.7207m
vdsat 156.0311m
vod
197.8506m
beta
1.9119m
gam eff 969.4786m
gm
263.3588u
gds
7.1085u
gmb
73.6157u
cdtot 736.5330a
cgtot
1.0500f
cstot
1.5688f
cbtot
1.4836f

.ac dec 100 10 10g


.meas ac GB when
vdb(vout) = 0
.alter
vg vg vin 0.8
r2 vs gnd 1.5k
.alter
vg vg vin 0.6
r2 vs gnd 2k
.end

cgs
cgd

730.8460a
216.5968a

subckt
element 0:m1
model 0:nch.12
region
Saturati
id
10.3910u
ibs
-2.734e-21
ibd
-5.0179n
vgs
579.2079m
vds
1.6752
vbs
0.
vth
538.6945m
vdsat
86.8280m
vod
40.5134m
beta
1.9317m
gam eff 969.4704m
gm
133.8681u
gds
2.6686u
gmb
37.1546u
cdtot 711.3068a
cgtot 933.1315a
cstot
1.3970f

Ceferino Kevin A. Tan


cbtot

1.4563f

BSECE 4
cgs

September 27, 2015

578.0375a

cgd

216.9081a

Figure 6 AC analysis of a CS amplifier with source degeneration: Varying source


resistance Rs. (Top to bottom) (Vg,Rs): (0.7,500 ),(0.8,1500 ),(0.6,2000).
A (Gain in
R2(k)
Vg(V)
Rout(k)
-3dB (Hz)
G.B. (Hz)
dB)
5.39029632
0.5
0.7
6.01
1.67M
2.8911M
8
7.21639052
1.5
0.8
5.02
1.67M
2.4667M
9
2

0.6

12.0251322

0.254

1.62M

0.39899M

Table 2 shows the variation of the gain, cutoff frequency, and G.B. when value of R s
is changed. The value of Rout is not changed even with the addition of a source
resistance Rs(http://whites.sdsmt.edu/classes/ee320/notes/320Lecture32.pdf). See
that the cutoff frequency does not change even when the gain does.
You can see that having a source resistance will result in a very little difference in
cutoff frequencies for all curves.
Addition of a source resistance will result in a lowering of V gs with respect to Vi. Also,
this will result in a lowering of the small-signal voltage gain as can be seen in the ff:

A v=

g m R D
1+ gm Rs

Ceferino Kevin A. Tan

BSECE 4

Despite these drawbacks, the source


resistances major benefit is that the smallsignal voltage gain will be made much less
dependent on the MOSFET transconductance.
Note that for CS with S.D., the output
impedance is given by the equations to the
right:

September 27, 2015

Ceferino Kevin A. Tan


Hand Calculations for step 4

BSECE 4

September 27, 2015

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Step 5:
Change the value of Rs in figure 4.5, and simulate the waveforms of figure 4.10 to
observe the relationship between Ids and Vin.
CODE
step5_tan
.lib 'C:\synopsys\rf018.l'
TT
m1 vout vg vs vs nch
l=0.18u w=0.6u
vdd vdd gnd 1.8v
vin vin gnd ac 1
.OP Results
subckt
element 0:m1
model
0:nch.12
region
Saturati
id
29.5816u
ibs
-7.778e21
ibd
-3.5038n
vgs
685.2074m
vds
1.4894
vbs
0.
vth
539.2353m
vdsat
133.3192m
vod
145.9721m
beta
1.9200m

vg vg vin 0.7
r1 vout vdd 10k
r2 vs gnd 500
cload vout gnd 10p
.op
.option post probe
.dc vg 0 1.8 0.01
.probe i1(m1)

.alter
r2 vs gnd 1k
.alter
r2 vs gnd 1.5k
.alter
r2 vs gnd 0k
.end

gam eff
969.4755m
gm
235.2223u
gds
5.5817u
gmb
65.3912u
cdtot
723.8702a
cgtot
1.0378f
cstot
1.5530f
cbtot
1.4717f
cgs
714.0206a
cgd
216.6196a
subckt
element 0:m1
model
0:nch.12
region
Saturati

id
26.8756u
ibs
-7.067e21
ibd
-3.6654n
vgs
673.1207m
vds
1.5043
vbs
0.
vth
539.1910m
vdsat
127.9119m
vod
133.9297m
beta
1.9217m
gam eff
969.4748m
gm
226.1405u
gds
5.2478u
gmb
62.8548u

cdtot
722.8043a
cgtot
1.0334f
cstot
1.5471f
cbtot
1.4707f
cgs
708.2111a
cgd
216.6307a
subckt
element 0:m1
model
0:nch.12
region
Saturati
id
24.6831u
ibs
-6.491e21
ibd
-3.7588n
vgs
662.9697m

Ceferino Kevin A. Tan


vds
1.5161
vbs
0.
vth
539.1561m
vdsat
123.3487m
vod
123.8136m
beta
1.9230m
gam eff
969.4742m
gm
217.8753u
gds
4.9653u
gmb
60.5530u

BSECE 4
cdtot
721.9729a
cgtot
1.0289f
cstot
1.5410f
cbtot
1.4700f
cgs
702.3453a
cgd
216.6422a
subckt
element 0:m1
model
0:nch.12
region
Saturati

id
33.0209u
ibs
-8.681e21
ibd
-3.2440n
vgs
700.0000m
vds
1.4698
vbs
0.
vth
539.2933m
vdsat
139.8792m
vod
160.7067m
beta
1.9179m

September 27, 2015


gam eff
969.4764m
gm
245.2395u
gds
5.9862u
gmb
68.2011u
cdtot
725.2805a
cgtot
1.0422f
cstot
1.5586f
cbtot
1.4729f
cgs
719.8207a
cgd
216.6093a

Figure 7 From top to bottom are the curves for when the source resistance(in
Ohms) is 0, 500, 1000, 1500.

Ceferino Kevin A. Tan

Vital equation Gm=

BSECE 4

1
1
+ Rs
gm

( )

September 27, 2015

for a CS amplifier with source degeneration. Thus,

when we increase Rs, we decrease the slope of our Ids-Vgs graph, which implies that
we will produce a much smaller output current for a given input DC voltage when
our source resistance is increased. Since A v=-GmRD, Av is now given by Av =

R D

( gm1 )+ Rs

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Step 6:
Following the amplifier configuration of figure
4.11, the input signal is an ideal sinusoidal wave
with 0.05v amplitude, and the frequency is
100kHz. Perform the FFT analysis to Vin to get the
frequency spectrum like figure 4.12
CODE
step6_tan
.lib
'C:\synopsys\rf0
18.l' TT
m1 vout vg vs
vs nch l=0.18u
w=0.6u
.OP Results
subckt
element 0:m1
model
0:nch.12
region
Saturati
id
29.5816u
ibs
-7.778e21

vdd vdd gnd 1.8


vin vin gnd
sin(0 0.05 100k
0 0 0)
vg vg vin 0.7
r1 vout vdd 10k
r2 vs gnd 500

ibd
-3.5038n
vgs
685.2074m
vds
1.4894
vbs
0.
vth
539.2353m
vdsat
133.3192m
vod
145.9721m

cload vout gnd


10p
.op
.option post
probe
.tran 625n
10.24m

beta
1.9200m
gam eff
969.4755m
gm
235.2223u
gds
5.5817u
gmb
65.3912u
cdtot
723.8702a

.fft v(vg)
start=0
stop=10.24m
np=16384
.end

cgtot
1.0378f
cstot
1.5530f
cbtot
1.4717f
cgs
714.0206a
cgd
216.6196a

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Figure 8 Fast-Fourier Transform of the Vin. The result should show no harmonic
component except for the 100kHz component, but this is the graph we obtained
during the simulation, the reasons for which, we cannot exactly point out. We have
at 100kHz a vdB value of -22.9 dB.

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Step 7:
Perform the FFT Analysis to Vout in the circuit of figure 4.11 while changing the value
of Rs to get the frequency spectrum like in figure 4.13-16. List the results of figure
4.13-16 like in table 4.3.
CODE
Step7_tan
.lib
'C:\synopsys\rf0
18.l' TT
m1 vout vg vs
vs nch l=0.18u
w=0.6u

.OP Results
subckt

Rs=0

element 0:m1
model
0:nch.12
region
Saturati
id
33.0209u
ibs
-8.681e21
ibd
-3.2440n
vgs
700.0000m
vds
1.4698
vbs
0.
vth
539.2933m
vdsat
139.8792m
vod
160.7067m

vdd vdd gnd 1.8


vin vin gnd
sin(0 0.05 100k
0 0 0)
vg vg vin 0.7
r1 vout vdd 10k
r2 vs gnd 0
cload vout gnd
10p

.op
.option post
probe
.tran 625n
10.24m
.fft v(vout)
start=0
stop=10.24m
np=16384

.alter
r2 vs gnd 500
.alter
r2 vs gnd 1k
.alter
r2 vs gnd 1.5k

beta
1.9179m
gam eff
969.4764m
gm
245.2395u
gds
5.9862u
gmb
68.2011u
cdtot
725.2805a
cgtot
1.0422f
cstot
1.5586f
cbtot
1.4729f
cgs
719.8207a
cgd
216.6093a

element 0:m1
model
0:nch.12
region
Saturati
id
29.5816u
ibs
-7.778e21
ibd
-3.5038n
vgs
685.2074m
vds
1.4894
vbs
0.
vth
539.2353m
vdsat
133.3192m
vod
145.9721m
beta
1.9200m
gam eff
969.4755m

gm
235.2223u
gds
5.5817u
gmb
65.3912u
cdtot
723.8702a
cgtot
1.0378f
cstot
1.5530f
cbtot
1.4717f
cgs
714.0206a
cgd
216.6196a

subckt
Rs=500

.end

subckt
Rs=1000
element 0:m1
model
0:nch.12

Ceferino Kevin A. Tan


region
Saturati
id
26.8756u
ibs
-7.067e21
ibd
-3.6654n
vgs
673.1207m
vds
1.5043
vbs
0.
vth
539.1910m
vdsat
127.9119m
vod
133.9297m
beta
1.9217m
gam eff
969.4748m
FFT Analysis of Vout

BSECE 4
gm
226.1405u
gds
5.2478u
gmb
62.8548u
cdtot
722.8043a
cgtot
1.0334f
cstot
1.5471f
cbtot
1.4707f
cgs
708.2111a
cgd
216.6307a

subckt
Rs=1500
without Rs

element 0:m1
model
0:nch.12
region
Saturati
id
24.6831u
ibs
-6.491e21
ibd
-3.7588n
vgs
662.9697m
vds
1.5161
vbs
0.
vth
539.1561m
vdsat
123.3487m
vod
123.8136m

September 27, 2015


beta
1.9230m
gam eff
969.4742m
gm
217.8753u
gds
4.9653u
gmb
60.5530u
cdtot
721.9729a
cgtot
1.0289f
cstot
1.5410f
cbtot
1.4700f
cgs
702.3453a
cgd
216.6422a

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Figure 9 When Rs=0, the gain for the 1st, 2nd, and 3rd Harmonics are -22.20dB,
-53.10dB, -75.80dB.
FFT Analysis of Vout with Rs=0.5k

Figure 10 When Rs=500, the gain for the 1st, 2nd, and 3rd Harmonics are -23.60dB,
-55.10dB, -80.80dB.
FFT Analysis of Vout with Rs=1k

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Figure 11 When Rs=1000, the gain for the 1st, 2nd, and 3rd Harmonics are -24.90dB,
-56.70dB, -81.10dB.
FFT Analysis of Vout with Rs=1.5k

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Figure 12 When Rs=1500, the gain for the 1st, 2nd, and 3rd Harmonics are 26.00dB,
-58.10dB, -81.50dB.

Rs(k)

Vin-DC(V)

Vin-AC(V)

0
0.500

0.7

0.05

1.5

A(dB)

Vout(dB)

2nd
Harmonic
(dB)

7.28

-22.20

-53.10

-75.80

6.01

-23.60

-55.10

-80.80

4.90

-24.90

-56.70

-81.10

3.94

-26.00

-58.10

-81.50

st

nd

3rd
Harmonic
(dB)

rd

Table 3 Shows how the gains for the 1 , 2 , and 3 harmonics change when the
value of Rs is changed. Generally, increasing the Rs value will result in the gains for
the 2nd and 3rd harmonics to approach some common value.

QUESTIONS

1. How to increase the gain of CS amplifier with resistive load? Explain what
changes will occur to the circuit characteristics when we use those methods.
From what I have observed in the experiment and the previous one, there are
a few things we can do:
a. Increase RD.
b. Increase W/L ratio.
Increasing RD would result in a much higher gain, as stated in the following
equation:

A v=

g m R D
1+ gm Rs

But for a common-source amplifier,

A v =gm R D
We have learned in the previous laboratory activity that increasing the W/L
ratio of our device would result in a much higher current output for the same
input voltage.

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

Note that increasing the W/L ratio increases the slope of the I ds-Vds graph of
our nMOS (as observed in the previous lab activity). Therefore, we increase
gm along with it, consequently, we get a much higher gain magnitude.

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

2. Replace Rs in figure 4.11 with a diode-connected nMOS. Using the steps we


followed before, what is the DC gain of this circuit?

Figure 13 The DC gain for the network with a diode-connected nMOS(of the
same aspect ratio as main nMOS) is now -38.70dB.

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

3. Using the configuration of question 2, perform the FFT Analysis of V in and Vout
to get the frequency spectrum of these waves. What happens to the circuit
linearity? Is there any difference with figure 4.11?
FFT of Vin

Figure 14 Note that for the FFT of the input voltage, we see no significant
difference compared to the network with source resistance instead of the
diode-connected nMOS in the source.

Ceferino Kevin A. Tan

BSECE 4

September 27, 2015

FFT of Vout

Figure 15 Note that for the FFT of the output voltage Vout, we we see no
significant difference compared to the network with source resistance instead
of the diode-connected nMOS in the source.

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