Sound Fader Control Circuit

INTEGRATED CIRCUITS
DATA SHEET
TEA6320
Sound fader control circuit
Preliminary specification
Supersedes data of September 1992
File under Integrated Circuits, IC01
1995 Dec 19
Philips Semiconductors
TEA6320
FEATURES
Source selector for four stereo and one mono inputs
Interface for noise reduction circuits
Interface for external equalizer
Volume, balance and fader control
Special loudness characteristic automatically controlled
in combination with volume setting
GENERAL DESCRIPTION
The sound fader control circuit TEA6320 is an I2C-bus
controlled stereo preamplifier for car radio hi-fi sound
applications.
Bass and treble control

Mute control at audio signal zero crossing
Fast mute control via I2C-bus
Fast mute control via pin
I2C-bus control for all functions
Power supply with internal power-on reset.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VCC
supply voltage
ICC
supply current
Vo(rms)
maximum output voltage level
Gv
CONDITIONS
MIN.
TYP.
MAX.
UNIT
7.5
8.5
9.5
VCC = 8.5 V
26
mA
VCC = 8.5 V; THD 0.1%
2000
mV
voltage gain
86
+20
dB
Gstep(vol)
step resolution (volume)
dB
Gbass
bass control
15
+15
dB
Gtreble
treble control
12
+12
dB
Gstep(treble)
step resolution (bass, treble)
1.5
dB
(S+N)/N
signal-plus-noise to noise ratio
VO = 2.0 V; Gv = 0 dB;
unweighted
105
dB
RR100
ripple rejection
Vr(rms) < 200 mV; f = 100 Hz;

Gv = 0 dB
76
dB
cs
channel separation
250 Hz f 10 kHz; Gv = 0 dB
90
96
dB
ORDERING INFORMATION
TYPE
NUMBER
TEA6320
TEA6320T
1995 Dec 19
PACKAGE
NAME
SDIP32
SO32
DESCRIPTION
VERSION
plastic shrink dual in-line package; 32 leads (400 mil)
SOT232-1
plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
20 k
CKVL 220 nF
100 F
Vref
VCC
10
MUTE
12
21
31
MUTE
FUNCTION
ZERO CROSS
DETECTOR
POWER
SUPPLY
GND
10 nF
150 nF
VOLUME I
+20 to 31 dB
LOUDNESS
LEFT
47 F
19
BASS
LEFT
TREBLE
LEFT
15 dB
12 dB
VOLUME II
0 to 55 dB
BALANCE
FADER REAR
output
left
VOLUME II
0 to 55 dB
BALANCE
FADER FRONT
9 x 220 nF
5.6 nF
Cm
33 nF
BLOCK DIAGRAM
1995 Dec 19
2.2 k
8.2 nF
16
32
15
input
left
source
I2C-BUS
RECEIVER
LOGIC
13
SCL
SDA
11
SOURCE
input
mono
source
14
SELECTOR
VOLUME I
+20 to 31 dB
LOUDNESS
RIGHT
22
BASS
RIGHT
TREBLE
RIGHT
15 dB
12 dB
VOLUME II
0 to 55 dB
BALANCE
FADER FRONT
output
right
20
input
right
source
18
TEA6320
17
23
25
26
24
27
VOLUME II
0 to 55 dB
BALANCE
FADER REAR
30
28
MED421
150 nF
8.2 nF 20 k
Fig.1 Block diagram.
TEA6320
2.2 k
5.6 nF
33 nF
CKVL 220 nF
handbook, full pagewidth
CKIN
29
TEA6320
PINNING
SYMBOL PIN
DESCRIPTION
SDA
serial data input/output
GND
ground
OUTLR
output left rear
OUTLF
output left front
TL
treble control capacitor left channel or

input from an external equalizer
B2L
bass control capacitor left channel or

output to an external equalizer
handbook, halfpage
SDA
32 SCL
GND
31 VCC
OUTLR
30 OUTRR
OUTLF
29 OUTRF
B1L
bass control capacitor, left channel
IVL
input volume I, left control part
TL
28 TR
ILL
input loudness, left control part
B2L
27 B2R
QSL
10
output source selector, left channel
B1L
26 B1R
IDL
11
input D left source
MUTE
12
mute control
IVL
ICL
13
input C left source
IMO
14
input mono source
QSL 10
23 QSR
IBL
15
input B left source
IDL 11
22 IDR
IAL
16
input A left source
MUTE 12
21 Vref
IAR
17
input A right source
ICL 13
20 ICR
IBR
18
input B right source
IMO 14
19 CAP
CAP
19
electronic filtering for supply
ICR
20
input C right source
IBL 15
18 IBR
Vref
21
reference voltage (0.5VCC)
IAL 16
17 IAR
IDR
22
input D right source
QSR
23
output source selector right channel
ILR
24
input loudness right channel
IVR
25
input volume I, right control part
B1R
26
bass control capacitor right channel
B2R
27
bass control capacitor right channel or

output to an external equalizer
TR
28
treble control capacitor right channel

or input from an external equalizer
OUTRF
29
output right front
OUTRR
30
output right rear
VCC
31
supply voltage
SCL
32
serial clock input
1995 Dec 19
25 IVR
TEA6320
ILL
24 ILR
MED422
Fig.2 Pin configuration.
TEA6320
and TL and TR are inputs for inserting an external
equalizer.
FUNCTIONAL DESCRIPTION
The source selector selects one of 4 stereo inputs or the
mono input. The maximum input signal voltage is
Vi(rms) = 2 V. The outputs of the source selector and the
inputs of the following volume control parts are available at
pins 8 and 10 for the left channel and pins 23 and 25 for
the right channel. This offers the possibility of interfacing a
noise reduction system.
The last section of the circuit is the volume II block. The

balance and fader functions are performed using the same
control blocks. This is realized by 4 independently
controllable attenuators, one for each output. The control
range of these attenuators is 55 dB in steps of 1 dB with an
additional mute step.
The circuit provides 3 mute modes:
The volume control function is split into two sections:

volume I control block and volume II control block.
1. Zero crossing mode mute via I2C-bus using

2 independent zero crossing detectors (ZCM,
see Tables 2 and 9 and Fig.16).
The control range of volume I is between +20 dB and

31 dB in steps of 1 dB. The volume II control range is
between 0 dB and 55 dB in steps of 1 dB. Although the
theoretical possible control range is 106 dB
(+20 to 86 dB), in practice a range of 86 dB (+20 to
66 dB) is recommended. The gain/attenuation setting of
the volume I control block is common for both channels.
2. Fast mute via MUTE pin (see Fig.10).

3. Fast mute via I2C-bus either by general mute (GMU,
see Tables 2 and 9) or volume II block setting
(see Table 4).
The mute function is performed immediately if ZCM is
cleared (ZCM = 0). If the bit is set (ZCM = 1) the mute is
activated after changing the GMU bit. The actual mute
switching is delayed until the next zero crossing of the
audio frequency signal. As the two audio channels (left and
right) are independent, two comparators are built-in to
control independent mute switches.
The volume I control block operates in combination with

the loudness control. The filter is linear when the maximum
gain for the volume I control (+20 dB) is selected. The filter
characteristic increases automatically over a range of
32 dB down to a setting of 12 dB. That means the
maximum filter characteristic is obtained at 12 dB setting
of volume I. Further reduction of the volume does not
further influence the filter characteristic (see Fig.5). The
maximum selected filter characteristic is determined by
external components. The proposed application gives a
maximum boost of 17 dB for bass and 4.5 dB for treble.
The loudness may be switched on or off via I2C-bus control
(see Table 7).
To avoid a large delay of mute switching when very low

frequencies are processed, the maximum delay time is
limited to typically 100 ms by an integrated timing circuit
and an external capacitor (Cm = 10 nF, see Fig.10). This
timing circuit is triggered by reception of a new data word
for the switch function which includes the GMU bit. After a
discharge and charge period of an external capacitor the
muting switch follows the GMU bit if no zero crossing was
detected during that time.
The volume I control block is followed by the bass control

block. A single external capacitor of 33 nF for each
channel in combination with internal resistors, provides the
frequency response of the bass control (see Fig.3). The
adjustable range is between 15 and +15 dB at 40 Hz.
The mute function can also be controlled externally. If the

mute pin is switched to ground all outputs are muted
immediately (hardware mute). This mute request
overwrites all mute controls via the I2C-bus for the time the
pin is held LOW. The hardware mute position is not stored
in the TEA6320.
Both loudness and bass control result in a maximum bass

boost of 32 dB for low volume settings.
The treble control block offers a control range between
12 and +12 dB in steps of 1.5 dB at 15 kHz. The filter
characteristic is determined by a single capacitor of 5.6 nF
for each channel in combination with internal resistors
(see Fig.4).
For the turn on/off behaviour the following explanation is

generally valid. To avoid AF output caused by the input
signal coming from preceding stages, which produces
output during drop of VCC, the mute has to be set, before
the VCC will drop. This can be achieved by I2C-bus control
or by grounding the MUTE pin.
The basic step width of bass and treble control is 3 dB. The
intermediate steps are obtained by switching 1.5 dB boost
and 1.5 dB attenuation steps.
For use where is no mute in the application before turn off,

a supply voltage drop of more than 1 VBE will result in a
mute during the voltage drop.
The bass and treble control functions can be switched off

via I2C-bus. In this event the internal signal flow is
disconnected. The connections B2L and B2R are outputs
1995 Dec 19
TEA6320
The hardware mute function is favourable for use in Radio
Data System (RDS) applications. The zero crossing mute
avoids modulation plops. This feature is an advantage for
mute during changing presets and/or sources (e.g. traffic
announcement during cassette playback).
The power supply should include a VCC buffer capacitor,

which provides a discharging time constant. If the input
signal does not disappear after turn off the input will
become audible after certain time. A 4.7 k resistor
discharges the VCC buffer capacitor, because the internal
current of the IC does not discharge it completely.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
10
Vn
voltage at all pins except pin 2

referenced to GND (pin 2)
VCC
Tamb
operating ambient temperature
40
+85
Tstg
storage temperature
65
+150
Ves
electrostatic handling
note 1
Note
1. Human body model: C = 100 pF; R = 1.5 k; V 2 kV. Charge device model: C = 200 pF; R = 0 ; V 500 V.
1995 Dec 19
TEA6320
CHARACTERISTICS
VCC = 8.5 V; RS = 600 ; RL = 10 k; CL = 2.5 nF; AC coupled; f = 1 kHz; Tamb = 25 C; gain control Gv = 0 dB; bass
linear; treble linear; fader off; balance in mid position; loudness off; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCC
supply voltage
7.5
8.5
9.5
ICC
supply current
26
33
mA
VDC
internal DC voltage at inputs and

outputs
3.83
4.25
4.68
Vref
internal reference voltage at pin 21
Gv(max)
maximum voltage gain
Vo(rms)
output voltage level for
4.25
RS = 0 ; RL =
19
20
21
dB
Pmax at the power output stage
THD 0.5%; see Fig.11
2000
mV
start of clipping
THD = 1%
2300
mV
RL = 2 k; CL = 10 nF;
THD = 1%
2000
mV
200
mV
low frequency (1 dB)
60
Hz
30
Hz
high frequency (1 dB)
20000
Hz
Vi(rms)
input sensitivity
Vo = 2000 mV; Gv = 20 dB
fro
roll-off frequency
CKIN = 220 nF;

CKVL = 220 nF; Zi = Zi(min)
CKIN = 470 nF;

CKVL = 100 nF; Zi = Zi(typ)
17
Hz
90
96
dB
Vi = 100 mV; Gv = 20 dB
0.1
cs
channel separation
Vi = 2 V; frequency range
250 Hz to 10 kHz
THD
total harmonic distortion
frequency range
20 Hz to 12.5 kHz
RR
(S+N)/N
ripple rejection
signal-plus-noise to noise ratio
Vi = 1 V; Gv = 0 dB
0.05
0.15
Vi = 2 V; Gv = 0 dB
0.1
Vi = 2 V; Gv = 10 dB
0.1
f = 100 Hz
70
76
dB
f = 40 Hz to 12.5 kHz
66
dB
unweighted;
20 Hz to 20 kHz (RMS);
Vo = 2.0 V; see Figs 6 and 7
105
dB
Gv = 0 dB
95
dB
Gv = 12 dB
88
dB
Gv = 20 dB
81
dB
Vr(rms) < 200 mV
CCIR468-2 weighted; quasi

peak; Vo = 2.0 V
1995 Dec 19
SYMBOL
TEA6320
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Pno(rms)
noise output power (RMS value)

only contribution of TEA6320;
power amplifier for 6 W
mute position; note 1
10
nW
ct
crosstalk
V bus ( p p )
20 log -------------------------- between bus
V o ( rms )
note 2
110
dB
25
35
45
inputs and signal outputs

Source selector
Zi
input impedance
input isolation of one selected

source to any other input
f = 1 kHz
105
dB
f = 12.5 kHz
95
dB
Vi(rms)
maximum input voltage

(RMS value)
THD < 0.5%; VCC = 8.5 V
2.15
THD < 0.5%; VCC = 7.5 V
1.8
Voffset
DC offset voltage at source

selector output by selection of any
inputs
10
mV
Zo
output impedance
80
120
RL
output load resistance
10
CL
output load capacity
2500
pF
Gv
voltage gain, source selector
dB
Control part (source selector disconnected; source resistance 600 )

Zi
input impedance volume input
100
150
200
input impedance loudness input
25
33
40
Zo
output impedance
80
120
RL
output load resistance
CL
output load capacity
10
nF
RDCL
DC load resistance at output to

ground
4.7
Vi(rms)
maximum input voltage

(RMS value)
THD < 0.5%
2.15
Vno
noise output voltage
CCIR468-2 weighted; quasi

peak
Gv = 20 dB
110
220
Gv = 0 dB
33
50
Gv = 66 dB
13
22
10
total continuous control range
106
dB
recommended control range
86
dB
step resolution
dB
step error between any adjoining

step
0.5
dB
mute position
CRtot
Gstep
1995 Dec 19
SYMBOL
TEA6320
PARAMETER
Ga
attenuator set error
Gt
gain tracking error
MUTEatt
Voffset
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Gv = +20 to 50 dB
dB
Gv = 51 to 66 dB
dB
Gv = +20 to 50 dB
dB
mute attenuation
see Fig.10
100
110
dB
DC step offset between any

adjoining step
Gv = 0 to 66 dB
0.2
10
mV
Gv = 20 to 0 dB
15
mV
10
mV
DC step offset between any step to Gv = 0 to 66 dB

mute
Volume I control and loudness
CRvol
continuous volume control range
51
dB
Gv
voltage gain
31
+20
dB
Gstep
step resolution
dB
LBmax
maximum loudness boost
f = 40 Hz
17
dB
f = 10 kHz
4.5
dB
14
15
16
dB
loudness on; referred to

loudness off; boost is
determined by external
components
Bass control
Gbass
Gstep
Voffset
bass control, maximum boost
f = 40 Hz
maximum attenuation
f = 40 Hz
14
15
16
dB
step resolution (toggle switching)
f = 40 Hz
1.5
dB

step
f = 40 Hz
0.5
dB
20
mV
11
12
13
dB
DC step offset in any bass position
Treble control
Gtreble
Gstep
Voffset
treble control, maximum boost
f = 15 kHz
maximum attenuation
f = 15 kHz
11
12
13
dB
maximum boost
f > 15 kHz
15
dB
step resolution (toggle switching)
f = 15 kHz
1.5
dB

step
f = 15 kHz
0.5
dB
10
mV
DC step offset in any treble

position
Volume II, balance and fader control

CR
continuous attenuation fader and

volume control range
53.5
55
56.5
dB
Gstep
step resolution
dB
attenuation set error
1.5
dB
1995 Dec 19
SYMBOL
TEA6320
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Mute function (see Fig.10)

HARDWARE MUTE
mute switch level (2 VBE)
1.45
VswLOW
input level
1.0
Ii
input current
300
Vsw
mute active
VswLOW = 1 V
mute passive: level internally defined

VswHIGH
saturation voltage
VCC
td(mute)
delay until mute passive
0.5
ms
ZERO CROSSING MUTE

Id
discharge current
0.3
0.6
1.2
Ich
charge current
300
150
VswDEL
delay switch level (3 VBE)
2.2
td
delay time
100
ms
Vwind
window for audio signal zero

crossing detection
30
40
mV
V19
0.7
Cm = 10 nF
Muting at power supply drop

VCCdrop
supply drop for mute active
Power-on reset (when reset is active the GMU-bit (general mute) is set and the I2C-bus receiver is in
reset position)
VCC
increasing supply voltage start of

reset
2.5
end of reset
5.2
6.5
7.2
decreasing supply voltage start of

reset
4.2
5.5
6.2
Digital part (I2C-bus pins); note 3

ViH
HIGH level input voltage
9.5
ViL
LOW level input voltage
0.3
+1.5
IiH
HIGH level input current
10
+10
IiL
LOW level input current
10
+10
VoL
LOW level output voltage
0.4
IL = 3 mA
Notes to the characteristics

1. The indicated values for output power assume a 6 W power amplifier at 4 with 20 dB gain and a fixed attenuator
of 12 dB in front of it. Signal-to-noise ratios exclude noise contribution of the power amplifier.
2. The transmission contains: total initialization with MAD and subaddress for volume and 8 data words, see also
definition of characteristics, clock frequency = 50 kHz, repetition burst rate = 400 Hz, maximum bus signal
amplitude = 5 V (p-p).
3. The AC characteristics are in accordance with the I2C-bus specification. This specification, The I2C-bus and how to
use it, can be ordered using the code 9398 393 40011.
1995 Dec 19
10
TEA6320
I2C-BUS PROTOCOL
I2C-bus format
S(1)
SLAVE ADDRESS(2)
A(3)
SUBADDRESS(4)
A(3)
DATA(5)
A(3)
P(6)
Notes
1. S = START condition.
2. SLAVE ADDRESS (MAD) = 1000 0000.
3. A = acknowledge, generated by the slave.
4. SUBADDRESS (SAD), see Table 1.
5. DATA, see Table 1; if more than 1 byte of DATA is transmitted, then auto-increment of the significant subaddress is
performed.
6. P = STOP condition.
Table 1
Second byte after MAD

MSB
FUNCTION
LSB
BIT
7
2(1)
1(1)
0(1)
Volume/loudness
Fader front right
FFR
Fader front left
FFL
Fader rear right
FRR
Fader rear left
FRL
Bass
BA
Treble
TR
Switch
Note
1. Significant subaddress.
1995 Dec 19
11

Table 2
TEA6320
Definition of third byte after MAD and SAD

MSB
FUNCTION
LSB
BIT
7
ZCM(1)
LOFF(2)
V5(3)
V4(3)
V3(3)
V2(3)
V1(3)
V0(3)
Volume/loudness
Fader front right
FFR
X(4)
X(4)
FFR5(5) FFR4(5) FFR3(5) FFR2(5) FFR1(5) FFR0(5)
Fader front left
FFL
X(4)
X(4)
FFL5(6)
FFL4(6)
FFL3(6)
FFL2(6)
FFL1(6)
FFL0(6)
Fader rear right
FRR
X(4)
X(4)
FRR5(7)
FRR4(7)
FRR3(7)
FRR2(7)
FRR1(7)
FRR0(7)
Fader rear left
FRL
X(4)
X(4)
FRL5(8)
FRL4(8)
FRL3(8)
FRL2(8)
FRL1(8)
FRL0(8)
Bass
BA
X(4)
X(4)
X(4)
BA4(9)
BA3(9)
BA2(9)
BA1(9)
BA0(9)
Treble
TR
X(4)
X(4)
X(4)
TR4(10)
TR3(10)
TR2(10)
TR1(10)
TR0(10)
Switch
GMU(11)
X(4)
X(4)
X(4)
X(4)
SC2(12)
SC1(12)
SC0(12)
Notes
1. Zero crossing mode.
2. Switch loudness on/off.
3. Volume control.
4. Dont care bits (logic 1 during testing).
5. Fader control front right.
6. Fader control front left.
7. Fader control rear right.
8. Fader control rear left.
9. Bass control.
10. Treble control.
11. Mute control for all outputs (general mute).
12. Source selector control.
1995 Dec 19
12

Table 3
TEA6320
Volume I setting
Gv
(dB)
DATA
V5
V4
V3
V2
V1
V0
Loudness on: the increment of the loudness characteristics is linear at every volume step in the range from
+20 to 11 dB
+20
+19
+18
+17
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
10
11
1995 Dec 19
13
Gv
(dB)
TEA6320
DATA
V5
V4
V3
V2
V1
V0
Loudness characteristic is constant in a range from 11 dB to 31 dB

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Repetition of steps in a range from 28 dB to 31 dB

28
29
30
31
28
29
30
31
28
29
30
31
1995 Dec 19
14

Table 4
TEA6320
Volume II setting (fader and balance); note 1

DATA
FRR5
FRR4
FRR3
FRR2
FRR1
FRR0
FRL5
FRL4
FRL3
FRL2
FRL1
FRL0
FFL5
FFL4
FFL3
FFL2
FFL1
FFL0
FFR5
FFR4
FFR3
FFR2
FFR1
FFR0
Gv
(dB)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1995 Dec 19
15
TEA6320
DATA
FRR5
FRR4
FRR3
FRR2
FRR1
FRR0
FRL5
FRL4
FRL3
FRL2
FRL1
FRL0
FFL5
FFL4
FFL3
FFL2
FFL1
FFL0
FFR5
FFR4
FFR3
FFR2
FFR1
FFR0
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Gv
(dB)
55
mute
mute
mute
mute
mute
mute
mute
mute
Note
1. For a particular range the data is always the same, only the subaddress changes.
1995 Dec 19
16

Table 5
TEA6320
Bass setting
DATA
Gbass
(dB)
BA4
BA3
BA2
BA1
BA0
+15.0
+13.5
+15.0
+13.5
+15.0
+13.5
+12.0
+10.5
+9.0
+7.5
+6.0
+4.5
+3.0
+1.5
0(1)
0(2)
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
13.5
15.0
note 3
note 3
note 3
notes 3 and 4
Notes
1. Recommended data word for step 0 dB.
2. Result of 1.5 dB boost and 1.5 dB attenuation.
3. The last four bass control data words mute the bass response.
4. The last bass control and treble control data words (00000) enable the external equalizer connection.
1995 Dec 19
17

Table 6
TEA6320
Treble setting
DATA
Gtreble
(dB)
TR4
TR3
TR2
TR1
TR0
+12.0
+10.5
+12.0
+10.5
+12.0
+10.5
+12.0
+10.5
+9.0
+7.5
+6.0
+4.5
+3.0
+1.5
0(1)
0(2)
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
note 3
note 3
note 3
note 3
note 3
note 3
note 3
notes 3 and 4
Notes
1. Recommended data word for step 0 dB.
2. Result of 1.5 dB boost and 1.5 dB attenuation.
3. The last eight treble control data words select treble output.
4. The last treble control and bass control data words (00000) enable the external equalizer connection.
1995 Dec 19
18

Table 7
TEA6320
Loudness setting
Table 9
CHARACTERISTIC
DATA LOFF
With loudness
Linear
Table 8
DATA
FUNCTION
Selected input
DATA
FUNCTION
SC2
SC1
SC0
Stereo inputs IAL and IAR
Stereo inputs IBL and IBR
Stereo inputs ICL and ICR
Stereo inputs IDL and IDR
Mono input IMO
X(1)
X(1)
Note
1. X = dont care bits (logic 1 during testing).
1995 Dec 19
Mute mode
19
GMU
ZCM
Direct mute off
Mute off delayed until the next zero

crossing
Direct mute
Mute delayed until the next zero

crossing
TEA6320
MED423
18
Gbass
(dB)
12
12
18
10
10 2
10 3
f (Hz)
10 4
Fig.3 Bass control.
MED424
15
Gtreble
(dB)
10
10
15
10 2
10 3
10 4
Fig.4 Treble control.
1995 Dec 19
20
f (Hz)
10 5
TEA6320
MED425
handbook,20
full pagewidth
Gv
(dB)
10
10
20
30
40
10
10 2
10 3
10 4
f (Hz)
10 5
Fig.5 Volume control with loudness (including low roll-off frequency).
MED426
100
S/N
(dB)
(1)
90
(2)
(3)
80
70
60
50
10 4
10 3
10 2
10 1
(1) Vi = 2.0 V.
(2) Vi = 0.5 V.
(3) Vi = 0.2 V.
Fig.6 Signal-to-noise ratio; noise weighted: CCIR468-2, quasi peak.
1995 Dec 19
21
Po (W)
10
TEA6320
MED427
110
S/N
(dB)
(1)
100
(2)
90
(3)
80
70
60
10 4
10 3
10 2
10 1
Po (W)
10
(1) Unweighted RMS.

(2) CCIR468-2 RMS.
(3) CCIR468-2 quasi peak.
Fig.7 Signal-to-noise ratio; Vi = 2 V; Pmax = 6 W.
MED428
200
noise
(V)
150
100
(1)
50
(2)
0
70
50
30
10
Stereo/mono inputs.
(1) Loudness on.
(2) Loudness off.
Fig.8 Noise output voltage; CCIR468-2, quasi peak.
1995 Dec 19
22
10
gain (dB)
30
TEA6320
MED429
60
(dB)
80
100
120
140
20
50
10 2
200
500
10 3
Fig.9 Muting.
1995 Dec 19
23
2 x 10 3
5 x 10 3
10 4
2 x 10 4
f (Hz)
TEA6320
mute pin 12
hardware mute switch

ICH = 150 A
TEA6320
U
(V)
ID = 0.6 A
Cm = 10 nF
I
(A)
0.5 ms delay until

mute passive
VCC
8.5
delay switch (1)

2.2
level
150
mute switch 1.45

level
MED430
100 ms
zero crossing
mute start
end of delay
t (ms)
hard mute
on
hard mute
off
(1) Typically 2.2 V; referenced to 3 VBE.
Fig.10 Mute function diagram.
1995 Dec 19
24
TEA6320
If the 20 dB gain is not required for the maximum volume

position, it will be an advantage to use the maximum boost
gain and then increased attenuation in the last section,
Volume II.
Therefore the loudness will be at the correct place and a

lower noise and offset voltage will be achieved.
POWER STAGE
handbook, halfpage
TEA6320
G = 20 dB
VI(min) = 200 mV
Vo = 2 V for P(max)
P(max) = 100 W at 4
MBE899
a.
POWER STAGE
handbook, halfpage
TEA6320
G = 26 dB
VI(min) = 200 mV
Vo = 1 V for P(max)
P(max) = 100 W at 4
MED431
b.
a. Gain volume I = 20 dB (Gv(max)); gain volume II = 0 dB; fader and balance range = 55 dB.
b. Gain volume I = 20 dB (Gv(max)); gain volume II = 6 dB global setting; fader and balance range now 49 dB, previously 55 dB.
Fig.11 Level diagram.
1995 Dec 19
25
TEA6320
VP
+8.5 V to
oscilloscope
VCC
8.5 V
470 F
4.7 k
inputs
31
16
15
13
11
14
17
18
20
22
3
4
TEA6320
outputs to
oscilloscope
29
30
9 220 nF
19
21
47
F
9 600
4 4.7 F
100
F
4 10 k
MED432
Fig.12 Turn-on/off power supply circuit diagram.
MED433
10
(V)
8
(1)
6
4
(2)
0
0
(1) VCC.
(2) VO.
Fig.13 Turn-on/off behaviour.
1995 Dec 19
26
t (s)
TEA6320
220 nF
33 nF
5.6 nF
10 nF
100 F
21 10
VCC = 8.5 V
12
31
0.1 F
10 k
32
SCL
SDA
2
TEA6320
1000 F
19
VP
47 F
0.2 V (RMS)
600
220 nF
output right
output left
front and rear
input A to D left and right

and input mono
23
25
26
27
4.7 F
VO
28
MED434
220 nF
5.6 nF
33 nF
Fig.14 Test circuit for power supply ripple rejection (RR).
220 nF
33 nF
5.6 nF
10 nF
100 F
21 10
VCC = 8.5 V
12
31
0.1 F
470 F
32
SCL
SDA
2
TEA6320
Vp
19
47 F
input A to D right and left
220 nF
Vi
600
220 nF
output left
output right
front and rear
input A to D left and right

and input mono
23
25
220 nF
26
27
33 nF
28
5.6 nF
MED435
Fig.15 Test circuit for channel separation (cs).

1995 Dec 19
27
4.7 F
VO
TEA6320
Selection of input signals by using the zero crossing

mute mode
follows the input A signal, until the next zero crossing

occurs and then activates mute.
A selection from input A (IAL) to input B (IBL) left sources

produces a modulation click depending on the difference
of the signal values at the time of switching.
After a fixed delay time at t2, the microcontroller sends the

bits for input switching and mute inactive.
The output signal remains muted until the next signal zero
crossing of input B (IBL) occurs, and then follows that
signal.
At t1 the maximum possible difference between signals is

7 V(p-p) (see Fig. 16) and gives a large click. Using the
cross detector no modulation click is audible.
The delay time t2 t1 is e.g. 40 ms. Therefore the capacity

Cm = 3.3 nF. The zero cross function is working at the
lowest frequency of 40 Hz determined by the Cm capacitor.
For example: The selection is enabled at t1, the

microcontroller sets the zero cross bit (ZCM = 1) and then
the mute bit (GMU = 1) via the I2C-bus. The output signal
MED436
V
4
(1)
3
2
1
0
1
(2)
t1
t2
(3)
2
3
4
(1) Input A (IAL).

(2) Output.
(3) Input B (IBL).
Fig.16 Zero cross function; only one channel shown.
1995 Dec 19
28
TEA6320
Loudness filter calculation example

Figure 17 shows the basic loudness circuit with an
external low-pass filter application. R1 allows an
attenuation range of 21 dB while the boost is determined
by the gain stage V2. Both result in a loudness control
range of +20 to 12 dB.
handbook, halfpage
CKVL
Defining fref as the frequency where the level does not

change while switching loudness on/off. The external
resistor R3 for fref can be calculated as:
0 dB
8
V1
R1
33 k
Gv
------20
C1
10
R3 = R1 -------------------- . With Gv = 21 dB and R1 = 33 k,
G
V2
R2
R3
------20
MED437
1 10
R3 = 3.2 k is generated.
For the low-pass filter characteristic the value of the
external capacitor C1 can be determined by setting a
specific boost for a defined frequency and referring the
gain to Gv at fref as indicated above.
Fig.17 Basic loudness circuit.
Gv
------20
( R1 + R3 ) 10 R3
1
--------------------- = ------------------------------------------------------------Gv
j ( C1 )
------20
1 10
For example: 3 dB boost at f = 1 kHz
Gv = Gv(ref) + 3 dB = 18 dB; f = 1 kHz and C1 = 100 nF.
If a loudness characteristic with additional high frequency
boost is desired, an additional high-pass section has to be
included in the external filter circuit as indicated in the
block diagram. A filter configuration that provides
AC coupling avoids offset voltage problems.
1995 Dec 19
29
TEA6320
INTERNAL PIN CONFIGURATIONS

Values shown in Figs 18 to 30 are typical DC values;
VCC = 8.5 V.
3
4.25 V
+
1
5V
1.8 k
80
MBE900
MBE901
Fig.18 Pin 1: SDA (I2C-bus data).
Fig.19 Pins 3, 4, 29, 30: output signals.
5
+
4.25 V
6
4.25 V
+
80
2.4 k
MBE902
MBE903
Fig.20 Pins 5 and 28: treble control capacitors.
1995 Dec 19
Fig.21 Pins 6 and 27: bass control capacitor outputs.
30
TEA6320
7
4.25 V
4.25 V
+
4.16 k
9.4 k
150 k
4.25 V
4.25 V
MED438
MBE904
Fig.22 Pins 7 and 26: bass control capacitor inputs.
Fig.23 Pins 8 and 25: input volume 1, control part.
+
4.25 V
+
10
4.25 V
80
1.12 k
MBE905
MBE906
Fig.24 Pins 9 and 24: input loudness, control part.
1995 Dec 19
Fig.25 Pins 10 and 23: output source selector.
31
TEA6320
12
11
4.25 V
1.3 k
8.5 V
constant
2.2 V
maximum
200A
35 k
0.6 A
constant
4.25 V
4.5 k
MBE907
MBE908
Fig.26 Pins 11, 13 to 18, 20, 22: inputs.
Fig.27 Pin 12: mute control.
19
4.7 k
8.4 V
300
+
3.4 k
5 k
4.25 V
21
3.4 k
MHA063
Fig.28 Pin 19: filtering for supply; pin 21: reference voltage.
31
32
apply +8.5 V to this pin
5V
MED440
MBE909
Fig.30 Pin 32: SCL (I2C-bus clock).
Fig.29 Pin 31: supply voltage.
1995 Dec 19
1.8 k
32
TEA6320
PACKAGE OUTLINES
SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
SOT232-1
ME
seating plane
A2 A
A1
c
e
(e 1)
w M
b1
MH
b
17
32
pin 1 index
E
16
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
min.
A2
max.
b1
D (1)
E (1)
e1
ME
MH
Z (1)
max.
mm
4.7
0.51
3.8
1.3
0.8
0.53
0.40
0.32
0.23
29.4
28.5
9.1
8.7
1.778
10.16
3.2
2.8
10.7
10.2
12.2
10.5
0.18
1.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT232-1
1995 Dec 19
EUROPEAN
PROJECTION
33
TEA6320
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
A
X
c
y
HE
v M A
Z
17
32
Q
A2
(A 3)
A1
pin 1 index
Lp
L
16
detail X
w M
bp
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (1)
HE
Lp
Z (1)
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.27
0.18
20.7
20.3
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.2
1.0
0.25
0.25
0.1
0.95
0.55
inches
0.10
0.012 0.096
0.004 0.086
0.01
0.02
0.01
0.011
0.007
0.81
0.80
0.30
0.29
0.050
0.419
0.394
0.055
0.043
0.016
0.047
0.039
0.01
0.01
0.004
0.037
0.022
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-01-25
97-05-22
SOT287-1
1995 Dec 19
EUROPEAN
PROJECTION
34
TEA6320
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 C.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate

the binding agent. Preheating duration: 45 minutes at
45 C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in
our IC Package Databook (order code 9398 652 90011).
Wave soldering techniques can be used for all SO

packages if the following conditions are observed:
A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
SDIP
SOLDERING BY DIPPING OR BY WAVE
The longitudinal axis of the package footprint must be

parallel to the solder flow.
The maximum permissible temperature of the solder is

260 C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The package footprint must incorporate solder thieves at

the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 C within
6 seconds. Typical dwell time is 4 seconds at 250 C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the

lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1995 Dec 19
35
TEA6320
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1995 Dec 19
36
TEA6320
NOTES
1995 Dec 19
37
TEA6320
NOTES
1995 Dec 19
38
TEA6320
NOTES
1995 Dec 19
39
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SCDS47
Philips Electronics N.V. 1995
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Printed in The Netherlands

513061/1100/02/pp40
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Date of release: 1995 Dec 19

9397 750 00533

Sound Fader Control Circuit

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INTEGRATED CIRCUITS

Sound fader control circuit

Bass and treble control

maximum output voltage level

VCC = 8.5 V; THD 0.1%

step resolution (volume)

step resolution (bass, treble)

signal-plus-noise to noise ratio

Vr(rms) < 200 mV; f = 100 Hz;

plastic shrink dual in-line package; 32 leads (400 mil)

plastic small outline package; 32 leads; body width 7.5 mm

Sound fader control circuit

Fig.1 Block diagram.

handbook, full pagewidth

Sound fader control circuit

serial data input/output

output left rear

output left front

treble control capacitor left channel or

bass control capacitor left channel or

bass control capacitor, left channel

input volume I, left control part

input loudness, left control part

output source selector, left channel

input D left source

input C left source

input mono source

input B left source

input A left source

input A right source

input B right source

electronic filtering for supply

input C right source

reference voltage (0.5VCC)

input D right source

output source selector right channel

input loudness right channel

input volume I, right control part

bass control capacitor right channel

bass control capacitor right channel or

treble control capacitor right channel

output right front

output right rear

serial clock input

Fig.2 Pin configuration.

Sound fader control circuit

The last section of the circuit is the volume II block. The

The volume control function is split into two sections:

1. Zero crossing mode mute via I2C-bus using

The control range of volume I is between +20 dB and

2. Fast mute via MUTE pin (see Fig.10).

The volume I control block operates in combination with

To avoid a large delay of mute switching when very low

The volume I control block is followed by the bass control

The mute function can also be controlled externally. If the

Both loudness and bass control result in a maximum bass

For the turn on/off behaviour the following explanation is

For use where is no mute in the application before turn off,

The bass and treble control functions can be switched off

Sound fader control circuit