Infineon TLE9832 DS v01 01 en

TLE9832
Microcontroller with LIN and Power Switches for Automotive Applications
Data Sheet
Rev. 1.1, 2012-03-08
Automotive Power
Edition 2012-03-08
Published by
Infineon Technologies AG
81726 Munich, Germany
2012 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TLE9832
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
1.1
1.2
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Device Types / Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
2.1
2.2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
3.1
3.1.1
3.1.2
3.1.3
3.2
3.2.1
3.2.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulator 5.0V (VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulator 1.5V (VDDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Voltage Regulator 5.0V (VDDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Unit - Power Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Unit - Digital Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC800 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer 1 (WDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplication/Division Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 and Timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Core Module (incl. ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Digital Converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Voltage Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
19
22
23
24
25
25
26
26
28
29
29
31
32
38
38
41
42
43
44
46
47
47
49
51
52
53
54
55
56
57
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electric Drive Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection of N.C. Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection of ADCGND Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection of Exposed Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulators-Blocking Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
58
59
59
59
59
59
60
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Data Sheet
Rev. 1.1, 2012-03-08
TLE9832
Table of Contents
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.2
5.2.1
5.2.2
5.2.3
5.3
5.3.1
5.3.2
5.4
5.5
5.5.1
5.5.2
5.6
5.6.1
5.7
5.8
5.8.1
5.8.2
5.8.3
5.8.4
5.9
5.9.1
5.9.1.1
5.9.1.2
5.9.2
5.10
5.11
5.11.1
5.11.2
5.12
5.12.1
5.12.2
General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMU I/O Supply Parameters VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMU Core Supply Parameters VDDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDDEXT Voltage Regulator 5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillators and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Parameters XTAL1, XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Digital Converter 8-Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Unit (VBAT_SENSE - Supply Voltage Attenuator) . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Functions Monitoring Input Voltage Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Sensor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC - 10-Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-Voltage Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Data Sheet
61
61
62
63
63
64
65
65
66
67
68
68
69
70
71
71
71
74
74
78
79
79
79
80
81
82
82
82
82
83
85
86
86
86
89
89
89
Rev. 1.1, 2012-03-08
TLE9832
Summary of Features
Summary of Features
High performance XC800 core
compatible to standard 8051 core
up to 40 MHz clock frequency
two clocks per machine cycle architecture
two data pointers
On-chip memory
32 kByte + 4 kByte Flash for program code and data (4 kByte EEPROM emulation built-in)
512 Byte One Time Programmable Memory (OTP)
512 Byte 100 Time Programmable Memory (100TP)
256 Byte RAM, 3 kByte XRAM
BootROM for startup firmware and Flash routines
Core logic supply at 1.5 V
On-chip OSC and PLL for clock generation
Loss of clock detection with fail safe mode for power switches
Watchdog timer (WDT) with programmable window feature for refresh operation and warning prior to overflow
General-purpose I/O Port (GPIO) with wake-up capability
Multiplication/division unit (MDU) for arithmetic calculation
Software libraries to support floating point and MDU calculations
Five 16-Bit timers - Timer 0, Timer 1, Timer 2, Timer 21 and Timer 3
Capture/compare unit for PWM signal generation (CCU6) with Timer 12 and Timer 13
Full duplex serial interface (UART) with LIN support
Synchronous serial channel (SSC)
On-chip debug support via 2-wire Device Access Port (DAP)
LIN Bootstrap loader (LIN BSL)
LIN transceiver compliant to LIN 1.3, LIN 2.0 and LIN 2.1
2 x Low Side Switches with clamping capability incl. PWM functionality, e.g. as relay driver
1x High Side Switch with cyclic sense option and PWM functionality, e.g. for LED or powering of switches
5 x High Voltage Monitor Input pins for wake-up and with cyclic sense and analog measurement option
Measurement unit with 10 channels, 8-Bit A/D Converter (ADC2) and data post processing
8 channels, 10-Bit A/D Converter (including battery voltage and supply voltage measurement) (ADC1)
Single power supply from 3.0 V to 27 V
Low-dropout voltage regulators (LDO)
Dedicated 5 V voltage regulator for external loads (e.g. hall sensor)
Programmable window watchdog (WDT1) with independent on-chip clock source
Power saving modes
MCU slow-down mode
Stop Mode
Sleep Mode
Cyclic wake-up and cyclic sense during Stop Mode and Sleep Mode
Power-on and undervoltage/brownout reset generator
Overtemperature protection
Overcurrent protection with shutdown
Supported by a full range of development tools including C compilers, macro assembler packages, emulators,
evaluation boards, HLL debugger, programming tools, software packages
Temperature Range TJ: -40 C up to 150 C
Packages TLE9832QV: VQFN-48-22 and TLE9832QX: VQFN-48-29
Green package (RoHS compliant)
Data Sheet
Rev. 1.1, 2012-03-08
TLE9832
Summary of Features
1.1
Device Types / Ordering Information
The TLE983x product family features devices with different peripheral modules, configurations and program
memory sizes to offer cost-effective solutions for different application requirements. Table 1 describes the
TLE9832 device configuration.
Table 1
Device Configuration
Device Name
Max Clock
Frequency
High Side
Switches
High Voltage Flash Size

Monitor
Inputs
Bidirectional
Parallel Port
I/Os
Operational
Amplifier
TLE9832QV
40 MHz
36 kByte
11
no
TLE9832QX
40 MHz
36 kByte
11
no
Data Sheet
Rev. 1.1, 2012-03-08
TLE9832
Summary of Features
1.2
Abbreviations
The following acronyms and terms are used within this document. List see in Table 2.
Table 2
Acronyms
Acronyms
Name
ALU
Arithmetic Logic Unit
CCU6
Capture Compare Unit 6
CGU
Clock Generation Unit
CMU
Cyclic Management Unit
DAP
Device Access Port
DPP
Data Post Processing
ECC
Error Correction Code
EEPROM
Electrically Erasable Programmable Read Only Memory
GPIO
General Purpose Input Output
FSR
Full Scale Range
ICU
Interrupt Control Unit
IRAM
Internal Random Access Memory - Internal Data Memory
LDO
Low DropOut voltage regulator
LIN
Local Interconnect Network
LSB
Least Significant Bit
MCU
Micro Controller Unit
MDU
Multiplication Division Unit
MMC
Monitor Mode Control
MSB
Most Significant Bit
NMI
Non Maskable Interrupt
OCDS
On Chip Debug Support
OTP
One Time Programmable
OSC
Oscillator
PC
Program Counter
PCU
Power Control Unit
PD
Pull Down
PGU
Power supply Generation Unit
PLL
Phase Locked Loop
PMU
Power Management Unit
PSW
Program Status Word
PU
Pull Up
PWM
Pulse Width Modulation
RAM
Random Access Memory
RCU
Reset Control Unit
RMU
Reset Management Unit
Data Sheet
Rev. 1.1, 2012-03-08
TLE9832
Summary of Features
Table 2
Acronyms
Acronyms
Name
ROM
Read Only Memory
SCK
SSC Clock
SFR
Special Function Register
SOW
Short Open Window (for WDT1)
SPI
Serial Peripheral Interface
SSC
Synchronous Serial Channel
SSU
System Status Unit
TMS
Test Mode Select
UART
Universal Asynchronous Receiver Transmitter
UDIG
Universal Digital Controller for ADC1
VBG
Voltage reference Band Gap
WDT
Watchdog timer
WMU
Wake-up Management Unit
XRAM
On-Chip eXternal Data Memory
XSFR
On-Chip eXternal Special Function Register
Data Sheet
Rev. 1.1, 2012-03-08
TLE9832
25 P0.5/MRST_0/EXI NT0_0/T21EX_2/T1/CCPOS2_1/COUT60_0
26 P1.4/EXINT2_1/T21EX1/CCPOS1_2/CLKOUT_1/COUT62_0
27 XTAL1
29 N.C.
30 GND
31 P2.5/AN5/T1_2
32 P2.4/AN4/T0_2
33 ADCGND
Pin Configuration
34 VAREF
2.1
36 P2.3/AN3/CCPOS1_0/EXINT0_2/CTRAP_1/CC60_1
General Device Information
35 P2.7/AN7/CCPOS2_0/EXI NT2_0/T13HR_1/CC62_1
28 XTAL2
24 P0.4/MTSR_0/CC60_0/T21_2/EXINT 2_2/CCPOS1_1/CLKOUT _0
P2. 1/AN1/CCPOS0_0/EXINT 1_0/T12HR_1/CC61_1 37
23 P0. 3/SCK_0/EXINT1_2/T0/ CCPOS0_1/EXF21_2
GND 38
P1.3/EXINT1_1/CC62_0/ CCPOS0_2/EXF21_1 39
22 P0. 2/CTRAP_0/ T21EX_0/EXINT 1_3/TXD_1/EXF 2_0
N.C. 40
21 RESET
N.C. 41
20 P0. 0/T12HR_0/T2_0/DAP0/EXINT 2_3/EXF 21_0/RXDO
VDDC 42
19 GND
GND 43
18 TMS/DAP1
VDDP 44
17 P0. 1/T13HR_0/RXD_1/T2EX_1/T21_0/EXINT0_3
VDDEXT 45
16 P1. 2/EXINT 0_1/T21_1/MRST_1/CCPOS2_2/COUT63_0
N.C. 46
15 P1. 1/T1_1/MTSR_1/ T21EX_3/COUT61_0
VS 47
14 P1.0/T0_1/CC61_0/ SCK_1/EXF 21_3
Figure 1
Data Sheet
LS2 12
LS1 11
N.C. 10
MON5 9
MON4 8
MON3 7
MON2 6
MON1 5
N.C. 4
HS1 3
LIN 1
13 LSGND
LINGND 2
VBATSENSE 48
TLE9832 pin configuration, VQFN-48-22 and VQFN-48-29 package (top view)
Rev. 1.1, 2012-03-08
TLE9832
2.2
Pin Definitions and Functions
After reset, all pins are configured as input (except supply and LIN pins) with one of the following settings:
Pull-up device enabled only (PU)

Pull-down device enabled only (PD)
Input with both pull-up and pull-down devices disabled (I)
Output with output stage deactivated = high impedance state (Hi-Z)
The functions and default states of the TLE9832 external pins are provided in the following table.
Type: indicates the pin type.
I/O: Input or output

I: Input only
O: Output only
P: Power supply
Table 3
Symbol
Pin Definitions and Functions

Pin Number Type
Reset
State
P0
Function
Port 0
Port 0 is an 6-Bit bidirectional general purpose I/O port.
Alternate functions can be assigned as follows:
DAP, CCU6, Timer 0, Timer 1, Timer 2, Timer 21, UART, SSC,
external interrupt input and clock output.
P0.0
20
I/O
I/PU
T12HR_0
T2_0
DAP0
EXINT2_3
EXF21_0
RXDO
CCU6 Timer 12 hardware run input

Timer 2 input
Debug Access Port 0
External interrupt input 0
Timer 21 external flag output
UART transmit data output (synchronous mode)
P0.1
17
I/O
I/PU
T13HR_0
RXD_1
T2EX_1
T21_0
EXINT0_3

UART receive input
Timer 2 external trigger input
Timer 21 input
P0.2
22
I/O
I/PU
CTRAP_0
T21EX_0
EXINT1_3
TXD_1
EXF2_0
CCU6 trap input

UART transmit output
P0.3
23
I/O
I/PU
SCK_0
EXINT1_2
T0
CCPOS0_1
EXF21_2
SSC clock input (for slave) / output (for master)

Timer 0 input
CCU6 hall input 0
P0.4
24
I/O
I/PU
MTSR_0
CC60_0
T21_2
EXINT2_2
CCPOS1_1
CLKOUT_0
SSC master transmit output / slave receive input

CCU6 capture/compare channel 0 input/output
Timer 21 input
CCU6 hall input 1
Clock output
Data Sheet
10
Rev. 1.1, 2012-03-08
TLE9832
Table 3
Pin Definitions and Functions (contd)
Symbol
Pin Number Type
Reset
State
Function
P0.5
25
I/PU
MRST_0
EXINT0_0
T21EX_2
T1
CCPOS2_1
COUT60_0
I/O
P1
SSC master receive input / slave transmit output

Timer 1 input
CCU6 hall input 2
CCU6 capture/compare channel 0 output
Port 1
Port 1 is an 5-Bit bidirectional general purpose I/O port.
CCU6, Timer 0, Timer 1 Timer 21, SSC, external interrupt input
and clock output.
P1.0
14
I/O
T0_1
CC61_0
SCK_1
EXF21_3
Timer 0 input
SSC clock input (for slave) / output (for master)
P1.1
15
I/O
T1_1
MTSR_1
T21EX_3
COUT61_0
Timer 1 input
SSC master transmit output/slave receive input
P1.2
16
I/O
EXINT0_1
T21_1
MRST_1
CCPOS2_2
COUT63_0

Timer 21 input
SSC master receive input/slave transmit output
CCU6 hall input 2
P1.3
39
I/O
EXINT1_1
CC62_0
CCPOS0_2
EXF21_1

CCU6 hall input 0
P1.4
26
I/O
EXINT2_1
T21EX_1
CCPOS1_2
CLKOUT_1
COUT62_0

CCU6 hall input 1
Clock output
P2
P2.1
Data Sheet
Port 2
Port 2 is an 5-Bit general purpose input-only port.
CCU6, Timer 0, Timer 1, Timer 21 and external interrupt input
It is also used as analog inputs for the 10-Bit ADC (ADC1).
37
AN1
CCPOS0_0
EXINT1_0
T12HR_1
CC61_1
11
ADC1 analog input channel 1

CCU6 hall input 0
CCU6 capture/compare channel 1 input
Rev. 1.1, 2012-03-08
TLE9832
Table 3
Symbol
Pin Number Type
Reset
State
Function
P2.3
36
AN3
CCPOS1_0
EXINT0_2
CTRAP_1
CC60_1

CCU6 hall input 1
CCU6 trap input
P2.4
32
AN4
T0_2

Timer 0 input
P2.5
31
AN5
T1_2

Timer 1 input
P2.7
35
AN7
CCPOS2_0
EXINT2_0
T13HR_1
CC62_1

CCU6 hall input 2
CCU6 timer 13 hardware run input
VS
47
Battery supply input
VDDP
44
I/O port supply (5.0 V). Do not connect external loads. For
buffer and bypass capacitors.
VDDC
42
Core supply (1.5 V during Active Mode,

0.9 V during Stop Mode). Do not connect external loads. For
buffer/bypass capacitor.
VDDEXT
45
External voltage supply output (5.0 V, 20 mA)
LSGND
13
Low Side ground LS1, LS2
GND
30, 43, 19,

38
Core supply ground; analog supply ground
ADCGND
33
Analog supply ground for ADC1
LINGND
LIN ground
MON1
High Voltage Monitor Input 1
MON2
MON3
MON4
MON5
Power Supply
Monitor Inputs
High Side Switch / Low Side Switch Outputs

LS1
11
Hi-Z
Low Side Switch output 1
LS2
12
Hi-Z
Low Side Switch output 2
HS1
Hi-Z
High Side Switch output 1
I/O
PU
LIN bus interface input/output
LIN Interface
LIN
Others
Data Sheet
12
Rev. 1.1, 2012-03-08
TLE9832
Table 3
Symbol
Pin Number Type
Reset
State
Function
VAREF
34
I/O
5V ADC1 reference voltage
XTAL1
27
External oscillator input
XTAL2
28
Hi-Z
External oscillator output
TMS
18
I/PD
TMS
DAP1
RESET
21
I/O
I/O/PU
Reset input, not available during Sleep Mode
VBAT_SENSE 48
Battery supply voltage sense input
N.C.
10, 29, 40,

41, 46
Not connected - can be connected to GND
N.C.
Not connected - leave pin open
Data Sheet
13
test mode select input

Debug Access Port 1
Rev. 1.1, 2012-03-08
TLE9832
Functional Description
This highly integrated circuit contains analog and digital functional blocks. For system and interface control an
embedded 8-Bit state-of-the-art microcontroller, compatible to the standard 8051 core with On-Chip Debug
Support (OCDS), is available. For internal and external power supply purposes, on-chip low drop-out regulators
are existent. An internal oscillator provides a cost effective and suitable clock in particular for LIN slave nodes. As
communication interface, a LIN transceiver and several High Voltage Monitor Inputs with adjustable threshold and
filters are available. Furthermore one High Side Switch (e.g. for driving LEDs or cyclic powering of switches), two
Low Side Switches (e.g. for relays) and several general purpose input/outputs (GPIO) with pulse-width modulation
(PWM) capabilities are available.
The Micro Controller Unit (MCU) supervision and system protection including reset feature is controlled by a
programmable window watchdog. A cyclic wake-up circuit, supply voltage supervision and integrated temperature
sensors are available on-chip.
All relevant modules offer power saving modes in order to support terminal 30 connected automotive applications.
A wake-up from the power saving mode is possible via a LIN bus message, via the monitoring inputs, via the GPIO
ports or repetitive with a programmable time period (cyclic wake-up).
The integrated circuit is available in a VQFN-48-22 and VQFN-48-29 package with 0.5 mm pitch and is designed
to withstand the severe conditions of automotive applications.
Data Sheet
14
Rev. 1.1, 2012-03-08
Figure 2
Data Sheet
XTAL2
XTAL1
P2.1, P2.3 P2.5, P2.7

(AN1, AN3 AN5, AN7)
ADCGND
VAREF
P1.0 P1.4
P0.1 P0.5
DAP
TMS
P0.0
8 Bit - MCU
6
7
0
2
Mux
15
3kB XRAM
256 Byte-RAM
MCU
PLL
8-ch.
10-bit ADC
LP_CLK
20MHz
Memories
Flash-36kB
BootROM
MAP
RAM
WMU
VREF5V
RC-Oszillator
5MHz
VMON 1...5
VS_SENSE
VBAT_SENSE
GPIO
Ports
5V
LP_CLK2
100kHz
Power Down Supply
VS
WDT
Timer
0/1
XSFR-BUS
UART
Timer 2/21
CCU6 (Capture
Compare Unit)
SSC (Synchr. Serial

Channel)
Debug (DAP)
Port Control
IRQ
XC800
EWARP Core
VS_SENSE
VBAT_SENSE
VDDP_SENSE
VDDC_SENSE
not used
LS1_SENSE
LS2_SENSE
T_SENSE
TS_LS_SENSE
REF_SENSE
BG
WDT1
Timer 3
0
1
2
3
5
8-Bit ADC
6
7
8
9
4
TSENSE
Measurement Unit
CMU
DPP
CTRL
Trigger
CLK_GEN
AP_SUB_CTRL
PMU/
PCU
Power-Control
IR
RCU
SCU_PM
CYCMU
CGU
PREWARN_SUP_NMI
XINT
PMU
VDDP
PMU/
PCU
MISC
MDU (Multiply /
Division Unit)
BRG
MISC
Control
LIN
Control
SCU
RMU
VPRE
VDDEXT
VDDEXT
VDDP
Attenuator
Attenuator
Wake
Wake
LIN Transceiver
Low Side 2
Low Side 1
High Side 1
PWM-Unit
VS_SENSE
VBAT_SENSE
VDDP_SENSE
VDDC_SENSE
VMON 1..5
MON
PMU-XSFR
VDDC
VDDC
LINGND
LIN
LS2
LSGND
LS1
HS 1
VBAT_SENSE
MON5
MON1
.
.
TLE9832
Block Diagram
XSFR-BUS
SFR-BUS
Block Diagram
The TLE9832 has several operational modes mainly to support low power consumption requirements. The low
power modes and state transitions are depicted in Figure 3 below.
Rev. 1.1, 2012-03-08
TLE9832
Power-up
VS > 3V
Reset
WDT1 reset
(error_wdt++)
Transition by software Transition by external event
VDDC stable &

error_supp < 5
VDDC fail
(error_supp++)
Safety Fallback
Safety fallback
error_supp = 5
Cyclic wake
LIN wake or
MON wake or
GPIO wake
Active Mode
Cyclic wake
LIN wake or
MON wake
STOP command
Stop Mode
Transition by internal event
SLEEP command
Safety fallback
error_wdt = 5
Sleep Mode
Cyclic-sense
Cyclic-sense
PCU_state_diagram_simple_Cus.vsd
Figure 3
Power Control State Diagram
Reset Mode
The Reset Mode is a transition mode e.g. during power-up of the device after a power-on reset. In this mode the
on-chip power supplies are enabled and all other modules are initialized. Once the core supply VDDC is stable,
the Active Mode is entered. In case the watchdog timer WDT1 fails for more than four times, a fail-safe transition
to the Sleep Mode is done.
Active Mode
In Active Mode all modules are activated and the TLE9832 is fully operational.
Stop Mode
The Stop Mode is one out of two low power modes. The transition to the low power modes is done by setting the
respective Bits in the mode control register. In Stop Mode the embedded microcontroller is still powered allowing
faster wake-up reaction times. A wake-up from this mode is possible by LIN bus activity, the High Voltage Monitor
Input pins or the respective 5V GPIOs.
Sleep Mode
The Sleep Mode is the second low-power mode. The transition to the low-power modes is done by setting the
respective Bits in the MCU mode control register. In Sleep Mode the embedded microcontroller power supply is
deactivated allowing the lowest system power consumption, but the wake-up time is longer compared to the Stop
Mode. A wake-up from this mode is possible by LIN bus activity or the High Voltage Monitor Input pins. A wakeup from Sleep Mode behaves similar to a power-on reset.
Data Sheet
16
Rev. 1.1, 2012-03-08
TLE9832
Cyclic Wake-up Mode
The cyclic wake-up mode is a special operating mode of the Sleep Mode and the Stop Mode. The transition to the
cyclic wake-up mode is done by first setting the respective Bits in the mode control register followed by the SLEEP
or STOP command. Additional to the cyclic wake-up behavior (wake-up after a programmable time period), the
wake-up sources of the normal Stop Mode and Sleep Mode are available.
Cyclic Sense Mode
The cyclic sense mode is a special operating mode of the Sleep Mode and the Stop Mode. The transition to the
cyclic sense mode is done by first setting the respective Bits in the mode control register followed by the STOP or
SLEEP command. In cyclic sense mode the High Side Switch can be switched on periodically for biasing some
switches for example. The wake-up condition is configurable, when the sense result of defined monitor inputs at
a window of interest changed compared to the previous wake-up period or reached a defined state respectively.
In this case the Active Mode is entered immediately. For cyclic sense in Stop Mode VDDEXT can be switched on
periodically. Furthermore cyclic sense allows to sense dedicated GPIO port states and transitions when in Stop
Mode.
The following table shows the possible power mode configurations of each major module or function respectively.
Table 4
Power mode configurations
Module/function
Active Mode Stop Mode
Sleep Mode
Comment
VDD1V5PD
ON
ON
ON
Power Down Supply
VPRE, VDDP, VDDC
ON
ON (no dynamic
load)
OFF
VDDEXT
ON/OFF
ON (no dynamic
load)/OFF
cyclic ON/OFF
OFF
HS
ON/OFF
cyclic ON/OFF
cyclic ON/OFF
cyclic sense
LSx
ON/OFF
OFF
OFF
PWM GEN.
ON/OFF
OFF
OFF
LIN TRx
ON/OFF
wake-up only/
OFF
wake-up only/
OFF
MON1 - MON5 (wake-up)
n.a.
disabled/static/cyclic disabled/static/
cyclic
cyclic: combined with

HS=on
MON1 - MON5
(measurement)
ON/OFF
OFF
OFF
available on four
channels
VS sense
ON/OFF
brownout
detection
brownout detection
brownout
detection
brownout detection
done in PCU
VBAT_SENSE
ON/OFF
OFF
OFF
GPIO 5V (wake-up)
n.a.
disabled/static/cyclic OFF
GPIO 5V (active)
ON
ON
OFF
WDT1
ON
OFF
OFF
Data Sheet
17
Rev. 1.1, 2012-03-08
TLE9832
Table 4
Power mode configurations
Module/function
Active Mode Stop Mode
Sleep Mode
CYCLIC Modes
n.a.
cyclic wake-up/
cyclic sense/OFF
cyclic wake-up/
cyclic sense with HS,
cyclic sense/OFF VDDEXT; wake-up
from cyclic wake
needs MC for
entering Sleep Mode /
Stop Mode again
Measurement Unit
ON1)
OFF
OFF
2)
Comment
MCU
ON/slowdown/HALT
STOP
OFF
CLOCK GEN (MC)
ON
OFF
OFF
LP_CLK (20 MHz)
ON
OFF
OFF
WDT1
LP_CLK2 (100 kHz)
ON
ON
ON
for cyclic wake-up
1) Cannot not be switched off due to safety reasons

2) MC PLL clock disabled, MC supply reduced to 0.9 V
Wake-up Source Prioritization

All wake-up sources have the same priority. In order to handle the asynchronous nature of the wake-up sources,
the first wake-up signal will initiate the wake-up sequence. Nevertheless all wake-up sources are latched in order
to provide all wake-up events to the application software. The software can clear the wake-up source flags. It is
ensured, that no wake-up event is lost.
As default wake-up sources, the LIN and MON inputs are activated after power-on reset only. GPIO ports as wakeup sources are disabled by default after power-on reset. The application software can reconfigure the wake-up
sources according to the application needs.
Wake-up Levels and Transitions
The wake-up can be triggered by rising, falling or both signal edges for each monitor and GPIO input individually.
Data Sheet
18
Rev. 1.1, 2012-03-08
TLE9832
3.1
Power Management Unit (PMU)
The purpose of the power management unit is to ensure the fail safe behavior of embedded automotive systems.
Therefore the power management unit controls all system modes including the corresponding transitions. The
power management unit is responsible for generating all required voltage supplies for the embedded MCU (VDDC,
VDDP) and the external sensor supply (VDDEXT). Additionally, the PMU provides well defined sequences for the
system mode transitions and generates hierarchical reset priorities. The reset priorities control the reset behavior
of all system functionalities, especially the reset behavior of the embedded MCU, including the test hardware. All
these functions are controlled by finite state machines. The system master functionality of the PMU forces the
generation of an independent logic supply (Power Down Supply) and system clock (LP_CLK). Therefore the PMU
needs a module internal logic supply and system clock which works independently of the MCU clock.
The following state diagram shows the available modes of the device.
Vs > 3V
start-up
LIN-wake |
MON-wake |
cyclic _wake
VDDC =stable &

error_supp<5
error_sup=5
sleep
VDDC = fail
Sleep command (from MCU) |

WDT1_SEQ_FAIL = 1
active
LIN-wake |
MON-wake |
GPIO-wake |
cyclic _wake |
PMU_PIN = 1 |
SUP_TMOUT = 1
PMU_PIN = 1 |
PMU_SOFT = 1 |
(PMU_Ext_WDT = 1 &
WDT1_SEQ_FAIL= 0)
stop
command
(from MCU)
stop
PMU_System _Modes _Cus.vsd
Figure 4
Data Sheet
Power Management Unit System Modes
19
Rev. 1.1, 2012-03-08
TLE9832
VS
Power Down Supply
VDDP
Power Supply Generation
(PSG)
VDDC
CLK_20MHz
Pheripherals
HALL_SUPPLY
CLK_100KHz
I
N
T
E
R
N
A
L
PMU-XSFR
VDDEXT
PMU-CYCMU
B
U
S
PMU-PCU
PMU-CMU
PMU-WMU
PMU-RMU
MON 1...5
LIN
P0.0.P0.5
P1.0.P1.4
PMU-Control
Power Management Unit
Figure 5
Data Sheet
Power Management Unit Block Diagram
20
Rev. 1.1, 2012-03-08
TLE9832
Table 5
Description of PMU Submodules
Mod.
Name
Modules
Functions
Power Down
Supply
Independent Supply Voltage

Generation for PMU
This supply is only dedicated to the PMU to ensure a

independent operation of generated power supplies
(VDDP, VDDC).
LP_CLK
(= 20 MHz)
- Clock Source for all PMU

submodules
- Backup Clock Source for System
- Clock Source for WDT1
This ultra low power oscillator generates the clock for the
PMU.
This clock is also used as backup clock for the system in
case of PLL clock failure and as independent clock source
for WDT1
LP_CLK2
(= 100 kHz)
Clock Source for PMU
This ultra low power oscillator generates the clock for the
PMU mainly in Stop Mode and in the cyclic modes.
Peripherals
Peripheral blocks of PMU
This blocks includes all relevant peripherals to ensure a

stable and fail safe PMU startup and operation
Power Supply
Generation
Unit (PGU)
Voltage regulators for VDDP and

VDDC
This block includes the voltage regulators for the pad

supply (VDDP) and the core supply (VDDC) including all
diagnosis and safety features
VDDEXT (Hall Voltage regulator for VDDEXT to

Sensor
supply external modules (e.g. Hall
Supply)
Sensors)
This voltage regulator is a dedicated supply for external

modules and can also be used for cyclic sense operations
(e.g. with hall sensor)
PMU-XSFR
All PMU relevant Extended Special

Function Registers
This module contains all PMU relevant registers, which

are needed to control and monitor the PMU.
PMU-PCU
Power Control Unit of the PMU
This block is responsible for controlling all power related

actions within the PGU Module.
PMU-WMU
Wake-up Management Unit of the

PMU
This block is responsible for controlling all wake-up related

actions within the PMU Module.
PMU-CYCMU
Cyclic Management Unit of the PMU This block is responsible for controlling all actions within
cyclic mode.
PMU-CMU
Clock Management Unit of the PMU This block is responsible for controlling all clocking actions
within the PMU.
PMU-RMU
Reset Management Unit of the PMU This block is responsible for generating all system
required resets.
Data Sheet
21
Rev. 1.1, 2012-03-08
TLE9832
3.1.1
Voltage Regulator 5.0V (VDDP)
This module represents the 5 V voltage regulator, which serves as pad supply for the parallel port pins and other
5 V analog functions.
Features
5 V low-drop voltage regulator

Current limitation
Overcurrent monitoring and shutdown with MCU signalling (Interrupt)
Overvoltage monitoring with MCU signalling (Interrupt)
Undervoltage monitoring with MCU signalling (Interrupt)
Preregulator for VDDC regulator
GPIO supply
Pull-down current source at the output for Sleep Mode (100 A)
The output capacitor CVDDP is mandatory to ensure a proper regulator functionality.
VDDP Regulator
VDDP-5V
VS
CVS
C VDDP
5V LDO
Figure 6
Data Sheet
PMU_5V_OVERVOLT
PMU_5V_OVERCURR
PMU_5V_OVERLOAD
Supervision
Module Block Diagram of VDDP Voltage Regulator
22
Rev. 1.1, 2012-03-08
TLE9832
3.1.2
Voltage Regulator 1.5V (VDDC)
This module represents the 1.5 V voltage regulator, which serves as core supply for the 8-bit C and other chip
internal analog 1.5 V functions (e.g. 8 Bit ADC). To further reduce the current consumption of the 8-bit MCU during
Stop Mode the output voltage is optionally reduced to 0.9 V.
Features
1.5 V low-drop voltage regulator

Optional 0.9 V in Stop Mode
Current limitation
Overcurrent monitoring and shutdown with MCU signalling (interrupt)
Overvoltage monitoring with MCU signalling (interrupt)
Undervoltage monitoring with MCU signalling (interrupt)
Pull-down current source at the output for Sleep Mode (100 A)
The output capacitor CVDDC is mandatory to ensure a proper regulator functionality.
VDDC Regulator
VDDC-1.5V
VDDP-5V
CVDDP
CVDDC
1.5 / 0.9V
LDO
Figure 7
Data Sheet
PMU_1V5_OVERVOLT
PMU_1V5_OVERCURR
PMU_1V5_OVERLOAD
Supervision
Module Block Diagram of VDDC Voltage Regulator
23
Rev. 1.1, 2012-03-08
TLE9832
3.1.3
External Voltage Regulator 5.0V (VDDEXT)
The external voltage regulator provides 5 V output voltage in order to supply external circuitry like LEDs, hall
sensors or potentiometers.
Features
Switchable +5 V, 20 mA low-drop voltage regulator

Switch-on overcurrent blanking time in order to drive small capacitive loads
Short circuit robust
Overvoltage monitoring with MCU interrupt signalling
Undervoltage monitoring with MCU interrupt signalling
Selectable switch-on slew-rate 0.95 V/s max. @10 mA supply current, 10 nF capacitive load
Pull-down current source at the output for Sleep Mode and off mode (100 A)
Cyclic sense option together with GPIOs
VDDEXT Regulator
VDDEXT-5V
VS
C VS
CVDDEXT
VDDEXT
LDO
Figure 8
Data Sheet
VDDEXT_OVERVOLT
VDDEXT_OVERCURR
VDDEXT_OVERLOAD
Supervision
Module Block Diagram
24
Rev. 1.1, 2012-03-08
TLE9832
3.2
System Control Unit
3.2.1
System Control Unit - Power Modules
The System Control Unit of the power modules consists of the following sub-modules:
Reset Control Unit (RCU): generation of all required subsystem resets

Clock Generation Unit (CGU): providing all required clocks to the analog subsystem
Interrupt Control Unit (ICU): all system relevant interrupt flags and status flags
Power Control Unit (PCU): takes over control when device enters and exits Sleep Mode and Stop Mode
System Status Unit (SSU): controls mode changes due to system failures
External Watchdog (WDT1): independent system watchdog to monitor system activity
On signals to analog
peripherals; status
signals from analog
peripherals
XSFR-BPI
Reset_Type_0
Reset_Type_1
PCU
RCU
Reset_Type_2
Reset_Type_3
Reset_Type_4
I
N
T
E
R
N
A
L
fsys
mi_clk
CGU
clk_2mhz
all STS bits from

analog peripherals
ICU
PREWARN_SUP_NMI
XINT
B
U
S
SSU
WDT1
LP_CLK
System Control Unit-Power Modules
Figure 9
Data Sheet
Block Diagram of System Control Unit - Power Modules
25
Rev. 1.1, 2012-03-08
TLE9832
3.2.2
System Control Unit - Digital Part
The System Control Unit - Digital Part supports all central control tasks in the TLE9832. It consists of the following
submodules:
Clock System and Control

Reset Control
Power Management
Interrupt Management
General Port Control
Flexible Peripheral Management
Module Suspend Control
Watchdog Timer
XRAM Addressing Modes
Error Detection and Correction in Data Memory
Miscellaneous Control
Register Mapping
3.3
XC800 Core
The XC800 Core is a complete, high performance CPU core that is functionally upward compatible to the 8051.
While the standard 8051 core is designed around a 12-clock machine cycle, the XC800 Core uses a two-clock
period machine cycle.
The instruction set consists of 45% one-Byte, 41% two-Byte and 14% three-Byte instructions. Each instruction
takes 1, 2 or 4 machine cycles to execute. In case of access to slower memory, the access time may be extended
by wait cycles (one wait cycle lasts one machine cycle, which is equivalent to two clock cycles).
Via the dedicated DAP interface the XC800 Core supports a range of debugging features including basic
stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory
and special function registers.
The key features of the XC800 Core implemented are listed below.
Two clocks per machine cycle

256 Byte of internal data memory
Program memory download option
15-source, 4-level interrupt controller
2 data pointers
Power saving modes
Dedicated debug mode via low-pin-count DAP interface (native JTAG mode)
Two 16-Bit timers (Timer 0 and Timer 1)
Data Sheet
26
Rev. 1.1, 2012-03-08
TLE9832
Figure 10 shows the functional blocks of the XC800 Core. The XC800 Core consists mainly of the instruction
decoder, the arithmetic section, the program control section, the access control section, and the interrupt
controller.
The instruction decoder decodes each instruction and accordingly generates the internal signals required to
control the functions of the individual units within the core. These internal signals have an effect on the source and
destination of data transfers and control the ALU processing.
Internal Data
Memory
Core SFRs
Register Interface
External SFRs
External Data
Memory
16-bit Registers &
Memory Interface
ALU
Opcode &
Immediate
Registers
Multiplier / Divider
Opcode Decoder
Timer 0 / Timer 1
Program Memory
Clocks
Memory Wait
Reset
Legacy External Interrupts (IEN0, IEN1)

External Interrupts
Non-Maskable Interrupt
State Machine &

Power Saving
Interrupt
Controller
Core Block Diagram
Figure 10
XC800 Core Block Diagram
The arithmetic section of the processor performs extensive data manipulation and consists of the arithmetic/logic
unit (ALU), A register, B register and PSW register. The ALU accepts 8-Bit data words from one or two sources
and generates an 8-Bit result under the control of the instruction decoder. The ALU performs both arithmetic and
logic operations. Arithmetic operations include add, subtract, multiply, divide, increment, decrement, BCDdecimal-add-adjust and compare. Logic operations include AND, OR, Exclusive OR, complement and rotate (right,
left or swap nibble (left four)). Also included is a Boolean unit performing the Bit operations as set, clear,
complement, jump-if-set, jump-if-not-set, jump-if-set-and-clear and move to/from carry. The ALU can perform the
Bit operations of logical AND or logical OR between any addressable Bit (or its complement) and the carry flag,
and place the new result in the carry flag.
The program control section controls the sequence in which the instructions stored in program memory are
executed. The 16-Bit program counter (PC) holds the address of the next instruction to be executed. The
conditional branch logic enables internal and external events to the processor to cause a change in the program
execution sequence.
The access control unit is responsible for the selection of the on-chip memory resources. The interrupt requests
from the peripheral units are handled by the interrupt controller unit.
Data Sheet
27
Rev. 1.1, 2012-03-08
TLE9832
3.4
Memory Architecture
The TLE9832 CPU manipulates operands in the following memory spaces:
36 kByte of Flash memory in code space

BootROM memory in code space
256 Byte of internal RAM data memory in internal data space
3 kByte of XRAM memory in code space and external data space (XRAM can be read/written as program
memory or external data memory)
128 Byte of special function registers SFR in internal data space
256 Byte of special function registers XSFR in external data space.
Figure 11 illustrates the memory address spaces of the TLE9832.
F' FFFF H
Bank F
F' 0000H
Bank E
E' 0000H
Bank D
Reserved
1)
Bank C
D' 0000H
C' 0000H
Bank B
B' 0000H
Bank A
Reserved
XRAM
3 KByte
Bank 9
A' 0C00H
A' 0000H
Reserved
2)
9' 0000H
Bank 8
8' 0000H
Bank 7
Reserved 1)
Bank 6
Bank 5
7' 0000H
Memory Extension
Stack Pointer
(MEXSP)
6' 0000H
5' 0000H
Bank 4
FFH
4' 0000H
Bank 3
Reserved
XRAM
3 KByte
3' 0000H
2' FC00H
2' F000H
Reserved
XRAM
3 KByte
80H
Bank 2
Boot ROM
2' 9C00 H
Reserved
Reserved
2' 8000H
Flash
Lower 32 KByte
2' 0100H
2' 0000H
XSFR, 256 Byte
1' 0000H
Flash Upper 4 Kbyte
0' 9000H
0' 8000H
Indirect
Address
Direct
Address
Internal RAM
Special Function Registers
FFH
Reserved 1)
Bank 1
Bank 0
Not user-accessible ;
HW access only
Extension Stack RAM
80H
Reserved 2)
7F H
Flash
Lower 32 Kbyte
40H
Code Space
Internal RAM
00H
0' 0000H
External Data Space
Internal Data Space

Memory Map User Mode
1) The lower 32 Kbyte of the 36 Kbyte NVM is always mapped and can be accessed in the lower half (0000H to 7FFFH) of each bank in
the code space (except bank A, where the 3 Kbyte XRAM is mapped.)
2) XRAM is always mapped and can be accessed in the range (F000H to FBFFH) of each bank in the external data space;
XSFR is always mapped and can be accessed in the range (0000H to 00FFH) of each bank in the external data space.
Figure 11
Data Sheet
TLE9832 Memory Map
28
Rev. 1.1, 2012-03-08
TLE9832
3.5
Flash Memory
The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable
storage of user code and data. It is operated from a single 1.5V supply (VDDC) from the internal voltage regulator
and does not require additional programming or erasing voltage.
Features
In-System Programming via LIN (Flash mode) and DAP

Error Correction Code (ECC) for dynamic correction of single Bit errors and signalling for double Bit failures
Support for aborting erase operation
Program width of 128 Byte (page)
Minimum erase width of 128 Byte (page)
4 Byte read access
Read access time: 75 ns
Program time for 1 page: 3 ms
Page erase time: 4 ms
3.6
Watchdog Timer 1 (WDT1)
Features
Windowed Watchdog Timer with programmable timing in Active Mode

Long open window (80ms) after power-up, reset, wake-up
Short open window (30ms) to facilitate Flash programming
Disabled during debugging
Safety shutdown to Sleep Mode after 5 missed WDT1 services
There are two watchdog timers in the system. The Watchdog Timer (WDT) within the microcontroller (see
Chapter 3.7) and the Watchdog Timer 1 (WDT1), which is described in this section.
In Active Mode, the WDT1 acts as a windowed watchdog timer, which provides a highly reliable and safe way to
recover from software or hardware failures.
The WDT1 is always enabled in Active Mode. In Sleep Mode, Stop Mode and OCDS mode the WDT1 is disabled.
The behavior of the Watchdog Timer 1 in Active Mode is depicted in Figure 12.
Data Sheet
29
Rev. 1.1, 2012-03-08
TLE9832
Power-up
Reset
RESET
timeout always
RESET
RESET
Timeout
or
Trigger in closed window
timeout
Trigger SOW
Maximum number
of SOW triggers
exceeded
Long
Open Window
Trigger
Normal
windowed
operation
Trigger SOW
Short
open window
Trigger
Trigger
Figure 12
Data Sheet
Trigger SOW
Watchdog Timer 1 Behavior
30
Rev. 1.1, 2012-03-08
TLE9832
3.7
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a sub-module in the System Control Unit (SCU). The Watchdog Timer provides a
highly reliable and secure way to detect and recover from software or hardware failures. The WDT helps to abort
an accidental malfunction of the TLE9832 in a user-specified time period. When enabled, the WDT will cause the
TLE9832 system to be reset if the WDT is not serviced within a user-programmable time period. The CPU must
service the WDT within this time interval to prevent the WDT from causing an TLE9832 system reset. Hence,
routine service of the WDT confirms that the system is functioning properly.
The WDT is disabled by default.
In debug mode, the WDT is suspended by default and stops counting (its debug suspend Bit is set by default i.e.
MODSUSP.WDTSUSP = 1). Therefore during debugging, there is no need to refresh the WDT.
Features
16-Bit Watchdog Timer

Programmable reload value for upper 8 Bits of timer
Programmable window boundary
Selectable input frequency of fPCLK/2 or fPCLK/128
The Watchdog Timer is a 16-Bit timer, which is incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-Bit
timer is realized as two concatenated 8-Bit timers. The upper 8 Bits of the Watchdog Timer can be preset to a userprogrammable value via a watchdog service access in order to vary the watchdog expiring time. The lower 8 Bits
are reset on each service access. Figure 13 shows the block diagram of the watchdog timer unit.
WDT
Control
Clear
1:2
MUX
f PCLK
WDTREL
WDT Low Byte
WDT High Byte
1:128
Overflow/Time-out Control &

Window-boundary control
WDTIN
ENWDT
WDTTO
WDTRST
Logic
ENWDT_P
Figure 13
Data Sheet
WINBCNT
WDT Block Diagram
31
Rev. 1.1, 2012-03-08
TLE9832
3.8
Interrupt System
The TLE9832 supports 14 interrupt vectors with four priority levels. Eleven of these interrupt vectors are assigned
to the on-chip peripherals: Timer 0, Timer 1, UART, SSC and A/D Converter are each assigned to one dedicated
interrupt vector; while Timer2, Timer21, MDU, LIN and the Capture/Compare Unit share six interrupt vectors.
Two interrupt vectors are assigned to the external interrupts. External interrupts 0 to 1 are each assigned to one
dedicated interrupt vector, external interrupt 2 shares on interrupt vector with Timer21 and the MDU.
One interrupt vector is dedicated to the XINT interrupt events whose interrupt flags are also located in registers in
XSFR area.
A non-maskable interrupt (NMI) with the highest priority is shared by the following:
Watchdog Timer, warning before overflow

MI_CLK Watchdog Timer overflow event
PLL, loss of lock
Flash, on operation complete, e.g. erase.
OCDS, on user IRAM event
Oscillator watchdog detection for too low oscillation of fOSC
Flash map error
Uncorrectable ECC error on Flash, XRAM and IRAM
VSUP supply pre warning when any supply voltage drops below or exceeds any threshold.
Figure 14, Figure 15, Figure 16, Figure 17 and Figure 18 give a general overview of the interrupt sources and
nodes, and their corresponding control and status flags. Figure 19 gives the corresponding overview for the NMI
sources.
Data Sheet
32
Rev. 1.1, 2012-03-08
TLE9832
Highest
Timer 0
Overflow
TF0
TCON.5
ET0
000B
IEN0.1
Timer 1
Overflow
ET1
001B
IEN0.3
IP.3/
IPH.3
RI
SCON.0
RIEN
SCON1.0
UART
Transmit
IP.1/
IPH.1
TF1
TCON.7
UART
Receive
Lowest
Priority Level
>=1
ES
TI
0023
IEN0.4
SCON.1
TIEN
IP.4/
IPH.4
SCON1.1
IE0
EINT0
TCON.1
IT0
EX0
0003
IEN0.0
TCON.0
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
IP.0/
IPH.0
EXINT0
EXICON0.0/1
IE1
EINT1
TCON.3
IT1
EX1
0013
IEN0.2
TCON.2
IP.2/
IPH.2
EXINT1
EA
EXICON0.2/3
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 14
Data Sheet
Interrupt Request Sources (Part 1)
33
Rev. 1.1, 2012-03-08
TLE9832
Highest
Timer 2
Overflow
TF2
T2_T2CON.7
T2EX
Lowest
Priority Level
TF2EN
T2_T2CON1.1
>=1
EXF2
EXEN2 T2_T2CON.6
T2_T2CON.3
EDGES
EL
T2_T2MOD.5
EXF2EN
T2_T2CON1.0
>=1
ET2
002B
IEN0.5
End of
Synch Byte
IP.5/
IPH.5
EOFSYN
LINST.4
Synch Byte
Error
>=1
ERRSYN
SYNEN
LINST.5
P
o
l
l
i
n
g
LINST.6
ADC Service
Request 0
ADCSR0
ADC Service
Request 1
ADCSR1
EADC
IRCON1.4
IEN1.0
IRCON1.3
>=1
0033
IP1.0/
IPH1.0
S
e
q
u
e
n
c
e
EA
IEN0.7
Bitaddressable
Figure 15
Data Sheet
34
Rev. 1.1, 2012-03-08
TLE9832
Highest
SSC_EIR
EIR
IRCON1.0
Lowest
Priority Level
EIREN
MODIEN.0
SSC_TIR
>=1
TIR
IRCON1.1
TIREN
MODIEN.1
ESSC
RIR
SSC_RIR
IRCON1.2
003B
IEN1.1
IP1.1/
IPH1.1
RIREN
MODIEN.2
P
o
l
l
i
n
g
EXINT2
EINT2
IRCON0.2
EXINT2
EXICON0.4/5
Timer 21
Overflow
TF2
T21_T2CON.7
TF2EN
T21_T2CON1.1
T21EX
>=1
EXF2
>=1
T21_T2CON.3
MDU_0
0043
IEN1.2
EXEN2 T21_T2CON.6 EXF2EN

EDGES
EL
T21_T2MOD.5
EX2
IP1.2/
IPH1.2
S
e
q
u
e
n
c
e
T21_T2CON1.0
IRDY
MDUSTAT.0
IE
MDUCON.7
MDU_1
IERR
MDUSTAT.1
IE
EA
MDUCON.7
IEN0.7
Bitaddressable
Figure 16
Data Sheet
35
Rev. 1.1, 2012-03-08
TLE9832
Highest
Lowest
Priority Level
XINTx
P
o
l
l
i
n
g
XINTxF
.
.
.
XINTxEN
XSFRc.d
XSFRa.b
>=1
XINTyF
XINTy
XINTyEN
XSFRu.v
XSFRs.t
XINTw
XINTz
.
.
.
004B
EXM
IEN1.3
S
e
q
u
e
n
c
e
IP1.3/
IPH1.3
XINTwF
XSFRe.f
>=1
XINTzEN
XINTzF
XSFRi.j
XSFRg.h
EA
IEN0.7
Bit-addressable
Figure 17

Highest
Lowest
Priority Level
CCU6 Node 0
CCU6SR0
IRCON3.0
ECCIP0
0053
IEN1.4
CCU6 Node 1
CCU6SR1
IRCON3.4
CCU6 Node 2
ECCIP1
IEN1.5
005B
IP1.5/
IPH1.5
CCU6SR2
IRCON4.0
ECCIP2
0063
IEN1.6
CCU6 Node 3
IP1.4/
IPH1.4
IP1.6/
IPH1.6
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
CCU6SRC3
IRCON4.4
ECCIP3
IEN1.7
006B
IP1.7/
IPH1.7
EA
IEN0.7
Bit-addressable
Figure 18
Data Sheet
36
Rev. 1.1, 2012-03-08
TLE9832
Watchdog Timer
Overflow
>=1
MI_CLK Watchdog
Timer Overflow
FNMIWDT
NMISR.0
(Type interrupt structure 1)
NMIWDT
NMICON.0
PLL Loss -of-Lock
FNMIPLL
NMISR.1
NMIPLL
NMICON.1
Flash Operation
Complete
FNMINVM
NMISR.2
IRAM read
event*
NMICON.2
FNMIRR
MMICR.2
NMIRRE
MMICR.0
IRAM write
event*
>=1
FNMIOCDS
NMISR.3
FNMIRW
MMICR.3
NMINVM
NMIOCDS
NMICON.3
NMIRWE
Non
Maskable
Interrupt
MMICR.1
Oscillator
Watchdog
>=1
FNMIOWD
NMISR.4
0073
NMIOWD
NMICON.4
Flash Map Error
FNMIMAP
NMISR.5
XRAM
Uncorrectable
ECC Error
XRDBE
NMIMAP
NMICON.5
EDCSTAT.0
XRIE
EDCCON.0
IRAM
Uncorrectable
ECC Error
IRDBE
>=1
EDCSTAT.1
Flash
Uncorrectable
ECC Error
IRIE
FNMIECC
NMISR.6
EDCCON.1
NMIECC
NMICON.6
NVMDBE
EDCSTAT.2
NVMIE
EDCCON.2
Supply Prewarning
(Type interrupt structure 1)
FNMISUP
NMISR.7
NMISUP
NMICON.7
* Includes other pre-condition
Figure 19
Data Sheet
Non-Maskable Interrupt Request Source
37
Rev. 1.1, 2012-03-08
TLE9832
3.9
Multiplication/Division Unit
The Multiplication/Division Unit (MDU) provides fast 16-Bit multiplication, 16-Bit and 32-Bit division as well as shift
and normalize features. It has been integrated to support the TLE9832 core in real-time control applications, which
require fast mathematical computations.
Features
Fast signed/unsigned 16-Bit multiplication

Fast signed/unsigned 32-Bit divide by 16-Bit and 16-Bit divide by 16-Bit operations
32-Bit unsigned normalize operation
32-Bit arithmetic/logical shift operations
3.10
Parallel Ports
The TLE9832 has 16 port pins organized into three parallel ports: Port 0 (P0), Port 1 (P1) and Port 2 (P2). Each
port pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. P0 and
P1 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output
functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected.
Bidirectional Port Features (P0, P1P1)
Configurable pin direction

Configurable pull-up/pull-down devices
Configurable open drain mode
Configurable drive strength
Transfer of data through digital inputs and outputs (general purpose I/O)
Alternate input/output for on-chip peripherals
Data Sheet
38
Rev. 1.1, 2012-03-08
TLE9832
PUDSEL
Internal
Bus
Pull -up/Pull -down

Select Register
Pull-up/Pull-down
Control Logic
PUDEN
Pull -up/Pull -down
Enable Register
TCCR
Temperature
Compensation
Control Register
Px_POCONy
Port Output
Driver Control
Registers
OD
Open Drain
Control Register
DIR
Direction Register
ALTSEL0
Alternate Select
Register 0
ALTSEL1
Pull
Device
Alternate Select
Register 1
AltDataOut 3
Output
Driver
11
AltDataOut 2
10
AltDataOut1
Pin
01
00
Data
Data Register
Out
Input
Driver
In
Schmitt
Trigger
AltDataIn
Pad
AnalogIn
Figure 20
Data Sheet
General Structure of a Bidirectional Port Pin
39
Rev. 1.1, 2012-03-08
TLE9832
Figure 21 shows the structure of an input-only port pin. Each P2 pin can only function in input mode. Register
P2_DIR is provided to enable or disable the input driver. When the input driver is enabled, the actual voltage level
present at the port pin is translated into a logic 0 or 1 via a Schmitt-Trigger device and can be read via register.
Each pin can also be programmed to activate an internal weak pull-up or pull-down device. The analog input
(Analog In) bypasses the digital circuitry and Schmitt-Trigger device for direct feed-through to the ADC1 input
channel.
Internal Bus
PUDSEL
Pull-up/Pull-down
Select Register
Pull-up/Pull-down
Control Logic
PUDEN
Pull-up/Pull-down
Enable Register
Pull
Device
In
Data
Input
Driver
Pin
Data Register
Schmitt Trigger
Pad
AltDataIn
AnalogIn
Figure 21
Data Sheet
General Structure of an Input Port Pin
40
Rev. 1.1, 2012-03-08
TLE9832
3.11
Timer 0 and Timer 1
Timer 0 and Timer 1 can function as both, timers or counters. When functioning as a timer, Timer 0 and Timer 1
are incremented with every machine cycle, i.e. every 2 input clocks (or 2 PCLKs). When functioning as a counter,
Timer 0 and Timer 1 are incremented in response to a 1-to-0 transition (falling edge) at its respective external input
pins, T0 or T1. Timer 0 and Timer 1 are fully compatible and can be configured in four different operating modes
to use in a variety of applications, see Table 6. In modes 0, 1 and 2, the two timers operate independently, but in
mode 3, their functions are specialized.
Table 6
Timer 0 and Timer 1 Modes
Mode
Operation
13-Bit-timer
The timer is essentially an 8-Bit counter with a divide-by-32 prescaler. This mode is
included solely for compatibility with Intel 8048 devices.
16-Bit-timer
The timer registers, TLx and THx, are concatenated to form a 16-Bit counter.
8-Bit timer with auto-reload

The timer register TLx is reloaded with a user-defined 8-Bit value in THx upon overflow.
Timer 0 operates as two 8-Bit timers

The timer registers, TL0 and TH0, operate as two separate 8-Bit counters. Timer 1 is
halted and retains its count even if enabled.
Data Sheet
41
Rev. 1.1, 2012-03-08
TLE9832
3.12
Timer 2 and Timer 21
Timer 2 and Timer 21 are 16-Bit general purpose timers that are fully compatible and have two modes of operation,
a 16-Bit auto-reload mode and a 16-Bit one channel capture mode, see Table 7. As a timer, the timers count with
an input clock of PCLK/12 (if prescaler is disabled). As a counter, they count 1-to-0 transitions on pin T2. In the
counter mode, the maximum resolution for the count is PCLK/24 (if prescaler is disabled).
Table 7
Timer 2 Modes
Mode
Description
Auto-reload
Up/Down Count Disabled

Count up only
Start counting from 16-Bit reload value, overflow at FFFFH
Reload event configurable for trigger by overflow condition only, or by
negative/positive edge at input pin T2EX as well
Programmable reload value in register RC2
Interrupt is generated with reload events.
Auto-reload
Up/Down Count Enabled

Count up or down, direction determined by level at input pin T2EX
No interrupt is generated
Count up
Start counting from 16-Bit reload value, overflow at FFFFH
Reload event triggered by overflow condition
Programmable reload value in register RC2
Count down
Start counting from FFFFH, underflow at value defined in register RC2
Reload event triggered by underflow condition
Reload value fixed at FFFFH
Channel capture
Data Sheet
Count up only
Start counting from 0000H, overflow at FFFFH
Reload event triggered by overflow condition
Reload value fixed at 0000H
Capture event triggered by falling/rising edge at pin T2EX
Captured timer value stored in register RC2
Interrupt is generate with reload or capture event
42
Rev. 1.1, 2012-03-08
TLE9832
3.13
Timer 3
Timer 3 can function as timer or counter. When functioning as a timer, Timer 3 is incremented in periods based
on the system clock. When functioning as a counter, Timer 3 is incremented in response to a 1-to-0 transition
(falling edge) at its respective input. Timer 3 can be configured in four different operating modes to use in a variety
of applications, see Table 8.
Table 8
Timer 3 Modes
Mode
Sub-Mode
Operation
13-Bit Timer
The timer is essentially an 8-Bit counter with a divide-by-32 prescaler. This mode is
included solely for compatibility with Intel 8048 devices.
16-Bit Timer
The timer registers, TLx and THx, are concatenated to form a 16-Bit counter.
16-Bit Timer
The timer registers, TLx and THx, are concatenated to form a 16-Bit counter, which is
triggered by the PWM Unit to enable a single shot measurement on a preset channel with
the measurement unit.
16-Bit Timer
The timer registers, TLx and THx, are concatenated to form a 16-Bit counter, which is
triggered by the PWM Unit to enable the LIN Baudrate Measurement.
8-Bit Timer with Auto-reload

The timer register TLx is reloaded with a user-defined 8-Bit value in THx upon overflow.
Timer 3 operates as Two 8-Bit Timers

The timer registers, TL3 and TH3, operate as two separate 8-Bit counters.
Timer 3 operates as Two 8-Bit Timers

The timer registers, TL3 and TH3, operate as two separate 8-Bit counters. In this mode the
100 kHz Low Power Clock can be measured. TL3 acts as an edge counter for the clock
edges and TH3 as an counter which counts the time between the edges.
Data Sheet
43
Rev. 1.1, 2012-03-08
TLE9832
3.14
Capture/Compare Unit 6 (CCU6)
The CCU6 unit is made up of a Timer T12 block with three capture/compare channels and a Timer T13 block with
one compare channel. The T12 channels can independently generate PWM signals or accept capture triggers, or
they can jointly generate control signal patterns to drive AC-motors or inverters.
A rich set of status Bits, synchronized updating of parameter values via shadow registers, and flexible generation
of interrupt request signals provide means for efficient software-control.
Note: The capture/compare module itself is named CCU6 (capture/compare unit 6). A capture/compare channel
inside this module is named CC6x.
Timer 12 Block Features
Three capture/compare channels, each channel can be used either as capture or as compare channel
Generation of a three-phase PWM supported (six outputs, individual signals for High Side and Low Side
Switches)
16-Bit resolution, maximum count frequency = peripheral clock
Dead-time control for each channel to avoid short-circuits in the power stage
Concurrent update of T12 registers
Center-aligned and edge-aligned PWM can be generated
Single-shot mode supported
Start can be controlled by external events
Capability of counting external events
Multiple interrupt request sources
Hysteresis-like control mode
Timer 13 Block Features
One independent compare channel with one output

16-Bit resolution, maximum count frequency = peripheral clock
Concurrent update of T13 registers
Can be synchronized to T12
Interrupt generation at period-match and compare-match
Single-shot mode supported
Start can be controlled by external events
Capability of counting external events
Data Sheet
44
Rev. 1.1, 2012-03-08
TLE9832
Additional Specific Functions
Block commutation for brushless DC-drives implemented

Position detection via hall sensor pattern
Noise filter supported for position input signals
Automatic rotational speed measurement and commutation control for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC-drives
Output levels can be selected and adapted to the power stage
The Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined
(e.g. a channel works in compare mode, whereas another channel works in capture mode). The Timer T13 can
work in compare mode only. The multi-channel control unit generates output patterns which can be modulated by
T12 and/or T13. The modulation sources can be selected and combined for the signal modulation.
CCU6 Module Kernel

Compare
CC63
Compare
Interrupt
Control
SR[3:0]
Trap Input
T13
Trap
Control
Output Select
Start
fCC 6
Hall Input
Multichannel
Control
Output Select
CC62
DeadTime
Control
Compare
Compare
Clock
Control
CC61
Compare
T13SUSP
T12
Capture
Debug T12 SUSP

Suspend
CC60
CTRAP
CCPOS2
CCPOS1
CCPOS0
CC62
COUT62
CC61
COUT61
CC60
COUT60
COUT63
T13HR
T12HR
Input / Output Control
Port Control
CCU6_MCB05506+
Figure 22
Data Sheet
CCU6 Block Diagram
45
Rev. 1.1, 2012-03-08
TLE9832
3.15
UART
The UART provides a full-duplex asynchronous receiver/transmitter, i.e. it can transmit and receive
simultaneously. It is also receive-buffered, i.e. it can commence reception of a second Byte before a previously
received Byte has been read from the receive register. However, if the first Byte still has not been read by the time
reception of the second Byte is complete, one of the Bytes will be lost. The serial port receive and transmit registers
are both accessed at Special Function Register (SFR) SBUF. Writing to SBUF loads the transmit register, and
reading SBUF accesses a physically separate receive register.
UART Features
Full-duplex asynchronous modes

8-Bit or 9-Bit data frames, LSB first
fixed or variable baud rate
Receive buffered
Multiprocessor communication
Interrupt generation on the completion of a data transmission or reception
Baud-rate generator with fractional divider for generating a wide range of baud rates
Hardware logic for break and synch Byte detection
UART Modes
The UART can be used in four different modes. In mode 0, it operates as an 8-Bit shift register. In mode 1, it
operates as an 8-Bit serial port. In modes 2 and 3, it operates as a 9-Bit serial port. The only difference between
mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. The variable baud rate is
set by the underflow rate on the dedicated baud-rate generator.
The different modes are selected by setting Bits SM0 and SM1 to their corresponding values, as shown in Table 9.
Table 9
UART Modes
SM0
SM1
Mode 0: 8-Bit shift register
fPCLK/2
Mode 1: 8-Bit shift UART
Variable
fPCLK/64
Variable
Data Sheet
Operating Mode
Baud Rate
46
Rev. 1.1, 2012-03-08
TLE9832
3.16
LIN Transceiver
The LIN module is a transceiver for the Local Interconnect Network (LIN) compliant to the standards LIN 1.3, LIN
2.0 and LIN 2.1. It operates as a bus driver between the protocol controller and the physical network. The LIN bus
is a single wire, bi-directional bus typically used for in-vehicle networks, using baud rates between 2.4 kbps and
20 kbps. Additionally baud rates up to 40 kBaud are implemented.
The LIN module offers several different operation modes, including a Sleep Mode and the normal operation mode.
The integrated slope control allows to use several data transmission rates with optimized EMC performance. For
data transfer at the end of line, a Flash Mode up to 115 kBaud is also implemented.
VS
LIN Transceiver
30 k
XSFR
LIN
CTRL
Driver
LIN-FSM
TxD
STATUS
GND_LIN
Transmitter
CTRL
STATUS
+ Curr. Limit. +
TSD
Filter
Filter
RxD
Receiver
LIN_Wake
Sleep Comparator
GND_LIN
Figure 23
LIN Transceiver Block Diagram
3.17
High-Speed Synchronous Serial Interface
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and half-duplex synchronous
communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16Bit baud-rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock
polarity and phase are programmable. This allows communication with SPI-compatible devices or devices using
other synchronous serial interfaces.
Features
Master and slave mode operation

Full-duplex or half-duplex operation
Transmit and receive buffered
Flexible data format
Data Sheet
47
Rev. 1.1, 2012-03-08
TLE9832
Programmable number of data Bits: 2 to 8 Bits

Programmable shift direction: LSB or MSB shift first
Programmable clock polarity: idle low or high state for the shift clock
Programmable clock/data phase: data shift with leading or trailing edge of the shift clock
Variable baud rate
Compatible with Serial Peripheral Interface (SPI)
Interrupt generation
On a transmitter empty condition
On a receiver full condition
On an error condition (receive, phase, baud rate, transmit error)
Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR (Master
Transmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line MS_CLK
(Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected
to the pin SCLK. Transmission and reception of data are double-buffered.
Figure 24 shows all functional relevant interfaces associated with the SSC Kernel.
f hw _clk
Address
Decoder
EIR
Data Sheet
MTSRA
MTSRB
MRST
RIR
TIR
BPI
Interface
Figure 24
MRSTA
MRSTB
MTSR
Master Slave
Interrupt
Control
SSC
Module
( Kernel )
Master
f cfg_ clk
Slave
Cloc
k
Control
Module
Port
Control
SCLKA
SCLKB
SCLK
Product
Interface
SSC Interface Diagram
48
Rev. 1.1, 2012-03-08
TLE9832
3.18
Measurement Unit
The measurement unit is a functional unit that comprises the following associated sub-modules:
1 x 8 Bit ADC (ADC2) with 10 inputs. 5 are for single ended input signals and 5 are for differential input signals.
Monitoring inputs voltage attenuators with two selectable attenuation settings: divide by 4 and divide by 6
Supply voltage attenuators with attenuation of VBAT_SENSE, VS, VDDP and VDDC.
VBG monitoring of 8-Bit ADC (ADC2) to guarantee functional safety requirements.
Low Side Switch current sensing of LS1 and LS2. Allows a scalable overcurrent pre warning.
Temperature sensor for monitoring the chip temperature and Low Side Switches temperature.
Supplement block with reference voltage generation, bias current generation, voltage buffer for Flash
reference voltage, voltage buffer for analog module reference voltage and test interface.
Table 10
Measurement functions and associated modules
Module
Name
Modules
Functions
Central Functions Bandgap reference circuit

Unit
The bandgap-reference sub-module provides two

reference voltages
1. a trimmable reference voltage for the 8-Bit ADC. A local
dedicated bandgap circuit is implemented to avoid
deterioration of the reference voltage arising e.g. from
crosstalk or ground voltage shift.
2. the reference voltage for the Flash module
8-Bit ADC (ADC2) 8-Bit ADC module with 10

multiplexed inputs
1. 5 single-ended inputs 0 ... 1.23V

2. 5 differential inputs 0 ... 1.23V
(allocation see following overview figure)
10-Bit ADC
(ADC1)
10-Bit ADC module including analog 1. VBAT_SENSE measurement on channel 0 of ADC1.

2. VS measurement on channel 2 of ADC1.
test bus interface - part of C
3. MONx measurement on channel 6 of ADC1.
subsystem
4. 5 additional (5V) analog inputs from Port 2.
Supply Voltage
Attenuator
Resistive supply voltage attenuator
Scales down the supply voltages of the system to the input

voltage range of ADC1 and ADC2.
Monitoring Input
Attenuator
Resistive attenuator for (HV)
Scales down 5 monitoring input voltages to the input

voltage range of the ADC1.
Central
Temperature Low Side Switch
Temperature
Sensor
Temperature sensor readout with

two multiplexed Vbe sensing
elements
Generates outputs voltage which is a linear function of the

local chip (junction) temperature.
Measurement
Core Module
Digital signal processing and ADC

control unit
1. Generates the control signal for the 8-Bit ADC2 and the
synchronous clock for the switched capacitor circuits,
2. Performs digital signal processing functions and
provides status outputs for interrupt generation.
The structure of the measurement functions module is shown in Figure 29.
Data Sheet
49
Rev. 1.1, 2012-03-08
TLE9832
VAREF
VS
* 0.252
CH0
5V
P2.1
CH1
* 0.252
CH2
UDIG
VREF
P2.3
CH3
P2.4
CH4
P2.5
CH5
MUX
10
/
SFR
ADC 1
CH6
CH7
P2.7
10 Bit ADC + UDIG

MON1
* 0,25 (0,166 )
MON2
* 0,25 (0,166 )
MON3
* 0,25 (0,166 )
MON4
* 0,25 (0,166 )
MON5
* 0,25 (0,166 )
VBAT_SENSE
M
U
X
Measurement-Unit
* 0.063
CH0
* 0.063
CH1
VDDP
* 0.2
CH2
VDDC
* 0.687
1. 23
V
CH3
VBG
DPP
CH4
MUX
n.u.
8
/
XSFR
CH5
Low Side 1
CH6
Low Side 2
CH7
TSENSE 1
ADC 2
CH8
TSENSE 2
CH9
Measurement Core
Figure 25
Data Sheet
TLE9832 Measurement Unit-Overview
50
Rev. 1.1, 2012-03-08
TLE9832
3.19
Measurement Core Module (incl. ADC2)
The basic function of this block is the digital postprocessing of several analog digitized measurement signals by
means of filtering, level comparison and interrupt generation. The measurement postprocessing block is built of
ten identical channel units attached to the outputs of the 10-channel 8-Bit ADC (ADC2). It processes ten channels,
where the channel sequence and prioritization is programmable within a wide range.
Features
10 individually programmable channels split into two groups of user configurable and non user configurable
Individually programmable channel prioritization scheme for measurement unit
Two independent filter stages with programmable low-pass and time filter characteristics for each channel
Two channel configurations:
Programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis
Two individually programmable trigger thresholds with limit hysteresis settings
Individually programmable interrupts and status for all channel thresholds
TSENSE_SEL
4
/
MUX_SEL<3:0>
Channel Controller
(Sequencer)
ADC2 - XSFR
VBAT_SENSE
CH0
VS
CH1
VDDP
CH2
VDDC
CH3
VBG
CH4
n.u.
CH5
LS1
CH6
LS2
CH7
TS1
CH8
TS2
CH9
TSENSE
Figure 26
Data Sheet
Digital Signal Processing

1st Order IIR
ADC2
VREF
MUX
8
/
Calibration Unit:
y= a + (1+b)*x
8
/
8
/
TH_UP_CHx
TH_LOW_CHx
+
+
1
/
+/-
UP_X_STS
1
/
+/-
LOW_X_STS
Measurement Core Module Block Diagram
51
Rev. 1.1, 2012-03-08
TLE9832
3.20
Analog Digital Converter (ADC1)
The TLE9832 includes a high-performance 10-Bit Analog-to-Digital Converter (ADC1) with eight multiplexed
analog input channels. The ADC1 uses a successive approximation technique to convert the analog voltage levels
from up to eight different sources. The analog input channels of the ADC1 are available at AN1, AN3 - AN5, AN7.
Features
Successive approximation
8-Bit or 10-Bit resolution
8 analog channels
Four independent result registers
Result data protection for slow CPU access (wait-for-read mode)
Single conversion mode
Autoscan functionality
Limit checking for conversion results
Data reduction filter (accumulation of up to 2 conversion results)
Two independent conversion request sources with programmable priority
Selectable conversion request trigger
Flexible interrupt generation with configurable service nodes
Programmable sample time
Programmable clock divider
Cancel/restart feature for running conversions
Integrated sample and hold circuitry
Compensation of offset errors
Low power modes
Data Sheet
52
Rev. 1.1, 2012-03-08
TLE9832
3.21
High Voltage Monitor Input
This module is dedicated to monitor external voltage levels above or below a specified threshold or it can be used
to detect a wake-up event at each high-voltage MON_IN pin in low-power mode. Each input is sensitive to an input
level monitoring. It is available when the module is switched to Active Mode via the MON_int (internal signal name)
output with a small filter delay of typical 2 s.
Features
High-voltage input with VS/2 threshold voltage

Edge sensitive wake capability for power saving modes
Level sensitive wake-up feature configurable for transitions from low to high, high to low or both directions
MON inputs can also be evaluated with ADC1 in Active Mode, using adjustable threshold values (see also
Chapter 3.20).
VS
MONx
MONx
Filter
MON_int
Logic
XSFR
Figure 27
Data Sheet
Monitoring Input Block Diagram
53
Rev. 1.1, 2012-03-08
TLE9832
3.22
High Side Switch
The High Side Switch is intended for resistive load connections (only small line inductance are allowed) leaving
the ECU board. Typical applications are single or multiple LEDs of a dashboard or switch illumination or other
loads that require a High Side Switch.
A cyclic switch activation during Sleep Mode or Stop Mode of the system is also available.
Features
Multi purpose High Side Switch for resistive load connections (only small line inductances are allowed)
Over-current detection with thresholds: 8 mA (also used for on-state Open Load detection), 50 mA, 100 mA,
150 mA
Cyclic switch activation in Sleep Mode and Stop Mode for cyclic sense support with reduced driver capability:
max. 40 mA
Open load detection in off mode with two different thresholds: Ground (0 V, for functional safety) and 0.67 * VS
Off-state open load detection operates with two different test currents: 75 A and 750 A
PWM capability up to 25 kHz (with disabled slew rate control only)
Robust output for off ECU connection
Slew rate control
Selectable PWM source: PWM-Unit or CCU6
VS
OCTH_SEL
8 mA
50 mA
100 mA
150 mA
OC-Detection
CyclicDriver
XSFR
ON
Driver
OLTH_SEL
HS
0V
0.67*Vs
OL-Detection
6.8 nF
High Side
Figure 28
Data Sheet
High Side Switch Module Block Diagram
54
Rev. 1.1, 2012-03-08
TLE9832
3.23
Low Side Switches
The general purpose Low Side Switches are intended to control an on-board relay. They include an over-current
detection function.The module is designed for on-board connections.
Features
Multi purpose Low Side Switch

configurable over-current protection with automatic shutdown
configurable over-temperature protection with automatic shutdown
Intended for relay driver
PWM relay driver
simple relay driver
Integrated clamping
PWM capability up to 25 kHz
Selectable PWM source: PWM-Unit or CCU6
LS
Clamp
XSFR
ON
Driver
250 mA
OC-Detection
Low Side
LSGND
Figure 29
Data Sheet
Module Block Diagram
55
Rev. 1.1, 2012-03-08
TLE9832
3.24
PWM Generator
The PWM generator provides up to two configurable PWM channels in order to drive the Low Side Switches LS1,
LS2 and the High Side Switch HS1 in a PWM mode.
Features
Programmable modulation frequency per channel

Programmable duty-cycle per channel with glitch-free reprogramming
PWM frequency up to 25 kHz
Duty-cycle resolution from 0 % ... 100 % in steps of 0.5 %
0
1
2
3
ls1_pwm_o
0
1
2
3
ls2_pwm_o
0
1
2
3
hs1_pwm_o
PWM 1
PWM2
XSFR
ccu6_int_o
TIMER 0
EXT_INT_O
TO_TRINP_SEL
ccu6_ch0__o
ccu6_ch1__o
0
1
2
3
0
1
ap_t2ex__o
0
1
ap_t21ex__o
MOD_PWM
Figure 30
Data Sheet
Module Block diagram of PWM module and included PWM switching matrix
56
Rev. 1.1, 2012-03-08
TLE9832
3.25
Debug System
The On-Chip Debug Support (OCDS) provides the basic functionality required for software development and
debugging of XC800 based systems.The OCDS design is based on the following principles:
Use the built-in debug functionality of the XC800 Core

Add a minimum of hardware overhead
Provide support for most of the operations by a monitor program
Use standard interfaces to communicate with the Host (a debugger)
Features
Set breakpoints on instruction address and on address range within the program memory
Set breakpoints on internal RAM address range
Support unlimited amount of software breakpoints in Flash / RAM code region
Step through the program code
The Monitor Mode Control (MMC) block at the center of the OCDS system brings together control signals and
supports the overall functionality. The MMC communicates with the XC800 Core, primarily via the Debug
Interface, and also receives reset and clock signals. After processing memory address and control signals from
the core, the MMC provides proper access to the dedicated extra-memories: a Monitor ROM (holding the code)
and a Monitor RAM (for work data and monitor stack). The OCDS system is accessed through the DAP, which is
an interface dedicated exclusively for testing and debugging activities and is not normally used in an application.
The dedicated TMS pin is used for external configuration and debugging control.
Note: All the debug functionality described here can normally be used only after TLE9832 has been started in
OCDS mode.
Data Sheet
57
Rev. 1.1, 2012-03-08
TLE9832
Application Information
4.1
Electric Drive Application
Figure 31 shows the TLE9832 in an electric drive application setup controlling a DC-brush motor. The two Low
Side Switches are controlling a relay each. An external FET allows to control the window lift motor with a PWM
signal as generated with the CCU6 module of the microcontroller.
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
LIN
LIN
GND
GND
VBAT_SENSE
V BAT
MON1
MON2
MON3
MON4
MON5
VS
HS
LS1
VDDC
LS2
PWM
VDDP
VDDEXT
Double Hall
Sensor
E.g. TLE4966
Figure 31
Data Sheet
Speed
Direction
CCPOS0
CCPOS1
Simplified Application Diagram
58
Rev. 1.1, 2012-03-08
TLE9832
4.2
Connection of N.C. Pins
It is recommended to connect N.C. pins to GND unless otherwise specified. Since pins 10 and 46 are located next
to high voltage pins (VS, MON5, LS1) these 2 N.C. pins can be also left unconnected in order to avoid huge current
flow and damage of the system in case of short-circuit.
4.3
Connection of ADCGND Pin
The ADCGND pin is chip-internal connected to reference ground. In order to provide full offset compensation and
achieve full accuracy of ADC1 the ADCGND pin must not be connected to board ground. ADCGND pin should be
connected with a capacitor (100 nF) to VAREF only.
4.4
Connection of Exposed Pad
It is recommended to connect the exposed pad to GND.
4.5
Voltage Regulators-Blocking Capacitors
Table 11
External Component Recommendation
Symbol
Function
Comment
CVS
blocking capacitor at VS pin
> 20 F Elco + 100 nF Ceramic, ESR < 1
CVDDP
blocking capacitor at VDDP pin
1 F typ. + 100 nF Ceramic, ESR < 1
CVDDEXT
blocking capacitor at VDDEXT pin
100 nF typ., ESR < 1
CVDDC
blocking capacitor at VDDC pin
> 330 nF + 100 nF Ceramic, ESR < 1
CVAREF
blocking capacitor at VAREF pin
> 100 nF, ESR < 1
4.6
Additional External Components
Table 12
External Component Recommendation
Symbol
Function
Comment
CHSx
HF blocking capacitor at HSx pin
6.8 nF
RMONx
resistor at MONx pin
1 k
RVBAT_
resistor at VBAT_SENSE pin
1 k
Data Sheet
59
Rev. 1.1, 2012-03-08
TLE9832
4.7
ESD Tests
Note: Test for ESD robustness to IEC61000-4-2 gun test (150pF, 330) will be performed. The result and test
condition can be provided in a test report
Table 13
ESD Gun Test
Performed Test
Result
ESD at pin LIN, versus GND > 6

ESD at pin LIN, versus GND < -6
Unit
Remarks
kV
1)
positive pulse
kV
1)
negative pulse
1) ESD susceptibility ESD GUN according LIN EMC 1.3 Test Specification, Section 4.3 (IEC 61000-4-2). Tested by external
test house (IBEE Zwickau).
Data Sheet
60
Rev. 1.1, 2012-03-08
TLE9832
Electrical Characteristics
This chapter includes all relevant Electrical Characteristics of the product TLE9832.
5.1
General Characteristics
5.1.1
Absolute Maximum Ratings
Table 14
Absolute Maximum Ratings 1)
Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
Number
Voltages Supply Pins

Supply voltage VS
VS
-0.3
40
P_5.1.1
Voltage VDDP
VDDP
-0.3
5.5
P_5.1.2
Voltage VDDP
VDDP
-0.3
6.0
t < 100ms, in Stop
P_5.1.50
Mode only
Output voltage VDDEXT
VDDEXT
-0.3
5.5
P_5.1.3
Voltage VDDC
VDDC
-0.3
1.6
P_5.1.4
Battery Voltage VBAT_SENSE
VBAT_SENSE
-27
40
P_5.1.5
Output voltage HS
VHS
-0.3
40
P_5.1.6
Input voltage at LIN
VLIN
-27
40
P_5.1.7
Input voltage MON_x
VMON_X_maxrate -40
40
P_5.1.8
Input voltage LS
VLS
-0.3
40
P_5.1.9
Vin
-0.3
VDDP
VIN < 5.4V
P_5.1.10
Voltages High Voltage Pins
Voltages GPIOs
Voltage on any port pin
+0.3
Voltages Others
VAREF
-0.3
5.3
P_5.1.11
Junction Temperature
Tj
-40
150
P_5.1.12
Storage Temperature
Tstg
-55
150
P_5.1.13
VESD1
-2
kV
EIA/JESD 22-A114B
(1.5k, 100pF)
P_5.1.14
Input voltage VAREF

Temperatures
ESD Resistivity
ESD Resistivity HBM
all pins
Data Sheet
61
Rev. 1.1, 2012-03-08
TLE9832
Table 14
Absolute Maximum Ratings 1)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
ESD Resistivity HBM

VESD2
pins HS, MON1, MON2, MON3,
MON4, MON5, VS,
VBATSENSE vs.GND
-4
kV
EIA/JESD 22-A114B
(1.5k, 100pF)
P_5.1.15
VESD2
-6
kV
EIA/JESD 22-A114B
(1.5k, 100pF)
P_5.1.16
ESD Resistivity HBM

pins LIN vs. LINGND
1) Not subject to production test, specified by design.
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as outside normal operating range. Protection functions are not
designed for continuous repetitive operation.
5.1.2
Functional Range
Table 15
Functional Range
Parameter
Supply voltage in Active Mode
Symbol
VS_AM
Values
Unit
Min.
Typ.
Max.
5.5
27
Note /
Test Condition
Number
P_5.1.17
P_5.1.18
Min. Supply voltage in Active Mode

with reduced functionality
(Microcontroller / Flash with full
operation)
VS_AMmin
3.0
5.5
1)
Supply voltage in
VS_PD
3.0
27
P_5.1.19
Supply voltage in Sleep Mode
VS_Sleep
3.0
27
P_5.1.20
P_5.1.21
Supply Voltage transients slew rate
dVS/dt
-1
V/s
2)
Output sum current for all GPIO pins
IGPIO,sum
60
mA
P_5.1.22
40
MHz
P_5.1.23
-40
150
P_5.1.24
3)
sys
Operating frequency
Junction Temperature
Tj
1) Reduced functionality (e.g. cranking pulse) - not part of production test

2) Not subject to production test, specified by design
3) Specified function not guaranteed when limits are exceeded
Data Sheet
62
Rev. 1.1, 2012-03-08
TLE9832
5.1.3
Current Consumption
Table 16
Electrical Characteristics 1)
Vs = 5.5V to 18V, TJ = -40C to 85C, all voltages with respect to ground, positive current flowing into pin
Parameter
Symbol
Values
Unit Note / Test Condition
Min. Typ.
Max.
Number
Current Consumption @VS pin

Current Consumption in
Active Mode
IActive
30
40
mA
fsys = 40 MHz
P_5.1.25
no loads on pins, LIN in recessive
state, LS1, LS2, HS1 off
Current consumption in
Stop Mode
IPowerdown
85
95
microcontroller in Stop Mode, LIN P_5.1.26

recessive state, MON1-5 disabled,
GPIOs open (no loads)
Stop Mode with cyclic
sense enabled
IPowerdown2
110
microcontroller in Stop Mode, LIN

recessive state, GPIOs open (no
loads)
Sleep Mode
ISleep
25
P_5.1.28
system in Sleep Mode,
microcontroller not powered, LIN
recessive state, MON1-5 disabled
and GPIOs open (no loads)
P_5.1.27
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
5.1.4
Thermal Resistance
Table 17
Thermal Resistance
Parameter
Junction to Ambient
Symbol
RthJA
Values
Min.
Typ.
Max.
23.9
1) EIA/JESD 52_2, FR4, 76.2 x 114.3 x 1.5 mm; 35 Cu, 5 Sn; 300 mm
Data Sheet
63
Unit
Note /
Test Condition
Number
K/W
1)
P_5.1.29
Rev. 1.1, 2012-03-08
TLE9832
5.1.5
Timing Characteristics
The transition times between the system modes are specified here. Generally the timings are defined from the
time when the corresponding Bits in register PMCON0 are set until the sequence is terminated.
Table 18
System Timing1)
VS = 5.5 V to 27 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin
Parameter
Symbol
Values
Min. Typ.
Max.
Unit
Note / Test Condition
Number
Wake-up over battery
tstart
ms
Battery ramp-up till MCU reset P_5.1.30

is released; Vs > 3V and
RESET = 1
Sleep Mode Exit
tsleep - exit
ms
rising/falling edge of any

wake-up signal (LIN, MONs)
till MCU reset is released;
P_5.1.31
Sleep Mode Entry
tsleep -
330
P_5.1.32
Stop Mode Exit
tstop - exit
300
rising/falling edge of any

wake-up signal (LIN, MONs,
GPIOs)
P_5.1.33
Stop Mode Entry
tstop - entry
300
P_5.1.34
entry
Data Sheet
64
Rev. 1.1, 2012-03-08
TLE9832
5.2
Power Management Unit (PMU)
This chapter includes all electrical characteristics of the Power Management Unit
5.2.1
PMU I/O Supply Parameters VDDP
Table 19
Parameter
Specified Output Current
Symbol
IVDDP
Values
Min.
Typ.
Max.
60
Unit
Number
mA
1)
P_5.2.1
Required Output Capacitance
CVDDP
0.1
10
1)
Output Voltage including line

regulation
VDDPOUT
4.9
5.0
5.1
Iload < 90mA;Vs > 5.5V
P_5.2.3
Output Drop
Vs V DDPout
+400
mV
Iload < 70mA;

3V < Vs < 5.5V
P_5.2.4
Dynamic Load Regulation
VVDDPLOR -50
50
mV
1)
2 ... 70mA; C=470nF;

dI/dt=100mA/s
P_5.2.5
Dynamic Line Regulation
VVDDPLIR
25
mV
1)
P_5.2.6
-25
ESR < 1
P_5.2.2
Vs= 5.5 ... 20V;
dV/dt=5V/s
Power Supply Ripple Rejection PSSRVDDP 50
dB
1)
Vs= 13.5V; f=0 ...

1KHz; Vr=2Vpp
P_5.2.7
Over Voltage Detection
VDDPOV
5.05
5.4
Vs > 5.5V; Overvoltage

leads to SUPPLY_NMI
P_5.2.8
Under Voltage Reset
VDDPUV
2.4
2.7
Vs > 5.5V
P_5.2.9
Over Current Shutdown
IVDDPOC
90
180
mA
P_5.2.10
Data Sheet
65
Rev. 1.1, 2012-03-08
TLE9832
5.2.2
PMU Core Supply Parameters VDDC
Table 20
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
Number
Specified Output Current
IVDDC
30
mA
1)
only used as
internal core supply
P_5.2.11
Required Output Capacitance
CVDDC
0.1
10
2)
ESR < 1
P_5.2.12

regulation @ Active Mode
VDDCOUT
1.44
1.5
1.56
Iload < 40mA
P_5.2.13

regulation @ Stop Mode
VDDCOUT
0.89
0.95
1.15
Iload < 200A
P_5.2.14
VDDCLOR
-50
50
mV
2)
2 ... 30mA;
C=330nF;
dI/dt=100mA/s
P_5.2.15
VDDCLIR
-25
25
mV
2)
P_5.2.16
VDDP= 2.5 ... 5.5V;
dV/dt=5V/s
VDDCOV
1.61
1.68
Overvoltage leads to P_5.2.17

SUPPLY_NMI
Under Voltage Reset
VDDVUV
1.10
1.19
P_5.2.18
Over Current Shutdown
IVDDCOC
35
80
mA
P_5.2.19
1) VDDC is not intended to be used as external voltage regulator

Data Sheet
66
Rev. 1.1, 2012-03-08
TLE9832
5.2.3
VDDEXT Voltage Regulator 5.0V
Table 21
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note /
Test Condition
Number
P_5.2.20
Output Current
IVDDEXT
20
mA
1)
Output Capacitance
CVDDEXT
10
1000
nF
1)

regulation
VDDEXT
4.9
5.0
5.1
Iload < 20mA;Vs >
Output Drop
Vs-VDDEXT
VDDEXTLOR
VVDDEXTLIR
Power Supply Ripple Rejection1)
PSSRVDDEXT 50
ESR < 1
P_5.2.21
P_5.2.22
5.5V
+400
mV
1)
Iload < 20mA;

3V < Vs < 5.5V
P_5.2.23
-50
50
mV
1)
2 ... 20mA;
C=10nF;
dI/dt=10mA/s
P_5.2.24
-25
25
mV
Vs= 5.5 ... 20V;

dV/dt=5V/s
P_5.2.25
dB
Vs= 13.5V; f=0 ...
P_5.2.26
1KHz; Vr=2Vpp
VVDDEXTOV
5.05
5.4
Vs > 5.5V
P_5.2.27
P_5.2.28
Under Voltage Detection
VVDDEXTUV
2.6
2.9
2)
Over Current Diagnostic
IVDDEXTOC
25
70
mA
Vs > 3.0V
P_5.2.29

2) When the condition is met, the Bit VDDEXT_CTRL.VDDEXT_SHORT will be set
Data Sheet
67
Rev. 1.1, 2012-03-08
TLE9832
5.3
System Clocks
5.3.1
Oscillators and PLL
Table 22
Parameter
Symbol
Values
Min.
Unit
Typ.
Max.
Number
PMU Oscillators (Power Management Unit)
fLP_CLK1
14
18
22
MHz this clock is used at startup

and can be used in case the
PLL fails
P_5.3.1
Frequency of LP_CLK2 fLP_CLK2
70
100
130
kHz
this clock is used for cyclic

wake and cyclic sense
P_5.3.2
MHz
1)
Frequency of LP_CLK
CGU Oscillator (Clock Generation Unit Microcontroller)

Short term frequency
deviation
fTRIMST
-1.5%
+1.5%
with respect to nominal

P_5.3.3
configured system frequency
within one LIN message

(< 10ms ... 100ms)
Long term frequency

deviation
fTRIMLT
-3.0%
+3.0%
MHz with respect to nominal

P_5.3.4
configured system frequency
over lifetime and temperature
CGU-OSC Start-up
time
TOSC
10
startup time OSC from Sleep P_5.3.5

Mode and Stop Mode, power
supply stable
PLL (Clock Generation Unit Microcontroller)

VCO frequency range
Mode 0
fVCO-0
48
112
MHz VCOSEL =0
P_5.3.6
VCO frequency range

Mode 1
fVCO-1
96
160
MHz VCOSEL =1
P_5.3.7
Input frequency range
fOSC
16
MHz
P_5.3.8
XTAL1 input freq. range fOSC
16
MHz
P_5.3.9
0.04687
80
MHz
P_5.3.10
Free-running frequency fVCOfree_0

Mode 0
38
MHz VCOSEL =0
P_5.3.11
Free-running frequency fVCOfree_1

Mode 1
76
MHz VCOSEL =1
P_5.3.12
Output freq. range
fPLL
Input clock high/low

time
thigh/low
10
ns
P_5.3.13
Peak period jitter
tjp
-500
500
ps
for K=1
P_5.3.14
Data Sheet
68
Rev. 1.1, 2012-03-08
TLE9832
Table 22
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Number
Accumulated jitter
jacc
ns
for K=1
P_5.3.15
lock-in time
TL
200
P_5.3.16
1)
VDDC = 1.5 V, Tj = 25C
5.3.2
External Clock Parameters XTAL1, XTAL2
Table 23
Functional Range
Parameter
Symbol
Values
Max.
Unit Note /
Test Condition
-1.7 + VDDC
1.7
1)
P_5.3.17
0.3 x VDDP
2)
Peak-to-peak
voltage
P_5.3.18
0 V < VIN < VDDC
P_5.3.19
Min.
Input voltage range limits
for signal on XTAL1
VIX1_SR
Input voltage (amplitude) on VAX1_SR

XTAL1
Typ.
Number
XTAL1 input current
IIL
20
Oscillator frequency
fOSC
24
MHz Clock signal
P_5.3.20
Oscillator frequency
fOSC
16
MHz Crystal or
Resonator
P_5.3.21
High time
t1
ns
P_5.3.22
Low time
t2
ns
P_5.3.23
Rise time
t3
ns
P_5.3.24
Fall time
t4
ns
P_5.3.25
1) Overload conditions must not occur on pin XTAL1.

2) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the operation and
the resulting voltage peaks must remain within the limits defined by VIX1.
Data Sheet
69
Rev. 1.1, 2012-03-08
TLE9832
5.4
Flash Parameters
This chapter includes the parameters for the 36 kByte embedded flash module.
Table 24
Flash Characteristics 1)
Parameter
Symbol
Values
Unit
Note /
Number
Test Condition
Min.
Typ.
Max.
3.5
ms
P_5.4.1
4.5
ms
P_5.4.2
1,000 erase /
P_5.4.3
program cycles
Programming time per 128 Byte page
tPR
2)
Erase time per sector/page
tER
2)
Data retention time
tRET
20
years
Flash erase endurance for user sectors NER
30
kcycles Data retention

time 5 years
P_5.4.4
1) Not subject for production test, specified by design

2) Programming and erase times depend on the internal Flash clock source. The control state machine needs a few system
clock cycles. This requirement is only relevant for extremely low system frequencies.
Data Sheet
70
Rev. 1.1, 2012-03-08
TLE9832
5.5
Parallel Ports (GPIO)
5.5.1
Functional Range
Table 25
Functional Range
Parameter
Symbol
Values
Min.
IOH , IOL
Output current on any pin

Max output current for all GPIOs
Imax
Typ.
Max.
20
60
Unit
Note /
Test Condition
Number
mA
1) 2)
P_5.5.1
mA
1) 2)
P_5.5.2
1) One of these limits must be kept.

5.5.2
DC Parameters
These parameters apply to the IO voltage range, 4.5 V VDDP 5.5 V.

Note: Operating Conditions apply.
Keeping signal levels within the limits specified in this table ensures operation without overload conditions.
For signal levels outside these specifications, also refer to the specification of the overload current IOV.
Table 26
DC Characteristics
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note /
Test Condition
Number
Input low voltage

(all except XTAL1)
VIL
-0.3
0.3 x VDDP V
P_5.5.3
Input high voltage

(all except XTAL1)
VIH
0.7 x VDDP
VDDP + 0.3 V
P_5.5.4
Input Hysteresis1)
HYS
0.11 x VDDP
Series resistance P_5.5.5

=0
Output low voltage
VOL
1.0
2)
IOL IOLmax
P_5.5.6
2)
IOL
3)
P_5.5.7
IOH IOHmax
VOL
Output low voltage

4)
0.4
IOLnom
Output high voltage
VOH
VDDP - 1.0
2)
Output high voltage
VOH
VDDP - 0.4
2)3)
Input leakage current

(Port 2)
IOZ1
-400
+400
nA
TJ 85C,
0 V < VIN < VDDP
P_5.5.10

(all other)5)
IOZ2
-5
+5
TJ 85C,
0.45 V < VIN
< VDDP
P_5.5.11
Data Sheet
71
IOH IOHnom
P_5.5.8
P_5.5.9
Rev. 1.1, 2012-03-08
TLE9832
Table 26
DC Characteristics
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note /
Test Condition
Number

(all other)
IOZ2
-15
+15
TJ 150C,
0.45 V < VIN
< VDDP
P_5.5.12
Pull level keep current
IPLK
-240
+240
6)
VPIN VIH (up)

VPIN VIL (dn)
P_5.5.13
Pull level force current
IPLF
-1.5
+1.5
mA
6)
VPIN VIL (up)

VPIN VIH (dn)
P_5.5.14
Pin capacitance
(digital inputs/outputs)
CIO
10
pF
P_5.5.15

2) The maximum deliverable output current of a port driver depends on the selected output driver mode. The limit for pin
groups must be respected.
3) As a rule, with decreasing output current the output levels approach the respective supply level (VOLGND, VOHVDDP).
However, only the levels for nominal output currents are verified.
4) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float
and the voltage is determined by the external circuit.
5) The given values are worst-case values. In production test, this leakage current is only tested at 125C; other values are
ensured by correlation. For derating, please refer to the following descriptions:
Leakage derating depending on temperature (TJ = junction temperature [C]):
IOZ = 0.05 e(1.5 + 0.028TJ) [A]. For example, at a temperature of 95C the resulting leakage current is 3.2 A.
Leakage derating depending on voltage level (V = VDDP - VPIN [V]):
IOZ = IOZtempmax - (1.6 V) [A]
This voltage derating formula is an approximation which applies for maximum temperature.
6) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level: VPIN VIH for a pull-up; VPIN VIL for a pull-down.
Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled
pull device: VPIN VIL for a pull-up; VPIN VIH for a pull-down.
These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose
IO pins.
Data Sheet
72
Rev. 1.1, 2012-03-08
TLE9832
Table 27
Current Limits for Port Output Drivers1)
Port Output Driver Mode
Number
Maximum Output Current
Nominal Output Current
(IOLmax , - IOHmax)
VDDP 4.5V VDDP < 4.5V
(IOLnom , - IOHnom)
VDDP 4.5V VDDP < 4.5V
Strong Driver
7.5 mA
7.5 mA
2.5 mA
2.5 mA
P_5.5.16
Medium Driver
4 mA
2.5 mA
1.0 mA
1.0 mA
P_5.5.17
Weak Driver
0.5 mA
0.5 mA
0.1 mA
0.1 mA
P_5.5.18
Note: Stresses above the values listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only. Functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for an extended time may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < GND) the voltage on VDDP pins
with respect to ground (GND) must not exceed the values defined by the absolute maximum ratings.
Data Sheet
73
Rev. 1.1, 2012-03-08
TLE9832
5.6
LIN Transceiver
5.6.1
Table 28
Electrical Characteristics LIN Transceiver
Vs = 5.5V - 18V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin
Parameter
Symbol
Values
Min.
Typ.
Number
Max.
Bus Receiver Interface

Receiver threshold voltage, Vth_dom
recessive to dominant edge
Receiver dominant state
VBUSdom -27
Receiver threshold voltage, Vth_rec

dominant to recessive edge
Receiver recessive state
0.4 VS 0.45 VS 0.53 x VS V
VBUSrec
0.47 x
VS
SAE J2602
P_5.6.1
0.4 VS
LIN Spec 2.1 (Par. 17)
P_5.6.2
0.55 VS 0.6 VS
SAE J2602
P_5.6.3
0.6 VS
1)
LIN Spec 2.1 (Par. 18) P_5.6.4
0.525
VS
2)
LIN Spec 2.1 (Par. 19) P_5.6.5
Receiver center voltage
VBUS_CN 0.475
VS
T
Receiver hysteresis
VHYS
0.07 VS 0.12 VS 0.175

VS
3)
LIN Spec 2.1 (Par. 20) P_5.6.6
Wake-up threshold voltage
VBUS,wk
0.4 VS 0.5 VS
0.6 VS
P_5.6.7
15
To achieve the required P_5.6.8

wake-up time from
30 s to 150 s
according to LIN spec.,
an additional digital filter
is added (see PMU
chapter)
0.8 VS
VS
VTxD = high Level
P_5.6.9
40
100
150
mA
VBUS = 13.5 V
P_5.6.10
-70
VS = 0 V; VBUS = -12 V;
P_5.6.11
Dominant time for bus wake- tWK,bus

up
0.5 VS
1.15 VS V
Bus Transmitter Interface

Bus recessive output voltage VBUS,ro
Bus short circuit current
IBUS,sc
Leakage current
IBUS_NO_ -1000
GND
Leakage current
IBUS_NO_
10
20
VS = 0 V; VBUS = 18 V;
P_5.6.12
BAT
Leakage current
IBUS_PAS -1
Leakage current
IBUS_PAS
mA
VS = 18 V; VBUS = 0 V;
P_5.6.13
20
VS = 8 V; VBUS = 18 V;
P_5.6.14
_dom
_rec
Bus pull-up resistance
RBUS
20
30
47
Normal mode LIN Spec P_5.6.15

2.1 (Param. 26)
LIN input capacity
CLIN_IN
15
30
pF
4)
Data Sheet
74
P_5.6.80
Rev. 1.1, 2012-03-08
TLE9832
Table 28
Electrical Characteristics (contd) LIN Transceiver
Parameter
Symbol
Values
Min.
Typ.
Number
Max.
AC Characteristics - Transceiver Normal Slope Mode
td(L),R
0.1
(LIN Spec 2.1;

Param. 31)
P_5.6.16
td(H),R
Propagation delay
bus recessive to RxD HIGH
0.1
(LIN Spec 2.1;

Param. 31)
P_5.6.17
tsym,R = td(L),R - td(H),R;(LIN P_5.6.18

Spec 2.1; Param. 31)
Propagation delay
bus dominant to RxD LOW
Receiver delay symmetry
tsym,R
-2
Duty cycle D1
Normal Slope Mode
(for worst case at 20 kBit/s)
tduty1
0.396
5)
duty cycle 1
THRec(max) =
0.744 VS;
THDom(max) =
0.581 VS; VS = 5.5
18 V;
tbit = 50 s;
D1 = tbus_rec(min)/2 tbit;
P_5.6.19
Duty cycle D2
Normal Slope Mode
tduty2
0.581
6)
duty cycle 2
THRec(max) =
0.422 VS;
THDom(max) =
0.284 VS;
VS = 5.5 18 V;
tbit = 50 s;
D2 = tbus_rec(max)/2 tbit;
P_5.6.20
AC Characteristics - Transceiver Low Slope Mode
td(L),R
0.1
(LIN Spec 2.1;

Param. 31)
P_5.6.21
td(H),R
Propagation delay
0.1
(LIN Spec 2.1;

Param. 31)
P_5.6.22
-2
tsym,R = td(L),R - td(H),R;
P_5.6.23
Propagation delay
tsym,R
(LIN Spec 2.1; Param.

32)
Data Sheet
75
Rev. 1.1, 2012-03-08
TLE9832
Table 28
Parameter
Symbol
Values
Min.
Typ.
Max.
Number
Duty cycle D3
(for worst case at
10,4 kBit/s)
tduty1
0.417
7)
duty cycle 3
THRec(max) =
0.778 VS;
THDom(max) =
0.616 VS; VS = 5.5
18 V;
tbit = 96 s;
P_5.6.24
Duty cycle D4
(for worst case at
10,4 kBit/s)
tduty2
0.590
duty cycle 4
THRec(max) =
0.389 VS;
THDom(max) =
0.251 VS;
VS = 5.5 18 V;
tbit = 96 s;
P_5.6.25
AC Characteristics - Transceiver Fast Slope Mode
td(L),R
0.1
P_5.6.26
td(H),R
Propagation delay
0.1
P_5.6.27
-1
P_5.6.28
6)
P_5.6.29
Propagation delay
tsym,R
Duty cycle D5
tduty1
0.395
duty cycle 5
THRec(max) =
0.744 VS;
THDom(max) =
0.581 VS;
VS = 5.5 18 V;
tbit = 25s;
Duty cycle D6
tduty2
0.581
6)
0.1
0.5
P_5.6.30
duty cycle 6
THRec(max)= 0.422 VS;
THDom(max)=
0.284 VS;
VS = 5.5 18 V;
tbit = 25 s;
AC Characteristics - Flash Mode

Propagation delay
Data Sheet
td(L),R
76
P_5.6.31
Rev. 1.1, 2012-03-08
TLE9832
Table 28
Parameter
Symbol
Propagation delay
td(H),R
tsym,R
Values
Number
Min.
Typ.
Max.
0.1
0.5
P_5.6.32
-1.0
1.0
P_5.6.33
8)
Duty cycle D7
tduty1
for +1 s Receiver delay
symmetry
0.399
duty cycle D7
P_5.6.34
THRec(max) =
0.744 VS;
THDom(max) =
0.581 VS; VS = 13.5 V;
tbit = 8.7 s;
tduty2
Duty cycle D8
for +1 s Receiver delay
symmetry
0.578
6)
12
20
TxD dominant time out
ttimeout
ms
duty cycle 8
THRec(max) =
0.422 VS;
THDom(max) =
0.284 VS;VS = 13.5 V;
tbit = 8.7 s;
P_5.6.35
8)
P_5.6.36
VTxD = 0 V
1)
2)
3)
4)
5)
Maximum limit specified by design.

VBUS_CNT = (Vth_dom +Vth rec)/2
VHYS = VBUSrec - VBUSdom
This parameter is not subject to production test
Bus load concerning LIN Spec 2.1:
Load 1 = 1 nF / 1 k = CBUS / RBUS
Load 2 = 6.8 nF / 660 = CBUS / RBUS
Load 3 = 10 nF / 500 = CBUS / RBUS
6) Bus loads:
7) Bus load concerning LIN Spec 2.1:
Load 2 = 6.8 nF / 660 = CBUS / RBUS
Load 3 = 10 nF / 500 = CBUS / RBUS
8) Timeout can be disabled optional
Data Sheet
77
Rev. 1.1, 2012-03-08
TLE9832
5.7
High-Speed Synchronous Serial Interface
The table below provides the SSC timing in the TLE9832.

Table 29
SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Values
Min.
Typ.
Unit
Max.
Note /
Number
Test Condition
P_5.7.1
SCLK clock period
t0
1)
MTSR delay from SCLK
t1
10
ns
P_5.7.2
MRST setup to SCLK
t2
10
ns
P_5.7.3
MRST hold from SCLK
t3
15
ns
P_5.7.4
2 * TSSC
1) TSSCmin = TCPU = 1/fCPU. When fCPU = 24 MHz, t0 = 83.3 ns. TCPU is the CPU clock period.
t0
SCLK1)
t1
t1
MTSR1)
t2
t3
Data
valid
MRST1)
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_Tmg1
Figure 32
Data Sheet
SSC Master Mode Timing
78
Rev. 1.1, 2012-03-08
TLE9832
5.8
Measurement Unit
5.8.1
Analog Digital Converter 8-Bit
Table 30
DC Specifications ADC 8 Bit
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Number
Test Condition
Resolution
Bit
P_5.8.1
Offset error
-10
+10
mV
P_5.8.2
Gain single-ended input mode
GSE
P_5.8.3
Input voltage single-ended

mode
Vainp,Vainn 0
VDD1V5_A V
P_5.8.4
Gain differential input mode
GDF
1.24
P_5.8.5
Common input voltage in

differential mode
Vicm
VDDP/2
Vicm=(Vainp +
Vainn)/2
P_5.8.6
Gain error
-5
1.5
+5
%FSR
P_5.8.7
Differential nonlinearity (DNL)
-1.5
0.5
+1.5
LSB
P_5.8.8
Integral Nonlinearity (INL)
-3
1.5
LSB
P_5.8.9
0.5
0.6
+0.1
5.8.2
Measurement Unit (VBAT_SENSE - Supply Voltage Attenuator)
Table 31
Supply voltage signal conditioning
Parameter
Symbol
Values
Min.
Number
Typ.
Max.
20
Max. value corresponds P_5.8.10

to typ. ADC full scale input
289
380
PD_N=1 (on-state)
P_5.8.11
1.0
PD_N=0 (off-state),
VBAT_SENSE=13.5V
P_5.8.12
Battery Voltage Measurement VBAT_SENSE

Nominal operating input
voltage range1)
VS/BAT_SENSE
Measurement input
resistance
Rin,VS/VBAT_SENS 200
Measurement input
leakage current
Ileak
Overall (calibrated) measurement accuracy after A/D-conversion2)

VBAT_SENSE / Vs 8-bit ADC
VBATADC8B
VBAT_SENSE / Vs 10-bit ADC VBATADC10B
Data Sheet
-250
250
mV
Vs= 5.5V to 18V,

Tj = 40..85C
P_5.8.13
-200
200
mV
Vs= 5.5V to 18V,

Tj = 40..85C
P_5.8.14
79
Rev. 1.1, 2012-03-08
TLE9832
Table 31
Supply voltage signal conditioning
Parameter
Symbol
Values
Min.
Typ.
Max.
Number
VDD5_SENSE
VDDP_SENSE
-150
150
mV
P_5.8.15
VDD1V5_SENSE
VDDC_SENSE
-45
45
mV
P_5.8.16
1) This parameter is not subject to production test

2) The device is calibrated based on an external 1k resistor
5.8.3
Measurement Functions Monitoring Input Voltage Attenuator
Table 32
Monitoring input voltage attenuation
Parameter
Symbol
Values
Min.
Typ.
Max.
Number
Power Supply
Input resistance1)
RIN
300
400
500
PD_N=1 (on-state) VMON_X=0 P_5.8.17

to 18V if
VMON_SEN_SEL_INRANGE
=0
Input resistance
RIN
250
P_5.8.18
VMON_X =0 to 28V if
VMON_SEN_SEL_INRANGE
=1
>200 k under all other
conditions
30
This time frame is valid from

writing the corresponding
selection register to proper
settling of the voltage at
channel 7 of the 10-Bit ADC
P_5.8.19
Vs=5.5V to 18V,
Tj = 40..85C
P_5.8.20
Timing Characteristics
Analog Multiplexer Settling TMUXsettle
Time
Overall (calibrated) measurement accuracy after A/D-conversion

VMONx 10-bit ADC
VMONxAD -200
200
C10B
mV
Data Sheet
80
Rev. 1.1, 2012-03-08
TLE9832
5.8.4
Temperature Sensor Module
Table 33
Electrical Characteristics Temperature Sensor Module
VS = 5.5 V to 27 V, Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin
Parameter
Symbol
Values
Min.
Typ.
Unit
Number
P_5.8.21
Max.
Linear temperature range
TRANGE
-40
Output voltage VTEMP at

T0=273 K (0C)
Mode 1
0.4893
1)
DVBE_MODE=0
T=273K (0C)
P_5.8.22
Output voltage VTEMP at

T0=273 K (0C)
Mode 2
0.5365
DVBE_MODE=1
T0=273 K (0C)
P_5.8.23
Temperature sensitivity b in b
Mode 1
1.685
mV/K
1)
P_5.8.24
Temperature sensitivity b
Mode 2
1.834
mV/K
DVBE_MODE=1
P_5.8.25
Accuracy_12)
Acc_1
-10
10
-40C < Tj < 125C
P_5.8.26
Accuracy_2
Acc_2
-15
15
125C < Tj < 175C
P_5.8.27
175
DVBE_MODE=0

2) Accuracy with reference to on-chip temperature calibration measurement
Data Sheet
81
Rev. 1.1, 2012-03-08
TLE9832
5.9
ADC - 10-Bit
5.9.1
VAREF
5.9.1.1
Functional Range
Table 34
Functional Range
Parameter
Symbol
VAREF_IN
VAREF input voltage
Values
Min.
Typ.
Max.
Note /
Test Condition
VDDP+0.3 V
5.9.1.2
Table 35
10-Bit ADC - VAREF
Unit
Number
P_5.9.1
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Number
Output Capacitance
CVAREF
0.1
ESR < 1
P_5.9.2
Reference output voltage
VAREF
4.95
5.05
Vs > 5.5V
P_5.9.3
P_5.9.4
P_5.9.5
DC Supply voltage
rejection
DCPSRVAREF 30
dB
1)
Supply voltage ripple

rejection
ACPSRVAREF 26
dB
1)
Vs= 13.5V; f=0 ... 1KHz;

Vr=2Vpp
Turn ON time
tso
200
1)
P_5.9.6
Cext=100nF
PD_N to 99.9% of final value
(test setup: measure 1,
calculate 5.
Data Sheet
82
Rev. 1.1, 2012-03-08
TLE9832
5.9.2
Analog/Digital Converter Parameters
These parameters describe the conditions for optimum ADC performance.

Note: Operating Conditions apply.
Table 36
A/D Converter Characteristics
VS = 5.5 V to 27 V, Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin
Parameter
Analog reference supply
Symbol
VAREFSR
Values
Min.
Typ.
Max.
Unit Note /
Number
Test Condition
VAGND
VDDPA
1)
P_5.9.7
+ 1.0
Analog reference ground
VAGNDSR
GND
+ 0.05
1.5
2)
P_5.9.8
VAREF
3)
P_5.9.9
MHz
4)
P_5.9.10
- 0.05
Analog input voltage range VAIN
VAGND
Analog clock frequency
fADCI
0.5
Conversion time for 10-bit

result5)
tC10
(13 + STC) (13 + STC) (13 + STC)

tADCI
tADCI
tADCI
+ 2 x tSYS + 2 x tSYS + 2 x tSYS
P_5.9.11
Conversion time for 8-bit

result
tC8
(11 + STC) (11 + STC) (11 + STC)

tADCI
tADCI
tADCI
+ 2 tSYS + 2 tSYS + 2 tSYS
P_5.9.12
Wake-up time from analog

Stop Mode, fast mode
tWAF
6)
P_5.9.13
Wake-up time from analog

Stop Mode, slow mode
tWAS
15
6)
P_5.9.14
Total unadjusted error7)
TUE
-15
+ 15
LSB
1)
20
VAREF =
P_5.9.15
5.0 V1%
DNL error
EADNLEA
-2
+2
LSB
P_5.9.16
INL error
EAINLEA
-5
+5
LSB
P_5.9.17
Gain error
EAGAINEA
-10
+ 10
LSB
P_5.9.18
Offset error
EAOFFEA
-2
+2
LSB
P_5.9.19
Total capacitance
of an analog input
CAINT
10
pF
6)8)
Switched capacitance
of an analog input
CAINS
pF
6)8)
P_5.9.21
Resistance of
the analog input path
RAIN
6)8)
P_5.9.22
Total capacitance
of the reference input
CAREFT
15
pF
6)8)
P_5.9.23
Switched capacitance
of the reference input
CAREFS
pF
6)8)
P_5.9.24
Resistance of
the reference input path
RAREF
6)8)
P_5.9.25
Data Sheet
83
P_5.9.20
Rev. 1.1, 2012-03-08
TLE9832
1)TUE is tested at VAREF = 5V1%, VAGND = 0 V. It is verified by design for all other voltages within the defined
voltage range.
The specified TUE is valid only if VAREF and VAGND remain stable during the measurement time.
2) Only valid in case of external supplied reference voltage.
3) VAIN may exceed VAGND or VAREFx up to the absolute maximum ratings. However, the conversion result in these cases will
be 000H or 3FFH, respectively.
4) The limit values for fADCI must not be exceeded when selecting the peripheral frequency and the prescaler setting.
5) This parameter includes the sample time (also the additional sample time specified by STC), the time to determine the
digital result and the time to load the result register with the conversion result.
7) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual errors.
All error specifications are based on measurement methods standardized by IEEE 1241.2000.
8) These parameter values cover the complete operating range. Under relaxed operating conditions (temperature, supply
voltage) typical values can be used for calculation. At room temperature and nominal supply voltage the following typical
values can be used:
CAINTtyp = 12 pF, CAINStyp = 5 pF, RAINtyp = 1.0 k, CAREFTtyp = 15 pF, CAREFStyp = 10 pF, RAREFtyp = 1.0 k.
Data Sheet
84
Rev. 1.1, 2012-03-08
TLE9832
5.10
High-Voltage Monitor Input
Table 37
Parameter
Symbol
Values
Min.
Typ.
Max.
0.4*Vs
0.5*Vs
0.6*Vs
Number
P_5.10.1
Input Pin characteristics

Wake-up/monitoring threshold VMONth
voltage
Threshold hysteresis
VMONth,hys 0.02*Vs 0.06*Vs 0.12*Vs V
without external serial

resistor Rs (with Rs:
V = IPD/PU * Rs);
P_5.10.2
in all modes; without
external serial resistor Rs
(with Rs: V = IPD/PU * Rs);
Pull-up current
IPU, MONx
MONx_CTRL_STS.MONx_PU
= high
MONx_CTRL_STS.MONx_PD
= low
-20
-10
-1
0 V < VMON_IN < Vs - 2 V
P_5.10.3
Pull-up current
IPU, MONx
= high
= high
-20
-10
-1
0.6*Vs < VMON_IN < Vs 2V
P_5.10.4
IPD, MONx
Pull-down current
= low
= high
10
18
2 V < VMON_IN < Vs
P_5.10.5
Pull-down current
IPD, MONx
= high
= high
10
18
2 V < VMON_IN < 0.4*Vs
P_5.10.6

ILK,I
= low
= low
-2
0 V < VMON_IN < 28 V
P_5.10.7
The Parameters of the analog measurement are listed in the chapter Measurement Interface.
Data Sheet
85
Rev. 1.1, 2012-03-08
TLE9832
5.11
High Side Switch
5.11.1
Functional Range
Table 38
Functional Range
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
Number
Nominal Operating Voltage
VS
5.5
27
P_5.11.1
Current range for Sleep

Mode / Stop Mode
IHS max
40
mA
Cyclic Sense Mode
P_5.11.2
sleep_pd
PWM frequency of HS with

Slew Rate Control
fPWM_W_SR
10
kHz
1)
PWM frequency of HS
without Slew Rate Control
fPWM_W/O_SR 0
252)
kHz
1)
Frequency must be P_5.11.3

configured in the
PWM Generator
Frequency must be P_5.11.4
configured in the
PWM Generator

2) referring to a 47ohm series resistor to charge an external power mos gate
5.11.2
Table 39
Parameter
Symbol
Values
Number
Min.
Typ. Max.
VHSxOUT
-0.3
VS
min. value referred to

GND_A
P_5.11.5
RON
20
VS =5.5 to 27 V,
P_5.11.6
Maximum ratings
Output voltage
Output HS
ON-State Resistance
Ids=100mA, higher
resistance below VS =5.5V
Output leakage Current
Ileakage
Output Slew Rate (rising) with SRraise_w_SR

Slew Rate Control
Data Sheet
10
V/s 10% to 90% of VS

VS = 9 to 18V
RL =3001)
86
Output OFF
0 V < VXLO < VS;
Tj < 85 C
P_5.11.7
P_5.11.8
Rev. 1.1, 2012-03-08
TLE9832
Table 39
Electrical Characteristics (contd)
Parameter
Symbol
Values
Number
Min.
Typ. Max.
-10
-1

VS = 9 to 18V
RL =3001)
P_5.11.9
Output Slew Rate (falling)

with Slew Rate Control
SRfall_w_SR
Output Slew Rate (rising)

SRraise_w/o_SR 25
60

VS = 9 to 18V
RL =3001)
P_5.11.10

SRfall_w/o_SR
30
-10

VS = 9 to 18V
RL =3001)
P_5.11.11
Turn ON Delay time
tIN-HS
ON = 1 to 10% of VS
RL =300
P_5.11.12
Turn ON time
tON
15
VS =13.5V
HS_ON=1 to 90% of VS
RL =300
Tj =25C
P_5.11.13
Turn OFF time
tOFF
15
VS =13.5V
HS_ON= 0 to 10% of VS
RL =300;
Tj =25C
P_5.11.14
Load current limitation
Ishort
-1.2
1)
VS =27V, VHS=0V,
max duration 200 s
P_5.11.15
Overcurrent threshold 0
Iocth0
18
mA
1)
HSx_OC_SEL =00
P_5.11.16
hysteresis
Iocth0,hyst
mA
1)
HSx_OC_SEL =00
P_5.11.17
Iocth1
50
75
mA
HSx_OC_SEL =01
P_5.11.18
P_5.11.19
Over-current detection
hysteresis
Iocth1,hyst
15
mA
1)
Iocth2
100
150
mA
HSx_OC_SEL =10
P_5.11.20
hysteresis
Iocth2,hyst
10
30
mA
1)
P_5.11.21
Iocth3
150
220
mA
HSx_OC_SEL =11
P_5.11.22
P_5.11.23
hysteresis
Iocth3,hyst
Overall over-current filter time tocft
HSx_OC_SEL =01
HSx_OC_SEL =10
20
50
mA
1)
80
1)
P_5.11.24
VS =13.5V,
RL =100, HS_ON to
OC_SD (including switchon time)
18
mA
1)
HSx_OC_SEL =11
ON-state open load detection

Open load threshold
Data Sheet
IOLONth
87
OL_EN = 1; HS_ON = 1 P_5.11.25

Rev. 1.1, 2012-03-08
TLE9832
Table 39
Parameter
Symbol
Values
Number
Min.
Typ. Max.
0.5*
VS
0.67 0.85* V
*VS VS
IOL_test; open load
VOLhys
0.1*
IOL_SEL = 1
P_5.11.28
Open load output current
IOL_test
-150
-25
IOL_SEL = 0
P_5.11.29
Open load output current
IOL_test
-1.5
-0.5
mA
IOL_SEL = 1
P_5.11.30
ON-State Resistance
RON,static
40
Definition:
differential resistance or
resistance at 40 mA
P_5.11.31
Output Slew Rate (rising)
SRrise 1)

VS = 9 to 18V
RL =300 1)
P_5.11.32
SRfall1)
-1

VS = 9 to 18V
RL =300
P_5.11.33
Delay Time CYCLIC_ON-HS tIN-CYC
ON =1 to 10% of VS
RL=300
P_5.11.34
Hysteresis
IOLONhys
mA
1)
OL_EN = 1; HS_ON = 1 P_5.11.26
Off-state open load detection

Open load voltage threshold
Hysteresis
VOLth1
0.3*
VS
P_5.11.27
activated; OLTH_SEL = 1
VS
Cyclic sense mode
Turn-ON time
tON
15
VS =13.5V
ON=1 to 90%
RL =300
P_5.11.35
Turn-OFF time
tOFF
15
VS =13.5V
ON=0 to 10% of VS
RL =300;
Tj=25C
P_5.11.36
Data Sheet
88
Rev. 1.1, 2012-03-08
TLE9832
5.12
Low Side Switches
5.12.1
Functional Range
Table 40
Functional Range
Parameter
Symbol
Nominal Operating Voltage VS

PWM Frequency of LS
fPWM
Values
Unit
Min.
Typ.
Max.
5.5
27
1)
25
Number
P_5.12.1
kHz
2)
P_5.12.2
1) referring to a 47ohm series resistor to charge an external power mos gate

Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
5.12.2
Table 41
Parameter
Symbol
Values
Min.
Typ.
Max.
Number
P_5.12.3
Overcurrent Limitation
ILSTyp
175
250
325
mA
ON-State Resistance 150C
RON
10
VS > 5.5 V, Ids =100mA,

Tj = 150C
P_5.12.4
Tj = 25C
P_5.12.5
ON-State Resistance 25C

Leakage Current
Ileakage
0 V < VLS < VS;

Tj < 85C
P_5.12.6
Turn ON Delay time, slow mode
tdOn-LS
50
1)
P_5.12.7
Turn ON Delay time, PWM mode tdOn,f-LS
LS_ON=1 to 0.9*Vs
VS=13.5V, RL =270
0.5
LS_ON=1 to 0.9*Vs
VS=13.5V, RL =270
P_5.12.8
Turn ON fall time, PWM mode
tONF,PWM
1.25
VLS 0.9*Vs to 0.1*Vs

VS=13.5V, RL =270
P_5.12.9
Turn ON fall time, slow mode
tONF,Slow
100
150
1)
VLS 0.9*Vs to 0.1*Vs

VS=13.5V, RL =270
P_5.12.10
50
1)
P_5.12.11
Turn OFF Delay time, slow mode tdOff-LS
Data Sheet
LS_ON=0 to 0.1*Vs
VS=13.5V, RL =270
89
Rev. 1.1, 2012-03-08
TLE9832
Table 41
Parameter
Symbol
Values
Number
Min.
Typ.
Max.
LS_ON=0 to 0.1*Vs
VS=13.5V, RL =270
P_5.12.12
Turn OFF Rise time, PWM mode tOFFR,PWM
1.25
VLS 0.1*Vs to 0.9*Vs;

VS=13.5V, RL =270
P_5.12.13
100
150
1)
VLS 0.9*Vs to 0.9*Vs;

VS=13.5V, RL =270
P_5.12.14
Turn OFF Delay time, PWM

mode
Turn OFF Rise time, slow mode
tdOff,f-LS
tOFFR,Slow
Minimum Duty Cycle Pulse Width tonMIN

variation
1.5
3.5
ton(dig) = 2s2)
P_5.12.15
Typical (systematic) Pulse Width d tonTYP

increase LS_ON to VLS
1.25
ton(dig) = 2s2)
P_5.12.16
Zener Clamp Voltage
VAZ
50
values are valid at

Tj = 25C
P_5.12.17
Clamping Energy (repetitive)
Eclamp
mJ
2)
1.000.000 cycles
P_5.12.18
mJ
2)
Tstart = 25C
P_5.12.19
mJ
2)
10 cycles, Tstart = 85C P_5.12.20
Clamping Energy
Clamping Energy (single), hot
Eclamp
Eclamp
14
1) Static ON mode (no PWM)

Data Sheet
90
Rev. 1.1, 2012-03-08
TLE9832
Package Outlines
Package Outlines
0.9 MAX.
(0.65)
0.5
0.4 x 45
Index Marking
(5.2)
37
26
48x
0.08
36
25
24
(6.2)
0.5
+0.03
0.
6.8
11 x 0.5 = 5.5
6.8
11 x 0.5 = 5.5
0.4 0.07
48
13
12
15
(0.2)
0.23 0.05
(5.2)
0.
SEATING PLANE
7 0.1
7 0.1
Index Marking
48x
0.1 M A B C
.0
0.05 MAX.
(6.2)
PG-VQFN-48-15, -19, -20, -22, -24, -48, -51, -52, -53, -54, -55, -56, -57-PO V12
0.10.03
48
1
12
5)
.3
Index Marking
37
13
(0
0.4 x 45
36
25
24
(5.2)
48x
0.08
1) Vertical burr 0.03 max. all sides
0.5
0.23 0.05
(5.2)
(0.2)
0.05 MAX.
(6)
0.5
+0.03
0.10 0.05
1)
11 x 0.5 = 5.5
6.8
11 x 0.5 = 5.5
0.5 0.07
6.8
SEATING PLANE
7 0.1
0.9 MAX.
(0.65)
0.15 0.05
Package outline TLE9832QV, VQFN-48-22
7 0.1
Figure 33
Index Marking
48x
0.1 M A B C
(6)
PG-VQFN-48-29, -31-PO V01
Figure 34
Package outline TLE9832QX, VQFN-48-29
Notes
1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page Products:
http://www.infineon.com/products.
2. Dimensions in mm.
Data Sheet
91
Rev. 1.1, 2012-03-08
TLE9832
Revision History
Revision History
Revision
Date
Changes
1.1
2012-03-08
Editorial Changes
1.1
2012-03-08
Added full package name (VQFN-48-22)
1.1
2012-03-08
Table 4: VDD1V5P: Power Mode configurations: added comment: "Power Down

Supply"
1.1
2012-03-08
Table 5: Description of PMU Submodules: PMU-CYCMU description added and

PMU-CMU changed from cyclic to clock management
1.1
2012-03-08
Table 30: Changed Value Max. from parameter Common input voltage in
differential mode from VDD to VDDP
1.1
2012-03-08
Table 23: Changed Value Min. from parameter Input voltage (amplitude) on
XTAL1 from 0.3xVDDI to 0.3xVDDP
1.1
2012-03-08
Table 41: for Turn ON..., Turn OFF... Parameters changed Test condition from
RL =1k to RL =270
1.1
2012-03-08
Table 14:
- Removed max from the symbol suffixes
- Corrected Symbol of Parameter Input voltage at LIN from VMONx to VLIN
1.1
2012-03-08
Table 41: Parameter Overcurrent Limitation:

- Renamed Parameter from Typical on-state current to Overcurrent Limitation.
- Added min. (175mA) and max (325mA) values
- Removed Parameter Overcurrent threshold accuracy. This information is
added in the Note/Test Condition of the Parameter Overcurrent Limitation
1.1
2012-03-08
Table 19:
- Renamed Parameter Output Current to Specified Output Current
- Renamed Parameter Output Capacitance to Required Output Capacitance
1.1
2012-03-08
Table 20:
- Renamed Parameter Output Current to Specified Output Current
- Renamed Parameter Output Capacitance to Required Output Capacitance
- Parameter Dynamic Line Regulation: Correct typo in Note/Test Condition
from VDDC to VDDP
- Parameter Output Voltage including line regulation @ Stop Mode: Value Max.
changed from 1.01 to 1.15
1.1
2012-03-08
Figure 31: Application Diagram updated
1.1
2012-03-08
Figure 29: Modul Block Diagram updated (replaced 500mA by 250mA)
1.1
2012-03-08
Table 27: Change Maximum Output Current to Nominal Output Current in third
row
1.1
2012-03-08
Table 14: Added Output voltage VDDP for t < 100ms, in Stop Mode only
1.1
2012-03-08
Chapter 4.1: Added disclaimer note
1.1
2012-03-08
Table 11: Changed value CVDDEXT of blocking capacitor at VDDEXT pin to100nF
(from 10nF)
1.1
2012-03-08
Table 11 and Table 12: Changed headline from External Component

Requirements to External Component Recommendation
Data Sheet
92
Rev. 1.1, 2012-03-08
TLE9832
Revision History
Revision
Date
Changes
1.1
2012-03-08
Table 14:
- Renamed Parameter Output voltage VDDP to Voltage VDDP (2x)
- Renamed Parameter Output voltage VDDC to Voltage VDDC
1.1
2012-03-08
Table 28: Added value LIN input capacity CLIN_IN
Trademarks of Infineon Technologies AG

AURIX, C166, CanPAK, CIPOS, CIPURSE, EconoPACK, CoolMOS, CoolSET,
CORECONTROL, CROSSAVE, DAVE, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPIM,
EiceDRIVER, eupec, FCOS, HITFET, HybridPACK, IRF, ISOFACE, IsoPACK, MIPAQ,
ModSTACK, my-d, NovalithIC, OptiMOS, ORIGA, PRIMARION, PrimePACK, PrimeSTACK,
PRO-SIL, PROFET, RASIC, ReverSave, SatRIC, SIEGET, SINDRION, SIPMOS,
SmartLEWIS, SOLID FLASH, TEMPFET, thinQ!, TRENCHSTOP, TriCore.
Other Trademarks
Advance Design System (ADS) of Agilent Technologies, AMBA, ARM, MULTI-ICE, KEIL,
PRIMECELL, REALVIEW, THUMB, Vision of ARM Limited, UK. AUTOSAR is licensed by AUTOSAR
development partnership. Bluetooth of Bluetooth SIG Inc. CAT-iq of DECT Forum. COLOSSUS,
FirstGPS of Trimble Navigation Ltd. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG.
FLEXGO of Microsoft Corporation. FlexRay is licensed by FlexRay Consortium. HYPERTERMINAL of
Hilgraeve Incorporated. IEC of Commission Electrotechnique Internationale. IrDA of Infrared Data
Association Corporation. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of
MathWorks, Inc. MAXIM of Maxim Integrated Products, Inc. MICROTEC, NUCLEUS of Mentor Graphics
Corporation. Mifare of NXP. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. muRata
of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc.,
OmniVision of OmniVision Technologies, Inc. Openwave Openwave Systems Inc. RED HAT Red Hat, Inc.
RFMD RF Micro Devices, Inc. SIRIUS of Sirius Satellite Radio Inc. SOLARIS of Sun Microsystems, Inc.
SPANSION of Spansion LLC Ltd. Symbian of Symbian Software Limited. TAIYO YUDEN of Taiyo Yuden
Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tektronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA.
UNIX of X/Open Company Limited. VERILOG, PALLADIUM of Cadence Design Systems, Inc. VLYNQ
of Texas Instruments Incorporated. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of
Diodes Zetex Limited.
Last Trademarks Update 2011-02-24
Data Sheet
93
Rev. 1.1, 2012-03-08
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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TLE9832

Microcontroller with LIN and Power Switches for Automotive Applications

General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Rev. 1.1, 2012-03-08

Rev. 1.1, 2012-03-08

Rev. 1.1, 2012-03-08

Device Types / Ordering Information

High Voltage Flash Size

Rev. 1.1, 2012-03-08

Arithmetic Logic Unit

Capture Compare Unit 6

Clock Generation Unit

Cyclic Management Unit

Device Access Port

Data Post Processing

Error Correction Code

Electrically Erasable Programmable Read Only Memory

General Purpose Input Output

Full Scale Range

Interrupt Control Unit

Internal Random Access Memory - Internal Data Memory

Low DropOut voltage regulator

Local Interconnect Network

Least Significant Bit

Micro Controller Unit

Multiplication Division Unit

Monitor Mode Control

Most Significant Bit

Non Maskable Interrupt

On Chip Debug Support

One Time Programmable

Power Control Unit

Power supply Generation Unit

Phase Locked Loop

Power Management Unit

Program Status Word

Pulse Width Modulation

Random Access Memory

Reset Control Unit

Reset Management Unit

Rev. 1.1, 2012-03-08

Read Only Memory

Special Function Register

Short Open Window (for WDT1)

Serial Peripheral Interface

Synchronous Serial Channel

System Status Unit

Test Mode Select

Universal Asynchronous Receiver Transmitter

Universal Digital Controller for ADC1

Voltage reference Band Gap

Wake-up Management Unit

On-Chip eXternal Data Memory

On-Chip eXternal Special Function Register

Rev. 1.1, 2012-03-08

General Device Information

General Device Information

P2. 1/AN1/CCPOS0_0/EXINT 1_0/T12HR_1/CC61_1 37

23 P0. 3/SCK_0/EXINT1_2/T0/ CCPOS0_1/EXF21_2