Design and Implementation of PRBS Generator Using VHDL 2009-10

CHAPTER 1

BASIC CONCEPT
AND
LITERATURE SURVEY

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1. Basic Concept and literature Survey

1.1 Basic Concept

1.1.1. PRBS Generator Circuits

Fig 1 shows two equivalent shift-register circuits for generating pseudo-random sequences.
Version 1a (sometimes called the Fibonacci circuit for no apparent reason) is commonly found in
textbooks, with feedback through an XOR tree back to the input. The tappings shown are at stages
4, 5 and 6.

Typing "PRBS 4 5 6" at the command line shows that the circuit has a cycle-length of 31,
compared to a maximum possible of 63 for a 6-stage shift register. A shift register of n stages has
a maximum possible cycle-length of 2^n-1. The all-zero state is forbidden, hence the "-1".

Version 1b (sometimes called the Galois circuit for no apparent reason) is better. Some
advantages over the Fibonacci circuit are;

1. Better for high clock speeds because there isn't a buildup of propagation delays through an
XOR tree.
2. The basic hardware module shown in Fig 1b can be simply cascaded to make longer
registers.
3. Any tapping list can be easily programmed in hardware and can be altered dynamically.
4. In software, the execution time is independent of the number of tappings.

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Also, from version 1b we can easily see how the circuit can be represented by a polynomial. The
circuit is really a multiplier that multiplies its own output (fed back) by a polynomial function.
The taps 4, 5, 6 give a polynomial;

D^6 + D^5 + D^4 + 1

Where D represents one clock-delay. Thus the output contains itself (1 = zero delay) plus
previous outputs delayed by 4,5 and 6 clocks, all added modulo-2, by XOR gates. This
polynomial can be represented by its coefficients as the GF2 number (1110001), where the higher
bits 111000 represent real physical tappings.

Just to add to the confusion, electronic engineers tend to think in terms of fig 1a, with the output
taken from the highest stage. All the tapping lists used by the programs are numbered this way.
The tapping list for the example above would be written as 4 5 6 as mentioned above. Internally,
the programs use the Galois ordering because the code runs very much faster, though it is harder
to understand.

From fig 1, you can see that it is very easy to convert a circuit from the first form to the second
form. Because the stages are numbered in opposite directions, the tapping list works out the same.
In general the two versions don't go through the same sequence of states. However, with the
appropriate initial states they will have the same cycle length and the same sequence of output
bits.

And how do we choose the initial state? In all the programs described below, the initial state is a 1
pushed into the least significant bit (LSB, or stage 1) of the register, with all other stages set to
zero. We find that this will always give the longest possible cycle length that the tapping list will
allow. Why? Dunno. Sorry about that.

The next problem is to decide whether this polynomial will give a maximal length sequence. This
is what most of the rest of this mini-tutorial will cover.

1.1.2. Maximal-length

Program PRMAX.C generates all possible tapping polynomials for a given register length (n) and
applies the following four tests. If the polynomial passes all tests, it gives a maximal-length
sequence and the tapping list is printed.

TEST 1: Checks the number of tappings. We need an even number of taps (odd number of
polynomial coefficients.) This test eliminates 50% of all polynomials, so it is done first. Knowing
this, we could have seen that Fig 1 is non-maximal by inspection. (Note that the feedback
connection from/to stage 6 counts as a tapping.)

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TEST 2: Checks the mirror-image of the polynomial. Each polynomial has an equivalent
reversed version and there is no need to test these. Also, we reject symmetrical polynomials.
There aren't many of these, but they are never maximal-length for PRBS generators of more than
2 stages.

TEST 3: Tests the polynomial for primality, also known as "irreducibility". This is done the hard
way, by dividing it by successive GF2 primes, exactly as you would test a real number. A file of
GF2 primes, up to 20 bits, is provided. This is enough to factorise polynomials of up to 40 terms
(registers of up to 39 stages). Actually this operation is quite fast, as most factors are very small,
so are quickly found.

TEST 4: Tests the prime polynomials for maximal cycle-length (ref 3). This is done by finding
the smallest exponent e such that 2^e-1 can be exactly divided by the polynomial. If the smallest e
is 2^n-1 then the polynomial is maximal-length (also known as "primitive"). This test can be quite
slow because we may be dividing the polynomial into a number with millions of bits. PRMAX.C
incorporates a little hack that reduces the amount of work involved, but nevertheless it is still slow
for large n, though much faster than a direct shift-register simulation.

For example, if n=7 stages, then 2^n-1=127. This means values of e up to 127 have to be tested.
For e=127, the dividend is 2^127-1 which is a number like (100...001) with 128 digits. However,
this can be divided by (11), leaving (111...111) with 127 digits. Also it may be possible to take a
factor out of 2^n-1, which reduces the number of digits.

Test 4 consists of dividing the shift-register polynomial into this stream of ones. This means that
each stage of the division performs the test for one value of e. The division is complete when the
remainder becomes zero. If the division runs all the way to the end before completing, then the
polynomial is primitive.

1.1.3. Size

The calculation in PRMAX.C is much quicker if you use a shift register with a prime number of
stages.

If the register length is one of 2,3,5,7,13,17,19,31,61,89,107,127 etc, the exponent e is a

"Mersenne prime", and test 4 isn't needed. Even so, please don't waste your life trying to calculate
127-stage shift registers! If you want to know about Mersenne primes and other number-theoretic
stuff, ref 4 is a good place to start.

Other prime number register lengths are also good because the exponent is a "Mersenne number"
and can be reduced by removing a large factor, so the cycle-length test can be reasonably quick.
Below these come odd-number non-prime register lengths.

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Program PRMAX.C will do best for these last three cases in longer registers. In shorter registers
program PRX.C will generally do best.

Even-number register lengths seem to be the worst for cycle-length testing. If you don't absolutely
need an even number, you'll get many more maximal-length sequences by going to the next odd-
number length above. Program PRX.C will probably do best for this case for short and medium
length registers.

My aim was to build a PRBS that:

1. Is easier to use
2. Avoids all those duplicate "random" numbers when using the Randomize and Rnd
methods,
3. DOESN'T use or rely on Randomize and Rnd (for anything),
4. Doesn't rely on Internal Random Number tables,
5. Produces acceptable randomness (see the test result below), and
6. Gives me peace of mind.

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1.2 Literature Survey

1.2.1 Galois-Field Arithmetic

Galois-field (or "finite-field") arithmetic is just one of the many forms of arithmetic that have
been invented over the years. It so happens that this one has found a practical application.

Surprisingly, doing "arithmetic on the Galois field (2)" as mathematicians like to call it is very
easy. Even easier, in fact than real-number arithmetic. I shall refer to it as GF2 arithmetic. The 2
signifies that it uses binary digits. Really these are bit-patterns or the coefficients of polynomials,
but it won't hurt to call them numbers.

Addition and subtraction are both done with exclusive-OR, so they are identical. There is no sign
or carry or overflow to worry about in GF2 arithmetic!

Example, subtract (1101) from (1011011);

1011011
1101
----------
1010110

We need subtraction when doing long-division, of course. The method is exactly like we learned
in primary school, though Miss Davies wouldn't approve of this "carryless" form of arithmetic.

Example, divide (1011011) by (1101);

1011011 dividend
1101 can subtract divisor, first digit=1
--------
110
1100 bring down 0
1101 can subtract divisor, second digit=1
--------
1 bring down 1
11 can't subtract divisor, third digit=0, bring down 1
111 can't subtract divisor, fourth digit=0 stop here, no more digits left

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Thus the quotient is (1100) and the remainder is (111).

Let's check this by multiplying it out, exactly like we did it in school;

1100 quotient
1101 divisor
-------------
1100 partial products
1100
1100
-------------
1011100 add partial products
111 add remainder
--------------
1011011 result!

Long division is needed for factorization, which works pretty much like the real-arithmetic
equivalent.

1.2.2 MUGI

MUGI is a pseudorandom number generator (PRNG) used as a stream cipher. The design aims to
be suitable for both software and hardware implementations. MUGI has two independent
parameters as input. The first one is a 128- bit secret key while the second one is a 128-bit initial,
public, vector. MUGI generates a 64-bit length random bit string in each round. Since the MUGI
is a PANAMA-like [6] stream cipher it consists of four main operational modules. As the Fig. 2
shows, similar to PANAMA, the Internal State is divided into two parts, State a and Buffer b. Fig.
2. A PANAMA-like stream cipher The Update Function is divided in proportion to the internal
state. Note that each update function uses another internal state as a parameter. We denote the
update function of State a and Buffer b as ñ and ë function respectively. The output filter f
abstracts some bits of State a for each round.

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1.2.3 Elliptic Curves

Elliptic Curves (EC) are not ellipses. They are so named because they are described by cubic
equations, similar to those used for calculating the circumference of an ellipse. In general, cubic
equations for elliptic curves (Weierstrass equation) take the form

The variables x and y and the constants a1, a2, a3, a4, a5 and a6 range over any given algebra that
meet field axioms. Also included in the definition of an elliptic curve is a single element denoted
by O and called the ‘point at infinity’ or the ‘zero point’. The points on an elliptic curve form an
abelian group under a EC addition operation.

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CHAPTER 2

INTRODUCTION

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2. Introduction

2.1 Resilience
The word “resilience” means the ability to adapt well to stress. It means that, overall you remain
stable and maintain healthy levels of physical functioning in the face of disruption or chaos.

A resilient network is a network, which does not fail under any circumstances. Failure refers to a
situation where the observed behaviour of a system differs from its specified behaviour. A failure
occurs due to an error, caused by a fault. Faults can be hard or soft. For example a cable break is a
hard failure whereas an intermittent noise in the network is a soft failure.

Resilience in the context of resilient network is the ability of the network, a device on the
network, or a path on the network to respond to failure, resist failure, handle flux in demand and
easily shift and configure – with little or no impact on service delivery. A resilient network is the
agent that can help to diminish the loss of employee productivity in the event of a major disaster.

2.2 Need For Resilient Network

Businesses in all the industries are becoming dependent on Information Technology (IT) and the
intra- and inter- organizational online communication and collaboration it enables. Digitization
and workforce mobilization, automation and embedded computing have changed the way
enterprises do business and interact with their customers, employees and business partners. The
requirements for business infrastructure have also changed. Business infrastructure must provide
a stable IT foundation for the internal organization as well as allow integration with a virtual
value chain of suppliers and customers. To effectively support the needs of today’s businesses,
business infrastructure must, in effect, be RESILIENT. Resilient implies flexible and adaptive yet
at the same 3 time fortified against all types of threats. Resilient network design is the key
component of Resilience.

Resilient networks incorporate many of the elements of a highly available network. The resilient
network architecture should include redundant (multiple) components that can take over the
function of one another if one should fail. How the network, device or path reacts to failure
should be determined before hand so that predictable network, device or path are present after
response to failure.

2.3 Types Of Failures

1. Single point failure: It indicates that a system or a network can be rendered inoperable, or
significantly impaired in operation, by the failure of one single component. For example, a

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single hard disk failure could bring down a server; a single router failure could break all
connectivity for a network.

2. Multiple points of failure: It indicates that a system or a network can be rendered

inoperable through a chain or combination of failures. For example, failure of a single
router plus failure of a backup modem link could mean that all the connectivity is lost for
a network. In general it is much more expensive to cope with multiple points of failure and
often financially impractical.
Disaster recovery is the process of identifying all potential failures, their impact on the network as
a whole, and planning the means to recover from such failures. In our project we have
implemented two types of failures:

o Link failure: In case of link failure if one link between two nodes fails then only that link
gets failed. It won’t affect any other nodes in the network.
o Node failure : In case of node failure if any node fails, then all the links connected to it
also fail

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CHAPTER 3

VHDL
THE LANGUAGE OF
HARDWARE

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3. VHDL – The Language Of Hardware

3.1 Introduction

The VHSIC Hardware Description Language (VHDL) is a formal notation intended for use in
all phases of the creation of electronic systems. Because it is both machine readable and human
readable, it supports the development, verification, synthesis, and testing of hardware designs; the
communication of hardware design data; and the maintenance, modification, and procurement of
hardware.

3.2 Design Entities and Configurations

The design entity is the primary hardware abstraction in VHDL. It represents a portion of a
hardware design that has well defined inputs and outputs and performs a well defined function. A
design entity may represent an entire system, a subsystem, a board, a chip, a macro-cell, a logic
gate, or any level of abstraction in between. A configuration can be used to describe how design
entities are put together to form a complete design.

A design entity may be described in terms of a hierarchy of blocks, each of which represents a
portion of the whole design. The top level block on such a hierarchy is the design entity itself;
such a block is an external block that resides in a library and may be used as a component of other
designs. Nested blocks in hierarchy are internal blocks, defined by block statements.

A design entity may also be described in terms of interconnected components. Each component of
a design entity may be bound to a lower-level design entity in order to define the structure or
behavior of that component. Successive decomposition of a design entity into components, and
binding those components to other design entities that may be decomposed in like manner, result
in a hierarchy of design entities representing complete design.

3.3 Entity Declaration

An entity declaration defines the interface between a given design entity and the environment in
which it is used. It may also specify declarations and statements that are part of the design entity.

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A given entity declaration may be shared by many design entities, each of which has a different
architecture. Thus, an entity declaration can potentially represent a class of design entities, each
with the same interface.

entity_declaration::=
entity identifier is
entity_header
entity_declarative_part
[ begin
entity_statement_part ]
end [entity][entity_simple_name];

The entity header and entity declarative part consist of declarative items that pertain to each
design entity whose interface is defined by the entity declaration. The entity statement part, if
present, consists of concurrent statements that are present in each such design entity. If a simple
name appears at the end of an entity declaration, it must repeat the identifier of the entity
declaration.

3.4 Architecture Bodies

An architecture body defines the body of a design entity. It specifies the relationships between the
inputs and outputs of a design entity and may be expressed in terms of structure, data ow, or
behavior. Such specifications may be partial or complete.

architecture_body ::=

architecture identifier of entity_name is

architecture_declarative_part
begin
architecture_statement _part
end [architecture] [architecture_simple_name];

The identifier defines the simple name of the architecture body , this simple name distinguishes
the architecture bodies with the same entity declaration. The entity name identifies the name of
the entity declaration that defines the interface of this design entity. For a given design entity,
both the entity declaration and the associated architecture body must reside in the same library. If
a architecture name appears at the end of the architecture name body, it must repeat the identifier
of the architecture body.

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More than one architecture body may exist corresponding to a given entity declaration. Each
declares a different body with the same identifier; thus, each together with the entity declaration
represents a different design entity with the same interface design entity with the same interface.

CHAPTER 4

Xilinx
ISE

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4. Xilinx ISE (Integrated Software Environment)

The Xilinx Integrated Software Environment (ISE) is a software suite that allows a user to take a
design from the design entry stage through to the Xilinx device programming stage. The ISE
Project Navigator provides management and processing of the design by implementing the
following steps in the ISE design flow. Design through the following steps in the ISE design flow.
This project uses the ISE project navigator version 8.2i to implement the design.

The standard design flow comprises the following steps:

1. Design Entry and Synthesis—In this step of the design flow, you create your design
using a Xilinx-supported schematic editor, a hardware description language (HDL) for text-based
entry, or both. If you use an HDL for text-based entry, you must synthesize the HDL file into an
EDIF file or, if you are using the Xilinx Synthesis Technology (XST) GUI, you must synthesize
the HDL file into an NGC file.
2. Design Implementation—By implementing to a specific Xilinx architecture, you
convert the logical design file format, such as EDIF, that you created in the design entry and
synthesis stage into a physical file format. The physical information is contained in the native
circuit description (NCD) file for FPGAs and the VM6 file for CPLDs. Then you create a bit
stream file from these files and optionally program a PROM or EPROM for subsequent
programming of your Xilinx device.
3. Design Verification—Using a gate-level simulator or cable, you ensure that your design
meets your timing requirements and functions properly. See the iMPACT online help for
information about Xilinx download cables and demonstration boards.
 Design Entry

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This is the very first step in the ISE design process. During this stage the user creates the project
source files based on the design objectives. Programming languages can be used to create the top-
level design file i.e. Hardware Description Languages(HDL) such as Verilog, ABEL or VHDL,
alternatively, a schematic may be used. A number of formats may be used to create the lower
level source files in the design. The designer may be working with a synthesized EDIF
(Electronic data Interchange Format) file that has been generated by a third party design entry tool
or an NGC/NGO file, if this is the case, design entry and synthesis can be skipped.

Figure 4.1: Architecture of Xilinx CPLD

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 Synthesis

Once Design Entry has been completed the designer may run the synthesis tool. During this stage
the language design used e.g. VHDL or Verilog is converted into netlist files that are used as
inputs into the implementation process. Once this step is completed a synthesis report is generated
which can be viewed. A Technology and Real-Time Logic (RTL) schematic is also created. The
Syntax is checked and once verified, the next step may be implemented.

 Implementation

Once the implementation tool has been run the logical design is converted into a physical format
(e.g. Bit File) that may be downloaded to the specified target device. In this project the target
device is the Spartan Nexys board. From within Project Navigator the implementation process
may be run in one or multiple steps depending on whether the designer is targeting a Field
Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).Multiple
reports are generated during this stage that may be useful to the designer.

 Verification

Verification may be carried out at multiple stages in the design flow. Simulation software such as
Modelsim can be used to test the timing and the functionality of the whole design or a particular
part of the design. Simulation allows the designer to create and verify complex functions speedily.
During simulation, the source code used e.g. VHDL or Verilog is interpreted into circuit
functionality and logical results of the described HDL are displayed to determine the correct
operation of the circuit.

 Device Configuration

Once a programming file has been generated, the target device may be configured. A
programming file generation report is also available after this stage is completed. During
configuration, the Xilinx tool generates configuration files and programming files may be
downloaded from a host computer to a Xilinx device.

4.1 Creating a Project in ISE Project Navigator

1. Launch the ISE Project Navigator by double-clicking on the Xilinx ISE 11 desktop icon.

2. Click the New Project button to launch the New Project Wizard.

3. Provide a name and an appropriate location for the project

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4. Click Next to continue.

5. In the window, select the device and project properties.

6. Change the settings to match the settings shown in Figure 3.1.

7. Click Next to continue.

8. Click Next in the next window. No new sources will be created for the tutorial design.

9. In the next window, point to the sources for the tutorial design. Click the Add Source button to
select the sources provided for the tutorial design.

10. Remove the check boxes under the column Copy to Project so the source files are not copied
into the project directory.

11. Click Next to continue.

12. Review the Project Summary page and make sure that the settings match those shown in
window.

13. Click Next to continue.

Figure 4.2: Change the Settings

14. In the next window, make sure that the association and libraries have been properly specified
for the tutorial sources. Compare your settings with the settings shown.

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15. Click OK to finalize the New Project Wizard and start using ISE with the tutorial design files.

4.2 Creating VHDL Source File

1. Click the New Source button in the New Project Wizard.

2. Select VHDL Module as the source type.

3. Type in the file name counter.

4. Verify that the Add to project checkbox is selected.

5. Click Next.

6. Declare the ports for the counter design by filling in the port information as shown below:

Figure 4.3: Define Module

7. Click Next, then Finish in the New Source Information dialog box to complete the new source
file template.

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8. Click Next, then Next, then Finish.

Figure 4.4: New Project in ISE

CHAPTER 5

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CPLD
Vs
FPGA

5. Cpld Vs Fpga
5.1 Definitions of Relevant Terminology

The most important terminology used in this paper is defined below.

1. Field-Programmable Device (FPD) — a general term that refers to any type of integrated
circuit used for implementing digital hardware, where the chip can be configured by the
end user to realize different designs. Programming of such a device often involves placing
the chip into a special programming unit, but some chips can also be configured “in-
system”. Another name for FPDs is programmable logic devices (PLDs); although PLDs
encompass the same types of chips as FPDs, we prefer the term FPD because historically
the word PLD has referred to relatively simple types of devices.

2. PLA — a Programmable Logic Array (PLA) is a relatively small FPD that contains two
levels of logic, an AND-plane and an OR-plane, where both levels are programmable
(note: although PLA structures are sometimes embedded into full-custom chips, we refer

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here only to thosePLAs that are provided as separate integrated circuits and are user-
programmable).

3. PAL* — a Programmable Array Logic (PAL) is a relatively small FPD that has a
programmable

AND-plane followed by a fixed OR-plane

4. SPLD — refers to any type of Simple PLD, usually either a PLA or PAL

5. CPLD — a more Complex PLD is that consists of an arrangement of multiple SPLD-like

blocks on a single chip. Alternative names (that will not be used in this paper) sometimes
adopted for this style of chip are Enhanced PLD (EPLD), Super PAL, Mega PAL, and
others.

6. FPGA — a Field-Programmable Gate Array is an FPD featuring a general structure that

allows very high logic capacity. Whereas CPLDs feature logic resources with a wide
number of inputs (AND planes), FPGAs offer more narrow logic resources. FPGAs also
offer a higher ratio of flip-flops to logic resources than do CPLDs.

7. HCPLDs — high-capacity PLDs: a single acronym that refers to both CPLDs and FPGAs.
This term has been coined in trade literature for providing an easy way to refer to both
types of devices.

8. Interconnect — the wiring resources in an FPD.

9. Programmable Switch — a user-programmable switch that can connect a logic element to
an interconnect wire, or one interconnect wire to another

10. Logic Block — a relatively small circuit block, that is replicated in an array in an FPD.
When a circuit is implemented in an FPD, it is first decomposed into smaller sub-circuits
that can each be mapped into a logic block. The term logic block is mostly used in the
context of FPGAs, but it could also refer to a block of circuitry in a CPLD.

11. Logic Capacity — the amount of digital logic that can be mapped into a single FPD. This
is usually measured in units of “equivalent number of gates in a traditional gate array”. In
other words, the capacity of an FPD is measured by the size of gate array that it is
comparable to. In simpler terms, logic capacity can be thought of as “number of 2-input
NAND gates”.
12. Logic Density—the amount of logic per unit area in an FPD.

13. Speed-Performance — measures the maximum operable speed of a circuit when

implemented in an FPD. For combinational circuits, it is set by the longest delay through
any path, and for sequential circuits it is the maximum clock frequency for which the
circuit functions properly.

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In the remainder of this section, to provide insight into FPD development the evolution of
FPD over the past two decades is described. Additional background information is also included
on the semiconductor technologies used in the manufacture of FPDs.

5.2 Why Choose a CPLD Over an FPGA?

As Complex Programmable Logic Devices (CPLDs) move into higher densities, they offer an
exciting alternative for implementing complex digital designs. CPLDs offer the digital designer a
level of flexibility, ease of use and fast time to market that until now has been unknown for large
designs.

CPLDs provide a programmable alternative with many advantages:

o Rich logic and memory resources (480 Kbits of RAM on the Delta39K200)

o A flexible timing model with abundant routing resources

o Flexibility in changing pin-out

o In-system re-programmability

o High number of I/Os

o Integrated memory control logic, with guaranteed performance

o Availability of single chip CPLD and programmable PHY solutions

These enable fast time to market, low costs for prototyping, and the ability to add to designs or
change pin-outs at any stage in the design cycle.

5.3 What is the difference between CPLDs and FPGAs?

CPLDs are available in a range of densities, scaling from the simplest logic design to the most
complex that integrate logic, high-performance multiport and FIFO memory, and a SERDES for
demanding communications designs. The CPLD architecture used as an example in this article is
the Cypress Delta39K™ family of high-density CPLDs and Programmable Serial Interface™
(PSI™) family of programmable PHYs.

 Discussion of CPLD architecture

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CPLDs are coarse-grained programmable logic devices. They are generally logic-rich (that is,
they have a high ratio of logic gates to registers), and have highly flexible routing resources.
CPLDs are arranged as an array of clusters, linked by horizontal and vertical routing channels.

 Functional building blocks of CPLDs

The most basic element in a CPLD is the macrocell (Figure 1, left). Each macrocell can
implement a significant amount of combinatorial logic without the penalty of an extra pass. This
is why CPLDs are considered "logic rich."

Macrocells are arranged in logic blocks (LBs), with 16 macrocells to each logic block (Figure 1,
center). The macrocell performs an AND operation, followed by an OR, to implement
combinatorial logic. There are eight logic blocks per cluster, all of which are connected to the
same programmable interconnect matrix (Figure 1, right). Each cluster also has significant
embedded single and dual port or FIFO memory.

5.4 What do CPLDs offer the FPGA designer?

High IO count - One of the advantages that CPLDs offer to the FPGA designer is a greater
number of I/Os for a given device density, up to 70% more in some circumstances.

 Simple timing model

One of the main advantages of CPLDs over other programmable architectures is the simple and
predicable timing model. This simple timing model is a result of the coarse granularity of the
CPLD.

Figure 2 shows the path of a combinatorial tPD (pin to pin propagation delay with one pass of
logic). The ability to offer wide equations, independent of the routing in guaranteed time, is a
simple formula for success. This speeds up both the initial design work and the process or
debugging a design.

 Benefits of the coarse-grained CPLD architecture

This coarse granularity means that paths into and out of CPLDs pass through fewer switches, and
thus incur less delay. As a result, CPLDs can operate at higher frequencies than equivalent
FPGAs, enabling higher performance, and are easier to route enabling faster compile time.

 Benefits of the fine-grained FPGA architecture

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The fine granularity of the FPGA architecture means FPGAs have fine-grained delays between
each element. For implementing a small amount of logic placed close together, FPGAs are quite
fast. However, as the size of a design grows, the routing delays rapidly accumulate, slowing
overall performance.

 Flexible pinout

The coarse granularity and predictable timing of CPLDs enables designers to change their pinouts
late in the design process and retain the same timing.

 Embedded memory in CPLDs

CPLDs offer abundant high-speed communications memory, with integrated FIFO and dual-port
control logic for guaranteed high-speed operation. Overall this translates to higher performance
for the user's design with fewer logic resources required. The integrated FIFO and dual port
control logic avoids the need for the user to create the logic manually. It also saves programmable
resources that the designer would otherwise have to use.

The Cypress Delta39K offers up to 5x more memory than an equivalent size widely used FPGA:
For designs requiring significant memory, a CPLD can satisfy this requirement using a lower
density (and thereby cheaper) device than can an FPGA. This is a definite advantage in terms of
cost and power utilization.

5.5 Design techniques required for CPLDs and FPGAs

Both CPLDs and FPGAs have their strengths and weaknesses. Many designers prefer CPLDs due
to the simplicity of use and high speed. CPLDs tend to be better at implementing logic-intensive
functions than register intensive functions, and vice-versa for FPGAs.

 Innovative packaging options for CPLDs

CPLDs are offered in a variety of densities and packages, including the single-chip self-boot
solution. The self-boot solution combines the FLASH memory and the CPLD in a single package,
eliminating the need for an external boot prom, reducing design complexity and saving board
space.

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 Power use of CPLDs

CPLDs offer ultra-low standby power (A) in comparison to an equivalent size widely used FPGA
(mA). CPLDs are considerably better suited to applications with a low power or temperature
budget, for example handheld applications.

5.6 Applications of FPGAs

FPGAs have gained rapid acceptance and growth over the past decade because they can be
applied to a very wide range of applications. A list of typical applications includes: random logic,
integrating multiple SPLDs, device controllers, communication encoding and filtering, small to
medium sized systems with SRAM blocks, and many more.

Other interesting applications of FPGAs are prototyping of designs later to be implemented in

gate arrays, and also emulation of entire large hardware systems. The former of these applications
might be possible using only a single large FPGA (which corresponds to a small Gate Array in
terms of capacity), and the latter would entail many FPGAs connected by some sort of
interconnect; for emulation of hardware, Quick Turn [Wolff90] (and others) has developed
products that comprise many FPGAs and the necessary software to partition and map circuits.

Another promising area for FPGA application, which is only beginning to be developed, is the
usage of FPGAs as custom computing machines. This involves using the programmable parts to
“execute” software, rather than compiling the software for execution on a regular CPU. The
reader is referred to the FPGA-Based Custom Computing Workshop (FCCM) held for the last
four years and published by the IEEE. However, designs mapped into an FPGA are broken up
into logic block-sized pieces and distributed through an area of the FPGA. Depending on the

FPGA’s interconnect structure, there may be various delays associated with the interconnections
between these logic blocks.

5.7 What is Synthesis?

Synthesis is the stage in the design flow which is concerned with translating your Verilog code
into gates - and that's putting it very simply! First of all, the Verilog must be written in a
particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't actually
produce gates - it will output a netlist of the design that you have synthesized that represents the
chip which can be fabricated through an ASIC or FPGA vendor

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CHAPTER 6

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GENERATE TESTBENCH

6. Generate Testbench
6.1 Introduction

The code for implementing the required PRBS is realized by writing VHDL program. In the
program the logic implemented is very simple. A 16-bit PRBS is realized by shifting the input
through the D-flip flops and feed backing the outputs of some registers known as taps again into
the first register after passing them through a XOR gate.

6.2 Features

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The process of realizing LFSR is carried out by first developing the VHDL code for a D-flip flop.
The same D- flip flop code is then called 16 times in the main program code to realize the
required LFSR.

In the code for the PRBS tapings are taken so as to get the maximum range of the binary numbers
generated.

In the developed code tapings are taken from 1st, 2nd, 4th and 15th taps so as to obtain the
maximum length of binary digits produced.

Initially when the reset is kept at zero the outputs of each of the registers is uninitialized and
hence the output is uninitialized as well. However as soon as the reset is made high the output of
all the registers start coming out.

A dead lock condition arises in the case when the initial input into the first register as output of
the XOR gate are all 0’s.Under this condition the output of all the register of the PRBS Generator
remains as 0 at all instants of time.

Therefore it is necessary that the initial input to the PRBS Generator be equal to 1, the output of
the XOR gate.

6.3 Create The Test Bench Waveform As Follows

1. Select the counter HDL file in the Sources window.

2. Create a new test bench source by selecting Project → New Source.

3. In the New Source Wizard, select Test Bench WaveForm as the source type, and type
counter_tbw in the File Name field. Click Next.

4. The Associated Source page shows that you are associating the test bench waveform with
the source file counter. Click Next.

5. The Summary page shows that the source will be added to the project, and it displays the
source directory, type and name. Click Finish.

6. You need to set the clock frequency, setup time and output delay times in the Initialize
Timing dialog box before the test bench waveform editing window opens.

The requirements for this design are the following:

♦ The counter must operate correctly with an input clock frequency = 25 MHz.

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♦ The DIRECTION input will be valid 10 ns before the rising edge of CLOCK.

♦ The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK.

The design requirements correspond with the values below.

Fill in the fields in the Initialize Timing dialog box with the following information:

♦ Clock Time High: 20 ns.

♦ Clock Time Low: 20 ns.

♦ Input Setup Time: 10 ns.

♦ Output Valid Delay: 10 ns.

♦ Offset: 0 ns.

♦ Global Signals: GSR (FPGA)

7. Click Finish to complete the timing initialization.

8. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input
Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the
input stimulus for the counter design as follows:

♦ Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the
counter will count up.

♦ Click on the blue cell at approximately the 900 ns to assert DIRECTION high so that the
counter will count down.

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Figure
6.1: Initialize
Timing

Figure 6.2: Test Bench Waveform

9. Save the waveform.

10. In the Sources window, select the Behavioral Simulation view to see that the test bench
waveform file is automatically added to your project.

11. Close the test bench waveform.

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Figure 6.3: Behavior Simulation Selection

CHAPTER 7

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SHIFT REGISTER

7. Shift Register

Shift registers, like counters, are a form of sequential logic. Sequential logic, unlike
combinational logic is not only affected by the present inputs, but also, by the prior history. In
other words, sequential logic remembers past events.

Shift registers produce a discrete delay of a digital signal or waveform. A waveform synchronized
to a clock, a repeating square wave, is delayed by "n" discrete clock times, where "n" is the
number of shift register stages. Thus, a four stage shift register delays "data in" by four clocks to

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"data out". The stages in a shift register are delay stages, typically type "D" Flip-Flops or type
"JK" Flip-flops.

Formerly, very long (several hundred stages) shift registers served as digital memory. This
obsolete application is reminiscent of the acoustic mercury delay lines used as early computer
memory.

Serial data transmission, over a distance of meters to kilometers, uses shift registers to convert
parallel data to serial form. Serial data communications replaces many slow parallel data wires
with a single serial high speed circuit.

Serial data over shorter distances of tens of centimeters, uses shift registers to get data into and
out of microprocessors. Numerous peripherals, including analog to digital converters, digital to
analog converters, display drivers, and memory, use shift registers to reduce the amount of wiring
in circuit boards.

Some specialized counter circuits actually use shift registers to generate repeating waveforms.
Longer shift registers, with the help of feedback generate patterns so long that they look like
random noise, pseudo-noise.

Basic shift registers are classified by structure according to the following types:

 Serial-in/serial-out
 Parallel-in/serial-out
 Serial-in/parallel-out
 Universal parallel-in/parallel-out
 Ring counter

Above we show a block diagram of a serial-in/serial-out shift register, which is 4-stages long.
Data at the input will be delayed by four clock periods from the input to the output of the shift
register. Data at "data in", above, will be present at the Stage A output after the first clock pulse.
After the second pulse stage A data is transferred to stage B output, and "data in" is transferred to
stage A output. After the third clock, stage C is replaced by stage B; stage B is replaced by stage
A; and stage A is replaced by "data in". After the fourth clock, the data originally present at "data
in" is at stage D, "output". The "first in" data is "first out" as it is shifted from "data in" to "data
out".

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Figure 7.1:

Data is loaded into all stages at once of a parallel-in/serial-out shift register. The data is then
shifted out via "data out" by clock pulses. Since a 4- stage shift register is shown above, four
clock pulses are required to shift out all of the data. In the diagram above, stage D data will be
present at the "data out" up until the first clock pulse; stage C data will be present at "data out"
between the first clock and the second clock pulse; stage B data will be present between the
second clock and the third clock; and stage A data will be present between the third and the fourth
clock. After the fourth clock pulse and thereafter, successive bits of "data in" should appear at
"data out" of the shift register after a delay of four clock pulses.

If four switches were connected to DA through DD, the status could be read into a microprocessor
using only one data pin and a clock pin. Since adding more switches would require no additional
pins, this approach looks attractive for many inputs.

Figure 7.2:

Above, four data bits will be shifted in from "data in" by four clock pulses and be available at Q A
through QD for driving external circuitry such as LEDs, lamps, relay drivers, and horns.

After the first clock, the data at "data in" appears at QA. After the second clock, The old QA data
appears at QB; QA receives next data from "data in". After the third clock, Q B data is at QC. After

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the fourth clock, QC data is at QD. This stage contains the data first present at "data in". The shift
register should now contain four data bits.

Figure 7.3:

A parallel-in/laralel-out shift register combines the function of the parallel-in, serial-out shift
register with the function of the serial-in, parallel-out shift register to yields the universal shift
register. The "do anything" shifter comes at a price– the increased number of I/O (Input/Output)
pins may reduce the number of stages which can be packaged.

Data presented at DA through DD is parallel loaded into the registers. This data at QA through QD
may be shifted by the number of pulses presented at the clock input. The shifted data is available
at QA through QD. The "mode" input, which may be more than one input, controls parallel loading
of data from DA through DD, shifting of data, and the direction of shifting. There are shift registers
which will shift data either left or right.

Figure 7.4:

7.1 Serial-in/serial-out shift register

Serial-in, serial-out shift registers delay data by one clock time for each stage. They will store a
bit of data for each register. A serial-in, serial-out shift register may be one to 64 bits in length,

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longer if registers or packages are cascaded. Below is a single stage shift register receiving data
which is not synchronized to the register clock. The "data in" at the D pin of the type D FF (Flip-
Flop) does not change levels when the clock changes for low to high. We may want to
synchronize the data to a system wide clock in a circuit board to improve the reliability of a
digital logic circuit.

Figure 7.5:

The obvious point (as compared to the figure below) illustrated above is that whatever "data in" is
present at the D pin of a type D FF is transfered from D to output Q at clock time. Since our
example shift register uses positive edge sensitive storage elements, the output Q follows the D
input when the clock transitions from low to high as shown by the up arrows on the diagram
above. There is no doubt what logic level is present at clock time because the data is stable well
before and after the clock edge. This is seldom the case in multi-stage shift registers. But, this was
an easy example to start with. We are only concerned with the positive, low to high, clock edge.
The falling edge can be ignored. It is very easy to see Q follow D at clock time above. Compare
this to the diagram below where the "data in" appears to change with the positive clock edge.

Figure 7.6:

Since "data in" appears to changes at clock time t1 above, what does the type D FF see at clock
time? The short over simplified answer is that it sees the data that was present at D prior to the

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clock. That is what is transfered to Q at clock time t1. The correct waveform is QC. At t1 Q goes to
a zero if it is not already zero. The D register does not see a one until time t2, at which time Q
goes high.

Figure 7.7:

Since data, above, present at D is clocked to Q at clock time, and Q cannot change until the next
clock time, the D FF delays data by one clock period, provided that the data is already
synchronized to the clock. The QA waveform is the same as "data in" with a one clock period
delay.

A more detailed look at what the input of the type D Flip-Flop sees at clock time follows. Refer to
the figure below. Since "data in" appears to changes at clock time (above), we need further
information to determine what the D FF sees. If the "data in" is from another shift register stage,
another same type D FF, we can draw some conclusions based on data sheet information.
Manufacturers of digital logic make available information about their parts in data sheets,
formerly only available in a collection called a data book. Data books are still available; though,
the manufacturer's web site is the modern source.

Figure 7.8:

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There is no problem meeting the setup time of 60ns as the data at D has been there for the whole
previous clock period if it comes from another shift register stage. For example, at a clock
frequency of 1 Mhz, the clock period is 1000 µs, plenty of time. Data will actually be present for
1000µs prior to the clock, which is much greater than the minimum required tS of 60ns.

The hold time tH=60ns is met because D connected to Q of another stage cannot change any faster
than the propagation delay of the previous stage t P=200ns. Hold time is met as long as the
propagation delay of the previous D FF is greater than the hold time. Data at D driven by another
stage Q will not change any faster than 200ns for the CD4006b.

To summarize, output Q follows input D at nearly clock time if Flip-Flops are cascaded into a
multi-stage shift register.

Figure 7.9:

Three type D Flip-Flops are cascaded Q to D and the clocks paralleled to form a three stage shift
register above.

Figure 7.10:

7.2 Serial-in, parallel-out shift register

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A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it
shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin. It is
different in that it makes all the internal stages available as outputs. Therefore, a serial-in/parallel-
out shift register converts data from serial format to parallel format. If four data bits are shifted in
by four clock pulses via a single wire at data-in, below, the data becomes available
simultaneously on the four Outputs QA to QD after the fourth clock pulse.

Figure 7.11:

The practical application of the serial-in/parallel-out shift register is to convert data from serial
format on a single wire to parallel format on multiple wires. Perhaps, we will illuminate four
LEDs (Light Emitting Diodes) with the four outputs (QA QB QC QD ).

Figure 7.12:

The above details of the serial-in/parallel-out shift register are fairly simple. It looks like a serial-
in/ serial-out shift register with taps added to each stage output. Serial data shifts in at SI (Serial
Input). After a number of clocks equal to the number of stages, the first data bit in appears at SO
(QD) in the above figure. In general, there is no SO pin. The last stage (QD above) serves as SO
and is cascaded to the next package if it exists.

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If a serial-in/parallel-out shift register is so similar to a serial-in/ serial-out shift register, why do

manufacturers bother to offer both types? Why not just offer the serial-in/parallel-out shift
register? They actually only offer the serial-in/parallel-out shift register, as long as it has no more
than 8-bits. Note that serial-in/ serial-out shift registers come in bigger than 8-bit lengths of 18 to
64-bits. It is not practical to offer a 64-bit serial-in/parallel-out shift register requiring that many
output pins. See waveforms below for above shift register.

The shift register has been cleared prior to any data by CLR', an active low signal, which clears
all type D Flip-Flops within the shift register. Note the serial data 1011 pattern presented at the SI
input. This data is synchronized with the clock CLK. This would be the case if it is being shifted
in from something like another shift register, for example, a parallel-in/ serial-out shift register
(not shown here). On the first clock at t1, the data 1 at SI is shifted from D to Q of the first shift
register stage. After t2 this first data bit is at QB. After t3 it is at QC. After t4 it is at QD. Four
clock pulses have shifted the first data bit all the way to the last stage QD. The second data bit a 0
is at QC after the 4th clock. The third data bit a 1 is at QB. The fourth data bit another 1 is at QA.
Thus, the serial data input pattern 1011 is contained in (QD QC QB QA). It is now available on the
four outputs.

7.3 Parallel-in, parallel-out, universal shift register

The purpose of the parallel-in/ parallel-out shift register is to take in parallel data, shift it, then
output it as shown below. A universal shift register is a do-everything device in addition to the
parallel-in/ parallel-out function.

Above we apply four bit of data to a parallel-in/ parallel-out shift register at DA DB DC DD. The
mode control, which may be multiple inputs, controls parallel loading vs shifting. The mode
control may also control the direction of shifting in some real devices. The data will be shifted
one bit position for each clock pulse. The shifted data is available at the outputs QA QB QC QD .
The "data in" and "data out" are provided for cascading of multiple stages. Though, above, we can
only cascade data for right shifting. We could accommodate cascading of left-shift data by adding
a pair of left pointing signals, "data in" and "data out", above.

The internal details of a right shifting parallel-in/ parallel-out shift register are shown below. The
tri-state buffers are not strictly

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necessary to the parallel-in/ parallel-out shift register, but are part of the real-world device shown
below.

Figure 7.13:

The above figure serves as a reference for the hardware involved in right shifting of data. It is too
simple to even bother with this figure, except for comparison to more complex figures to follow.

If we need to shift left, the FFs need to be rewired. Compare to the previous right shifter. Also, SI
and SO have been reversed. SI shifts to QC. QC shifts to QB. QB shifts to QA. QA leaves on the SO
connection, where it could cascade to another shifter SI. This left shift sequence is backwards
from the right shift sequence.

7.4 Shift Register Application

Shift registers can be found in many applications. Here is a list of a few.

 To produce time delay

The serial in -serial out shift register can be used as a time delay device. The amount of delay can
be controlled by:

1. The number of stages in the register

2. The clock frequency

 To simplify combinational logic

The ring counter technique can be effectively utilized to implement synchronous sequential
circuits. A major problem in the realization of sequential circuits is the assignment of binary
codes to the internal states of the circuit in order to reduce the complexity of circuits required. By

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assigning one flip-flop to one internal state, it is possible to simplify the combinational logic
required to realize the complete sequential circuit. When the circuit is in a particular state, the
flip-flop corresponding to that state is set to HIGH and all other flip-flops remain LOW.

 To convert serial data to parallel data

A computer or microprocessor-based system commonly requires incoming data to be in parallel

format. But frequently, these systems must communicate with external devices that send or
receive serial data. So, serial-to-parallel conversion is required. As shown in the previous
sections, a serial in - parallel out register can achieve this.

CHAPTER 8

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Start
FLOWCHART
Clear Register

Set the Left shift Count Bit (N)

Tapping the Register Output

Yes
Count =
N?
8. Flowchart

Increment

Shift Right Register a bit

N
N-1 = 0 ?

Shift Left with carry

Shift Right with carry

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RE
T
 Design and Implementation of PRBS Generator Using VHDL 2009-10

Figure 8.1: A Flowchart of PRBS Generator

CHAPTER 9

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ALGORITHM

9. Algorithm

1. Set N (defaut N=8), the number of stages in the register

2. Click "Find Coefficients" button will cause the applet to find a set of feedback coefficients
a. The set of coefficient correspond to a primitive polynomial. However, there may
be other valid sets.
b. The user can decide to enter his own set of coefficients by
i. Check "Coefficients Editable"
ii. Enter "c5 c2 ..." as the customized values in the text area for coefficients.
3. Enter a initial bit sequence which has exactly N [0/1] values under "Initial data vector"
4. Enter an integer under "Sequence length i_max"
5. Enter a value, Nw, for "Displayed width". The output will be rendered in lines of Nw
values

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6. Click "Simulate" button to see a bit sequence at the register's output (right-most stage)
7. Read result in the text area window, which is also presented in a plot below
8. The plot can be zoomed in by dragging the mouse to form a rectangle, and the region will
be updated to fill the whole plot. Clicks on the “fill” button cause the plot to resume its
initial scale.

CHAPTER 10

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LFSR

10. LFSR
One of the two main parts of an LFSR is the shift register (the other being the feedback function).
A shift register is a device whose identifying function is to shift its contents into adjacent
positions within the register or, in the case of the position on the end, out of the register. The
position on the other end is left empty unless some new content is shifted into the register.

The contents of a shift register are usually thought of as being binary, that is, ones and zeroes. If a
shift register contains the bit pattern 1101, a shift (to the right in this case) would result in the
contents being 0110; another shift yields 0011. After two more shifts, things tend to get boring
since the shift register will never contain anything other than zeroes.

Two uses for a shift register are:

1) convert between parallel and serial data

2) delay a serial bit stream.

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The conversion function can go either way -- fill the shift register positions all at once (parallel)
and then shift them out (serial) or shift the contents into the register bit by bit (serial) and then
read the contents after the register is full (parallel). The delay function simply shifts the bits from
one end of the shift register to the other, providing a delay equal to the length of the shift register.
Parrelal IO

Input Output
Bit Bit

Figure 10.1: Basic of LFSR

10.1 Feedback Action

In an LFSR, the bits contained in selected positions in the shift register are combined in some sort
of function and the result is fed back into the register's input bit. By definition, the selected bit
values are collected before the register is clocked and the result of the feedback function is
inserted into the shift register during the shift, filling the position that is emptied as a result of the
shift.

Feedback around an LFSR's shift register comes from a selection of points (taps) in the register
chain and constitutes XORing these taps to provide tap(s) back into the register. Register bits that
do not need an input tap, operate as a standard shift register. It is this feedback that causes the
register to loop through repetitive sequences of pseudo-random value. The choice of taps
determines how many values there are in a given sequence before the sequence repeats. The
feedback is done so as to make the system more stable and free from errors. Specific taps are
taken from the tapping points and then by using the XOR operation on them they are feedback
into the registers.

The table for Xor is given below for various inputs:

Input A Input B Input C XOR Output

Input A Input B Input C Xor Output

0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1

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1 0 1 0
1 1 0 0
1 1 1 1
Table 10.1: Xor`ed Output of 3 Input

The bit positions selected for use in the feedback function are called "taps". The list of the taps is
known as the "tap sequence". By convention, the output bit of an LFSR that is n bits long is the
nth bit; the input bit of an LFSR is bit 1

10.2 Tapping Action

An LFSR is one of a class of devices known as state machines. The contents of the register, the
bits tapped for the feedback function, and the output of the feedback function together describe
the state of the LFSR. With each shift, the LFSR moves to a new state. (There is one exception to
this -- when the contents of the register are all zeroes, the LFSR will never change state.) For any
given state, there can be only one succeeding state. The reverse is also true: any given state can
have only one preceding state.

A state space of an LFSR is the list of all the states the LFSR can be in for a particular tap
sequence and a particular starting value. Any tap sequence will yield at least two state spaces for
an LFSR. (One of these spaces will be the one that contains only one state -- the all zero one.) Tap
sequences that yield only two state spaces are referred to as maximal length tap sequences.

The state of an LFSR that is n bits long can be any one of 2^n different values. The largest state
space possible for such an LFSR will be 2^n - 1 (all possible values minus the zero state).
Because each state can have only once succeeding state, an LFSR with a maximal length tap
sequence will pass through every non-zero state once and only once before repeating a state.

One corollary to this behavior is the output bit stream. The period of an LFSR is defined as the
length of the stream before it repeats. The longest period possible corresponds to the largest
possible state space, which is produced by a maximal length tap sequence.

Register States

Bit 1 (Tap) Bit 2 Bit 3 Bit 4 (Tap) Output Stream

1 1 0 1

0 1 1 0 1

0 0 1 1 0

1 0 0 1 1

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0 1 0 0 1

0 0 1 0 0

0 0 0 1 0

1 0 0 0 1

1 1 0 0 0

1 1 1 0 0

1 1 1 1 0

0 1 1 1 1

1 0 1 1 1

0 1 0 1 1

1 0 1 0 1

1 1 0 1 0

Table 9.2: LFSR output bit stream

10.3 Maximal Length Tap Sequences

LFSR's can have multiple maximal length tap sequences. A maximal length tap sequence also
describes the exponents in what is known as a primitive polynomial mod 2.

Example,

A tap sequence of 4, 1 describes the primitive polynomial

X^4 + X^1 + 1.

Finding a primitive polynomial mod 2 of degree n (the largest exponent in the polynomial) will
yield a maximal length tap sequence for an LFSR that is n bits long.
There is no quick way to determine if a tap sequence is maximal length. However, there are some
ways to tell if one is not maximal length:

1) Maximal length tap sequences always have an even number of taps.

2) The tap values in a maximal length tap sequence are all relatively prime.

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A tap sequence like 12, 9, 6, 3 will not be maximal length because the tap values are all divisible
by 3.

Discovering one maximal length tap sequence leads automatically to another. If a maximal length
tap sequence is described by [n, A, B, C], another maximal length tap sequence will be described
by [n, n-C, n-B, n-A]. Thus, if [32, 3, 2, 1] is a maximal length tap sequence, [32, 31, 30, 29] will
also be a maximal length tap sequence. An interesting behavior of two such tap sequences is that
the output bit streams are mirror images in time.

10.4 Characteristics Of Output Stream

By definition, the period of an LFSR is the length of the output stream before it repeats. Besides
being non-repetitive, a period of a maximal length stream has other features that are characteristic
of random streams.

1) Sums of ones and zeroes.

In one period of a maximal length stream, the sum of all ones will be one greater than the sum of
all zeroes. In a random stream, the difference between the two sums will tend to grow
progressively smaller in proportion to the length of the stream as the stream gets longer. In an
infinite random stream, the sums will be equal.

2) Runs of ones and zeroes.

A run is a pattern of equal values in the bit stream. A bit stream like 10110100 has six runs of the
following lengths in order: 1, 1, 2, 1, 1, 2. One period of an n-bit LFSR with a maximal length tap
sequence will have 2^(n-1) runs (e.g., a 5 bit device yields 16 runs in one period). 1/2 the runs
will be one bit long, 1/4 the runs will be 2 bits long, 1/8 the runs will be 3 bits long, etc., up to a
single run of zeroes that is n-1 bits long and a single run of ones that is n bits long. A random
stream of sufficient length shows similar behavior statistically.

3) Shifted stream.
Take the stream of bits in one period of an LFSR with a maximal length tap sequence and
circularly shift it any number of bits less than the total length. Do a bitwise XOR with the original
stream. A random stream also shows this behavior.

One characteristic of the LFSR output not shared with a random stream is that the LFSR stream is
deterministic. Given knowledge of the present state of the LFSR, the next state can always be
predicted.

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CHAPTER 11

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PRBS
BaSIC IMPLEMENTATION
TECHNIQUES

11. PRBS-Basic Implementation Techniques

11.1 Introduction

PRBS or Pseudo Random Binary Sequence is essentially a random sequence of binary numbers.
It is random in a sense that the value of an element of the sequence is independent of the values
of any of the other elements. It is 'pseudo' because it is deterministic and after N elements it starts
to repeat itself, unlike real random sequences.. Examples of random sequences are radioactive
decay and white noise. A binary sequence (BS) is a sequence of N bits, aj for j = 0, 1, ..., N - 1,
i.e. m ones and N m zeros. A binary sequence is pseudo-random (PRBS) if its autocorrelation
function,

has only two values:

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C (v) = m if v = 0 (mod N)
C (v) = mc if v ≠ 0 (mod N)

where

c = (m - 1)/(N - 1)

is called the duty cycle of the PRBS.

The implementation of PRBS generator is based on the linear feedback shift register, which
consists of ‘n’ master slave flip-flops. The PRBS generator produces a predefined sequence of 1's
and 0's, with 1 and 0 occurring with the same probability

11.2 Implementation

PRBS is implemented using LFSR or Linear Feedback Shift Register.

LFSR is an n-bit shift register which pseudo-randomly scrolls between 2n-1 values, but does it
very quickly because there is minimal combinational logic involved. Once it reaches its final
state, it will traverse the sequence exactly as before.

 What is the difference between a LATCH and a FLIP-FLOP ?

• Latch is a level sensitive device while flip-flop is an edge sensitive device.

• Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to

glitches.

• Latches take less gates (also less power) to implement than flip-flops.

• Latches are faster than flip-flops.

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CHAPTER 12

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PROGRAM CODE

12. Program code

12.1 VHDL Code for D Flip-Flop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if
instantiating
--library UNISIM;

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--use UNISIM.VComponents.all;
entity dff is
Port ( CLK : in std_logic;
RSTn : in std_logic;
D : in std_logic;
Q : out std_logic);
end dff;
architecture Behavioral of dff is
begin
process(CLK)
begin
if CLK'event and CLK='1' then
if RSTn='1' then
Q <= '1';
else
Q <= D;
end if;
end if;
end process;
end Behavioral;

12.2 LFSR Program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity lfsr is

Port ( clk : in STD_LOGIC;

rstn : in STD_LOGIC;

data_out : out STD_LOGIC_VECTOR (15 downto 0));

end lfsr;

architecture Behavioral of lfsr is

component dff

Port ( CLK : in std_logic;

RSTn : in std_logic;

D : in std_logic;

Q : out std_logic);

end component;

signal data_reg : std_logic_vector(15 downto 0);

signal tap_data : std_logic;

begin

process(CLK)

begin

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tap_data <= (data_reg(1) xor data_reg(2)) xor (data_reg(4) xor

data_reg(15));

end process;

stage0: dff port map(CLK, RSTn, tap_data, data_reg(0));

g0:for i in 0 to 14 generate

stageN: dff port map(CLK, RSTn, data_reg(i), data_reg(i+1));

end generate;

data_out <= data_reg after 3 ns;

end Behavioral;

12.3 PIN Diagram

Figure
12.1 PIN diagram

12.4 Schematic Diagram

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CHAPTER 13

SIMULATION
AND
OUTPUT WAVEFORM

13. Simulation and Output Waveform

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13.1 Simulation Results

13.1.1 Summary

Design Name lfsr

Fitting Status Successful
Software Version J.36
Device Used XC9572-7-PC84
Date 4- 4-2010, 8:27PM

13.1.2 Resources Summary

Macrocells Used Pterms Used Registers Used Pins Used Function Block
Inputs Used
16/72 (23%) 23/360 (7%) 16/72 (23%) 18/69 (27% 22/144 (16%)
)

13.1.3 Pin Resources

Signal Type Required Mapped Pin Type Used Total

Input 1 1 I/O 17 63
Output 5 5 GCK/IO 1 3
Bidirectional 11 11 GTS/IO 0 2
GCK 1 1 GSR/IO 0 1
GTS 0 0
GSR 0 0

13.1.4 Global Resources

Signal mapped onto global clock net clk

(GCK1)

13.1.5 Power Data

Macrocells in high performance mode 16

(MCHP)
Macrocells in low power mode (MCLP) 0
Total macrocells used (MC) 16

13.1.6 Pin List

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Pin Pin Type Assigned Signal

Num
1 I/O data_out<6>
2 I/O data_out<7>
3 I/O TIE
4 I/O TIE
5 I/O TIE
6 I/O TIE
7 I/O TIE
8 GND GND
9 I/O/GCK1 clk
10 I/O/GCK2 TIE
11 I/O TIE
12 I/O/GCK3 TIE
13 I/O data_out<8>
14 I/O TIE
15 I/O TIE
16 GND GND
17 I/O data_out<10>
18 I/O TIE
19 I/O data_out<13>
20 I/O TIE
21 I/O TIE
22 VCCIO VCC
23 I/O data_out<9>
24 I/O TIE
25 I/O TIE
26 I/O data_out<1>
27 GND GND
28 TDI TDI
29 TMS TMS
30 TCK TCK
31 I/O TIE
32 I/O TIE
33 I/O TIE
34 I/O TIE
35 I/O TIE
36 I/O TIE
37 I/O TIE
38 VCCINT VCC
39 I/O TIE
40 I/O TIE
41 I/O TIE
42 GND GND

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43 I/O data_out<2>
44 I/O data_out<11>
45 I/O TIE
46 I/O TIE
47 I/O data_out<14>
48 I/O TIE
49 GND GND
50 I/O data_out<3>
51 I/O TIE
52 I/O TIE
53 I/O TIE
54 I/O TIE
55 I/O TIE
56 I/O TIE
57 I/O TIE
58 I/O TIE
59 TDO TDO
60 GND GND
61 I/O data_out<4>
62 I/O TIE
63 I/O TIE
64 VCCIO VCC
65 I/O TIE
66 I/O TIE
67 I/O TIE
68 I/O TIE
69 I/O data_out<0>
70 I/O TIE
71 I/O data_out<12>
72 I/O rstn
73 VCCINT VCC
74 I/O/GSR TIE
75 I/O TIE
76 I/O/GTS1 TIE
77 I/O/GTS2 TIE
78 VCCINT VCC
79 I/O data_out<15>
80 I/O TIE
81 I/O TIE
82 I/O data_out<5>
83 I/O TIE
84 I/O TIE

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13.1.7 Inputs

Signal Name Function Macrocell Pin Pin Type Pin

Block Number Use
clk FB1 MC9 9 I/O/GCK1 GCK
rstn FB2 MC8 72 I/O I

Logic
Signal Total Tota Functi Macroc Pow Sle Pin Pin Pi Reg
Name Pter l on ell er w Numb Ty n Init
ms Inpu Block Mod Rat er pe Us Stat
ts e e e e

data_out< 8 5 FB2 MC2 STD FAS 69 I/O I/O RES

0> T ET

data_out< 1 2 FB3 MC2 STD FAS 17 I/O I/O RES

10> T ET

data_out< 1 2 FB4 MC2 STD FAS 44 I/O I/O RES

11> T ET

data_out< 1 2 FB2 MC6 STD FAS 71 I/O I/O RES

12> T ET

data_out< 1 2 FB3 MC5 STD FAS 19 I/O I/O RES

13> T ET

data_out< 1 2 FB4 MC5 STD FAS 47 I/O I/O RES

14> T ET

data_out< 1 2 FB2 MC12 STD FAS 79 I/O O RES

15> T ET

data_out< 1 2 FB3 MC9 STD FAS 26 I/O I/O RES

1> T ET

data_out< 1 2 FB3 MC13 STD FAS 43 I/O I/O RES

2> T ET

data_out< 1 2 FB4 MC9 STD FAS 50 I/O O RES

3> T ET

data_out< 1 2 FB4 MC13 STD FAS 61 I/O I/O RES

4> T ET

data_out< 1 2 FB2 MC16 STD FAS 82 I/O I/O RES

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5> T ET

data_out< 1 2 FB1 MC2 STD FAS 1 I/O O RES

6> T ET

data_out< 1 2 FB1 MC5 STD FAS 2 I/O O RES

7> T ET

data_out< 1 2 FB1 MC10 STD FAS 13 I/O O RES

8> T ET

data_out< 1 2 FB1 MC16 STD FAS 23 I/O I/O RES

9> T ET

13.2 Output Waveform

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CHAPTER 14

APPLICATION

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14. APPLICATIONS

LFSRs can be implemented in hardware, and this makes them useful in applications that require
very fast generation of a pseudo-random sequence, such as direct-sequence spread spectrum radio.
LFSRs have also been used for generating an approximation of white noise in various
programmable sound generators.

The Global Positioning System uses an LFSR to rapidly transmit a sequence that indicates high-
precision relative time offsets.

Applications Include:

 Data Encryption/Decryption
 Digital Signal Processing
 Wireless Communications
 Built-in Self Test (BIST)
 Data Integrity Checksums
 Data Compression
 Pseudo-random Number Generation (PN)
 Direct Sequence Spread Spectrum
 Scrambler/Descrambler
 Optimized Counters

14.1 Data Encryption/Decryption

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LFSRs have long been used as pseudo-random number generators for use in stream ciphers
(especially in military cryptography), due to the ease of construction from simple
electromechanical or electronic circuits, long periods, and very uniformly distributed
output streams. However, an LFSR is a linear system, leading to fairly easy cryptanalysis.
For example, given a stretch of known plaintext and corresponding cipher text, an attacker
can intercept and recover a stretch of LFSR output stream used in the system described,
and from that stretch of the output stream can construct an LFSR of minimal size that
simulates the intended receiver by using the Berlekamp-Massey algorithm. This LFSR
can then be fed the intercepted stretch of output stream to recover the remaining plaintext.

Three general methods are employed to reduce this problem in LFSR-based stream ciphers:

• Non-linear combination of several bits from the LFSR state;

• Non-linear combination of the output bits of two or more LFSRs (see also: shrinking
generator); or
• Irregular clocking of the LFSR, as in the alternating step generator.

Important LFSR-based stream ciphers include A5/1 and A5/2, used in GSM cell phones, E0, used
in Bluetooth, and the shrinking generator. The A5/2 cipher has been broken and both A5/1 and E0
have serious weaknesses.

14.2 Built in self tester (BIST)

At the heart of this BIST approach, lie a pseudo-random binary sequence (PRBS) generator and a
signature register. The PRBS generator is most easily implemented using a linear feedback shift
register (LFSR). A PRBS generator allows us to generate all (well, almost all) of the required
binary patterns for the circuit under test. The LFSR can be used to both generate the test sequence
for the design that is to incorporate BIST and with slight modification can be used to capture the
response of the design and generate a signature (the bit pattern held in the signature register).

The signature in the signature register can be compared to a known good signature. Within certain
realms of mathematical probability, if the signature for the circuit being tested is the same as the
known good signature, then the tested circuit is deemed as being functionally correct. There is a
little maths involved in discovering the known good value for the signature of the circuit being
tested but more on that in Part Two. This month we are going to concentrate on the design of an
LFSR and one kind of signature register.

The maximal length LFSR generates data that is almost random (hence the term ‘pseudorandom').
The output of the LFSR can be taken in parallel-out form or as a serial bit stream. The serial bit
stream is usually taken from the MSB of the LFSR. Given taps 6 and 9, it turns out that the only

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pattern not generated is all zeroes. It is a fairly simple task to add a little extra circuitry to generate
this pattern, but we won't tackle this just yet. Naturally this would give us a RBS generator, not a
pseudo to be seen.

14.3 Wireless Communications

To prevent short repeating sequences (e.g., runs of 0's or 1's) from forming spectral lines that may
complicate symbol tracking at the receiver or interfere with other transmissions, linear feedback
registers are often used to "randomize" the transmitted bit stream. This randomization is removed
at the receiver after demodulation. When the LFSR runs at the same rate as the transmitted
symbol stream, this technique is referred to as scrambling. When the LFSR runs considerably
faster than the symbol stream, expanding the bandwidth of the transmitted signal, this is direct-
sequence spread spectrum.

Neither scheme should be confused with encryption or decipherment; scrambling and spreading
with LFSRs do not protect the information from eavesdropping. They are instead used to produce
equivalent streams that possess convenient engineering properties to allow for robust and efficient
modulation and demodulation.

One of the most important uses of PRBS comes in wireless communication using CDMA
technology.

Here the input signal at the transmitter end is multiplied with a pseudo random binary number
generated by PRBS to generate a unique code which identifies itself with that particular user. At
the receiver end again the same process of multiplying the input signal with the pseudo random
binary number takes place.

The user is identified by the fact that the correlation between the numbers generated for the same
user is very high while in the case of other users the generated numbers are orthogonal to each
other.
PRBS’s application in generating a spread spectrum is also some what similar, where the obtained
spectrum is multiplied with the generated pseudo random number. In all other applications the
PRBS generates binary numbers and provides all possible numbers within the given range and
hence help in testing for all possibilities.

14.4 RADAR

The magnitude of the radial component of velocity of an object, i.e., a target, relative to a radar
site, that cannot be measured by the radar unit. Note: Radar blind speeds occur because of the
relationship between the transmitted pulse repetition rate (PRR) and the received pulse-repetition
rate. The Doppler pulse repetition rate is the difference between the transmitted and received

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pulse repetition rates. For example, when the object is stationary with respect to the radar site, the
reflected PRR is the same as the transmitted PRR and therefore a net zero signal is indicated for
the radial component of velocity.

If it happens that the Doppler PRR is the same as the transmitted PRR, i.e., the illuminating PRR,
or it is a multiple of the transmitted PRR, a zero signal is also obtained and hence the radar is
blind to these speeds, one for each multiple of the transmitted pulse repetition rate. It is not the
absolute magnitude of the speed of the object that is measured, but only the radial component of
the speed. The radial components of blind speeds, vm , are given by

vm = m f /102,

where v is the blind speed in knots, m is the multiple of the radar pulse repetition rate and the
number of the blind speed, namely a positive integer, 1, 2, 3, 4, . . ., for the first, second, third,
fourth, and so on, blind speed, is the wavelength of the illuminating radar in centimeters; f is the
transmitter pulse repetition rate in pps (pulses per second); and the 102 is a units conversion
factor. In the radar technology there is problem when the object is flying with constant speed
during the radar range.

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15. Advantages

 Two Sequence Generates With Single Program

 Variable Length LFSR

 Variable Tapping Sequence

16. CONCLUSION

As the PRBS generator using LFSR is easy because of ease of

construction from simple electronics circuit, long periods, and very uniformly
distributed output. An LFSR is a linear system, leading to fairly easy
cryptanalysis. The program code design having capability to generate two
sequence at a time with variable length of LFSR with simple logic.

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17. REFERENCES

1. S.W. Golomb, Shift Register Sequences, Holden-Day,San Francisco, 1967

2. E.J. Watson, Primitive Polynomials (Mod 2), Math. Comp. v.16 pp. 368, 1962

3. N. Zierler and J. Brillhart, On Primitive Trinomials, Information and Control v. 13, pp

541-554, 1968, and v. 14, pp. 566-569, 1969

4. R.W. Marsh, Table of Irreducible Polynomials, Dept. of Commerce, October 1957

5. B. Schneier, “Applied Cryptography - Protocols, Algorithms and Source Code in C”,

Second Edition, John Wiley and Sons, New York, 1996.

6. S. Fluhrer, I. Mantin, and A. Shamir, “Weaknesses in the Key Scheduling Algorithm of

RC4”, In Proc. of 8th Annual Workshop onSelected Areas in Cryptography (SAC 2001),
Toronto, Canada, 2001.

7. P. D. Kundarewich, S. J. E. Wilton, A. J Hu, “`A CPLD-based RC4 Cracking System'”, In

Proc. of 1999 Canadian Conference on Electrical and Computer Engineering , May 1999.

8. D. Watanabe, S. Furuya, H. Yoshida, and K. Takaragi, “MUGI Pseudorandom Number

Generator”, Specification, 2001, on line available at
http://www.sdl.hitachi.co.jp/crypto/mugi/index-e.html

9. G. Gong, T.A. Berson, and D.R. Stinson, “Elliptic curve pseudorandom sequence
generators”, Technical Report, University of Waterloo, December 1998,
http://www.cacr.math.uwaterloo.ca

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10. Lap-piu Lee, Kwok-wo Wong, “Elliptic Curve Random Number Generation”:
Proceedings of IEEE Region 10 International Conference on Electrical and Electronic
Technology, 2001. TENCON. 2001, Volume: 1, pp. 239-241.

11. Elaine Barker and John Kelsey, “Recommendation for random number generation using
deterministic random bit generators”, Special Publication 800-90, National Institute of
Standards and Technology, December 2005.

12. [Birk92] J. Birkner et al, “A very-high-speed field-programmable gate array using metal-
tometal antifuse programmable elements,” Microelectronics Journal, v. 23, pp. 561-568.

13. [Ham88] E. Hamdy et al, “Dielectric-based antifuse for logic and memory ICs,” IEEE
International Electron Devices Meeting Technical Digest, pp. 786 - 789, 1988.

APPENDICES

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